JP2018098476A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit an increase in unintended current in a structure where a bidirectional Zener diode is formed in a trench.SOLUTION: A semiconductor device 1 includes an n-type semiconductor layer 2 having a principal surface where a diode trench 46 is formed. The diode trench 46 includes an inner wall insulation film 47 on an inner wall. The inner wall insulation film 47 includes a sidewall insulation film 48 and a bottom wall insulation film 49 having a thickness larger than a thickness of the sidewall insulation film 48. The semiconductor device 1 includes a bidirectional Zener diode D formed in the diode trench 46 and on the bottom wall insulation film 49. The bidirectional Zener diode D has a pair of ntype parts 52 and at least one p type part 53 formed between the pair of ntype parts 52.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a semiconductor device including a semiconductor layer in which a trench is formed, and having a structure in which a bidirectional Zener diode is formed in the trench.

Patent Document 1 discloses a semiconductor device including a bidirectional Zener diode. The semiconductor device includes an n ⁺ type semiconductor substrate. An n ⁻ type epitaxial layer is formed on the semiconductor substrate. A trench is formed in the surface layer portion of the epitaxial layer. A gate oxide film is formed on the inner wall of the trench. A bidirectional Zener diode including an n ⁺ type region, a p type region, and an n ⁺ type region is formed in the trench.

JP 2001-257349 A

The semiconductor device according to Patent Document 1 has a structure in which a p-type region of a bidirectional Zener diode is opposed to an n ⁻ -type epitaxial layer with a gate oxide film interposed therebetween. Therefore, when a voltage drop occurs between a pair of n ⁺ -type regions sandwiching the p-type region, electrons may be attracted to a region facing the n ⁻ -type epitaxial layer in the p-type region. In this case, an inversion layer in which the p-type is inverted to the n-type is formed in the p-type region, which may cause an undesired increase in current.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of suppressing an undesired increase in current in a structure in which a bidirectional Zener diode is formed in a trench.

  A semiconductor device according to an embodiment of the present invention includes a first conductivity type semiconductor layer having a main surface in which a diode trench is formed, a sidewall insulating film formed along a sidewall of the diode trench, and the diode An inner wall insulating film including a bottom wall insulating film formed along a bottom wall of the trench and having a thickness larger than a thickness of the sidewall insulating film; and formed on the bottom wall insulating film in the diode trench. And a bidirectional Zener diode having a pair of first conductivity type parts and at least one second conductivity type part formed between the pair of first conductivity type parts.

  A semiconductor device according to another embodiment of the present invention includes a first conductivity type semiconductor layer having a main surface in which a diode trench is formed, an inner wall insulating film formed along an inner wall of the diode trench, and the diode. A bidirectional Zener diode formed in a trench and having a pair of first conductivity type portions and at least one second conductivity type portion formed between the pair of first conductivity type portions; and And a second conductivity type floating region formed in a region along the bottom wall of the diode trench.

In the semiconductor device according to the embodiment of the present invention, the bottom wall insulating film is interposed between the bottom wall of the diode trench and the bidirectional Zener diode. The bottom wall insulating film forms an inversion suppression structure that suppresses the inversion of the conductivity type of the second conductivity type portion of the bidirectional Zener diode to the first conductivity type.
Thereby, even if a voltage drop arises between a pair of 1st conductivity type parts, it can suppress that the conductivity type of a 2nd conductivity type part reverse | inverts to a 1st conductivity type. Therefore, a semiconductor device that can suppress an increase in undesired current can be provided.

  In a semiconductor device according to another embodiment of the present invention, an inner wall insulating film is interposed between the bottom wall of the diode trench and the bidirectional Zener diode. In addition, a second conductivity type floating region facing the bidirectional Zener diode is formed in the semiconductor layer with the inner wall insulating film interposed therebetween. By the inner wall insulating film and the floating region, an inversion suppression structure that suppresses the inversion of the conductivity type of the second conductivity type portion of the bidirectional Zener diode to the first conductivity type is formed.

  Thereby, even if a voltage drop arises between a pair of 1st conductivity type parts, it can suppress that the conductivity type of a 2nd conductivity type part reverse | inverts to a 1st conductivity type. Therefore, a semiconductor device that can suppress an increase in undesired current can be provided.

FIG. 1 is a plan view showing a semiconductor device according to the first embodiment of the present invention. 2 is a cross-sectional view taken along the line II-II in FIG. FIG. 3 is a diagram showing a main part of the trench gate structure. FIG. 4 is an enlarged view of a region surrounded by a two-dot chain line IV in FIG. FIG. 5 is a cross-sectional view taken along the line VV in FIG. FIG. 6 is a diagram showing a main part of the trench diode structure. FIG. 7 is a diagram illustrating a main part of the electric field relaxation structure. FIG. 8A is a cross-sectional view for explaining the method for manufacturing the semiconductor device of FIG. FIG. 8B is a cross-sectional view showing a step subsequent to FIG. 8A. FIG. 8C is a cross-sectional view showing a step subsequent to FIG. 8B. FIG. 8D is a cross-sectional view showing a step subsequent to FIG. 8C. FIG. 8E is a cross-sectional view showing a step subsequent to FIG. 8D. FIG. 8F is a cross-sectional view showing a step subsequent to FIG. 8E. FIG. 8G is a cross-sectional view showing a step subsequent to FIG. 8F. FIG. 8H is a cross-sectional view showing a step subsequent to FIG. 8G. FIG. 8I is a cross-sectional view showing a step subsequent to FIG. 8H. FIG. 8J is a cross-sectional view showing a step subsequent to FIG. 8I. FIG. 8K is a cross-sectional view showing a step subsequent to FIG. 8J. FIG. 8L is a cross-sectional view showing a step subsequent to FIG. 8K. 8M is a cross-sectional view showing a step subsequent to FIG. 8L. FIG. 9 is a diagram for explaining the operation of the bidirectional Zener diode. FIG. 10 is a diagram for explaining the operation of the bidirectional Zener diode. FIG. 11 is a cross-sectional view of a portion corresponding to FIG. 5 and shows a semiconductor device according to the second embodiment of the present invention. FIG. 12 is a cross-sectional view of a portion corresponding to FIG. 5 and shows a semiconductor device according to the third embodiment of the present invention. FIG. 13 is a cross-sectional view of a portion corresponding to FIG. 4 and is a diagram showing a modification of the bidirectional Zener diode. FIG. 14 is a plan view showing a modification of the surface electrode. FIG. 15 is a schematic plan view of a semiconductor device according to an embodiment of the reference invention. 16 is a view showing a cross section taken along the line XVI-XVI of FIG. FIG. 17 is a diagram showing a main part of the gate insulating film. 18 is an enlarged view of a region surrounded by a broken line XVIII in FIG. 19 is a view showing a cross section taken along the line XIX-XIX in FIG. FIG. 20 is a flowchart illustrating the manufacturing method of the semiconductor device. 21A to 21D are cross-sectional views for explaining a process related to the formation of the gate insulating film. FIG. 22 is a diagram illustrating a breakdown waveform between the gate and the source. FIG. 23 is a diagram for explaining a breakdown mechanism of the bidirectional Zener diode according to the first embodiment. FIG. 24 is a diagram for explaining a breakdown mechanism of the bidirectional Zener diode according to the second embodiment. FIG. 25 is a diagram for comparing breakdown waveforms of the avalanche design and the punch-through design. FIG. 26 is a diagram for explaining how the gate-source breakdown voltage BVgss and the electrostatic breakdown resistance change with respect to the design dimension of the p ⁻ -type layer of the bidirectional Zener diode. FIG. 27 is a diagram showing the relationship between the area of the active region and the electrostatic breakdown tolerance for each transistor having a different structure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First Embodiment>
FIG. 1 is a plan view showing a semiconductor device 1 according to the first embodiment of the present invention.
The semiconductor device 1 according to this embodiment is a composite semiconductor device that integrally includes an insulated gate field effect transistor Tr and a bidirectional Zener diode D. The bidirectional Zener diode D is formed as a protective element that protects the insulated gate field effect transistor Tr from, for example, overvoltage or overcurrent.

With reference to FIG. 1, a semiconductor device 1 includes a semiconductor layer 2. The semiconductor layer 2 includes a first main surface 3, a second main surface 4 located on the opposite side of the first main surface 3, and a side surface 5 connecting the first main surface 3 and the second main surface 4. The semiconductor layer 2 is formed in a rectangular chip shape in a plan view (hereinafter simply referred to as “plan view”) viewed from the normal direction of the first main surface 3.
In the semiconductor layer 2, an element formation region 6 and an outer region 7 that is an outer region of the element formation region 6 are set. The element formation region 6 is a region where the insulated gate field effect transistor Tr and the bidirectional Zener diode D are formed.

  In the present embodiment, the element formation region 6 is set in a square shape in plan view having four sides parallel to each side of the semiconductor layer 2 in plan view. The element formation region 6 is set with an interval from the periphery of the semiconductor layer 2 to the inside of the semiconductor layer 2. In the present embodiment, the outer region 7 is set to be endless (a square ring in plan view) in a region between the side wall of the semiconductor layer 2 and the periphery of the element forming region 6 so as to surround the element forming region 6. .

  A surface electrode 8 is formed on the first main surface 3 of the semiconductor layer 2. The surface electrode 8 may contain, for example, at least one of copper, an alloy containing copper, aluminum, or an alloy containing aluminum. The surface electrode 8 may contain, for example, an aluminum-copper alloy (Al—Cu alloy) or an aluminum-silicon-copper alloy (Al—Si—Cu alloy).

The surface electrode 8 includes a gate pad 9, a gate finger 10 and a source pad 11. The gate pad 9 and the gate finger 10 form the gate electrode of the insulated gate field effect transistor Tr. The source pad 11 forms the source electrode of the insulated gate field effect transistor Tr.
The gate pad 9 is formed along one corner that connects the two side surfaces 5 of the semiconductor layer 2 in plan view. The gate pad 9 is formed in a square shape in plan view. The gate finger 10 is integrally formed with the gate finger 10. The gate finger 10 is formed along the periphery of the element formation region 6 in the outer region 7. The gate finger 10 is formed in an endless shape (a square ring in plan view) surrounding the element formation region 6.

  An insulating region 12 is formed in a region surrounded by the gate pad 9 and the gate finger 10. The insulating region 12 extends along the inner edge of the gate pad 9 and the inner edge of the gate finger 10 and electrically isolates the gate pad 9 and the source pad 11. The source pad 11 is formed in an L shape in plan view within a region surrounded by the insulating region 12.

2 is a cross-sectional view taken along the line II-II in FIG.
Referring to FIG. 2, semiconductor layer 2 includes an n ⁺ type semiconductor substrate 21 made of silicon, and an n ⁻ type epitaxial layer 22 formed on the main surface of n ⁺ type semiconductor substrate 21. The n ⁻ type epitaxial layer 22 forms the first main surface 3 of the semiconductor layer 2, and the n ⁺ type semiconductor substrate 21 forms the second main surface 4 of the semiconductor layer 2.

The n type impurity concentration of the n ⁺ type semiconductor substrate 21 is, for example, 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.0 × 10 ²⁰ cm ⁻³ or less. The n type impurity concentration of the n ⁻ type epitaxial layer 22 is, for example, 1.0 × 10 ¹⁵ cm ⁻³ or more and 1.0 × 10 ¹⁷ cm ⁻³ or less.
A drain electrode 23 is connected to the second main surface 4 of the semiconductor layer 2. As a result, the n ⁺ type semiconductor substrate 21 is formed as the n ⁺ type drain region 24, and the n ⁻ type epitaxial layer 22 is formed as the n ⁻ type drift drain region 25. As the electrode material of the drain electrode 23, the same electrode material as that of the surface electrode 8 can be applied.

  A trench gate structure 27 is formed in the element formation region 6 immediately below the source pad 11. The trench gate structure 27 defines the unit cell 26 of the insulated gate field effect transistor Tr. The trench gate structure 27 includes a gate trench 28, a first inner wall insulating film 29, and a buried gate electrode 30. In the trench gate structure 27, the first inner wall insulating film 29 is formed as a gate insulating film.

  The gate trench 28 is formed in the first main surface 3 of the semiconductor layer 2. The gate trench 28 may be formed in a stripe shape in plan view, or may be formed in a lattice shape in plan view. The cell pitch P of the unit cells 26 defined by the distance between adjacent gate trenches 28 is, for example, not less than 1.0 μm and not more than 2.0 μm. The gate trench 28 has an inner wall including a side wall and a bottom wall.

The first inner wall insulating film 29 is formed along the inner wall of the gate trench 28. The buried gate electrode 30 is buried in the gate trench 28 with the first inner wall insulating film 29 interposed therebetween. The first inner wall insulating film 29 may contain silicon oxide (SiO ₂ ). The buried gate electrode 30 may include conductive polysilicon.
Although not shown, the trench gate structure 27 is electrically connected to the gate finger 10 in the outer region 7. The trench gate structure 27 supplies power to the unit cell 26.

FIG. 3 is a view showing a main part of the trench gate structure 27.
Referring to FIG. 3, the first inner wall insulating film 29 integrally includes a first side wall insulating film 31, a first bottom wall insulating film 32, and a first connection insulating film 33. The first sidewall insulating film 31 is formed along the sidewall of the gate trench 28. The first bottom wall insulating film 32 is formed along the bottom wall of the gate trench 28. The first connection insulating film 33 is formed along the connection portion that connects the side wall and the bottom wall of the gate trench 28.

The thickness t1 of the first bottom wall insulating film 32 is larger than the thickness t2 of the first side wall insulating film 31 (thickness t2 <thickness t1). The thickness t3 of the first connection insulating film 33 is equal to or less than the thickness t2 of the first sidewall insulating film 31 (thickness t3 ≦ thickness t2 <thickness t1).
A ratio t1 / Dg of the thickness t1 of the first bottom wall insulating film 32 to the depth Dg of the gate trench 28 is, for example, not less than 0.08 and not more than 0.35. A ratio t2 / t1 of the thickness t2 of the first sidewall insulating film 31 to the thickness t1 of the first bottom wall insulating film 32 is, for example, not less than 0.16 and not more than 0.6.

  The depth Dg of the gate trench 28 is, for example, not less than 9000 mm and not more than 12000 mm (in this embodiment, about 10,000 mm). The thickness t1 of the first bottom wall insulating film 32 is, for example, not less than 1000 mm and not more than 3000 mm. The thickness t2 of the first sidewall insulating film 31 is not less than 500 mm and not more than 600 mm, for example. The thickness t3 of the first connection insulating film 33 is not less than 400 mm and not more than 600 mm, for example.

Referring to FIG. 2 again, a p-type body region 34 is formed in the surface layer portion of the first main surface 3 of the semiconductor layer 2 on the side of the trench gate structure 27. The p-type body region 34 is shared by the trench gate structures 27 adjacent to each other. In the present embodiment, the p-type body region 34 is formed over substantially the entire area of the first main surface 3 of the semiconductor layer 2. The impurity concentration of p-type body region 34 is, for example, not less than 1.0 × 10 ¹⁵ cm ^{−3 and not} more than 1.0 × 10 ¹⁷ cm ⁻³ .

On the side of the trench gate structure 27, an n ⁺ -type source region 35 is formed in the surface layer portion of the p-type body region 34. The n ⁺ type source region 35 is exposed from the first main surface 3 of the semiconductor layer 2. The n type impurity concentration of the n ⁺ type source region 35 is higher than the n type impurity concentration of the n ⁻ type epitaxial layer 22, for example, 1.0 × 10 ¹⁹ cm ⁻³ or more and 1.0 × 10 ²⁰ cm ⁻³ or less. is there.

A p ⁺ type body contact region 36 is formed in the surface layer portion of the p type body region 34 on the side of the trench gate structure 27. The p ⁺ type body contact region 36 penetrates the n ⁺ type source region 35 from the first main surface 3 of the semiconductor layer 2 and is connected to the p type body region 34. The p ⁺ type body contact region 36 has a p type impurity concentration higher than the p type impurity concentration of the p type body region 34, for example, 1.0 × 10 ¹⁶ cm ⁻³ or more and 1.0 × 10 ¹⁷ cm ⁻³ or less. is there.

On the side of the trench gate structure 27, from the first main surface 3 to the second main surface 4 of the semiconductor layer 2, the n ⁺ type source region 35, the p type body region 34, and the n ⁻ type epitaxial layer 22 (n ^- -type drift drain region 25) are formed in this order.
The buried gate electrode 30 faces the n ⁺ type source region 35, the p type body region 34, and the n ⁻ type epitaxial layer 22 with the first sidewall insulating film 31 interposed therebetween. In the p-type body region 34, a region between the n ⁺ -type source region 35 and the n ⁻ -type epitaxial layer 22 is a channel of the insulated gate field effect transistor Tr.

An insulating layer 40 that covers the trench gate structure 27 is formed on the first main surface 3 of the semiconductor layer 2. The insulating layer 40 may have a stacked structure in which a plurality of insulating films are stacked, or may have a single layer structure including only one insulating film. The insulating layer 40 may include, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiN).
A source contact hole 41 is formed in the insulating layer 40. Source contact hole 41 exposes n ⁺ -type source region 35 and p-type body region 34 from insulating layer 40.

The aforementioned source pad 11 is formed on the insulating layer 40. The source pad 11 enters the source contact hole 41 from above the insulating layer 40. Source pad 11 is connected to n ⁺ type source region 35 and p ⁺ type body contact region 36 in source contact hole 41.
FIG. 4 is an enlarged view of a region surrounded by a two-dot chain line IV in FIG. FIG. 5 is a sectional view taken along line VV in FIG. In FIG. 4, for convenience of explanation, the gate pad 9 and the source pad 11 are indicated by broken lines, and the layout of the first main surface 3 of the semiconductor layer 2 is indicated by a solid line.

Referring to FIGS. 4 and 5, trench diode structure 45 is formed in element formation region 6 immediately below gate pad 9. The trench diode structure 45 includes a diode trench 46, a second inner wall insulating film 47, and a bidirectional Zener diode D.
The diode trench 46 is formed on the main surface of the semiconductor layer 2. The diode trench 46 is led out from a region immediately below the gate pad 9 to a region directly below the source pad 11. In the present embodiment, the diode trench 46 is formed in a rectangular shape in plan view.

The diode trench 46 has a depth Dd substantially equal to the depth Dg of the gate trench 28. Therefore, the depth Dd of the diode trench 46 is, for example, not less than 9000 mm and not more than 12000 mm (in this embodiment, about 10,000 mm).
The diode trench 46 has one end portion located in the region immediately below the gate pad 9 and the other end portion located in the region immediately below the source pad 11. The diode trench 46 has an inner wall including a side wall and a bottom wall.

The second inner wall insulating film 47 is formed along the inner wall of the diode trench 46. The bidirectional Zener diode D is embedded in the diode trench 46 with the second inner wall insulating film 47 interposed therebetween.
FIG. 6 is a diagram showing a main part of the trench diode structure 45.
Referring to FIG. 6, second inner wall insulating film 47 has a structure that is substantially the same as first inner wall insulating film 29. More specifically, the second inner wall insulating film 47 integrally includes a second side wall insulating film 48, a second bottom wall insulating film 49, and a second connection insulating film 50. The second sidewall insulating film 48 is formed along the sidewall of the diode trench 46. The second bottom wall insulating film 49 is formed along the bottom wall of the diode trench 46. The second connection insulating film 50 is formed along the connection portion that connects the side wall and the bottom wall of the diode trench 46.

The thickness t4 of the second bottom wall insulating film 49 is larger than the thickness t5 of the second side wall insulating film 48 (thickness t5 <thickness t4). The thickness t6 of the second connection insulating film 50 is equal to or less than the thickness t5 of the second sidewall insulating film 48 (thickness t6 ≦ thickness t5 <thickness t4).
A ratio t4 / Dd of the thickness t4 of the second bottom wall insulating film 49 to the depth Dd of the diode trench 46 is, for example, not less than 0.08 and not more than 0.35. A ratio t5 / t4 of the thickness t5 of the second sidewall insulating film 48 to the thickness t4 of the second bottom wall insulating film 49 is, for example, not less than 0.16 and not more than 0.6.

  In the present embodiment, the thickness t4 of the second bottom wall insulating film 49 is substantially equal to the thickness t1 of the first bottom wall insulating film 32 (thickness t4 = thickness t1 or thickness t4≈thickness t1). ). In the present embodiment, the thickness t5 of the second sidewall insulating film 48 is substantially equal to the thickness t2 of the first sidewall insulating film 31 (thickness t5 = thickness t2 or thickness t5≈thickness t2). In the present embodiment, the thickness t6 of the second connection insulating film 50 is substantially equal to the thickness t3 of the first connection insulating film 33 (thickness t6 = thickness t3 or thickness t6≈thickness t3).

  Referring to FIGS. 4 and 5 again, the bidirectional Zener diode D is formed on the second bottom wall insulating film 49 in the diode trench 46. In the present embodiment, the bidirectional Zener diode D is formed in a rectangular shape in plan view extending along the diode trench 46. The bidirectional Zener diode D has one end portion located in a region immediately below the gate pad 9 and the other end portion located in a region immediately below the source pad 11.

The bidirectional Zener diode D has a flat upper surface 51 that faces the opening of the diode trench 46. The upper surface 51 of the bidirectional Zener diode D is formed substantially parallel to the bottom wall of the diode trench 46.
With respect to the normal direction of the first main surface 3 of the semiconductor layer 2, the distance between the first main surface 3 of the semiconductor layer 2 and the bottom wall of the diode trench 46 is the upper surface 51 of the bidirectional Zener diode D and the diode trench 46. It is approximately equal to the distance between the bottom walls. Therefore, the upper surface 51 of the bidirectional Zener diode D is formed on the same plane as the first main surface 3 of the semiconductor layer 2.

  The bidirectional Zener diode D is formed at a distance from the side wall of the diode trench 46. The side wall of the bidirectional Zener diode D is formed in a region surrounded by the side wall of the diode trench 46. The distance between the sidewall of the bidirectional Zener diode D and the sidewall of the diode trench 46 is larger than the thickness of the bidirectional Zener diode D.

The bidirectional Zener diode D includes an n ⁺ type portion 52 (first conductivity type portion) and a p type portion 53 (second conductivity type portion), and the n ⁺ type portion 52 and the p type portion 53 are alternately repeated. It has a structure. The n ⁺ -type portion 52 is formed at one end and the other end of the bidirectional Zener diode D, respectively. In the region between the pair of n ⁺ type parts 52 formed at both ends of the bidirectional Zener diode D, n ⁺ type parts 52 and p type parts 53 are alternately and repeatedly formed.

In the present embodiment, the n ⁺ -type portion 52 and the p-type portion 53 are formed in a strip shape extending along a crossing direction intersecting with the direction in which the diode trench 46 extends in a plan view. As a result, the n ⁺ -type portion 52 and the p-type portion 53 are formed in a stripe shape extending along the intersecting direction. The intersecting direction may be an orthogonal direction orthogonal to the direction in which the diode trench 46 extends.

A pn junction is formed in a region between the n ⁺ -type portion 52 and the p-type portion 53. Zener diodes DZ1 and DZ2 having the n ⁺ type portion 52 as a cathode and the p type portion 53 as an anode are formed by the pn junction.
The bidirectional Zener diode D includes a plurality (four in this embodiment) of bidirectional Zener diode elements DE. The bidirectional Zener diode element DE includes a pair of Zener diodes DZ1 and DZ2 that are electrically connected to each other via an anode (p-type portion 53).

The bidirectional Zener diode elements DE adjacent to each other are electrically connected via a cathode (n ⁺ type portion 52). In the present embodiment, one bidirectional Zener diode D is formed by such a plurality of bidirectional Zener diode elements DE.
The bidirectional Zener diode D may have a structure including only one bidirectional Zener diode element DE. Therefore, the bidirectional Zener diode D may have a pair of n ⁺ -type portions 52 and at least one p-type portion 53 formed between the pair of n ⁺ -type portions 52.

The bidirectional Zener diode D includes a polysilicon body 54 in this embodiment. In the present embodiment, the n ⁺ type portion 52 includes an n ⁺ type impurity region formed by selectively injecting an n type impurity into the polysilicon body 54. In this embodiment, the p-type portion 53 includes a p-type impurity region formed by selectively injecting a p-type impurity into the polysilicon body 54.
The n ⁺ type portion 52 may have an n type impurity concentration substantially equal to the n type impurity concentration of the n ⁺ type source region 35. The p-type portion 53 may have a p-type impurity concentration substantially equal to the p-type impurity concentration of the p-type body region 34.

Referring to FIG. 5, p-type floating region 55 is formed in a region along the bottom wall of diode trench 46 in semiconductor layer 2. The p-type floating region 55 is formed along part of the side wall of the diode trench 46 in addition to the bottom wall of the diode trench 46. The p-type floating region 55 also covers the corners connecting the side walls and the bottom wall of the diode trench 46. The p-type impurity concentration of the p-type floating region 55 is, for example, 1.0 × 10 ¹⁵ cm ⁻³ or more and 1.0 × 10 ¹⁷ cm ⁻³ or less.

  In the present embodiment, the second bottom wall insulating film 49 is interposed between the bottom wall of the diode trench 46 and the bidirectional Zener diode D. In addition, a p-type floating region 55 facing the bidirectional Zener diode D with the second bottom wall insulating film 49 interposed therebetween is formed in the semiconductor layer 2. The second bottom wall insulating film 49 and the p-type floating region 55 form an inversion suppression structure 56 that suppresses the conductivity type of the p-type portion 53 of the bidirectional Zener diode D from being inverted to n-type.

  Referring to FIG. 5, an insulating sidewall protective film 57 is formed on the sidewall of the bidirectional Zener diode D. The side wall protective film 57 fills a region between the side wall of the bidirectional Zener diode D and the side wall of the diode trench 46. The side wall protective film 57 protects the bidirectional Zener diode D from the side wall side. Further, the side wall protective film 57 enhances the insulation between the bidirectional Zener diode D and the semiconductor layer 2 in the lateral direction parallel to the first main surface 3 of the semiconductor layer 2.

  Referring to FIGS. 4 and 5, in element formation region 6, an electric field relaxation structure 61 that relaxes the electric field in the peripheral region is formed in the peripheral region along the periphery of diode trench 46. In the present embodiment, the electric field relaxation structure 61 includes a plurality (four in this embodiment) of electric field relaxation structures 61A, 61B, 61C, and 61D that are formed in this order at intervals in a direction away from the diode trench 46.

The electric field relaxation structures 61 </ b> A, 61 </ b> B, 61 </ b> C, 61 </ b> D are formed so as to surround the diode trench 46. The electric field relaxation structures 61A, 61B, 61C, 61D include an electric field relaxation trench 62, a third inner wall insulating film 63, a buried conductor 64, and a p-type floating region 65, respectively.
The electric field relaxation trench 62 is formed in the first main surface 3 of the semiconductor layer 2. In the present embodiment, the electric field relaxation trench 62 is formed in an endless shape in plan view (a square ring in plan view) surrounding the periphery of the diode trench 46.

The electric field relaxation trench 62 has a depth Dd substantially equal to the depth Dg of the gate trench 28 and the depth of the diode trench 46. Accordingly, the depth De of the electric field relaxation trench 62 is, for example, not less than 9000 mm and not more than 12000 mm (in this embodiment, about 10,000 mm). The electric field relaxation trench 62 has an inner wall including a side wall and a bottom wall.
The third inner wall insulating film 63 is formed along the inner wall of the electric field relaxation trench 62. The buried conductor 64 is buried in the electric field relaxation trench 62 with the third inner wall insulating film 63 interposed therebetween. The third inner wall insulating film 63 may contain silicon oxide. The embedded conductor 64 may include polysilicon having conductivity.

FIG. 7 is a diagram illustrating a main part of the electric field relaxation structure 61.
The third inner wall insulating film 63 has substantially the same structure as the first inner wall insulating film 29 and the second inner wall insulating film 47. More specifically, the third inner wall insulating film 63 integrally includes a third side wall insulating film 66, a third bottom wall insulating film 67, and a third connection insulating film 68.
The third sidewall insulating film 66 is formed along the sidewall of the electric field relaxation trench 62. The third bottom wall insulating film 67 is formed along the bottom wall of the electric field relaxation trench 62. The third connection insulating film 68 is formed along the connection portion that connects the side wall and the bottom wall of the electric field relaxation trench 62.

The thickness t7 of the third bottom wall insulating film 67 is larger than the thickness t8 of the third side wall insulating film 66 (thickness t7 <thickness t8). The thickness t9 of the third connection insulating film 68 is equal to or less than the thickness t8 of the third sidewall insulating film 66 (thickness t9 ≦ thickness t8 <thickness t7).
A ratio t7 / De of the thickness t7 of the third bottom wall insulating film 67 to the depth De of the electric field relaxation trench 62 is, for example, not less than 0.08 and not more than 0.35. A ratio t8 / t7 of the thickness t8 of the third sidewall insulating film 66 to the thickness t7 of the third bottom wall insulating film 67 is, for example, not less than 0.16 and not more than 0.6.

  In the present embodiment, the thickness t7 of the third bottom wall insulating film 67 is substantially equal to the thickness t4 of the second bottom wall insulating film 49 (thickness t7 = thickness t4 or thickness t7≈thickness t4). ). In the present embodiment, the thickness t8 of the third sidewall insulating film 66 is substantially equal to the thickness t5 of the second sidewall insulating film 48 (thickness t8 = thickness t5 or thickness t8≈thickness t5). In the present embodiment, the thickness t9 of the third connection insulating film 68 is substantially equal to the thickness t6 of the second connection insulating film 50 (thickness t9 = thickness t6 or thickness t9≈thickness t6).

  Referring to FIG. 5 again, the p-type floating region 65 is formed in a region along the bottom wall of the electric field relaxation trench 62 in the semiconductor layer 2. The p-type floating region 65 is formed along a part of the side wall of the electric field relaxation trench 62 in addition to the bottom wall of the electric field relaxation trench 62. Therefore, the p-type floating region 65 also covers the corner portion connecting the side wall and the bottom wall of the electric field relaxation trench 62.

  The p-type floating region 65 may have a p-type impurity concentration substantially equal to the p-type impurity concentration of the p-type floating region 55 on the diode trench 46 side. The p-type floating region 65 may be formed with a depth substantially equal to the depth of the p-type floating region 55. The p-type floating region 65 can relax the electric field at the bottom of the electric field relaxation trench 62, particularly at the corner of the electric field relaxation trench 62.

  The number and shape of the electric field relaxation structures 61 can be appropriately changed according to the electric field to be relaxed. Therefore, a structure in which only one electric field relaxation structure 61 is formed may be employed, or a structure in which eight or more electric field relaxation structures 61 are formed may be employed. Further, an intermittent electric field relaxation structure 61 in the form of dots or lines may be formed so as to surround the periphery of the diode trench 46.

The trench diode structure 45 and the electric field relaxation structure 61 are covered with the insulating layer 40 described above. The sidewall protective film 57 formed on the trench diode structure 45 may be formed by a part of the insulating layer 40. A first contact hole 71 and a second contact hole 72 are formed in the insulating layer 40.
The first contact hole 71 exposes one end portion (n ⁺ type portion 52) of the bidirectional Zener diode D located immediately below the gate pad 9. The bottom of the first contact hole 71 may be located in one end of the bidirectional Zener diode D.

The second contact hole 72 exposes the other end portion (n ⁺ type portion 52) of the bidirectional Zener diode D located immediately below the source pad 11. The bottom of the second contact hole 72 may be located in the other end of the bidirectional Zener diode D.
A first contact plug 73 is embedded in the first contact hole 71. The first contact plug 73 is electrically connected to the gate pad 9 and one end portion (n ⁺ type portion 52) of the bidirectional Zener diode D. The first contact plug 73 may contain tungsten (W).

A second contact plug 74 is embedded in the second contact hole 72. The second contact plug 74 is electrically connected to the source pad 11 and the other end portion (p-type portion 53) of the bidirectional Zener diode D. The second contact plug 74 may contain tungsten (W).
Next, an example of a method for manufacturing the semiconductor device 1 will be described. 8A to 8M are cross-sectional views for explaining a method for manufacturing the semiconductor device 1 of FIG. 8A to 8M are sectional views of a portion corresponding to FIG. 5 described above. 8A to 8M, description will be made mainly on the trench diode structure 45 and its surrounding structure.

First, referring to FIG. 8A, an n ⁺ type semiconductor substrate 21 is prepared. Next, silicon is epitaxially grown from the main surface of the semiconductor substrate 21 while n-type impurities are introduced. As a result, the n ⁻ type epitaxial layer 22 is formed on the main surface of the n ⁺ type semiconductor substrate 21. The semiconductor layer 2 is formed by a stacked structure including the n ⁺ type semiconductor substrate 21 and the n ⁻ type epitaxial layer 22. The semiconductor layer 2 has a first main surface 3 and a second main surface 4.

Next, referring to FIG. 8B, a mask 81 is formed on first main surface 3 of semiconductor layer 2. The mask 81 may be a silicon oxide film formed by selectively oxidizing the first main surface 3 of the semiconductor layer 2. The mask 81 selectively has an opening 82 that exposes a region where the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 are to be formed.
Next, unnecessary portions of the semiconductor layer 2 are selectively removed by etching through the mask 81. Thereby, the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 are formed in the first main surface 3 of the semiconductor layer 2.

  Next, referring to FIG. 8C, p-type impurities are introduced into semiconductor layer 2 exposed from the bottoms of diode trench 46 and electric field relaxation trench 62. The p-type impurity is implanted into the semiconductor layer 2 through, for example, an ion implantation mask (not shown). As a result, a p-type floating region 55 is formed along the bottom of the diode trench 46, and a p-type floating region 65 is formed along the bottom of the electric field relaxation trench 62.

Next, referring to FIG. 8D, an insulating material layer 83 is formed by, for example, a CVD (Chemical Vapor Deposition) method. The insulating material layer 83 is formed so as to fill the gate trench 28, the diode trench 46 and the electric field relaxation trench 62 so as to cover almost the entire area of the first main surface 3 of the semiconductor layer 2.
Next, referring to FIG. 8E, unnecessary portions of the insulating material layer 83 are removed by etch back up to the middle portions in the depth direction of the gate trench 28, the diode trench 46 and the electric field relaxation trench 62. Thereby, the first bottom wall insulating film 32, the second bottom wall insulating film 49, and the third bottom wall insulating film 67 are formed.

  Next, referring to FIG. 8F, the semiconductor layer 2 exposed from the side wall of the gate trench 28, the side wall of the diode trench 46, and the side wall of the electric field relaxation trench 62 is oxidized by, for example, a thermal oxidation method or a wet oxidation method. Thereby, the first sidewall insulating film 31, the second sidewall insulating film 48, and the third sidewall insulating film 66 are formed. Thereby, the first connection insulating film 33, the second connection insulating film 50, and the third connection insulating film 68 are formed.

Next, referring to FIG. 8G, a polysilicon layer 84 is formed by, eg, CVD. The polysilicon layer 84 is formed so as to fill the gate trench 28, the diode trench 46 and the electric field relaxation trench 62 so as to cover almost the entire area of the first main surface 3 of the semiconductor layer 2.
Next, a mask 86 for selectively covering the flat region 85 located in the diode trench 46 in the polysilicon layer 84 is formed. A step portion 87 is formed between the polysilicon layer 84 formed in the diode trench 46 and the polysilicon layer 84 formed on the first main surface 3 of the semiconductor layer 2. The flat region 85 is a flat region surrounded by the step portion 87 in the polysilicon layer 84 located in the diode trench 46.

  Next, referring to FIG. 8H, unnecessary portions of the polysilicon layer 84 are removed by etch back through the mask 86. Thereby, the buried gate electrode 30 is formed in the first bottom wall insulating film 32. In addition, a polysilicon body 54 that forms the basis of the bidirectional Zener diode D is formed in the diode trench 46. Further, a buried conductor 64 is formed in the electric field relaxation trench 62.

  In this step, a polysilicon body 54 having a flat upper surface 51 facing the opening of the diode trench 46 is formed. With respect to the normal direction of the first main surface 3 of the semiconductor layer 2, the distance between the first main surface 3 of the semiconductor layer 2 and the bottom wall of the diode trench 46 is determined by the top surface 51 of the polysilicon body 54 and the bottom of the diode trench 46. It is almost equal to the distance between the walls. Therefore, the upper surface 51 of the polysilicon body 54 is formed on substantially the same plane as the first main surface 3 of the semiconductor layer 2.

  In this step, the polysilicon body 54 is formed in the diode trench 46 with a space from the side wall of the diode trench 46. The side wall of the polysilicon body 54 is formed in a region surrounded by the side wall of the diode trench 46. The distance between the side wall of the polysilicon body 54 and the side wall of the diode trench 46 is formed larger than the thickness of the polysilicon body 54.

  As a result, the step portion 87 existing between the polysilicon layer 84 formed on the first main surface 3 of the semiconductor layer 2 and the polysilicon layer 84 formed in the diode trench 46 can be removed. Therefore, it is possible to suppress the stepped portion 87 from remaining as a part of the polysilicon body 54, so that the bidirectional Zener diode D having the flat upper surface 51 can be formed.

Next, with reference to FIG. 8I, a photomask 88 is formed on the first main surface 3 of the semiconductor layer 2. The photomask 88 may be a negative type or a positive type. Here, a negative photomask 88 will be described as an example.
Next, an opening 89 that exposes a region where the p-type body region 34 is to be formed and an opening 90 that exposes a region where the p-type portion 53 of the polysilicon body 54 is to be formed are exposed to the photomask 88 by exposure and development. Selectively formed.

  Next, a p-type impurity is implanted into the surface layer portion of the first main surface 3 of the semiconductor layer 2 and the entire area of the polysilicon body 54 through the photomask 88. The p-type impurity implanted into the surface layer portion of the first main surface 3 of the semiconductor layer 2 becomes the p-type body region 34. The p-type impurity implanted into the polysilicon body 54 becomes the p-type portion 53 through a process described later. After the p-type impurity is implanted, the photomask 88 is removed.

Here, in the photomask 88, a case is considered where a relatively large step exists between a portion covering the upper surface 51 of the polysilicon body 54 and a portion covering the first main surface 3 of the semiconductor layer 2. .
When this photomask 88 is exposed, different focus margins must be set for the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. I must. Therefore, it is almost impractical to perform the exposure on the portion covering the upper surface 51 of the polysilicon body 54 and the exposure on the portion covering the first main surface 3 of the semiconductor layer 2 in the same process.

The focus margin is the width of the depth region that can be maintained in a practical state when the focus of light with respect to the photomask is shifted upward or downward from the optimal focus position during exposure.
On the other hand, in the present embodiment, the upper surface 51 of the polysilicon body 54 is formed on substantially the same plane as the first main surface 3 of the semiconductor layer 2. Therefore, in the photomask 88, it can suppress that a level | step difference is formed between the part which covers the upper surface 51 of the polysilicon body 54, and the part which coat | covers the 1st main surface 3 of the semiconductor layer 2. FIG. In addition, since the upper surface 51 of the polysilicon body 54 is formed flat, the formation of a step in the photomask 88 on the upper surface 51 of the polysilicon body 54 can also be suppressed.

Therefore, when the photomask 88 is exposed, an equal focus margin is set for the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. be able to.
Thereby, the formation process of the p-type body region 34 and the formation process of the p-type portion 53 of the polysilicon body 54 can be made common. At the same time, the process of forming the p-type portion 53 for the polysilicon body 54 formed in the diode trench 46 can be simplified.

Next, referring to FIG. 8J, another photomask 91 is formed on first main surface 3 of semiconductor layer 2. The photomask 91 may be a negative type or a positive type. Here, a negative photomask 91 will be described as an example.
Next, an opening (not shown) for exposing a region where the n ⁺ -type source region 35 is to be formed by exposure and development, and an opening 92 for exposing a region where the p-type portion 53 of the polysilicon body 54 is to be formed are exposed. Are selectively formed on the photomask 91.

Next, n-type impurities are implanted into the surface layer portion of the first main surface 3 of the semiconductor layer 2 and the polysilicon body 54 through the photomask 91. The n-type impurity implanted into the surface layer portion of the first main surface 3 of the semiconductor layer 2 becomes an n ⁺ -type source region 35. The n-type impurity implanted into the polysilicon body 54 becomes the n ⁺ -type portion 52.
This step includes an n ⁺ 52 and the p-type portion 53, the bidirectional Zener diode D of the n ⁺ -type portion 52 and the p-type portion 53 are repeated alternately structure is formed in the diode trench 46 . After the n-type impurity is implanted, the photomask 91 is removed.

  In this step, it is possible to suppress the formation of a step between the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2 in the photomask 91. In addition, since the upper surface 51 of the polysilicon body 54 is formed flat, it is possible to suppress the formation of a step in the photomask 91 on the upper surface 51 of the polysilicon body 54.

Therefore, when exposing the photomask 91, an equal focus margin is set for each of the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. be able to.
Thereby, the formation process of the n ⁺ type source region 35 and the formation process of the n ⁺ type portion 52 of the polysilicon body 54 can be made common. At the same time, the process of forming the n ⁺ type portion 52 for the polysilicon body 54 formed in the diode trench 46 can be simplified.

  Next, referring to FIG. 8K, insulating layer 40 is formed by, eg, CVD. The insulating layer 40 is formed so as to fill the region between the side wall of the polysilicon body 54 and the side wall of the diode trench 46 so as to cover almost the entire area of the first main surface 3 of the semiconductor layer 2. In the insulating layer 40, a portion where the region between the side wall of the polysilicon body 54 and the side wall of the diode trench 46 is filled becomes a side wall protective film 57 that protects the side wall of the polysilicon body 54.

Next, referring to FIG. 8L, a mask 93 is formed on insulating layer 40. The mask 93 has an opening 94 that selectively exposes a region where the first contact hole 71 and the second contact hole 72 are to be formed.
Next, unnecessary portions of the insulating layer 40 are removed by etching through the mask 93. As a result, a first contact hole 71 exposing one end of the polysilicon body 54 and a second contact hole 72 exposing the other end of the polysilicon body 54 are formed in the insulating layer 40. After the first contact hole 71 and the second contact hole 72 are formed, the mask 93 is removed.

Next, referring to FIG. 8M, tungsten is buried in first contact hole 71 and second contact hole 72 by, for example, CVD and etch back. As a result, the first contact plug 73 is formed in the first contact hole 71. Accordingly, the second contact plug 74 is formed in the second contact hole 72.
Next, an electrode material (for example, aluminum) is deposited on the insulating layer 40 by, for example, sputtering to form an electrode material layer. Next, unnecessary portions of the electrode material layer are removed, for example, by etching through a mask (not shown). Thereby, the surface electrode 8 including the gate pad 9, the gate finger 10, and the source pad 11 is formed. Thereafter, the drain electrode 23 is formed on the second main surface 4 of the semiconductor layer 2 by, for example, sputtering. The semiconductor device 1 is obtained through the above steps.

Next, the operation of the bidirectional Zener diode D will be described. Here, two bidirectional Zener diodes D in which the width Wp of the p-type portion 53 is adjusted were prepared, and their operations were examined.
9 and 10 are diagrams for explaining the operation of the bidirectional Zener diode D, respectively. FIG. 9 and FIG. 10 show operations when the bidirectional Zener diode D is broken down by avalanche breakdown, respectively.

In the bidirectional Zener diode D of FIG. 9, the width Wp of the p-type portion 53 is larger than the width Wd of the depletion layer extending from the pn junction formed between the n ⁺ -type portion 52 and the p-type portion 53 ( The width Wp> the width Wd). The width Wd of the depletion layer is the width of the depletion layer that expands from the pn junction when a breakdown voltage is applied between the gate pad 9 and the source pad 11.

Referring to FIG. 9, when a breakdown voltage is applied between gate pad 9 and source pad 11, bidirectional Zener diode D becomes conductive due to avalanche breakdown. A gate current including a noise component flows between the gate pad 9 and the source pad 11 through the bidirectional Zener diode D.
The width Wp of the p-type portion 53 is set to a value larger than the width Wd of the depletion layer (width Wp> width Wd). Therefore, in the breakdown state, each p-type portion 53 is not filled with the depletion layer, and a part of the p-type portion 53 remains with a certain width.

Since the remaining portion of the p-type portion 53 becomes a series resistance, it becomes an obstacle when the gate current is released to the ground potential (gate pad 9). As a result, inconvenience such as destruction of the gate insulating film occurs.
On the other hand, in the bidirectional Zener diode D of FIG. 10, the width Wp of the p-type portion 53 is equal to or smaller than the width Wd of the depletion layer extending from the pn junction formed between the n ⁺ -type portion 52 and the p-type portion 53. (Width Wp ≦ width Wd) is set.

Therefore, when a breakdown voltage is applied between the gate pad 9 and the source pad 11, the region of each p-type portion 53 can be filled with the depletion layer. Thereby, the source-side n ⁺ -type portion 52 and the gate-side n ⁺ -type portion 52 can be made conductive by punch-through, and the series resistance formed by the p-type portion 53 can be reduced.
In the present embodiment, the inversion suppression structure 56 including the second bottom wall insulating film 49 and the floating region is formed immediately below the bidirectional Zener diode D (see FIG. 5). The inversion suppression structure 56 suppresses the conductivity type of the p-type portion 53 of the bidirectional Zener diode D from being inverted to n-type. Therefore, it is possible to suppress formation of an undesired current path between the gate pad 9 and the source pad 11. Therefore, the stability of the on / off operation by the bidirectional Zener diode D can be improved.

Thereby, the gate current can be released to the ground potential (gate pad 9) satisfactorily. Therefore, inconveniences such as the breakdown of the gate insulating film can be suppressed, and the resistance against electrostatic breakdown and the avalanche resistance can be improved. The avalanche resistance is a resistance that the bidirectional Zener diode D does not break down in the avalanche breakdown state.
As described above, in the semiconductor device 1 according to the present embodiment, the second bottom wall insulating film 49 is interposed between the bottom wall of the diode trench 46 and the bidirectional Zener diode D. The thickness t4 of the second bottom wall insulating film 49 is larger than the thickness t5 of the second side wall insulating film 48.

In addition, a p-type floating region 55 facing the bidirectional Zener diode D with the second bottom wall insulating film 49 interposed therebetween is formed in the semiconductor layer 2. The second bottom wall insulating film 49 and the floating region form an inversion suppression structure 56 that suppresses the conductivity type of the p-type portion 53 of the bidirectional Zener diode D from being inverted to the n-type.
Thereby, even if a voltage drop arises between a pair of n ⁺ type ^| mold part 52, it can suppress that the conductivity type of the p-type part 53 inverts to n type. Therefore, in the bidirectional Zener diode D, an increase in an undesired current such as a leakage current can be suppressed. Therefore, since the stability of the on / off operation of the bidirectional Zener diode D can be enhanced, the stability of the on / off operation can contribute to the improvement of the resistance against electrostatic breakdown and the improvement of the avalanche resistance.

Further, in the semiconductor device 1 according to the present embodiment, the bidirectional Zener diode D has the upper surface 51 facing the opening of the diode trench 46, and the upper surface 51 of the bidirectional Zener diode D is the second layer of the semiconductor layer 2. 1 formed on the same plane as the main surface 3.
Thereby, in the photomask 88 used in the process of forming the p-type body region 34 and the p-type portion 53, the portion covering the upper surface 51 of the polysilicon body 54 and the first main surface 3 of the semiconductor layer 2 are covered. It can suppress that a level | step difference is formed between the parts to cover (refer FIG. 8I).

Moreover, the upper surface 51 of the polysilicon body 54 is formed flat on the bottom wall of the diode trench 46. As a result, the formation of a step in the photomask 88 on the upper surface 51 of the polysilicon body 54 can also be suppressed.
Therefore, when the photomask 88 is exposed, an equal focus margin is set for the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. be able to. Thereby, the formation process of the p-type body region 34 and the formation process of the p-type portion 53 of the polysilicon body 54 can be made common. At the same time, the process of forming the p-type portion 53 for the polysilicon body 54 formed in the diode trench 46 can be simplified.

Further, in the photomask 91 used in the process of forming the n ⁺ type source region 35 and the n ⁺ type portion 52, the portion covering the upper surface 51 of the polysilicon body 54 and the first main surface 3 of the semiconductor layer 2. It can suppress that a level | step difference is formed between the part which coat | covers (refer FIG. 8J).
Moreover, the upper surface 51 of the polysilicon body 54 is formed flat on the bottom wall of the diode trench 46. Thereby, it is possible to suppress the formation of a step in the photomask 91 on the upper surface 51 of the polysilicon body 54.

Therefore, when exposing the photomask 91, an equal focus margin is set for each of the portion covering the upper surface 51 of the polysilicon body 54 and the portion covering the first main surface 3 of the semiconductor layer 2. be able to. Thereby, the formation process of the n ⁺ type source region 35 and the formation process of the n ⁺ type portion 52 of the polysilicon body 54 can be made common. At the same time, the process of forming the n ⁺ type portion 52 for the polysilicon body 54 formed in the diode trench 46 can be simplified.

In the semiconductor device 1 according to the present embodiment, the bidirectional Zener diode D is formed in the diode trench 46 with a space from the side wall of the diode trench 46. The distance between the side wall of the bidirectional Zener diode D and the side wall of the diode trench 46 is larger than the thickness of the bidirectional Zener diode D.
According to this configuration, the polysilicon layer 84 formed on the first main surface 3 of the semiconductor layer 2 and the polysilicon layer 84 formed in the diode trench 46 in the steps of FIGS. 8G to 8H described above. The stepped portion 87 existing between them can be removed. Thereby, it is possible to suppress the stepped portion 87 from remaining as the polysilicon body 54, and therefore, the bidirectional Zener diode D having the flat upper surface 51 can be formed.

Further, the semiconductor device 1 according to the present embodiment is formed in a region between the side wall of the diode trench 46 and the side wall of the bidirectional Zener diode D, and has insulating side wall protection for protecting the side wall of the bidirectional Zener diode D. A membrane 57 is included. The sidewall protective film 57 fills a region between the sidewall of the diode trench 46 and the sidewall of the bidirectional Zener diode D.
According to this configuration, the bidirectional Zener diode D can be protected from the side wall side by the side wall protective film 57. Further, the sidewall protective film 57 can enhance the insulation between the bidirectional Zener diode D and the semiconductor layer 2 in the lateral direction parallel to the first main surface 3 of the semiconductor layer 2. Therefore, the influence of the electric field exerted on the semiconductor layer 2 by the bidirectional Zener diode D can be reduced.

In addition, the semiconductor device 1 according to the present embodiment is formed in the surface layer portion of the main surface of the semiconductor layer 2 in the peripheral region along the periphery of the diode trench 46, and relaxes the electric field of the peripheral region. including.
According to this configuration, the electric field relaxation structure 61 can suppress the concentration of the electric field in the peripheral region along the periphery of the diode trench 46. Therefore, it is possible to suppress a decrease in the resistance to electrostatic breakdown and a decrease in the avalanche resistance due to the concentration of the electric field.

In the semiconductor device 1 according to this embodiment, the trench gate structure 27, the trench diode structure 45, and the electric field relaxation structure 61 have substantially the same configuration. Therefore, the trench gate structure 27, the trench diode structure 45, and the electric field relaxation structure 61 can be formed in the semiconductor layer 2 by a common process. Therefore, the manufacturing process can be simplified and the number of steps can be reduced.
Second Embodiment
FIG. 11 is a cross-sectional view of a portion corresponding to FIG. 5 and shows a semiconductor device 95 according to the second embodiment of the present invention. In FIG. 11, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

The semiconductor device 95 according to the present embodiment has the same configuration as that of the semiconductor device 1 according to the first embodiment described above except that the p-type floating region 55 along the bottom wall of the diode trench 46 is not provided. ing.
In the semiconductor device 95 according to the present embodiment, the conductivity type of the p-type portion 53 of the bidirectional Zener diode D is reduced by the second bottom wall insulating film 49 interposed between the bottom wall of the diode trench 46 and the bidirectional Zener diode D. An inversion suppression structure 56 that suppresses inversion to n-type is formed.

Even with such a configuration, the same operational effects as those described in the first embodiment can be obtained.
<Third Embodiment>
FIG. 12 is a cross-sectional view of a portion corresponding to FIG. 5 and shows a semiconductor device 97 according to the third embodiment of the present invention. In FIG. 12, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

The semiconductor device 97 according to this embodiment is the same as the first embodiment except that the thickness t4 of the second bottom wall insulating film 49 is formed to be substantially equal to the thickness t5 of the second side wall insulating film 48. The configuration is the same as that of the semiconductor device 1 according to the embodiment.
In the semiconductor device 97 according to the present embodiment, the bidirectional Zener diode D is formed by the thin second bottom wall insulating film 49 interposed between the bottom wall of the diode trench 46 and the bidirectional Zener diode D and the p-type floating region 55. An inversion suppression structure 56 that suppresses the conductivity type of the p-type portion 53 from being inverted to the n-type is formed.

Even with such a configuration, the same operational effects as those described in the first embodiment can be obtained.
As mentioned above, although embodiment of this invention was described, this invention can also be implemented with another form.
In the first embodiment described above, in the bidirectional Zener diode D, the example in which the n ⁺ -type portion 52 and the p-type portion 53 are formed in a stripe shape has been described. However, the bidirectional Zener diode D may have a structure as shown in FIG.

FIG. 13 is a cross-sectional view of a portion corresponding to FIG. 4, and shows a modification of the bidirectional Zener diode D. In FIG. 13, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.
In the bidirectional Zener diode D according to the present modification, the n ⁺ -type portion 52 at one end is disposed in the center of the inner region of the gate pad 9. The remaining p-type part 53 and n ⁺ -type part 52 are arranged concentrically so as to surround the central n ⁺ -type part 52. And the 1st contact plug 73 is connected with respect to the n ^<+> type ^| mold part 52 of the one end part located in the center. The second contact plug 74 is connected to the n ⁺ type portion 52 at the other end located on the outermost periphery.

Even in such a structure, the n ⁺ -type portion 52 and the p-type portion 53 are alternately repeated from the n ⁺ -type portion 52 at one end toward the n ⁺ -type portion 52 at the other end. A Zener diode D can be obtained. Of course, the bidirectional Zener diode D having such a structure can also be applied to the second and third embodiments.
In the first embodiment described above, the example in which the surface electrode 8 includes the gate pad 9 formed along the corner of the semiconductor layer 2 has been described. However, instead of this, the surface electrode 8 having the structure shown in FIG. 14 may be employed.

FIG. 14 is a plan view showing a modification of the surface electrode. In FIG. 14, the same components as those described in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. FIG. 14 shows an example in which the semiconductor layer 2 is formed in a chip shape having a rectangular shape in plan view.
In the surface electrode 8 according to this modification, the source pad 11 is formed in a rectangular shape in plan view extending along the longitudinal direction of the semiconductor substrate 21. The source pad 11 is formed with a removal region 99 extending from one end portion in the longitudinal direction toward the other end portion, one end portion being an open end and the other end portion being a closed end. The closed end of the removal region 99 is a pad region 100 that is wider than other sections of the removal region 99.

  The gate pad 9 is disposed in the pad region 100 of the removal region 99. The gate pad 9 is surrounded by the source pad 11 except for the connection portion with the gate finger 10. The gate finger 10 extends from the gate pad 9 toward the open end of the removal region 99 of the source pad 11. The gate finger 10 is further routed from the open end of the removal region 99 to the outer region 7 (the outer periphery of the source pad 11). The gate finger 10 may surround the entire circumference of the source pad 11.

Even with such a structure, the trench diode structure 45 straddling the gate pad 9 and the source pad 11 can be formed in the region immediately below the gate pad 9. Of course, the surface electrode 8 having such a structure can also be applied to the second and third embodiments.
In each of the above-described embodiments, the example in which the trench gate structure 27, the trench diode structure 45, and the electric field relaxation structure 61 have substantially the same configuration has been described. However, the trench gate structure 27, the trench diode structure 45, and the electric field relaxation structure 61 may have different structures.

For example, the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 may be formed at different depths by forming the gate trench 28, the diode trench 46, and the electric field relaxation trench 62 in different steps, respectively. .
Further, the first inner wall insulating film 29, the second inner wall insulating film 47, and the third inner wall insulating film 63 are formed in separate steps, respectively, so that the first inner wall insulating film 29, the second inner wall insulating film 47, and the third inner wall insulating film 47 are formed. The inner wall insulating films 63 may be formed with different thicknesses.

Further, at least one of the first inner wall insulating film 29, the second inner wall insulating film 47, and the third inner wall insulating film 63 may be formed with a uniform thickness.
Further, the second inner wall insulating film 47 integrally includes the second side wall insulating film 48, the second bottom wall insulating film 49, and the second connection insulating film 50, while the first inner wall insulating film 29 and the third inner wall insulating film. The film 63 may be formed with a uniform thickness.

Further, the third inner wall insulating film 63 integrally includes the third side wall insulating film 66, the third bottom wall insulating film 67, and the third connection insulating film 68, while the first inner wall insulating film 29 has a uniform thickness. It may be formed.
In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be employed. That is, the p-type portion may be n-type and the n-type portion may be p-type.

In addition, various design changes can be made within the scope of matters described in the claims. Examples of features extracted from this specification and drawings are shown below.
Item 1: A first conductivity type semiconductor layer having a main surface, a diode trench formed in the main surface of the semiconductor layer, a pair of first conductivity type portions and the pair of first conductivity type portions formed in the diode trench. A bidirectional Zener diode having at least one second conductivity type part formed between the first conductivity type parts, and the diode trench interposed between the bidirectional Zener diode and the bottom wall of the diode trench. And a bottom wall insulating film in which a ratio of thickness to depth is set to 0.08 or more and 0.35 or less.

  In the semiconductor device according to Item 1, the bottom wall insulating film is interposed between the bottom wall of the diode trench and the bidirectional Zener diode. The ratio of the thickness of the bottom wall insulating film to the depth of the diode trench is set to 0.08 or more and 0.35 or less. The bottom wall insulating film forms an inversion suppression structure that suppresses the inversion of the conductivity type of the second conductivity type portion of the bidirectional Zener diode to the first conductivity type.

Thereby, even if a voltage drop arises between a pair of 1st conductivity type parts, it can suppress that the conductivity type of a 2nd conductivity type part reverse | inverts to a 1st conductivity type. Therefore, a semiconductor device that can suppress an increase in undesired current can be provided.
Item 2: The inversion suppression structure that suppresses the inversion of the conductivity type of the second conductivity type part of the bidirectional Zener diode to the first conductivity type is formed by the bottom wall insulating film. Semiconductor device.

Item 3: The semiconductor device according to Item 1 or 2, wherein a depth of the diode trench is 9000 mm to 12000 mm, and a thickness of the bottom wall insulating film is 1000 mm to 3000 mm.
Item 4: The semiconductor device according to any one of Items 1 to 3, further including a sidewall insulating film formed along a sidewall of the diode trench and having a thickness smaller than a thickness of the bottom wall insulating film. .

Item 5: The semiconductor device according to Item 4, wherein a ratio of the thickness of the sidewall insulating film to the thickness of the bottom wall insulating film is 0.16 or more and 0.6 or less.
<Reference invention>
As a problem different from the “problem to be solved by the invention”, in recent years, for example, in the in-vehicle market and the industrial machine market, there is an increasing demand for a transistor satisfying low on-resistance and low capacity (high-speed switching). For example, a measure is taken to reduce the input capacitance Ciss (= Cgd + Cgs) by reducing the effective area of each gate electrode by reducing the area of the active region of the transistor. However, such a reduction in the capacity of the transistor leads to a reduction in the electrostatic breakdown resistance of the transistor.

As a countermeasure against electrostatic breakdown, as in Patent Document 1, it is common to incorporate a bidirectional Zener diode in a transistor.
However, in the method of avalanche breakdown of the bidirectional Zener diode as in Patent Document 1, the noise current is released, for example, a part of the p ⁻ type region remains in a certain width without being depleted after breakdown. Become. The remaining portion of the p ⁻ type region serves as a series resistance when noise current flows through the bidirectional Zener diode. Therefore, the noise current is not sufficiently absorbed, and the gate insulating film is easily broken.

On the other hand, a measure to increase the breakdown tolerance of the gate insulation film itself by increasing the thickness of the gate insulation film can be studied, but it is difficult to accurately adjust the thickness of the gate insulation film according to the design value of the breakdown resistance of the film . Further, since the thickness of the gate insulating film is closely related to the switching performance of the transistor, it is not preferable to change the thickness of the gate insulating film unnecessarily.
An object of the reference invention is to provide a semiconductor device capable of realizing high electrostatic breakdown resistance while having low on-resistance and low capacitance.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor layer having a first conductivity type source region, a second conductivity type body region, and a first conductivity type drain region, and the body region via a gate insulating film. And a source electrode connected to the source region, a pair of first conductivity type portions at both ends, and at least one second conductivity type portion between the pair of first conductivity types. And the pair of first conductivity type parts includes a bidirectional Zener diode connected to the source electrode and the gate electrode, respectively, and the second conductivity type part of the bidirectional Zener diode includes the source electrode and the gate electrode. When a predetermined voltage is applied between the gate electrode and the gate electrode, the width is smaller than the width of the depletion layer extending from the pn junction between the first conductivity type portion and the second conductivity type portion.

  According to this configuration, the width of the depletion layer generated when a predetermined voltage is applied between the gate and the source> the width of the second conductivity type portion of the bidirectional Zener diode. Therefore, for example, when a voltage due to electrostatic discharge is applied between the gate and the source, the first conductivity type portion at one end of the bidirectional Zener diode is changed to the first at the other end of the bidirectional Zener diode by punch-through. It can be conducted with the conductive type part. As a result, the series resistance when a current flows after breakdown can be reduced as compared with the structure in which the bidirectional Zener diode is made to conduct by avalanche breakdown. As a result, even if a noise current enters the semiconductor device due to electrostatic discharge, the noise current can be released well through the bidirectional Zener diode. As a result, it is possible to achieve a high withstand capability against electrostatic breakdown. For example, it is possible to reduce the on-resistance and the capacity by miniaturizing each part of the semiconductor device.

Further, since it is not necessary to increase the thickness of the gate insulating film in order to improve the breakdown resistance, the thickness of the gate insulating film can be designed with a focus on the switching performance of the transistor. Therefore, the influence on the switching performance of the transistor can be reduced.
In the semiconductor device according to the embodiment of the reference invention, the “predetermined voltage” may include, for example, a voltage equal to or higher than the “gate-source rated voltage Vgss” guaranteed for a distributed semiconductor device. .

  The semiconductor device according to an embodiment of the reference invention may further include a gate trench formed in the semiconductor layer and a buried insulating film buried in a bottom portion of the gate trench. In that case, the source region, the body region, and the drain region are arranged in the depth direction of the gate trench along the side surface of the gate insulating film, and the gate insulating film is connected to the buried insulating film. It may be formed on a side surface of the gate trench. The semiconductor device may include a thin film portion that is disposed at a boundary portion between the gate insulating film and the buried insulating film and is thinner than the gate insulating film.

As described above, since the semiconductor device according to the embodiment of the reference invention can achieve a high electrostatic breakdown tolerance, it can be applied well to a semiconductor device having a structure in which a thin film portion is disposed in a gate trench. it can.
In the semiconductor device according to an embodiment of the reference invention, the bidirectional Zener diode is formed of a polysilicon layer, and the first conductivity type portion and the second conductivity type portion are respectively formed on the polysilicon layer. A first conductivity type impurity region and a second conductivity type impurity region which are selectively formed may be included.

The breakdown voltage (breakdown voltage) of the bidirectional Zener diode is defined by the width of the second conductivity type portion. Therefore, if the second conductivity type part is an impurity region in the polysilicon layer as described above, the width of the second conductivity type part is easily adjusted by the width of the mask when the impurity is implanted into the polysilicon layer. It is also possible to adjust the width of the second conductivity type part with high accuracy.
When the bidirectional Zener diode is formed of a polysilicon layer, specifically, the thin film portion has a thickness of 400 to 450 mm, and the second impurity region is 2.0 × 10 ¹⁶ cm. ^It may have an impurity concentration of ^{−3 to} 6.0 × 10 ¹⁶ cm ⁻³ and a width of 2.4 μm to 2.6 μm.

In the semiconductor device according to an embodiment of the reference invention, in the bidirectional Zener diode, the first conductivity type portion at one end is disposed in the center, and the remaining second conductivity type portion and the first conductivity type portion are You may arrange | position concentrically so that the said 1st conductivity type part of the center may be surrounded.
When the semiconductor device according to an embodiment of the reference invention includes a gate pad that is connected to the gate electrode and exposed on the outermost surface of the semiconductor device, the bidirectional Zener diode is disposed in a region immediately below the gate pad. May be.

According to this configuration, it is not necessary to secure a space for arranging the bidirectional Zener diode in the outer peripheral region of the chip by effectively utilizing the region immediately below the gate pad, which contributes to miniaturization of the semiconductor device. it can.
In the semiconductor device according to one embodiment of the reference invention, the semiconductor layer may include a silicon substrate.

Hereinafter, embodiments of the reference invention will be described in detail with reference to the accompanying drawings.
FIG. 15 is a schematic plan view of a semiconductor device 101 according to an embodiment of the reference invention.
Referring to FIG. 15, a semiconductor device 101 includes a semiconductor substrate 102, an electrode film 103, and a surface protective film 104 as an example of a semiconductor layer according to a reference invention. The surface protective film 104 partially covers the electrode film 103 and selectively exposes a source pad 110 and a gate pad 111 described later. As the surface protective film 104, for example, silicon nitride (SiN) or the like can be used.

The semiconductor substrate 102 defines the outer shape of the semiconductor device 101 and has, for example, a chip shape that is rectangular in plan view. The semiconductor substrate 102 may be, for example, a silicon substrate, or may be a wide band gap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) that can be used for a power device.
The electrode film 103 is made of a conductive material such as an aluminum (Al) base material (for example, AlCu) and includes a source metal 105 and a gate metal 106.

  The source metal 105 has a substantially rectangular outer shape in plan view extending in the longitudinal direction of the semiconductor substrate 102. The source metal 105 is formed with a removal region 107 extending from one end in the longitudinal direction toward the other end, one end being an open end and the other end being a closed end. The closed end of the removal region 107 is a pad region 108 that is wider than other sections of the removal region 107. Further, a part of the source metal 105 is exposed from the pad opening 109 of the surface protection film 104 to the outermost surface of the semiconductor device 101 as the source pad 110.

The gate metal 106 includes a gate pad 111 and a gate finger 112.
The gate pad 111 is disposed in the pad region 108 and exposed from the pad opening 113 of the surface protective film 104 to the outermost surface of the semiconductor device 101. The gate pad 111 is surrounded by the source metal 105 except for the connection portion with the gate finger 112.
On the other hand, the gate finger 112 may be covered with the surface protective film 104 (in FIG. 15, it is indicated by a solid line for clarity). The gate finger 112 extends from the gate pad 111 toward the open end of the removal region 107 of the source metal 105, and is further drawn around the periphery of the semiconductor substrate 102 from the open end to surround the source metal 105. In this embodiment, the entire circumference of the source metal 105 is surrounded by the gate fingers 112.

16 is a diagram showing a cross section taken along line XVI-XVI in FIG. FIG. 17 is a view showing a main part of the gate insulating film 115 of FIG.
Referring to FIG. 16, semiconductor device 101 includes semiconductor substrate 102, gate trench 114, gate insulating film 115, gate electrode 116, p ⁻ type body region 117, n ⁺ type source region 118, n ^{A −} type drain region 119, a p ⁺ type body contact region 120, an interlayer insulating film 121, a source metal 105, and a drain electrode 122 are included.

The semiconductor substrate 102 may be an epitaxial substrate obtained by crystal growth of an epitaxial layer 124 made of n ⁻ -type silicon on a base substrate 123 made of n ⁺ -type silicon, for example. The impurity concentration of the n ⁺ -type base substrate 123 is, for example, 2.0 × 10 ¹⁹ cm ^{−3 to} 7.0 × 10 ¹⁹ cm ⁻³ , and the impurity concentration of the n ⁻ -type epitaxial layer 124 is, for example, It may be 8.0 × 10 ¹⁵ cm ^{−3 to} 2.0 × 10 ¹⁶ cm ⁻³ .

  The gate trench 114 is formed in a predetermined pattern on the surface portion of the semiconductor substrate 102. The pattern of the gate trench 114 may be various patterns such as a stripe shape and a lattice shape. The surface portion of the semiconductor substrate 102 is partitioned into a plurality of unit cells 125 according to the pattern of the gate trench 114. Further, an interval (cell pitch) between adjacent gate trenches 114 may be, for example, about 1.0 μm to 2.0 μm.

The gate insulating film 115 is formed on the inner surface of the gate trench 114, and will be described in more detail with reference to FIG.
Referring to FIG. 17, a buried insulating film 126 is disposed inside the gate trench 114 in addition to the gate insulating film 115. Both the gate insulating film 115 and the buried insulating film 126 may be made of an insulating material such as silicon oxide (SiO ₂ ). The buried insulating film 126 is buried from the deepest part of the gate trench 114 to a certain height, and the gate insulating film 115 is arranged on the side surface of the gate trench 114 in a manner continuous with the buried insulating film 126. The thickness t ₁ of the buried insulating film 126 in the depth direction of the gate trench 114 may be, for example, 1000 to 3000 mm, and the thickness t ₂ of the gate insulating film 115 may be, for example, 500 to 600 mm.

A gate electrode 116 is buried in a region surrounded by the gate insulating film 115 and the buried insulating film 126. Gate electrode 116 may be made of a conductive material such as polysilicon.
In this embodiment, the thin film portion 127 having a thickness t ₃ (for example, 400 to 450 mm) thinner than the thickness t ₂ of the gate insulating film 115 at the boundary between the gate insulating film 115 and the buried insulating film 126. Are provided integrally. That is, in the insulating film in the gate trench 114, the thin film portion 127 is formed in a portion in contact with the bottom portion of the gate electrode 116. The thin film portion 127 may be made of the same insulating material such as silicon oxide (SiO ₂ ) as the gate insulating film 115 and the buried insulating film 126.

Referring to FIG. 16 again, p ⁻ type body region 117 is formed in the surface portion of epitaxial layer 124 in each unit cell 125. The impurity concentration of p ⁻ type body region 117 may be, for example, 1.0 × 10 ¹⁶ cm ^{−3 to} 3.5 × 10 ¹⁶ cm ⁻³ .
The n ⁺ type source region 118 is formed on the surface portion of the p ⁻ type body region 117 in each unit cell 125. The impurity concentration of the n ⁺ -type source region 118 may be, for example, 1.0 × 10 ¹⁹ cm ^{−3 to} 1.0 × 10 ²⁰ cm ⁻³ .

The n ⁻ -type drain region 119 is an n ⁻ -type portion on the opposite side of the n ⁺ -type source region 118 with respect to the p ⁻ -type body region 117 in the epitaxial layer 124, and is a region common to the plurality of unit cells 125. is there. The n ⁻ type drain region 119 is a region where the conductivity type of the epitaxial layer 124 is maintained. Therefore, the impurity concentration of n ⁻ type drain region 119 may be, for example, 2.0 × 10 ¹⁶ cm ^{−3 to} 6.0 × 10 ¹⁶ cm ⁻³ (same as n ⁻ type epitaxial layer 124). . The n ⁻ type drain region 119 may be referred to as an n ⁻ type drift region.

The p ⁺ type body contact region 120 is formed in each unit cell 125 so as to penetrate the n ⁺ type source region 118 from the surface of the epitaxial layer 124 and to be in contact with the p ⁻ type body region 117. The impurity concentration of p ⁺ type body contact region 120 may be, for example, 1.0 × 10 ¹⁶ cm ^{−3 to} 3.5 × 10 ¹⁶ cm ⁻³ .
Interlayer insulating film 121 is made of an insulating material such as silicon oxide (SiO ₂ ), for example, and is arranged on semiconductor substrate 102. A contact hole 128 is formed in the interlayer insulating film 121 to expose the n ⁺ type source region 118 and the p ⁺ type body contact region 120. Source metal 105 is connected to n ⁺ type source region 118 and p ⁺ type body contact region 120 through contact hole 128.

The drain electrode 122 is made of a conductive material such as an aluminum (Al) base material (for example, AlCu), and is formed on the back surface of the semiconductor substrate 102.
FIG. 18 is an enlarged view of a region surrounded by a broken line IV in FIG. 19 is a view showing a cross section taken along the line XIX-XIX in FIG. 18 and 19, the same reference numerals are given to the configurations shown in FIGS. 15 to 17, and the description thereof may be omitted.

Referring to FIGS. 18 and 19, a bidirectional Zener diode 129 is arranged in a region immediately below gate pad 111. The bidirectional Zener diode 129 is formed on the semiconductor substrate 102 via an insulating film 130 (for example, silicon oxide). The bidirectional Zener diode 129 has a structure in which an n ⁺ type portion 131 as an example of the first conductivity type portion of the reference invention and a p ⁻ type portion 132 as an example of the second conductivity type portion of the reference invention are alternately repeated. Both end portions of the repetitive structure are n ⁺ type portions 131. In this embodiment, as shown in FIG. 18, in the bidirectional Zener diode 129, the n ⁺ type portion 131 at one end is arranged in the center of the inner region of the gate pad 111, and the remaining p ⁻ type portion 132 and n ^{The +} mold part 131 is arranged concentrically so as to surround the central n ⁺ mold part 131.

In this embodiment, the bidirectional Zener diode 129 is formed of a polysilicon layer. The n ⁺ -type portion 131 and the p ⁻ -type portion 132 are configured as n-type or p-type impurity regions selectively formed in the polysilicon layer. For example, n ⁺ type portion 131 and p ⁻ type portion 132 may have the same impurity concentration as n ⁺ type source region 118 and p ⁻ type body region 117, respectively.

The interlayer insulating film 121 covers the bidirectional Zener diode 129. In the interlayer insulating film 121, a gate-side contact hole 133 that exposes the n ⁺ -type portion 131 at one end is formed in the inner region of the gate pad 111.
The gate side contact hole 133 is formed, for example, in a straight line along the periphery of the central n ⁺ type portion 131. In this embodiment, the central n ⁺ type part 131 is formed in a square shape in plan view, and a total of four gate side contact holes 133 are formed on each peripheral edge of the central n ⁺ type part 131. ing.

The gate pad 111 is connected to the central n ⁺ -type portion 131 via a contact plug 134 (for example, a conductive material such as tungsten (W)) embedded in each gate-side contact hole 133.
Further, in the interlayer insulating film 121, a source that exposes the n ⁺ type portion 131 at the other end portion directly under the source pad 110 behind the gate pad 111 (opposite side of the gate pad 111 where the gate finger 112 is connected). A side contact hole 135 is formed.

The source-side contact hole 135 is formed, for example, in a straight line along one peripheral edge of the outermost n ⁺ type part 131. In this embodiment, the outermost n ⁺ type part 131 is formed in a square ring shape in plan view, and the source side contact hole 135 is formed along one peripheral edge of the outermost peripheral n ⁺ type part 131. Yes.
The source pad 110 is connected to the outermost n ⁺ type portion 131 via a contact plug 136 (for example, a conductive material such as tungsten (W)) embedded in the source side contact hole 135.

Next, a method for manufacturing the semiconductor device 1 will be described. FIG. 20 is a flowchart illustrating a method for manufacturing the semiconductor device 101. 21A to 21D are cross-sectional views for explaining a process related to the formation of the gate insulating film 115.
In order to manufacture the semiconductor device 101, for example, the epitaxial layer 124 made of n ⁻ type silicon is formed on the base substrate 123 made of n ⁺ type silicon by epitaxial growth (S1).

The next step is formation of the gate trench 114 and the gate insulating film 115. As shown in FIG. 21A, a gate trench 114 is formed in the epitaxial layer 124 by a method such as reactive ion etching (RIE) (S2).
Next, as shown in FIG. 21B, an insulating film 137 is deposited on the epitaxial layer 124 by, eg, CVD (S3). The deposition of the insulating film 137 is continued until the gate trench 114 is backfilled and the surface of the epitaxial layer 124 is covered with an insulating material.

Next, as shown in FIG. 21C, a part of the insulating film 137 is removed by, for example, etch back (S4). As a result, a buried insulating film 126 made of the insulating film 137 remaining at the bottom of the gate trench 114 is obtained.
Next, as shown in FIG. 21D, the side surface of the gate trench 114 is oxidized by, for example, thermal oxidation to form the gate insulating film 115 (S5).

Although specific illustration is omitted from here again, after forming the gate insulating film 115, polysilicon, which is the material of the gate electrode 116, is deposited by, for example, CVD (S6), and is unnecessary after the deposition, for example, by etchback. The part is removed (S7). Thereby, the gate electrode 116 embedded in the gate trench 114 is obtained.
Next, the insulating film 130 that is the base of the bidirectional Zener diode 129 is formed on the epitaxial layer 124 by, eg, CVD (S8).

Next, polysilicon, which is a material of the bidirectional Zener diode 129, is deposited by, for example, the CVD method (S9). After deposition, unnecessary portions are removed by, for example, etch back (S10). As a result, a diode polysilicon layer is obtained on the insulating film 130.
Next, a mask having an opening is selectively applied to the region where the n ⁺ -type source region 118 is to be formed over the epitaxial layer 124, and n-type impurities are implanted through the mask. At this time, an n-type impurity is simultaneously implanted into the diode polysilicon layer (S11). The implantation into the polysilicon layer for the diode may be a whole surface implantation without a mask.

Next, on the epitaxial layer 124, a mask having an opening is selectively applied to a region where the p ⁻ type body region 117 is to be formed, and a p-type impurity is implanted through the mask. At this time, a p-type impurity is simultaneously implanted into the polysilicon layer for the diode (S12). Implantation into the diode polysilicon layer may be performed by masking a region where the p ⁻ type portion 132 is not formed.

Next, a mask having an opening is selectively applied to the region where the p ⁺ type body contact region 120 is to be formed on the epitaxial layer 124, and a p-type impurity is implanted through the mask (S13).
Then, by the diffusion process of the implanted impurities is performed in S11 to S13, p ^- type body region 117, ^{n +} -type ^{n +} -type source region 118, ^{p +} -type body contact region 120 and the bidirectional Zener diode 129, A part 131 and a p ^- type part 132 are formed.

Next, an interlayer insulating film 121 is formed on the epitaxial layer 124 by, eg, CVD (S14), and contact holes 128, 133, and 135 are formed in the interlayer insulating film 121 (S15).
Next, after the contact plugs 134 and 136 are buried in the gate side contact hole 133 and the source side contact hole 135, the source metal 105 and the gate metal 106 are formed on the interlayer insulating film 121 (S16).

Next, the drain electrode 122 is formed on the back surface of the semiconductor substrate 102 by, for example, sputtering. The semiconductor device 1 is obtained through the above steps.
The semiconductor device 101 can be used as a switching element, for example. In this case, a predetermined voltage (a voltage equal to or higher than the gate threshold voltage) is applied to the gate metal 106 with a drain voltage having a positive drain side applied between the source metal 105 and the drain electrode 122 (between the source and drain). To do. As a result, a channel is formed along the depth direction of the gate trench 114 in the vicinity of the gate insulating film 115 in the p ⁻ type body region 117, and a current flows in the depth direction of the gate trench 114.

  According to this semiconductor device 101, as shown in FIGS. 18 and 19, the bidirectional Zener diode 129 is connected between the gate metal 106 and the source metal 105 (between the gate and the source). Therefore, even if a noise current or the like due to electrostatic discharge enters the semiconductor device 101, the noise current can be released to the outside (ground potential) by flowing the noise current preferentially through the bidirectional Zener diode 129.

  That is, as shown in FIG. 22, when the breakdown tolerance of the gate insulating film 115 (here, the gate insulating film 115 is a concept including the thin film portion 127) is around 25V, the bidirectional Zener diode 129 is incorporated. When a voltage of about 25 V is applied between the gate and the source in a state in which the gate insulating film is not connected, the gate insulating film 115 is broken near 25 V and a leak current flows. This leakage current becomes more prominent as the gate-source voltage Vgs increases, and increases almost proportionally from the voltage value corresponding to the breakdown tolerance.

  On the other hand, as shown by the breakdown waveforms of the two diodes in FIG. 22, if a bidirectional Zener diode 129 that causes breakdown at a voltage lower than the breakdown withstand voltage of the gate insulating film 115 is incorporated, noise current or the like Even if the semiconductor device 101 enters, the bidirectional Zener diode 129 is broken down before the gate insulating film 115, so that the noise current flows preferentially through the bidirectional Zener diode 129, and ESD protection of the semiconductor device 101 can be achieved. it is conceivable that.

However, in the diode of the first form in FIG. 22, the waveform after breakdown is considerably gentler than that of the gate insulating film 115, so that the gate-source voltage Vgs of about 40 V is the boundary (diode waveform and gate insulation). At the intersection A) with the film waveform, a noise current flows out to the gate insulating film 115 and the gate insulating film 115 is destroyed.
On the other hand, if the waveform after breakdown is steeper than that of the first embodiment and the slope is close to the slope of the waveform of the gate insulating film 115 as in the diode of the second form of FIG. Even when the gate-source voltage Vgs is applied, the noise current can continue to flow preferentially through the bidirectional Zener diode 129, and the gate insulating film 115 can be prevented from being destroyed.

Next, the breakdown mechanism of the diode of the first form and the diode of the second form will be described in detail with reference to FIG. 23 and FIG.
First, FIG. 23 is a diagram for explaining the breakdown mechanism of the bidirectional Zener diode 129 according to the first embodiment, in which the bidirectional Zener diode 129 is broken down by avalanche breakdown (avalanche design). .

According to FIG. 23, since the breakdown voltage (breakdown voltage) of the bidirectional Zener diode 129 is defined by the impurity concentration of the n ⁺ -type portion 131 and the p ⁻ -type portion 132, the gate-source corresponding to the breakdown voltage when voltage Vgs is applied, and the n ⁺ -type portions 131 of the n ⁺ -type portion 131 and the gate side of the source side is turned on by an avalanche breakdown. Therefore, even after breakdown, each p ⁻ type portion 132 is not filled with the depletion layer 138 (lower side in FIG. 23), and a part of the p ⁻ type portion 132 remains with a certain width. The remaining portion of the p ⁻ type portion 132 becomes a series resistance 139 when a noise current flows through the bidirectional Zener diode 129 from the source side to the gate side. Therefore, as shown in FIG. 22 and FIG. 25, the noise current (vertical axis lgs in FIG. 22 and FIG. 25) increases only slowly even after breakdown, and the gate insulating film 115 is likely to be destroyed.

On the other hand, FIG. 24 is a diagram for explaining the breakdown mechanism of the bidirectional Zener diode 129 according to the second embodiment, in which the bidirectional Zener diode 129 is broken down by punch-through (punch). Through design).
According to FIG. 24, the breakdown voltage (breakdown voltage) of the bidirectional Zener diode 129 is defined by the width of the p ⁻ type portion 132. Specifically, the width Wp of the p ⁻ type portion 132 is defined to be smaller than the width Wd of the depletion layer 138 that expands when, for example, a breakdown voltage is applied between the gate and the source (Wp ≦ Wd). ). Therefore, when the gate-source voltage Vgs corresponding to the breakdown voltage of the bidirectional Zener diode 129 is applied, the source-side n ⁺ -type portion 131 and the gate-side n ⁺ -type portion 131 are electrically connected by punch-through. Can be made. Therefore, after breakdown, the region of each p ⁻ -type portion 132 is filled with the depletion layer 138 (lower side in FIG. 24), so that the series resistance can be reduced as compared with the avalanche design in FIG. As a result, as shown in FIGS. 22 and 25, the increase in noise current after breakdown (vertical axis lgs in FIGS. 22 and 25) becomes steeper than in the avalanche design of FIG. Can be satisfactorily released to the ground potential via the bidirectional Zener diode 129.

FIG. 26 is a diagram for explaining how the gate-source breakdown voltage BVgss and the electrostatic breakdown resistance change with respect to the design dimension of the p ⁻ type portion 132 of the bidirectional Zener diode 129. is there.
According to FIG. 26, with the design dimension of 2.6 μm as a boundary, the gate-source breakdown voltage BVgss converges at about 27 V even if the width of the p ⁻ type portion 132 is larger than that. On the other hand, the electrostatic breakdown resistance is drastically decreased in the region of 2.6 μm or more. That, and the 2.6μm on the boundary, p ^- the width of the mold portion 132 is more regions, p ^- regardless of the breadth of the mold portion 132 p ^- Break by avalanche breakdown, which is defined by the concentration of mold portion 132 As a result, the gate insulating film 115 is easily broken (low electrostatic breakdown resistance).

On the other hand, in the region where the width of the p ⁻ type portion 132 is 2.6 μm or less, the breakdown voltage BVgss between the gate and the source increases in proportion to the design size of the p ⁻ type portion 132. ^- it can be confirmed that the breakdown by punch-through related to the width of the mold portion 132 has occurred. Therefore, in the region where the width of the p ⁻ type portion 132 is 2.6 μm or less, the noise current is favorably absorbed according to the mechanism shown in FIG. 24, and thus high electrostatic breakdown resistance is maintained.

Therefore, based on FIG. 26, for example, if the “gate-source rated voltage Vgss” guaranteed for the semiconductor device 101 is 20 V, the application of the gate-source voltage exceeding the rated voltage Vgss is applied to the gate insulating film 115. Therefore, the design dimension of the p ⁻ type portion 132 is set to 2.5 μm (± 0.1 μm) in anticipation of the variation of 0.1 μm. Then, when the voltage exceeds 20 V, the bidirectional Zener diode 129 is broken down by punch-through to sufficiently release the noise current, while the current flowing through the gate insulating film 115 can be suppressed. As a result, a high electrostatic breakdown resistance of about 30V can be maintained.

Note that the preferable design dimension described above is merely an example for demonstrating the effect of the semiconductor device 101, and varies depending on the impurity concentration of the p ⁻ type portion 132 constituting the bidirectional Zener diode 1029. For example, if the impurity concentration of the p ⁻ type portion 132 is in the range of 2.0 × 10 ¹⁶ cm ^{−3 to} 6.0 × 10 ¹⁶ cm ⁻³ , the width of 2.4 μm to 2.6 μm is preferable.
As described above, according to the semiconductor device 101, it is possible to achieve high electrostatic breakdown resistance.

  This can be further proved by FIG. FIG. 27 is a diagram showing that sufficient electrostatic breakdown resistance can be realized even if the area of the active region of the semiconductor device 101 is reduced and miniaturized. In FIG. 27, the second form and the first form correspond to the second form and the first form shown in FIGS. 22 to 25 described above. On the other hand, in the conventional example, the buried insulating film 126 and the thin film portion 127 are not formed in the gate trench 114, except that the gate insulating film thicker than the thin film portion 127 is formed with a substantially uniform thickness. The semiconductor device which has the same structure as the 1st form is shown.

That is, according to FIG. 27, since the semiconductor device of the second form has the thin film portion 127, the semiconductor device in spite of the fact that the breakdown resistance of the insulating film itself in the gate trench 114 is lower than that of the conventional example. Overall, high electrostatic breakdown resistance can be achieved.
Therefore, for example, the buried insulating film 126 thicker than the gate insulating film 115 is adopted to reduce the gate-drain capacitance, or each part of the semiconductor device 101 is miniaturized to reduce the on-resistance and the capacitance. You can plan.

In addition, since it is not necessary to increase the thickness of the gate insulating film 115 in order to improve the breakdown tolerance, the thickness of the gate insulating film 115 can be designed by focusing on the switching performance of the transistor. Therefore, the influence on the switching performance of the transistor can be reduced.
Although one embodiment of the reference invention has been described above, the reference invention can be implemented in other forms.

  For example, a configuration in which the conductivity type of each semiconductor portion of the semiconductor device 101 is inverted may be employed. That is, in the semiconductor device 101, the p-type portion may be n-type and the n-type portion may be p-type.

1: Semiconductor device 2: Semiconductor layer 27: Trench gate structure 28: Gate trench 29: First inner wall insulating film (gate insulating film)
30: buried gate electrode 34: p-type body region 35: n ⁺ type source region 46: diode trench 47: second inner wall insulating film (inner wall insulating film)
48: Second sidewall insulating film (sidewall insulating film)
49: Second bottom wall insulating film (bottom wall insulating film)
51: Upper surface of bidirectional Zener diode 52: n ⁺ type portion 53 of bidirectional Zener diode 53: p type portion 54 of bidirectional Zener diode: Polysilicon body 55: p type floating region 56: Inversion suppression structure 57: Side wall protective film 61: Electric field relaxation structure 62: Electric field relaxation trench 63: Third inner wall insulating film (electric field relaxation inner wall insulating film)
64: embedded conductor 95: semiconductor device 96: inversion suppression structure 97: semiconductor device 98: inversion suppression structure D: bidirectional Zener diode Tr: insulated gate field effect transistor 101: semiconductor device 102: semiconductor substrate 105: source metal 106 : Gate metal 111: gate pad 114: gate trench 115: gate insulating film 116: gate electrode 117: p ⁻ type body region 118: n ⁺ type source region 119: n ⁻ type drain region 126: buried insulating film 127: thin film portion 129: Bidirectional Zener diode 131: n ⁺ type part 132: p ⁻ type part 138: depletion layer

Claims (18)

A semiconductor layer of a first conductivity type having a main surface on which a diode trench is formed;
A sidewall insulating film formed along the sidewall of the diode trench, and an inner wall including a bottom wall insulating film formed along the bottom wall of the diode trench and having a thickness greater than the thickness of the sidewall insulating film An insulating film;
The diode trench has a pair of first conductivity type portions and at least one second conductivity type portion formed between the pair of first conductivity type portions and formed on the bottom wall insulating film in the diode trench. A semiconductor device including a bidirectional Zener diode.   The bottom wall insulating film interposed between the bottom wall of the diode trench and the bidirectional Zener diode prevents the conductivity type of the second conductivity type part of the bidirectional Zener diode from being inverted to the first conductivity type. The semiconductor device according to claim 1, wherein an inversion suppressing structure is formed. A semiconductor layer of a first conductivity type having a main surface on which a diode trench is formed;
An inner wall insulating film formed along the inner wall of the diode trench;
A bidirectional Zener diode formed in the diode trench and having at least one second conductivity type portion formed between the pair of first conductivity type portions and the pair of first conductivity type portions;
And a second conductivity type floating region formed in a region along the bottom wall of the diode trench in the semiconductor layer.   The inner wall insulating film interposed between the bottom wall of the diode trench and the bidirectional Zener diode, and the floating region facing the bidirectional Zener diode across the inner wall insulating film, The semiconductor device according to claim 3, wherein an inversion suppression structure that suppresses inversion of the conductivity type of the second conductivity type part to the first conductivity type is formed. The inner wall insulating film includes a sidewall insulating film formed along a side wall of the diode trench, and a bottom formed along the bottom wall of the diode trench and having a thickness larger than the thickness of the side wall insulating film. Including wall insulation film,
The bidirectional Zener is formed by the bottom wall insulating film interposed between the bottom wall of the diode trench and the bidirectional Zener diode, and the floating region facing the bidirectional Zener diode across the bottom wall insulating film. 4. The semiconductor device according to claim 3, wherein an inversion suppression structure that suppresses inversion of the conductivity type of the second conductivity type portion of the diode to the first conductivity type is formed. 5. The bidirectional Zener diode has an upper surface facing the opening of the diode trench;
The semiconductor device according to claim 1, wherein an upper surface of the bidirectional Zener diode is formed on the same plane as a main surface of the semiconductor layer.   The semiconductor device according to claim 1, wherein the bidirectional Zener diode is formed in the diode trench with a gap from a side wall of the diode trench. The bidirectional Zener diode is formed in the diode trench spaced from a side wall of the diode trench;
The semiconductor device according to claim 1, wherein a distance between a sidewall of the bidirectional Zener diode and a sidewall of the diode trench is larger than a thickness of the bidirectional Zener diode.   The semiconductor device according to claim 7, further comprising an insulating sidewall protective film that protects a sidewall of the bidirectional Zener diode. The bidirectional Zener diode includes a polysilicon body,
The pair of first conductivity type portions includes a first conductivity type impurity region selectively formed in the polysilicon body,
The semiconductor device according to claim 1, wherein the second conductivity type portion includes a second conductivity type impurity region selectively formed in the polysilicon body. A body region of the second conductivity type formed in the surface layer portion of the main surface of the semiconductor layer, a source region of the first conductivity type formed in the surface layer portion of the body region, and the body region across the gate insulating film A gate electrode, and a source electrode connected to the source region, further including an insulated gate field effect transistor having the semiconductor layer as a drain region,
In the bidirectional Zener diode, one of the pair of first conductivity type portions is electrically connected to the gate electrode, and the other of the pair of first conductivity type portions is electrically connected to the source electrode. The semiconductor device as described in any one of Claims 1-10 currently connected. A gate trench is further formed on the main surface of the semiconductor layer,
The gate insulating film is formed along an inner wall of the gate trench;
The gate electrode is embedded in the gate trench with the gate insulating film interposed therebetween, and is opposed to the source region, the body region, and the drain region with the gate insulating film interposed therebetween. Semiconductor device. The gate trench has the same depth as the diode trench;
The gate insulating film has the same structure as the inner wall insulating film,
The semiconductor device according to claim 12, wherein the gate electrode has the same conductive material as that of the bidirectional Zener diode.   The surrounding area along the periphery of the diode trench further includes an electric field relaxation structure that is formed in a surface layer portion of the main surface of the semiconductor layer and that relaxes the electric field of the surrounding area. The semiconductor device according to item.   The semiconductor device according to claim 14, wherein the plurality of electric field relaxation structures are formed at intervals in a direction away from the diode trench.   The semiconductor device according to claim 14, wherein the electric field relaxation structure is formed so as to surround the diode trench. An electric field relaxation trench is further formed in the main surface of the semiconductor layer,
The electric field relaxation structure is
An electric field relaxation inner wall insulating film formed along the inner wall of the electric field relaxation trench;
The semiconductor device according to claim 14, further comprising a buried conductor buried in the electric field relaxation trench with the electric field relaxation inner wall insulating film interposed therebetween. The electric field relaxation trench has the same depth as the diode trench;
The electric field relaxation inner wall insulating film has the same structure as the inner wall insulating film,
The semiconductor device according to claim 17, wherein the embedded conductor has the same conductive material as that of the bidirectional Zener diode.

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