JP6945836B2 - Field effect transistors and electronics - Google Patents

Description

The present invention relates to field effect transistors and electronic devices.

Among semiconductor devices, field effect transistors (FETs) are widely used in various electronic devices and the like.

FIG. 6 shows an example of the structure of the field effect transistor. 6 (A) to 6 (C) are cross-sectional views and plan views schematically showing the structure of a horizontal (bottom gate / top contact type) field effect transistor. As shown in the figure, in the conventional horizontal field effect transistor, a semiconductor layer 13 is formed on the gate electrode 11 via an insulating film 12, and a rectangular source electrode 14 and a drain electrode 15 are spaced on the gate electrode 11 at regular intervals. Are arranged so as to face each other.

When forming such a source electrode and a drain electrode, as shown in FIG. 6C, when a misalignment with respect to the gate electrode occurs, the xy direction and the gate electrode are separated from each other between the source electrode and the drain electrode and the gate electrode. Misalignment in the θ direction occurs. As a result, there is a problem that the area of the overlapping portion between the source electrode and the drain electrode and the gate electrode fluctuates, which leads to the fluctuation of the parasitic capacitance. Further, there is a problem that the on-current varies due to the fluctuation of the channel length and the channel width.

In a vertical field-effect transistor in which the source electrode and the drain electrode are formed in different layers in the vertical direction, the same problem occurs due to misalignment.

On the other hand, as shown in FIG. 7, a field effect transistor having a configuration in which a source electrode 14 and a drain electrode 15 are meshed in a comb-tooth shape has been proposed (Patent Document 1). As a result, even when the alignment deviation occurs, the influence of the alignment deviation in the xy direction can be reduced to some extent.

Japanese Unexamined Patent Publication No. 2010-238873

However, there is a need for a method that can more effectively reduce the influence of the alignment deviation in the θ direction as well as the alignment deviation in the xy direction.

Therefore, an object of the present invention is to more effectively reduce the influence of misalignment in the field effect transistor.

In order to achieve the above object, the field effect transistor of the present invention can be used.
A substrate, a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode are included.
The gate electrode, the gate insulating film, and the semiconductor layer are laminated on the substrate in the above order.
The source electrode and the drain electrode are in contact with the semiconductor layer, and the source electrode and the drain electrode are in contact with the semiconductor layer.
At least one of the source electrode and the drain electrode is characterized in that it has a substantially arc shape in all or a part of the portions facing each other when viewed from the upper surface.

The electronic device of the present invention is characterized by including the field effect transistor of the present invention.

According to the present invention, it is possible to reduce the influence of misalignment in the field effect transistor. Therefore, for example, fluctuations in the channel width and channel length caused by the deviation can be suppressed, and a stable on-current can be obtained. Further, for example, it is possible to improve the variation in the characteristics of the field effect transistor. Further, according to the present invention, since the influence of the misalignment can be reduced, for example, the design margin for the misalignment can be made smaller than before, and the device can be miniaturized and integrated. be able to.

FIG. 1 is a cross-sectional view and a plan view showing an example of a field effect transistor according to the first embodiment. FIG. 2 is a plan view showing an example of the structure of the field effect transistor in the modified example of the first embodiment. FIG. 3 is a plan view showing an example of the structure of the field effect transistor according to the second embodiment. FIG. 4 is a plan view showing an example of the structure of the field effect transistor according to the third embodiment. FIG. 5 is a cross-sectional view showing an example of the structure of the field effect transistor according to the fourth embodiment. FIG. 6 is a cross-sectional view and a plan view showing an example of the structure of a conventional field effect transistor. FIG. 7 is a plan view showing an example of the structure of a conventional field effect transistor.

In the field effect transistor of the present invention, for example, one of the source electrode and the drain electrode has a convex substantially arc shape and the other is concave in all or a part of the portions facing each other when viewed from the upper surface. It has a substantially arc shape.

In the field effect transistor of the present invention, for example, one of the source electrode and the drain electrode is formed so as to surround the other in all or a part of the portions facing each other when viewed from the upper surface.

In the field effect transistor of the present invention, for example, at least one of the source electrode and the drain electrode has an island shape when viewed from the upper surface.

In the field effect transistor of the present invention, for example, the source electrode and the drain electrode include a substantially arc-shaped shape when viewed from the upper surface.

In the field effect transistor of the present invention, for example, the source electrode and the drain electrode are formed in different layers in the vertical direction.

In the field effect transistor of the present invention, for example, the installation surface of the gate electrode is larger than the installation surface of the drain electrode and the source electrode when viewed from the upper surface.

In the field effect transistor of the present invention, for example, the semiconductor layer is smaller than the installation surface of the gate electrode when viewed from the upper surface.

In the field effect transistor of the present invention, for example, the semiconductor layer is an organic semiconductor layer.

Next, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited or limited by the following embodiments. In the drawings below, the same parts are designated by the same reference numerals. The descriptions in each embodiment can be referred to each other. Further, in the drawings, for convenience of explanation, the structure of each part may be shown in a simplified manner as appropriate, and the dimensional ratio of each part may be shown schematically, which is different from the actual one.

(Embodiment 1)
FIG. 1A is a schematic view (cross-sectional view) of the field effect transistor 1 according to the present embodiment as viewed from the side. As shown in FIG. 1A, the field effect transistor 1 of the present embodiment includes a substrate 10, a gate electrode 11, a gate insulating film 12, a semiconductor layer 13, a source electrode 14, and a drain electrode 15. Including, the gate electrode 11, the gate insulating film 12, and the semiconductor layer 13 are laminated on the substrate 10 in the above order. Then, in the present embodiment, the source electrode 14 and the drain electrode 15 are arranged in contact with the upper surface of the semiconductor layer 13.

In the field effect transistor 1, the materials of the substrate 10, the gate electrode 11, the gate insulating film 12, the semiconductor layer 13, the source electrode 14, and the drain electrode 15 are not particularly limited, and known materials can be used.

Examples of the material forming the gate electrode 11 include Al-Nd, Au, Ag, Cu, Mo-Nb, Ta, Cr, and alloys thereof. Examples of the material forming the source electrode 14 and the drain electrode 15 include Al-Nd, Au, Ag, Cu, Al, Mo-Nb, and alloys thereof. The gate electrode 11, the source electrode 14, and the drain electrode 15 may be, for example, laminated films, respectively. The laminated film can be formed, for example, by forming the material into a clad structure of an electrode and a barrier metal.

The field effect transistor 1 is preferably an organic transistor in which the semiconductor layer 13 is an organic semiconductor, for example. The material for forming the organic semiconductor is, for example, pentacene, 5,6,11,12-tetraphenylnaphthacene (rubrene), 2,3-benzoanthracene (tetrasene), 2,6- as a low molecular weight p-type semiconductor. Asenes such as diphenylanthracene, dinaphtho [3,2-b: 2', 3'-f] thieno [3,2-b] thiophene (DNTT), 2,7-diphenyl [1] benzothieno [3,2- b] [1] Heteroacenes such as benzothiophene (DPh-BTBT), phenanthro [1,2-b: 8,7-b'] dithiophene, benzo [a] chrysene, 2,5-bis (4-biphenylyl) ) Thiophene, 2,8-dimethylanthracene [2,3-b: 7,6-b'] Thiophenes such as dithiophene (DMADT) and oligothiophenes, porphyrins such as phthalocyanine and copper phthalocyanine, 4,7-di Examples thereof include benzothiazoles such as (2-thienyl) -2,1,3-benzothiaiazole, and bis (ethylenedithio) tetrathiafulvalene (TTF). Further, the material for forming the organic semiconductor is, for example, as a low molecular weight n-type semiconductor, fullerene such as fullerene C60 and fullerene C70 and derivatives thereof, N, N'-dimethyl-3,4,9,10-perylenetetra. Diimide Carboxylic Acid, N, N'-di-n-octyl-3,4,9,10-Perylenetetracarboxylic Acid Diimide, N, N'-Dioctyl-3,4,9,10-Pererenedicarboxydiimide (PTCDI) ) Etc., copper (II) 1,2,3,4,8,9,10,11,15,16,17,18,22,23,24,25-hexadecafluorophthalocyanine, naphthalene-1 , 4,5,8-Tetracarboxylic acid dianhydride and other tetracarboxylic acids, 3,4,9,10-perylene tetracarboxylic acid dianhydride, tetracyanoquinodimethane (TCNQ) and the like. Examples of the material for forming the organic semiconductor include polythiophenes and polyfluorenes as organic semiconductors using polymers.

Since the organic transistor can be formed by a low temperature process, has a wide range of material choices, and has a high degree of freedom in design, it has been widely developed in recent years, and organic EL display devices, communication devices, and the like. It is expected to be applied to lighting and the like.

The organic transistor is generally formed as a thin film element on a transparent substrate. As the transparent substrate, for example, glass, a flexible film, or the like can be used. Examples of the flexible film include polyimide, polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). Since the flexible film is lightweight, bendable, and hard to break, it is expected to have various applications such as the organic EL display device.

The flexible film generally has a large coefficient of thermal expansion and a coefficient of linear expansion, and has a large dimensional variation due to heat as compared with a glass substrate, a Si substrate, or the like. When the organic transistor is formed on the flexible film, it can be formed by a lower temperature process as compared with the case where the inorganic transistor is formed. However, even in the low temperature process, the resist is fired and the substrate is dehydrated. Since heating at around 100 to 180 ° C. is required for processing and the like, a load is applied to the flexible film by heat. Further, for example, when an electrode (for example, a gate electrode in the case of a bottom gate structure) is formed on the flexible film, the flexible film is also loaded by being exposed to an etching solution or a developing solution. In this way, when the thin film element is formed on the flexible film, dimensional variation occurs due to a load on the flexible film or the like, alignment misalignment between electrodes, and resulting variation / variation in transistor characteristics are likely to occur. According to the present invention, the influence of misalignment between the source electrode and the drain electrode can be reduced, and thereby, for example, fluctuations and variations in transistor characteristics can be suppressed. Therefore, for example, a thin film on the flexible film can be suppressed. In element formation, stable transistor characteristics can be obtained even when the dimensions of the substrate fluctuate as described above.

As shown in FIG. 1A, the field effect transistor 1 of the present embodiment has a top contact type laminated structure. The top contact type laminated structure can be produced, for example, by first forming an organic semiconductor layer on the gate insulating film and then forming a source electrode and a drain electrode on the organic semiconductor layer. When the field effect transistor 1 has the top contact type laminated structure, for example, the metal electrode film formed by vapor deposition diffuses into the organic semiconductor layer, so that the contact is made as compared with the bottom contact type laminated structure. The resistance is small, the element characteristics are excellent, and the stability such as reproducibility and reliability is also excellent. The laminated structure of the field effect transistor 1 may be a laminated structure other than the top contact type, such as a bottom gate type and a bottom contact type. When the field effect transistor 1 has a bottom gate type and bottom contact type laminated structure, for example, photolithography and microfabrication technology can be used when forming the source electrode and the drain electrode, so that the short channel of the transistor can be used. Can be converted. In any case, the thickness of each layer is not particularly limited and can be appropriately set according to the forming material and the like.

FIG. 1B is a plan view of the field effect transistor 1 according to the present embodiment. In the plan view below, the portion where the source electrode 14 and the drain electrode 15 face each other is shown by a thick line. As shown in FIG. 1 (B), the field effect transistor 1 of the present embodiment has a substantially arc shape in a portion where the source electrode 14 and the drain electrode 15 face each other when viewed from the upper surface. In the following description, the description of the source electrode 14 and the drain electrode 15 can be the same even when each of them is replaced.

As described above, since the source electrode 14 and the drain electrode 15 are formed so as to have a substantially arc shape in the portions facing each other, for example, the positions of the source electrode 14 and the drain electrode 15 are displaced in the θ direction. Even in this case, fluctuations in the channel length and channel width can be suppressed, so that the influence of misalignment can be reduced.

In the present invention, the vertical direction is the stacking direction of each member with respect to the substrate 10, the substrate 10 side is the downward direction, and the side opposite to the substrate 10 is the upward direction. Further, the upper surface means an upward surface of the field effect transistor.

The direction of the substantially arc is, for example, a direction along a circle centered on the vicinity of the center of the source electrode 14 and the drain electrode 15.

In the present invention, the substantially arcuate shape may be, for example, a perfect arcuate shape, a curved line shape close to an arc shape, a linear shape including a curved line and / or a straight line, and a linear shape close to an arc shape.

Further, in the present invention, it is preferable that at least one of the source electrode 14 and the drain electrode 15 has a substantially arcuate shape when viewed from the upper surface. In the plan view below, the substantially arcuate shape portions of the source electrode 14 and the drain electrode 15 are shown by diagonal lines. In FIG. 1B, the drain electrode 15 includes a substantially arc-shaped portion. By forming in this way, for example, even if the positions of the source electrode 14 and the drain electrode 15 including the substantially arcuate shape are displaced in the θ direction, the outside of the source electrode 14 and the drain electrode 15 (opposing each other). Even on the non-side), since the fluctuation of the area of the overlapping portion between the electrodes 14 and 15 and the gate electrode 11 can be suppressed, the influence of the deviation can be reduced. The source electrode 14 and the drain electrode 15 may both include, for example, a substantially arcuate shape.

In FIG. 1B, the drain electrode 15 is formed larger than the source electrode 14, but the present invention is not limited to this, and for example, the source electrode 14 may be formed larger than the drain electrode 15. However, the source electrode 14 and the drain electrode 15 may have the same size.

As shown in FIG. 1B, it is preferable that one of the source electrode 14 and the drain electrode 15 has a convex substantially arc shape and the other has a concave substantially arc shape in the portions facing each other. .. However, the present invention is not limited to this, and for example, in the portions facing each other, one has a convex substantially arc shape and the other has a linear or convex shape other than the substantially arc shape such as a straight line. In the portions facing each other, one is a concave substantially arc shape and the other is a linear shape other than the substantially arc shape such as a straight line, or a concave substantially arc shape. There may be.

Further, in the present embodiment, one of the source electrode 14 and the drain electrode 15 is formed so as to surround the other, as shown in FIG. 1 (B). By forming in this way, for example, even when the positions of the source electrode 14 and the drain electrode 15 deviate not only in the θ direction but also in the xy direction, the influence of the misalignment can be reduced.

Further, in FIG. 1B, the source electrode 14 and the drain electrode 15 have a substantially arcuate shape in all of the portions facing each other, but the present invention is not limited to this, and the drain electrode 15 and the drain electrode 15 and the drain electrode 15 and the drain electrode 15 are not limited to this. The source electrodes 14 may have a substantially arcuate shape in a part of the portions facing each other, and the portion other than the portion may have a linear shape other than the substantially arcuate shape such as a straight line. In this case, among the portions of the electrodes facing each other, for example, the portion along the circle centered near the center of the source electrode 14 and the drain electrode 15 is preferably substantially arcuate.

In the source electrode 14 and the drain electrode 15, the position where the take-out wiring portion is provided is not particularly limited and can be provided at any position. The take-out wiring portion can be at an arbitrary position, for example, when the source electrode 14 and the drain electrode 15 include a substantially arcuate shape, the source electrode 14 and the drain electrode 15 are connected to the substantially arcuate shape.

The take-out wiring portion may be installed three-dimensionally, for example, and in this case, for example, a contact hole can be formed in the source electrode 14 and / or the drain electrode 15 and wired. By forming in this way, for example, even when the alignment between the electrodes is misaligned, the drain electrode, the source electrode, and the gate electrode can be compared with the case where the take-out wiring portion is two-dimensionally wired. Since the fluctuation of the area of the overlapping portion can be suppressed, the influence of the deviation can be reduced.

In the present embodiment, as shown in FIG. 1A, the gate insulating film 12 is formed on the gate electrode 11 up to the end of the gate electrode 11. As shown in FIG. 1B, the gate electrode 11 preferably has, for example, a size of the installation surface of the gate electrode 11 larger than the installation surface of the source electrode 14 and the drain electrode 15 when viewed from the upper surface. In the present invention, the "installation surface of the source electrode and the drain electrode" refers to the installation surface of the portion of the source electrode and the drain electrode excluding the wiring portion. By forming in this way, for example, even when the alignment between the electrodes is misaligned, the fluctuation of the area of the overlapping portion between the drain electrode and the source electrode and the gate electrode on the installation surface can be suppressed. The effect of misalignment can be reduced.

When the semiconductor layer 13 is an organic semiconductor layer, the semiconductor layer 13 is preferably formed smaller than the installation surface of the gate electrode 11 as shown in FIGS. 1A and 1B, for example. .. In organic semiconductors, carriers are injected from the entire surface of the electrode, unlike the pn junction of silicon-based semiconductors. Therefore, if the region of the organic semiconductor layer is large, the number of paths through which the off-leakage current flows increases, and the on-off ratio (rectification ratio) becomes small. Therefore, the off-leakage can be reduced by forming the semiconductor layer 13 in an island shape instead of a solid film, for example, smaller than the installation surface of the gate electrode 11 and specifically, for example, on the substrate 10. can.

The source electrode 14 and the drain electrode 15 are preferably installed within the range of the installation surface of the semiconductor layer 13 when viewed from the upper surface. By forming in this way, for example, the semiconductor layer 13 is located in the region where the gate electrode 11, the source electrode 14, and the drain electrode 15 overlap, so that the gate electrode 11, the source electrode 14, and the drain electrode 15 are combined. Fluctuations in parasitic capacitance can be suppressed. Further, for example, since the fluctuation of the channel length and the channel width can be reduced, the fluctuation of the on-resistance and the on-current can be reduced, and the transistor characteristics can be stabilized.

(Modification example)
FIG. 2 is a plan view of the field effect transistor 1 in the modified example of the present embodiment. In this example, the source electrode 14 and the drain electrode 15 are each formed so as to surround each other. Both the source electrode 14 and the drain electrode 15 include a substantially arcuate shape (hatched portion). Except for the above points, it is the same as that of the first embodiment.

Even when the source electrode 14 and the drain electrode 15 have such a configuration, it is possible to reduce the influence of misalignment of the source electrode 14 and the drain electrode 15, for example, as in the first embodiment. For example, even when the positions of the source electrode 14 and the drain electrode 15 deviate not only in the θ direction but also in the xy direction, the influence of the misalignment can be reduced. Further, since both the source electrode 14 and the drain electrode 15 include a substantially arcuate shape, for example, the influence of misalignment can be reduced and the channel width can be increased.

(Embodiment 2)
FIG. 3 is a plan view of the field effect transistor 1 in this embodiment. In this example, the drain electrode 15 is formed so as to surround the source electrode 14, and the source electrode 14 has an island shape in a portion surrounded by the drain electrode 15. Except for the above points, it is the same as that of the first embodiment.

In the present invention, the island shape means a shape in which the portion is larger like an island as compared with other portions. The island shape is, for example, a circular shape, a substantially circular shape, a polygonal shape such as a quadrangle, or the like.

As described above, since the source electrode 14 has an island shape in the portion surrounded by the drain electrode 15, the fluctuation of the distance between the electrodes can be further suppressed, so that the source electrode 14 and the source electrode 14 and the source electrode 14 can be further suppressed. The influence of the misalignment of the drain electrode 15 can be further reduced.

(Embodiment 3)
FIG. 4 is a plan view of the field effect transistor 1 in this embodiment. FIG. 4A is an example of the field effect transistor in the present embodiment, in which the source electrode 14 has an island shape and the drain electrode 15 is formed so as to surround the island shape of the source electrode 14. Further, the source electrode 14 includes one annular structure when viewed from the upper surface, and the drain electrode 15 includes two annular structures when viewed from the upper surface (hatched portion). Except for the above points, it is the same as that of the above embodiment.

FIG. 4B is another example of the field effect transistor 1 in the present embodiment, in which the drain electrode 15 has an island shape and the source electrode 14 is formed so as to surround the island shape of the drain electrode 15. ing. Further, the source electrode 14 includes two annular structures when viewed from the upper surface, and the drain electrode 15 includes one annular structure when viewed from the upper surface (hatched portion). The drain electrode 15 is three-dimensionally wired by forming a contact hole. Except for the above points, it is the same as that of the above embodiment.

In the present invention, as shown in FIGS. 4A and 4B, the annular structure is, for example, a substantially arcuate shape, and the substantially arcuate shape of one electrode is larger than the other. It is in a state of surrounding. In the present invention, the annular structure may or may not be a closed annular structure.

The number of the annular structures contained in the source electrode 14 and the drain electrode 15 is not particularly limited, and is, for example, 1 to 50, 1 to 10, and 1 to 5, respectively. The number of the annular structures contained in the source electrode 14 and the drain electrode 15 may be the same or different, for example, respectively. Further, for example, both the source electrode 14 and the drain electrode 15 may include the annular structure, or one may include the annular structure and the other may not include the annular structure.

As described above, since the source electrode 14 and the drain electrode 15 are configured to include the annular structure, for example, even when the positions of the source electrode 14 and the drain electrode 15 are displaced not only in the θ direction but also in the xy direction. The effect of misalignment can be reduced.

The annular structure included in the source electrode 14 and the drain electrode 15 preferably has a configuration in which the annular structures alternately surround each other, for example, as shown in FIGS. 4A and 4B. With the above configuration, for example, the influence of misalignment can be reduced, and the channel width can be increased.

(Embodiment 4)
FIG. 5 is a schematic view (cross-sectional view) of the field effect transistor 1 according to the present embodiment as viewed from the side. As shown in FIG. 5, in the field effect transistor 1 of the present embodiment, the gate electrode 11, the gate insulating film 12, and the semiconductor layer 13 are laminated in the above order on the substrate 10, and the source electrode 14 and the drain are laminated. The electrodes 15 are formed in contact with the upper surface and the lower surface of the semiconductor layer 13, respectively, in the vertical direction. That is, in the present embodiment, the source electrode 14 and the drain electrode 15 are provided in different layers in the vertical direction. Except for the above points, it is the same as that of the above embodiment.

In this way, when the source electrode 14 and the drain electrode 15 are provided in different layers, each electrode can be formed in the vertical direction, so that, for example, the channel can be easily shortened.

Also in the present embodiment, similarly to the above-described embodiment in which the source electrode 14 and the drain electrode 15 are provided on the same layer, the field effect transistor 1 is formed in a portion where the source electrode 14 and the drain electrode 15 face each other when viewed from the upper surface. , It has a substantially arc shape. Therefore, even in the present embodiment in which the source electrode 14 and the drain electrode 15 are provided in different layers, the influence of the misalignment can be reduced as in the above embodiment.

(Embodiment 5)
The electronic device of the present invention is characterized by including the field effect transistor of the present invention. The application of the electronic device of the present invention is not particularly limited, and for example, a motor control device (for example, for an electric vehicle, an air conditioner, etc.), a power supply device (for example, for a computer, etc.), an inverter lighting, a high-frequency power generator (for example, for a microwave oven). , For electromagnetic cookers, etc.), image display devices, information recording / playback devices, communication devices, etc. can be widely used. According to the field-effect transistor of the present invention, the influence of misalignment can be reduced, so that variations in the characteristics of these electronic devices (electronic devices) can be suppressed, for example, for organic EL displays. Brightness variation can be suppressed.

Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the structure and details of the present invention within the scope of the present invention.

According to the present invention, it is possible to reduce the influence of misalignment in the field effect transistor. Therefore, for example, by using the field effect transistor of the present invention in an image display device, a communication device, lighting, or the like, it is possible to suppress variations in the characteristics of these electronic devices (electronic devices), for example.

1 Field effect transistor 10 Substrate 11 Gate electrode 12 Gate insulating film 13 Semiconductor layer 14 Source electrode 15 Drain electrode

Claims (7)

A substrate, a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, and a drain electrode are included.
The gate electrode, the gate insulating film, and the semiconductor layer are laminated on the substrate in this order.
The source electrode and the drain electrode are in contact with the semiconductor layer, and the source electrode and the drain electrode are in contact with the semiconductor layer.
The source electrode and the drain electrode include an annular structure when viewed from above.
At least one of the source electrode and the drain electrode includes the plurality of said annular structures.
The annular structure of the source electrode and the drain electrode is formed so as to alternately surround each other .
A field-effect transistor characterized in that the source electrode and the drain electrode are formed in different layers in the vertical direction. At least one of the source electrode and the drain electrode includes an island shape when viewed from above, and the annular structure of the source electrode and the other electrode of the drain electrode is formed so as to surround the island shape. The field effect transistor according to claim 1. 1 Or the field effect transistor according to 2. The field effect transistor according to any one of claims 1 to 3 , wherein the installation surface of the gate electrode is larger than the installation surface of the drain electrode and the source electrode when viewed from the upper surface. The field effect transistor according to any one of claims 1 to 4 , wherein the semiconductor layer is smaller than the installation surface of the gate electrode when viewed from the upper surface. The field effect transistor according to any one of claims 1 to 5 , wherein the semiconductor layer is an organic semiconductor layer. An electronic device comprising the field effect transistor according to any one of claims 1 to 6.

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