CN111665669A - Display panel - Google Patents

Abstract

The present invention discloses a display panel, which comprises scan lines and data lines staggeredly arranged on a substrate, an active layer arranged on the substrate and located between the data lines and the substrate, and a transparent conductive layer arranged on the substrate and located above the active layer, wherein the active layer comprises a first contact hole area electrically connected to the data lines, a second contact hole area electrically connected to the transparent conductive layer, and an intermediate connection area located between the first contact hole area and the second contact hole area, the portion where the intermediate connection area overlaps with the scan lines is a channel area, the portion where the intermediate connection area does not overlap with the scan lines is a non-channel area, and the width of the non-channel area is greater than the width of the channel area.

Description

display panel

This application is a divisional application of a Chinese invention patent application (application number: 201510008774.3, application date: January 8, 2015, invention name: display panel).

technical field

The present invention relates to display panel technology, in particular to active layer pattern design of a display panel using low temperature polysilicon to fabricate the active layer of thin film transistors.

Background technique

In recent years, liquid crystal displays have become the most important flat-panel displays due to their advantages of thinning, light weight, low power consumption and low radiation, and are widely used in various electronic devices. In an active matrix liquid crystal display, a thin-film transistor (TFT) is used as a driving component to control pixel switching. According to the active layer material of the thin-film transistor, thin-film transistors can be divided into two categories: one is amorphous silicon. Thin film transistor, another type is polysilicon thin film transistor.

In the previous technology, the manufacture of polysilicon thin film transistors required the use of high temperatures above 1000 degrees, causing the amorphous silicon layer to melt and recrystallize into polysilicon layers. However, with the development of laser technology, it is currently possible to use lower than 600 degrees. The process temperature forms the polysilicon layer, and this fabrication technique is called low-temperature polysilicon (LTPS) thin-film transistor technology.

Compared with amorphous silicon thin film transistors, low temperature polysilicon thin film transistors have faster carrier mobility. Therefore, liquid crystal displays manufactured using low temperature polysilicon thin film transistors have the advantages of high performance and short response time.

However, for a liquid crystal display made of low temperature polysilicon, the low temperature polysilicon forming the active layer of the thin film transistor still has many areas for improvement, so that the liquid crystal display can achieve better display quality.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a display panel that improves the low temperature polysilicon active layer of the thin film transistor, and uses the pattern width design of the low temperature polysilicon active layer to reduce the overall resistance of the low temperature polysilicon active layer, thereby improving the thin film The electrical characteristics of the transistors further improve the image display quality of the display panel.

In order to achieve the above purpose, in some embodiments of the present invention, a display panel is provided, which includes: a first substrate; scan lines and data lines are alternately arranged on the first substrate; an active layer is arranged on the first substrate, and the active layer is The layer is located between the data line and the first substrate; and the first transparent conductive layer is disposed on the first substrate, and the first transparent conductive layer is located above the active layer, wherein the active layer includes: a first contact area and a data line electrically connected, the second contact hole area is electrically connected to the first transparent conductive layer, and the intermediate connection area is located between the first contact hole area and the second contact hole area, and the intermediate connection area and the scan line overlap include a first channel area, The non-channel area is where the intermediate connection area and the scan line do not overlap, and the width of the non-channel area is greater than the width of the first channel area.

Description of drawings

FIG. 1 is a partial plan view of a display panel according to some embodiments of the present invention;

2 is a partial cross-sectional schematic diagram of a display panel along section line 2-2' of FIG. 1 according to some embodiments of the present invention;

3 is a schematic partial plan view of a display panel according to other embodiments of the present invention;

4 is a partial cross-sectional schematic diagram of a display panel along section line 4-4' of FIG. 3 according to some embodiments of the present invention;

5 is a schematic partial plan view of a display panel according to some other embodiments of the present invention;

FIG. 6 is a partial plan view of a display panel according to some other embodiments of the present invention.

Symbol Description

100～display panel;

101 to the first substrate;

102 to the second substrate;

1301 ~ the first contact hole area;

1302 ~ the second contact hole area;

1303~Intermediate connection area;

1303-L1, 1303-L2 ~ the side of the intermediate connection area;

1304 ~ the first non-channel area;

1305～Second non-channel area;

1306 ~ the third non-channel area;

1307～protrusion;

1308 ~ first passage area;

1309～Second passage area;

1311 ~ District 1;

1312～Second District;

110～the first transparent conductive layer;

113～the slit of the first transparent conductive layer;

115, 117, 119 ~ via holes;

117-1, 119-1 ~ bottom edge;

117-2, 119-2 ~ top edge;

120～the second transparent conductive layer;

122 to the slit of the second transparent conductive layer;

125 to the opening of the second transparent conductive layer;

126～the first insulating layer;

128～Second insulating layer;

132 to the third insulating layer;

134 to the fourth insulating layer;

130～active layer;

136～display medium layer;

140～scan lines;

150～data line;

152 ~ drain electrode;

W1～the width of the first channel area;

W2～the width of the second channel area;

W3～the width of the third non-channel area;

W4 ~ the width of the first area;

W5 ~ the width of the second area;

W6～the width of the first non-channel area;

W7～the width of the second non-channel area;

W8～the width of the first contact hole area;

W9～the width of the second contact hole area.

Detailed ways

1 shows a partial plan view of a display panel 100 according to some embodiments of the present invention. The display panel 100 includes a plurality of scan lines 140 and a plurality of data lines 150 disposed on a first substrate (not shown in FIG. 1 ) in a staggered manner. to define multiple pixel regions. In this embodiment, the sub-pixel area is an area surrounded by adjacent data lines and adjacent scan lines. A thin film transistor is disposed adjacent to the intersection of the scan line 140 and the data line 150 , and the thin film transistor is used to control the sub-pixel region and a switch element electrically connected to the data line. According to an embodiment of the present invention, the thin film transistor includes an active layer 130 made of low temperature polysilicon. The active layer 130 includes a first contact hole region 1301, a second contact hole region 1302, and the first contact hole region 1301 and the second contact hole region 1302. The intermediate connection region 1303 between the two contact hole regions 1302 . Two channel regions are generated where the intermediate connection region 1303 of the active layer 130 overlaps with the scan line 140 , namely the first channel region 1308 and the second channel region 1309 , while the intermediate connection region 1303 of the active layer 130 is not connected to the scan line 140 . The overlapping area is the non-channel area, as indicated in FIG. 1 , the first non-channel area 1304 located on the upper side of the scan line 140 and close to the data line, the second non-channel area 1305 located on the upper side of the scan line and farther from the data line, and the scan line Third non-channel region 1306 on the underside of line 140 .

In addition, as shown in FIG. 1 , in some embodiments, the display panel 100 further includes a second transparent conductive layer 120 serving as an upper transparent conductive layer. In this embodiment, the second transparent conductive layer 120 serves as a shared electrode, and the second transparent conductive layer 120 The transparent conductive layer 120 has a plurality of slits 122 formed therein, and the second transparent conductive layer 120 covers the scan lines 140 , the data lines 150 and the active layer 130 . In some embodiments, the second transparent conductive layer 120 covers the vias 115 located in the first contact hole region 1301 of the active layer 130 and the vias 115 located in the second contact hole region 1302 of the active layer 130 Vias 117 and 119. In other embodiments, the second transparent conductive layer 120 may have an opening (not shown in FIG. 1 ), and the opening is adjacent to the formation position of the via holes 117 and 119 , that is, the second transparent conductive layer The opening of 120 is adjacent to the second contact hole region 1302 and allows the second transparent conductive layer 120 to avoid without covering the via holes 117 and 119 . In this embodiment, the data lines 150 are in the form of non-linear wiring, but the data lines 150 generally have a substantial extension direction; in other embodiments, the data lines 150 may be in the form of straight wiring. In this embodiment, the scan lines 140 are in the form of linear wiring; in other embodiments, the scan lines 140 may be in the form of non-linear wiring, but the scan lines 140 generally have a substantial extension direction.

As shown in FIG. 1 , the first channel region 1308 has a first width W1 , the second channel region 1309 has a second width W2 , and the directions of the first width W1 and the second width W2 are substantially parallel to the extending direction of the scan line 140 . . The portion of the intermediate connecting region 1303 between the first channel region 1308 and the second channel region 1309 , that is, the third non-channel region 1306 has a third width W3 which is the first side 1303 of the intermediate connecting region 1303 - Vertical distance between L1 and second side 1303-L2. The first side 1303-L1 refers to the inner side of the middle connection region 1303 of the active layer 130, and the second side 1303-L2 refers to the outer side of the middle connection region 1303 of the active layer.

According to an embodiment of the present invention, the third width W3 of the third non-channel region 1306 is larger than the first width W1 of the first channel region 1308 , and the third width W3 of the third non-channel region 1306 is also larger than that of the second channel region 1309 . The second width W2. In addition, according to the embodiment of the present invention, the widths of the first non-channel region 1304 and the second non-channel region 1305 where the intermediate connection region 1303 does not overlap the scan line 140 are greater than the first width W1 of the first channel region 1308 , and the first The widths of the non-channel region 1304 and the second non-channel region 1305 are also larger than the second width W2 of the second channel region 1309 . In the embodiment of the present invention, the width of each part of the middle connecting region 1303 is defined as the vertical distance between the two sides 1303-L1 and 1303-L2 of the middle connecting region 1303, so the width of some parts of the middle connecting region 1303 The direction of the width may not be parallel to the extending direction of the scan line 140 .

In order to meet the functional requirements of the thin film transistor as a pixel switch component, the aspect ratio of the first channel region 1308 and the aspect ratio of the second channel region 1309 generated at the overlap between the active layer 130 of the thin film transistor and the scan line 140 need to be maintained. Within a certain ratio range, the first width W1 of the first channel region 1308 and the second width W2 of the second channel region 1309 must meet the design requirements of the resolution of the display panel for the channel aspect ratio of the thin film transistor. In the known display panel manufacturing technology, the active layer of the thin film transistor has a uniform width except for the part of the contact hole area. Usually, the width of the active layer is made with a width that meets the aspect ratio of the channel area. However, the resistance of the active layer fabricated in this way cannot be reduced, resulting in the inability to improve the performance of the thin film transistor.

According to an embodiment of the present invention, the widths of the first non-channel region 1304 , the second non-channel region 1305 and the third non-channel region 1306 of the active layer 130 are larger than the width of the first channel region 1308 and also larger than the width of the second channel region 1309 , so that the pattern of the active layer 130 has a width variation in which the non-channel region is wider and the channel region is narrower. Through the larger width of the first non-channel region 1304, the second non-channel region 1305 and the third non-channel region 1306, the overall resistance of the active layer 130 made of low temperature polysilicon can be reduced. At the same time, the first channel region 1308 And the width of the second channel region 1309 also conforms to the length-width ratio requirement of the channel region of the thin film transistor. Therefore, the embodiments of the present invention can improve the electrical performance of the thin film transistor.

In some embodiments, as shown in FIG. 1 , the third non-channel region 1306 of the intermediate connection region 1303 between the first channel region 1308 and the second channel region 1309 has two protrusions 1307 , the two protrusions 1307 They protrude out of the first channel region 1308 and the second channel region 1309 in a direction parallel to the scan line 140 , respectively. In addition, in some embodiments, the width W1 of the first channel region 1308 and the width W2 of the second channel region 1309 may be approximately the same. In some other embodiments, the width W1 of the first channel region 1308 may be different from the width W2 of the second channel region 1309 . In addition, as shown in FIG. 1 , in some embodiments, the data line 150 may be a data line having a meandering curve, and the first contact hole region 1301 and the second contact hole region 1302 of the active layer 130 are away from the scan line 140 The distance is not much different, forming the active layer 130 with a shorter length of the intermediate connection region 1303 .

FIG. 2 shows a schematic partial cross-sectional view of the display panel 100 along the section line 2-2' of FIG. 1 according to some embodiments of the present invention. As shown in FIG. 2 , the display panel 100 includes a first substrate 101 , the scan lines 140 and the data lines 150 are disposed on the first substrate 101 , the active layer 130 is disposed on the first substrate 101 , and the active layer 130 is located on the data lines 150 and the scan lines 140 , while the active layer 130 is located between the data lines 150 and the first substrate 101 . In some embodiments, the thin film transistor of the display panel 100 may have a top-gate structure. As shown in FIG. 2 , the channel region generated by the overlapping of the scan line (gate) 140 and the active layer 130 is located in the active layer. above the source layer 130 . In other embodiments, the thin film transistor of the display panel 100 may be a bottom-gate structure, and the channel region generated where the scan line (gate) overlaps with the active layer is located below the active layer.

Referring to FIGS. 1 and 2 , a via hole 115 is formed above the first contact hole region 1301 of the active layer 130 , and the first contact hole region 1301 of the active layer 130 is connected to the data line through the via hole 115 150 electrical connections. In addition, as shown in FIG. 2 , the display panel 100 further includes a first transparent conductive layer 110 , via holes 117 and 119 are formed above the second contact hole region 1302 of the active layer 130 , and the second contact hole of the active layer 130 is formed with via holes 117 and 119 . The hole region 1302 is electrically connected to the first transparent conductive layer 110 via the via holes 117 and 119 . The via hole 115 is a hole formed in the first insulating layer 126 and the second insulating layer 128 above the first contact hole region 1301 of the active layer 130, and the metal material forming the data line 150 is filled in the via hole 115, The data line 150 can be electrically connected to the first contact hole region 1301 of the active layer 130 via the via hole 115, and a part of the data line 150 forms a source electrode of the thin film transistor. In addition, the via hole 117 is a hole formed in the first insulating layer 126 and the second insulating layer 128 above the second contact hole region 1302 of the active layer 130 , forming the metal of the drain electrode 152 of the thin film transistor. The material may be connected to the active layer 130 via the vias 117 . In addition, the via hole 119 is a hole formed in the third insulating layer 132 above the second insulating layer 128 , and the material for forming the first transparent conductive layer 110 is filled in the via hole 119 , so that the first transparent conductive layer 110 It can be electrically connected to the drain electrode 152 of the thin film transistor via the via hole 119 , and then electrically connected to the second contact hole region 1302 of the active layer 130 via the via hole 117 . The first insulating layer 126 and the second insulating layer 128 may be the same or different inorganic materials, such as SiO _x or SiN _x .

As shown in FIG. 2 , a first insulating layer 126 is formed between the active layer 130 and the double gate formed by the scan line 140 , and a second insulating layer 128 and a third insulating layer 132 are formed above the scan line 140 . The vias 115 and 117 are formed in the first insulating layer 126 and the second insulating layer 128, and the via 119 is formed in the third insulating layer 132. In some embodiments, a portion of the first transparent conductive layer 110 may be Compliantly formed in the via hole 119 of the third insulating layer 132, and the metal material forming the source electrode of the thin film transistor can be conformally formed in the via hole 115, and forming the drain electrode 152 of the thin film transistor. A metal material may also be conformably formed in the via hole 117 . The third insulating layer 132 can be an organic material, which can be used for planarization, for example, an organic material (eg, polyfluoroalkoxy, PFA) or a color filter material.

The display panel 100 further includes a second substrate 102 , and a display medium layer 136 is disposed between the second substrate 102 and the first substrate 101 . In some embodiments, the display medium layer 136 may be a liquid crystal layer, the second substrate 102 may be a color filter (CF) substrate, and the first substrate 101 may be a thin film transistor array (Array) substrate. In other embodiments, the color filter layer may be disposed on the first substrate 101 , for example, the third insulating layer 132 may be replaced by a color filter layer material.

In some embodiments, as shown in FIG. 1 and FIG. 2 , the display panel 100 further includes a second transparent conductive layer 120 located above the first transparent conductive layer 110 , and between the first transparent conductive layer 110 and the second transparent conductive layer 120 There is a fourth insulating layer 134 therebetween, the first transparent conductive layer 110 is electrically insulated from the second transparent conductive layer 120 by the fourth insulating layer 134, and the fourth insulating layer 134 can be an inorganic material, such as silicon oxide _SiOx or nitride Silicon _SiNx . In some embodiments, the second transparent conductive layer 120 is a patterned electrode including a plurality of slits 122 , and the display panel 100 is configured by the slits 122 of the second transparent conductive layer 120 and the first transparent conductive layer 110 A wide viewing angle liquid crystal display panel with Fringe Field Switching (FFS). In this embodiment, the slit 122 does not extend beyond the sub-pixel area; in other embodiments, the slit 122 may extend beyond the sub-pixel area, such as spanning the data line 150 or the scan line 140 .

3 is a schematic partial plan view of the display panel 100 according to other embodiments of the present invention. Two channel regions are generated where the intermediate connection region 1303 of the active layer 130 and the scan line 140 overlap, which are the first channel region 1308 and the second channel region 1308 respectively. In the two channel regions 1309 , where the intermediate connection region 1303 of the active layer 130 and the scan line 140 do not overlap are the first non-channel region 1304 , the second non-channel region 1305 and the third non-channel region 1306 . According to an embodiment of the present invention, the widths of the first non-channel region 1304 , the second non-channel region 1305 and the third non-channel region 1306 are larger than the widths of the first channel region 1308 and the second channel region 1309 , so that the width of the active layer 130 is The pattern has a width variation in which the non-channel region is wider and the channel region is narrower, thereby achieving the effect of reducing the resistance of the active layer.

As shown in FIG. 3 , in some embodiments, the first contact hole region 1301 of the active layer 130 is farther away from the scan line 140 than the second contact hole region 1302 , so that the distance between the first contact hole region 1301 and the scan line 140 is The first non-channel region 1304 in between has a longer length. Because the length of the first non-channel area 1304 is longer than that of the third non-channel area 1306, the first contact hole area 1301 and the second contact hole area 1302 can be staggered, because the contact hole area requires a larger area ( The alignment error in the manufacturing process is retained), so the staggering can make the two contact hole regions closer in the direction of the parallel scan line 140 , which can reduce the width of a single sub-pixel in the direction of the parallel scan line 140 . However, because the length of the first non-channel area 1304 is relatively long, maintaining a fixed width may reduce the number of sub-pixels that can be set, thereby limiting the resolution design requirements of the display panel. Therefore, the first non-channel area 1304 has different widths. (But still wider than the channel area), it can not only maintain the resistance value, but also reduce the impact on the aperture ratio.

In some embodiments, as shown in FIG. 3 , the data line 150 may be a data line having a straight curve, and the middle connection region 1303 of the active layer 130 partially overlaps the data line 150 such that the middle connection region 1303 and the data line 150 are partially overlapped. The non-overlapping portion has a first area 1311 and a second area 1312 located on both sides of the data line 150 respectively, wherein the second area 1312 is located between the data line 150 and the second contact hole area 1302, and the first area 1311 is located at the data line 150. Line 150 is on the opposite side of second region 1312 . The first region 1311 has a width W4 , the second region 1312 has a width W5 , and the directions of the width W4 and the width W5 are substantially parallel to the substantially extending direction of the scan line 140 . In some embodiments, the width W4 of the first region 1311 is approximately equal to the width W5 of the second region 1312 . In other embodiments, the width W4 of the first region 1311 may be greater than the width W5 of the second region 1312 . In some other embodiments, the width W4 of the first region 1311 may be smaller than the width W5 of the second region 1312 .

Compared with the example in which the active layer and the data line completely overlap, in some embodiments of the present invention, the intermediate connection region 1303 of the active layer 130 partially overlaps the data line 150, which can reduce the distance between the active layer 130 and the data line 150. The parasitic capacitance generated between them. In addition, compared to the case where the active layer and the data line are completely staggered, in some embodiments of the present invention, the intermediate connection region 1303 of the active layer 130 and the data line 150 are partially overlapped, which can increase the aperture ratio of the display panel.

In addition, in some embodiments, as shown in FIG. 3 , the first non-channel region 1304 of the intermediate connection region 1303 of the active layer 130 has a width W6 adjacent to the first contact hole region 1301 , and the second non-channel region 1303 of the intermediate connection region 1303 has a width W6 . The non-channel region 1305 has a width W7 adjacent to the second contact hole region 1302, and the width W6 is greater than the width W7. In addition, in some embodiments, the first contact hole region 1301 has a width W8, and the second contact hole region 1302 has a width W9, and the width W9 is greater than the width W8. In some embodiments, the directions of the widths W4 - W9 are substantially parallel to the substantially extending direction of the scan lines 140 .

4 is a schematic partial cross-sectional view of the display panel 100 along the section line 4-4' of FIG. 3 according to some embodiments of the present invention. As shown in FIG. 4 , in some embodiments, the first transparent conductive layer 110 electrically connected to the second contact hole region 1302 of the active layer 130 is a patterned electrode including a plurality of slits 113 , and the second transparent conductive layer 120 is located under the first transparent conductive layer 110, and the second transparent conductive layer 120 has an opening 125 adjacent to the second contact hole area 1302. The setting of the opening 125 can prevent the second transparent conductive layer 120 from covering the via hole 119. Further, the position of the via hole 119 is avoided. In this embodiment, through the arrangement of the slits 113 of the first transparent conductive layer 110 and the second transparent conductive layer 120 , the display panel 100 becomes a boundary field switching (FFS) liquid crystal display panel.

FIG. 5 is a partial plan view of the display panel 100 according to other embodiments of the present invention. As shown in FIG. 5 , in some embodiments, the first contact hole region 1301 of the active layer 130 is far away from the scan line 140 , so that the The first non-channel region 1304 of the intermediate connection region 1303 between the first contact hole region 1301 and the second contact hole region 1302 has a longer length. In addition, in the embodiment shown in FIG. 5 , the data lines 150 may be in the form of wirings with bent curves, and the data lines 150 generally have a substantial extension direction, so that the middle connection region 1303 of the active layer 130 and the data lines 150 are connected. Partially overlapping, the intermediate connection area 1303 may include two areas located on both sides of the data line 150, respectively. In this embodiment, the area of the intermediate connection area 1303 located on the left side of the data line 150 is compared with the intermediate connection area 1303 located on the data line 150. The area on the right has a larger width. In addition, as shown in FIG. 5 , the via hole 117 located in the second contact hole region 1302 of the active layer 130 has a bottom edge (or lower edge of the via hole) 117-1 and a top edge (or called the upper edge of the via hole) 117-1 117-2, wherein the area surrounded by the bottom edge 117-1 is smaller than the area surrounded by the top edge 117-2, so in the plan view shown in FIG. 5, the via hole 117 has two annular boundaries. The via hole 115 and the via hole 119 also have a top edge and a bottom edge, and only the top edge of the via hole is shown in FIG. 1 , FIG. 3 , and FIG. 5 .

In the embodiment of FIG. 5 , the widths of the first non-channel region 1304 , the second non-channel region 1305 and the third non-channel region 1306 generated by the non-overlapping of the intermediate connection region 1303 of the active layer 130 with the scan line 140 are greater than the widths of the middle The widths of the first channel region 1308 and the second channel region 1309 generated by the overlapping of the connection region 1303 and the scan line 140 make the pattern of the active layer 130 have a width variation in which the non-channel region is wider and the channel region is narrower. To achieve the effect of reducing the resistance and parasitic capacitance of the active layer.

In addition, the first transparent conductive layer and the second transparent conductive layer of the display panel 100 are not shown in FIG. 5 . In some embodiments, the display panel 100 of FIG. 5 may use the slit 122 as shown in FIG. 1 . The patterned electrodes of the second transparent conductive layer 120 are used to form a boundary electric field switching (FFS) liquid crystal display panel. In other embodiments, the display panel 100 of FIG. 5 can also use the patterned electrodes of the first transparent conductive layer 110 including the slits 113 as shown in FIG. 3 to form a boundary electric field switching (FFS) liquid crystal display panel .

FIG. 6 is a partial plan view of the display panel 100 according to other embodiments of the present invention. As shown in FIG. 6 , in some embodiments, the first contact hole region 1301 of the active layer 130 is close to the scan line 140 , so that the The first non-channel region 1304 and the second non-channel region 1305 between a contact hole region 1301 and the second contact hole region 1302 have shorter lengths, but the length of the first non-channel region 1304 is greater than the length of the second non-channel region 1305 , so the positions of the first contact hole area 1301 and the second contact hole area 1302 can be staggered to reduce the impact on the resolution. This is because the contact hole area needs to occupy a large area. If the two contact hole areas are arranged side by side, it may A larger sub-pixel width (parallel to the substantial extension direction of the scan line) is required to accommodate the first contact hole area 1301 and the second contact hole area 1302, which will limit the number of sub-pixels, thereby affecting the display panel for higher Resolution design requirements. In this embodiment, the middle connection region 1303 of the active layer 130 has a width W6 adjacent to the first contact hole region 1301 , and the middle connection region 1303 adjacent to the second contact hole region 1302 has a width W7 , and the width W6 is greater than the width W7 . In addition, the scan lines 140 and the data lines 150 may be linear wiring patterns. In other embodiments, the scan lines 140 and the data lines 150 may not be straight lines, but the scan lines 140 and the data lines 150 generally respectively have a substantial extension direction.

In addition, as shown in FIG. 6 , the via hole 117 located in the second contact hole region 1302 of the active layer 130 has a bottom edge (or lower edge of the via hole) 117-1 and a top edge (or called the upper edge of the via hole) 117-1 117-2, wherein the area surrounded by the bottom edge 117-1 is smaller than the area surrounded by the top edge 117-2, and the via hole 119 located in the second contact hole region 1302 of the active layer 130 also has a bottom edge (or called The lower edge of the through hole) 119-1 and the top edge (or the upper edge of the through hole) 119-2, wherein the area surrounded by the bottom edge 119-1 is smaller than the area surrounded by the top edge 119-2, so as shown in FIG. 6 In the plan view of , the via hole 117 and the via hole 119 respectively have two annular boundaries. In other embodiments, the via holes may be non-circular, such as oval or irregular.

In the embodiment shown in FIG. 6 , the widths of the first non-channel region 1304 , the second non-channel region 1305 and the third non-channel region 1306 generated by the non-overlapping of the middle connection region 1303 of the active layer 130 and the scan line 140 are greater than the widths of the middle The widths of the first channel region 1308 and the second channel region 1309 generated by the overlapping of the connection region 1303 and the scan line 140 make the pattern of the active layer 130 have a width variation in which the non-channel region is wider and the channel region is narrower. To achieve the effect of reducing the resistance and parasitic capacitance of the active layer.

In addition, the first transparent conductive layer and the second transparent conductive layer of the display panel 100 are not shown in FIG. 6 . In some embodiments, the display panel 100 of FIG. 6 may adopt the slit 122 as shown in FIG. 1 . The patterned electrodes of the second transparent conductive layer 120; in other embodiments, the slits 122 of the second transparent conductive layer 120 of the display panel 100 of FIG. design requirements. In other embodiments, the display panel 100 of FIG. 6 can also use the patterned electrodes of the first transparent conductive layer 110 including the slits 113 as shown in FIG. 3 to form a boundary electric field switching (FFS) liquid crystal display panel .

In summary, according to some embodiments of the present invention, the pattern of the active layer of the thin film transistor of the display panel is improved, especially for the active layer made of low temperature polysilicon, the first contact hole of the active layer is improved. The width of the non-channel region generated by the non-overlapping of the intermediate connection region and the scan line between the region and the second contact hole region is greater than the width of the channel region generated by the overlap of the intermediate connection region and the scan line, so that the pattern of the active layer has a non-overlapping width. The width of the channel region is wider and the width of the channel region is narrower, thereby achieving the effect of reducing the resistance value and parasitic capacitance of the active layer, so as to improve the electrical performance of the thin film transistor.

Although the present invention is disclosed in conjunction with the above preferred embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in this technical field should understand that some changes and modifications can be made without departing from the spirit and scope of the present invention. retouch. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims (10)

1. A display panel, comprising:

a first substrate;

a scan line disposed on the first substrate, the scan line having an extending direction; and

an active layer disposed on the first substrate;

wherein the overlapping portion of the active layer and the scan line comprises a first overlapping region and a second overlapping region, and a minimum width of the non-overlapping portion between the first overlapping region and the second overlapping region and along the extending direction is larger than a minimum width of the first overlapping region along the extending direction.

2. The display panel of claim 1, wherein a minimum width along a direction perpendicular to the extending direction where the first overlapping region and the second overlapping region do not overlap with the scan line is a distance between a first side edge and a second side edge.

3. The display panel of claim 1, wherein a minimum width of a portion between the first overlapping area and the second overlapping area that does not overlap with the scan line along a direction perpendicular to the extending direction is greater than a minimum width of the second overlapping area along the extending direction.

4. The display panel of claim 1, further comprising a data line, wherein the data line is not overlapped between the first overlapping area and the second overlapping area where the scan line is not overlapped.

5. The display panel of claim 4, wherein the active layer is between the data line and the first substrate.

6. The display panel of claim 4, wherein the active layer further comprises a first via region electrically connected to the data line.

7. The display panel of claim 1, wherein the first overlapping area and the second overlapping area are located under the scan line at a position not overlapping with the scan line.

8. The display panel of claim 1, further comprising a conductive layer disposed on the first substrate, the conductive layer overlapping a portion between the first overlapping area and the second overlapping area that does not overlap the scan line.

9. The display panel of claim 8, wherein the conductive layer is an electrode.

10. The display panel of claim 8, wherein the active layer further comprises a second via region electrically connected to the conductive layer.

Images