JP6787658B2 - Processing equipment, traffic signal equipment and information display equipment - Google Patents

Description

The present invention relates to a processing device that performs multitasking processing in which a plurality of tasks are executed in parallel, and a traffic signal device and an information display device using the same.

Conventionally, a watchdog timer has been generally used in order to detect an abnormality such as a runaway of a program of a processing device by a CPU, an MPU, or the like. The processing device generates a watchdog timer clear signal for resetting the watchdog timer at a predetermined cycle when the program is normal without runaway, and when an abnormality such as program runaway occurs, the watchdog timer is generated. It is designed not to generate a clear signal.

For example, in the traffic signal controller that controls the traffic signal lamp disclosed in Patent Document 1 below, an abnormality of the MPU is detected by using a watchdog timer. In this traffic signal controller, there are an MPU and a signal control LSI. Normally, the MPU performs signal control via the signal control LSI, and when an MPU abnormality occurs, the MPU is put into the HALT state. Therefore, signal control is performed only by the signal control LSI.

Japanese Patent No. 3369087

In recent years, processing devices such as CPUs and MPUs have adopted a multitasking processing method in which a plurality of tasks are executed in parallel.

In such a multitasking processing method, when a plurality of tasks are periodically started and executed, one of the tasks is a task that periodically outputs a watchdog timer clear signal (watchdog timer clear). If the task) is performed, even if an abnormal operation occurs in another task, if the watchdog timer clear task operates normally, the watchdog timer clear signal will be output periodically, and the processing device will be abnormal. Cannot be detected.

The present invention has been made in view of such circumstances, and is a processing device that performs multitask processing in which a plurality of tasks, each of which is started periodically, are executed in parallel, and detects an abnormality more appropriately. It is an object of the present invention to provide a processing device capable of the above, and a traffic signal device and an information display device using the processing device.

The following aspects are presented as means for solving the above problems. The processing device according to the first aspect is a processing device that performs multitasking processing in which a plurality of tasks, each of which is periodically started, are executed in parallel, and the plurality of tasks are one to be monitored. The above-mentioned monitored task and the monitoring task that monitors the one or more monitored tasks at predetermined intervals are included, and the one or more monitored tasks have predetermined information in a holding unit corresponding to their own task. Is included in each predetermined cycle, and the monitoring task is among the one or more monitored tasks based on the information held in the holding unit corresponding to the one or more monitored tasks. Includes a process of determining whether or not at least one of the monitored tasks in the above is in a state of not operating normally for a predetermined time or longer, and when the monitoring task determines that the state is in the above state, the watchdog thereafter. While the output of the timer clear signal is stopped, when it is determined by the monitoring task that the state is not the above state, the watchdog timer clear signal thereafter is periodically output.

According to this first aspect, since one or more monitored tasks include a process of holding predetermined information in a holding unit corresponding to its own task at predetermined intervals, the monitored task is normal. If the above operation is performed, the predetermined information is held in the holding unit. The monitoring task is based on whether or not at least one monitoring target task is not operating normally for a predetermined time or longer based on the information held in the holding unit corresponding to the one or more monitoring target tasks. Includes processing to determine. Then, when the monitoring task determines that the state is the same, the subsequent output of the watchdog timer clear signal is stopped, while the monitoring task determines that the state is not the state. Subsequent periodic output of the watchdog timer clear signal is performed.

Therefore, according to the first aspect, whether or not each monitored task is operating normally is monitored by the monitoring task, and if the monitored task is operating normally, the watchdog timer clear signal is periodically issued. On the other hand, if any of the monitored tasks is not operating normally, the output of the watchdog timer clear signal is stopped. Therefore, according to the first aspect, the abnormality can be detected more appropriately even though the multitasking process in which a plurality of tasks, each of which is periodically started, is executed in parallel is performed. ..

In the first aspect, the processing device according to the second aspect holds, for each of the at least one monitored task, in the holding unit corresponding to the monitored task when the monitored task is started. When the information is the predetermined information, the process includes a process of causing the holding unit corresponding to the monitored task to hold information different from the predetermined information.

In this second aspect, the so-called reset operation of the information indicating the operation status of the monitored task is clarified.

The processing device according to the third aspect includes the watchdog timer that detects an abnormality of the processing device based on the watchdog timer clear signal in the first or second aspect.

The traffic signal device according to the fourth aspect controls the traffic signal light device, the processing device according to any one of the first to third aspects, and the traffic signal light device under the control of the processing device or autonomously. It is equipped with a control circuit.

The information display device according to the fifth aspect is a display panel, a processing device according to any one of the first to third aspects, and a control circuit that controls the display panel under the control of the processing device or autonomously. And, it is equipped with.

The fourth and fifth aspects give examples of use of the processing apparatus according to the first to third aspects, but the first to third aspects are not limited to those examples. Absent.

According to the present invention, a processing device that performs multitasking processing in which a plurality of tasks, each of which is started periodically, is executed in parallel, and is capable of detecting an abnormality more appropriately, and a processing device thereof. It is possible to provide a traffic signal device and an information display device using the above.

It is a block diagram which shows the schematic structure of the processing apparatus according to 1st Embodiment of this invention. It is a figure which shows typically the relationship between the OS and a task in the processing apparatus shown in FIG. It is a figure which shows typically an example of the structure of the data used in the monitoring task in the processing apparatus shown in FIG. It is a schematic flowchart which shows the process performed at a predetermined cycle in the monitored task in the processing apparatus shown in FIG. It is a schematic flowchart which shows the processing content of the monitoring task in the processing apparatus shown in FIG. It is a block diagram which shows the schematic structure of the traffic signal device according to the 2nd Embodiment of this invention. It is a block diagram which shows the schematic structure of the information display device according to the 2nd Embodiment of this invention.

Hereinafter, the processing device, the traffic signal device, and the information display device according to the present invention will be described with reference to the drawings.

[First Embodiment]

FIG. 1 is a block diagram showing a schematic configuration of a processing device 1 according to the first embodiment of the present invention.

The processing device 1 according to the present invention includes a microcomputer 2 and a watchdog timer 3. The microcomputer 2 has a CPU 11, a ROM 12, a RAM 13, a non-volatile memory 14 such as EEPROM 14, an input / output interface 15, and a bus 16 that connects them to each other. Peripheral devices and the like are connected to the input / output interface 15 as needed, but their illustration is omitted.

When the watchdog timer 3 periodically receives a watchdog clear signal from the CPU 11 and does not receive the watchdog clear signal for a certain period of time when the CPU 11 operates normally without a runaway program or the like. Outputs an abnormality detection signal indicating that an abnormality has occurred in the CPU 11. In the present embodiment, the abnormality detection signal from the watchdog timer 3 is used as a reset signal for resetting the CPU 11. However, depending on the abnormality detection signal, the system may be forcibly stopped by turning off the power of the microcomputer 2, or the system may be turned on again after the power is turned off, or the abnormality may be simply displayed on the display device or other management. It may be used to notify the device of an abnormal state. In the present embodiment, the watchdog timer 3 is provided outside the microcomputer 2, but may be built in the microcomputer 2.

FIG. 2 is a diagram schematically showing the relationship between the OS (operating system) 20 and tasks 21-1 to 21-n, 22 in the processing device 1 shown in FIG. The OS 20 and a desired processing program are stored in the ROM 12, and when the microcomputer 2 is started, the OS 20 divides the processing program into appropriate processing units into n tasks (n is an integer of 2 or more). 21-1 to 21-n and the monitoring task 22 are set, and these tasks 21-1 to 21-n and 22 are managed and executed by the CPU 11.

In the present embodiment, under the control of the OS 20, tasks 21-1 to 21-n and 22, each of which is periodically activated, are executed in parallel by using an interrupt or the like by a timer (not shown). Multitask processing is realized. In the present embodiment, task 21-1 is started in cycle T1, task 21-2 is started in cycle T2, ..., Task 21-n is started in cycle Tn, and monitoring task 22 is started in cycle T0. It will be started. The cycles T1 to Tn and T0 may be different from each other, some cycles may be different from each other, some cycles may be the same as each other, or all cycles may be the same. For example, when n = 5, T1 = 100 ms, T2 = 200 ms, T3 = 100 ms, T4 = 100 ms, T5 = 500 ms, T0 = 1 second.

One or more of the n tasks 21-1 to 21-n are preset as monitored tasks to be monitored whether or not they are operating normally. All of the n tasks 21-1 to 21-n may be monitored tasks, or only any part of the tasks may be monitored tasks. The monitoring task 22 is started in the cycle T0, and the monitored task is monitored every predetermined cycle T0. The processing content of the monitoring task 22 will be described in detail later.

FIG. 3 is a diagram schematically showing an example of the data configuration used in the monitoring task 22. In the present embodiment, in the monitoring task 22, a task ID for identifying each task of a predetermined maximum number of tasks (for example, 256) and a task ID associated with each task ID are provided for each task ID. The assigned task activation number, alive check flag F, health check count value C, and task name are used as data.

The task start number is a number indicating whether or not the task is to be monitored, and if it is 0, the task is neither of n tasks 21-1 to 21-n and does not actually exist. Or, even if any of n tasks 21-1 to 21-n, the task is not a monitoring target. If the task is a task to be monitored among n tasks 21-1 to 21-n, the task activation number of the task is a number other than 0. The task name is used for creating a log, which will be described later. In the present embodiment, the task ID, the task activation number, and the task name are predetermined and cannot be rewritten by the operation described later. On the other hand, the alive check flag F is a flag rewritten by the operation described later for the task, and the health check count value C is a count value rewritten by the operation described later for the task.

In the present embodiment, the task activation number and the task name for each task ID are stored in the non-volatile memory 14 as setting information, and predetermined data from the non-volatile memory 14 to the RAM 13 when the microcomputer 2 is activated. Read to the area. The alive check flag F and the health check count value C for each task ID are set in a predetermined data area of the RAM 13 when the microcomputer 2 is started. As a result, when the microcomputer 2 is started, the data shown in FIG. 3 is stored in the RAM 13 for each task ID. In the present embodiment, the storage area of the alive check flag F in the RAM 13 constitutes a holding unit for holding the alive check flag F. When the microcomputer 2 is started, the alive check flag F of each task is initially set to 0, and the health check count value C of each task is initially set to a predetermined value Cmax described later.

FIG. 4 is a schematic flowchart showing processing performed at predetermined intervals in the monitored task in the processing device 1 shown in FIG. In the present embodiment, each monitored task has a predetermined cycle set for each monitored task in addition to the original process performed by its own task (original process determined based on the processing program). As the processing of the subroutine called by each monitored task, the processing of setting the alive check flag F of the own task to 1 is performed. Therefore, if the monitored task is operating normally at this point, the alive check flag F of the own task is set to 1, and if the operation of the monitored task is abnormal at this point, the own task Alive check flag F cannot be set to 1.

For example, if task 21-1 is a monitored task, the subroutine is called every time task 21-1 is started in cycle T1 in task 21-1, and the alive check flag of own task 21-1 is called. The process of setting F to 1 is performed. In this case, in the task 21-1, the process of setting the alive check flag F of the own task 21-1 to 1 is performed in the predetermined cycle T1. Not limited to this, in task 21-1, the subroutine is called at a rate of once every m times (m is an integer of 2 or more) out of every time (times) when task 21-1 is started in cycle T1. A process of setting the alive check flag F of the own task 21-1 to 1 may be performed. In this case, in the task 21-1, the process of setting the alive check flag F of the own task 21-1 to 1 is performed in the predetermined cycle m × T1. These points are the same when any of the other tasks 21-2 to 21-n is a monitored task.

FIG. 5 is a schematic flowchart showing the processing contents of the monitoring task 22 in the processing device 1 shown in FIG. In the present embodiment, the monitoring task 22 performs the process shown in FIG. 5 each time it is started in the cycle T0 as described above.

When the monitoring task 22 is activated, the CPU 11 outputs a watchdog timer clear signal (WDT clear signal) (step S1). After that, the CPU 11 sequentially changes the tasks to be processed after that at the loop start end R1 up to the maximum number of tasks (all tasks to which the task ID is assigned), and after the loop start end R1. Perform processing.

When the task (task ID) to be processed is set at the loop start end R1, the CPU 11 refers to the task activation number of the task in the RAM 13 and determines whether or not the task is a monitored task. Then (step S2), if the task is not the monitored task (if the task start number is 0), the loop start end R1 is returned, while if the task is the monitored task (the task start number must be 0). B) Move to step S3.

In step S3, the CPU 11 normally operates the alive check flag F of the task currently set as the processing target at the loop start end R1 (that is, the task operates normally after the previous startup of the monitoring task 22). Was done) or not.

When it is determined in step S3 that the alive check flag F of the task is 1, the CPU 11 resets the alive check flag F of the task to 0 and sets the health check count value C of the task to a predetermined value Cmax ( Cmax is reset to (an integer of 1 or more) (step S4), and then returns to the loop start end R1.

On the other hand, if it is determined in step S3 that the alive check flag F of the task is not 1 (0), the process proceeds to step S5.

In step S5, the CPU 11 decrements the health check count value C of the task currently set as the processing target at the loop start end R1 by 1.

After that, the CPU 11 determines whether or not the health check count value C of the task currently set as the processing target at the loop start end R1 is 0 (step S6). If the health check count value C is not 0, the process proceeds to the loop end end R2, while if the health check count value C is 0, the process proceeds to step S7. Here, the fact that the health check count value C is 0 means that the alive check flag F of the monitored task is set over the number of consecutive times indicated by the predetermined value Cmax every time the monitoring task 22 is activated (times). It means that it was not 1 (it was 0), that is, it could not be confirmed that the monitored task operated normally for a predetermined time of Cmax × T0 or more. In the present embodiment, if the task is normal for each monitored task, the alive check flag F of the task is always set to 1 at least once within the predetermined time Cmax × T0 (in the figure in the task). ), The cycle for setting the alive check flag F of the task in the task, the predetermined value Cmax, and the activation cycle T0 of the monitoring task 22 are set. Therefore, when the health check count value C is 0, it means that the monitored task is not operating normally for a predetermined time of Cmax × T0 or more.

At the loop end end R2, if the task currently set as the processing target at the loop start end R1 is not the last task in the maximum number of tasks, the process returns to the loop start end R1 while the task is the last task. If so, the process of the monitoring task 22 started this time is terminated.

In step S7, the CPU 11 causes the non-volatile memory 14 to write a log indicating that the task currently set as the processing target at the loop start end R1 is abnormal, the task name of the task, and the current time, and other In order to forcibly terminate the task (tasks 21-1 to 21-n other than the monitoring task 22), a notification (notification of completion of another task) is generated to the other task. The log can be used for abnormality analysis and the like. The other task that has received the task end notification requests the OS 20 to forcibly terminate itself, and is forcibly terminated by the OS 20.

After step S7, the CPU 11 finishes the monitoring task 22 and then requests the OS 20 not to start the monitoring task 22 even at the start timing of each cycle T0, so that the CPU 11 proceeds to the self-destruction process (step S8). In response to this request, the OS 20 terminates the monitoring task 22 and does not start the monitoring task 22 thereafter. As a result, the WDT clear signal is no longer output from the CPU 11, and the watchdog timer 3 detects an abnormality in the microcomputer 2.

The system of the microcomputer 2 is forcibly terminated by steps S7 and S8.

The process of step S1 may be performed after the loop end end R2 and immediately before the end of the monitoring task 22 instead of immediately after the start of the monitoring task 22.

According to the present embodiment, each monitored task has predetermined information "1" in the holding unit (in the present embodiment, the area of the alive check flag F of the task in the RAM 13) corresponding to its own task. Is included in each predetermined cycle (process shown in FIG. 4), so that if the monitored task operates normally, the predetermined information "1" is held in the holding unit. The monitoring task 22 determines whether or not at least one monitored task is not operating normally for a predetermined time of Cmax × T0 or more based on the information of the alive check flag F corresponding to the monitoring task 22. The process (step S6 in FIG. 5 and the like) is included. Then, when the monitoring task 22 determines that the state is met (YES in step S6 in FIG. 5), the subsequent output of the WDT clear signal is stopped, while the monitoring task 22 stops the state. If it is determined that this is not the case (NO in step S6 in FIG. 5), the subsequent WDT clear signal is periodically output.

Therefore, according to the present embodiment, the monitoring task 22 monitors whether or not each monitored task is operating normally, and if the monitored task is operating normally, the WDT clear signal is periodically issued. On the other hand, if any of the monitored tasks is not operating normally, the output of the WDT clear signal is stopped. Therefore, according to the present embodiment, it is more appropriate to perform multitask processing in which a plurality of tasks 21-1 to 21-n and 22, each of which is started periodically, are executed in parallel. Abnormality can be detected.

[Second Embodiment]

FIG. 6 is a block diagram showing a schematic configuration of a traffic signal device according to a second embodiment of the present invention. In FIG. 6, the same or corresponding elements as those in FIG. 1 are designated by the same reference numerals, and the duplicated description thereof will be omitted.

The traffic signal device according to the present embodiment is a control circuit that controls the processing device 1 according to the first embodiment, the traffic signal lamp 31, and the traffic signal lamp 31 under the control of the processing device 1 or autonomously. The abnormality processing is performed based on the abnormality detection signal from the control LSI 32, the data storage unit 33 that stores the control data (for example, display color, lighting pattern, etc.) of the traffic signal lamp 31, and the watchdog timer 3. It includes a processing circuit 34.

Unlike the first embodiment, the abnormality detection signal from the watchdog timer 3 is supplied to the abnormality processing circuit 34 instead of being used as a reset signal for resetting the CPU 11. The CPU 11 is kept in the reset state continuously for a time (first predetermined time TA) of receiving the reset signal from the abnormality processing circuit 34.

The control LSI 32 outputs a signal for directly controlling the traffic signal lamp 31 as a lighting output while referring to the data of the data storage unit 33. The control LSI 32 controls the traffic signal lamp 31 autonomously independently of the CPU 11 or the normal operation mode in which the traffic signal lamp 31 is controlled under the control of the CPU 11 in response to the operation mode command from the abnormality processing circuit 34. Perform the fail operation mode. In the normal operation mode, the CPU 11 receives a signal indicating the state of the control LSI 32 from the control LSI 32 via the input / output interface 15, controls the control LSI 32 based on the signal, and passes through the control LSI 32. Controls the traffic signal lamp 31. In this embodiment, this control is realized by tasks 21-1 to 21-n. In the fail operation mode, the CPU 11 is not involved in the control of the traffic signal lamp 31.

Upon receiving the abnormality detection signal from the watchdog timer 3, the abnormality processing circuit 34 gives an operation mode command to the control LSI 32 to start the fail operation mode. Further, when the abnormality processing circuit 34 receives the abnormality detection signal from the watchdog timer 3, the abnormality processing circuit 34 supplies the reset signal to the CPU 11 for the first predetermined time TA. After that, the abnormality processing circuit 34 determines whether or not the CPU 11 has been restored to the normal state after being reset within the second predetermined time TB based on the signal from the watchdog timer 3 (or the WDT clear signal from the CPU 11). Is determined. The abnormality handling circuit 34 gives an operation mode command to the control LSI 32 to start the normal operation mode when the CPU 11 is restored to the normal state within the second predetermined time TB. On the other hand, if the CPU 11 does not recover to the normal state within the second predetermined time TB, the control LSI 32 continues the fail operation mode.

According to the present embodiment, since the processing device 1 according to the first embodiment is used, a plurality of tasks 21-1 to 21-n and 22, each of which is periodically activated, are performed in parallel. Despite performing the multitasking process to be executed, the abnormality can be detected more appropriately, and the traffic signal lamp 31 can be controlled more appropriately.

Further, according to the present embodiment, when the watchdog timer 3 outputs an abnormality detection signal, the fail operation mode is set, but the CPU 11 is kept in the reset state by continuing TA for the first predetermined time. After resetting the CPU 11, it is determined whether or not the CPU 11 has recovered to the normal state within the second predetermined time TB, and when it is determined that the CPU 11 has recovered to the normal state within the second predetermined time TB, it is usually determined. Automatically restores to operating mode. Therefore, according to the present embodiment, when an abnormality of the CPU 11 temporarily occurs due to a transient factor such as the influence of external noise, the normal operation mode is automatically restored. Therefore, according to this embodiment, maintenance / inspection work that is not originally necessary can be omitted, and maintenance costs can be reduced.

However, in the present invention, the abnormality processing circuit 34 may continue the fail operation mode once the abnormality detection signal is received from the watchdog timer 3 without supplying the reset signal to the CPU 11.

[Third Embodiment]

FIG. 7 is a block diagram showing a schematic configuration of an information display device according to a third embodiment of the present invention, and corresponds to FIG. In FIG. 7, the same or corresponding elements as the elements in FIG. 6 are designated by the same reference numerals, and duplicate description thereof will be omitted.

The information display device according to the present embodiment is configured as, for example, a device for displaying road traffic information and the like, and as a control target, instead of the traffic signal lamp 31, a display panel (for example, a large number arranged in a two-dimensional manner) is used. A display panel (41) having an LED is provided.

In the present embodiment, the control LSI 32 is a control circuit that controls the display panel 41 under the control of the CPU 11 or autonomously. Further, in the present embodiment, the data storage unit 33 stores data related to the control of the display panel 41 (for example, display color, display pattern, etc.). Further, in the present embodiment, the control LSI 32 outputs a signal for directly controlling the display panel 41 as a display output while referring to the data of the data storage unit 33.

The present embodiment also provides the same advantages as the second embodiment.

Although each embodiment of the present invention has been described above, the present invention is not limited to these embodiments. For example, the application of the processing device according to the present invention is not limited to the above-mentioned traffic signal device and information display device.

1 Processing device 2 Microcomputer 3 Watchdog timer 21-1 to 21-n task 22 Monitoring task 31 Traffic signal lamp 32 Control LSI
41 Display panel

Claims (4)

It is a processing device that performs multitasking processing in which multiple tasks, each of which is started periodically, are executed in parallel.
The plurality of tasks include one or more monitored tasks to be monitored and a monitoring task that monitors the one or more monitored tasks at predetermined intervals.
The one or more monitored tasks cause the holding unit corresponding to the own task to hold the same predetermined information every predetermined cycle without checking whether or not the processing of the own task is normally executed. Including processing
In the monitoring task, at least one of the one or more monitored tasks has a predetermined time or more based on the information held in the holding unit corresponding to the one or more monitored tasks. Includes processing to determine whether or not the system is not operating normally.
When the monitoring task determines that the state is in the above state, the output of the watchdog timer clear signal after that is stopped, while when the monitoring task determines that the state is not the state, the watch after that is stopped. There row regular output of the watchdog timer clear signal,
For each of the at least one monitored tasks, the monitoring task monitors the predetermined information when the information held in the holding unit corresponding to the monitored task at the time of starting the monitoring task is the predetermined information. Including a process of causing the holding unit corresponding to the target task to hold information different from the predetermined information.
A processing device characterized by that. Processing apparatus according to claim 1, further comprising a watchdog timer for detecting an abnormality of the processing apparatus based on the watchdog timer clear signal. Traffic light and
The processing apparatus according to claim 1 or 2 ,
A control circuit that controls the traffic signal lamp under the control of the processing device or autonomously.
A traffic signal device characterized by being equipped with. Display panel and
The processing apparatus according to claim 1 or 2 ,
A control circuit that controls the display panel under the control of the processing device or autonomously.
An information display device characterized by being equipped with.

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