JP5041290B2 - PROGRAMMABLE CONTROLLER AND ITS ERROR RECOVERY METHOD - Google Patents

Description

  The present invention relates to a programmable controller and an abnormality recovery method thereof. More specifically, the present invention relates to a programmable controller system in which the programmable controller CPU module self-determines the cause of the abnormality and restarts the programmable controller CPU module itself when each component in the programmable controller is abnormal. The present invention relates to a programmable controller and a method for recovering from an abnormality in order to avoid an overall abnormal stop.

  As is conventionally known, a programmable controller (hereinafter also abbreviated as PLC) is used as a control device for factory automation (FA). This PLC is composed of a plurality of modules. These modules include a power supply module that is a power supply source, a CPU module that controls the overall control of the PLC, and an input for inputting signals from switches and sensors that are installed at appropriate locations in FA production equipment and equipment equipment. There are output modules for outputting control signals to modules, actuators, etc., communication modules for connecting to communication networks, and the like. A PLC is configured by appropriately combining these modules.

  The CPU module fetches the signal input from the input module into the I / O (Input / Output) memory of the CPU module (input refresh), and performs a logical operation based on a user program (sequence program) registered in advance (calculation execution) The operation execution result is written in the I / O memory, sent to the output module (output refresh), and then a series of processing for performing so-called peripheral system processing (loader processing, various system processing) is repeatedly performed. The CPU module controls a target device (hereinafter referred to as a control target device) by performing this repeated processing.

  The user program (sequence program) for controlling such a device to be controlled and various setting data are stored in a RAM (Random Access Memory), and are sequentially read and written at the time of calculation execution.

  On the other hand, in the factory environment where the PLC is installed, various devices such as a servo motor, an inverter, and a high-voltage power device are connected to the PLC or arranged in the vicinity of the PLC. Therefore, the entire RAM or a part of the data may be destroyed or lost due to radiation noise, an instantaneous power failure of the power supply, an electromagnetic field, or the like. When the control target device is controlled based on the data in which the data destruction / disappearance has occurred, the PLC does not operate normally. Therefore, the PLC confirms whether the data destruction / disappearance has occurred during the operation.

  Since such data destruction / erasure is often a transient abnormality, the system is often recovered simply by restarting the system after the system is stopped. In this case, for example, a reset circuit is provided. It has been necessary to manually operate the reset button to generate a system reset signal to reset the CPU and restart the system. In order to eliminate the need for such an artificial operation, when an abnormality is detected on the memory or data bus for storing data, the occurrence of the abnormality is detected and the operation of the PLC is temporarily stopped. There has been proposed a PLC abnormality detection device provided with reset means for generating a reset signal for restarting the PLC (see, for example, Patent Document 1).

  Further, in a PLC unit including a user memory storing a user program read out during arithmetic processing, and a backup memory storing data having the same contents as the user program stored in the user memory, the user memory and the backup memory The user data stored in and are compared cyclically to determine whether there is a memory error. If a memory error is detected, the detected memory error data is restored with the corresponding data in the backup memory. Has been proposed (for example, Patent Document 2).

Japanese Patent Laid-Open No. 2001-242901 JP 2004-220580 A

  However, not only when there is a memory failure such as data destruction / erasure, but also when the CPU module stops due to a transient failure in a component within the PLC, such as a malfunction of the built-in IC or a PLC-specific bus failure, For safety purposes, it was necessary to prevent system runaway and unauthorized output. When these transient abnormalities are detected, the CPU module is stopped, and as a result, the entire controlled system is stopped. In addition, since the PLC is generally installed in the back of the control panel, in order to operate the system again, maintenance personnel and the like visit the site, investigate the cause of the abnormal stop, and restart the system (that is, power supply) However, this operation is not easy, and there is a problem that a lot of time is spent until the system is restarted.

  Therefore, in the present invention, in view of the above points, when the CPU in the PLC CPU module detects an abnormality in a component in the PLC, the CPU self-determines to restart the CPU module. An object of the present invention is to provide a programmable controller and a method for recovering from the abnormality.

  It is another object of the present invention to provide a programmable controller and a method for recovering from an abnormality in which the CPU module itself determines whether or not to restart the CPU module according to the type of abnormality in the components in the PLC. .

To achieve the above object, a first aspect of the present invention, at least including C PU module a CPU and various memories and I / O interface for the programmable controller, the I / O interface unit are connected via, possess the I / O module for controlling the external control target device, an input refresh process, a programmable controller for executing a user program operation processing, and the output refresh process cyclically, the CPU module, or When an abnormality is detected in the I / O interface, there are an occurrence abnormality factor information file that records the cause of the abnormality and a restartable abnormality factor file that stores the cause of the abnormality that can restart the CPU module. The cause of the abnormality that can be restarted is determined in advance or Via the programming device is changeably setting a restartable error factors file, the state of the CPU module, normal operation, normal stop, or determines the operating condition determining whether either abnormal stop And an abnormality occurs in the CPU module or the I / O module in the determination, the cause of the abnormality is recorded in the occurrence abnormality factor information file, and the state of the CPU module is abnormally stopped. If it is determined, the recorded abnormality factor is compared with a plurality of restartable abnormality factors recorded in the restartable abnormality factor file, and the abnormality is determined based on the comparison result. However, the abnormality factor determination means for determining whether or not the abnormality is a transient abnormality and the abnormality factor determination means determine that the abnormality is a transient abnormality. When, characterized in that a restarting means for restarting the previous SL C PU module.

The invention according to claim 2 further comprises restart number recording means for recording the number of times the CPU module has been restarted by the restart means in the invention according to claim 1, wherein the restart number is preset. if it exceeds the number of times defined, wherein the CPU, the pre-Symbol C PU module, characterized in that to hang.

According to a third aspect of the present invention, a CPU for a programmable controller, various memories, and a CPU module including at least an I / O interface unit are connected to the CPU module via the I / O interface unit to control an external control target device. A programmable controller abnormality recovery method that cyclically executes an input refresh process, a user program operation process, and an output refresh process, wherein the memory includes the CPU module or the I / O module. An occurrence error factor information file that records the cause of the abnormality when an abnormality is detected in the O interface, and a restartable error factor file that stores an error factor capable of restarting the CPU module; Possible causes of abnormalities that can be restarted are A restartable abnormality factor file set so as to be changeable via a ramming device, and whether the state of the CPU module is normal operation, normal stop, or abnormal stop In the operation state determination step and the determination, an abnormality occurs in the CPU module or the I / O module, the cause of the abnormality is recorded in the occurrence abnormality factor information file, and the state of the CPU module is determined. If it is determined that there is an abnormal stop, the recorded abnormality factor is compared with a plurality of restartable abnormality factors recorded in the restartable abnormality factor file, and the comparison result is obtained. Based on the abnormality factor determination step for determining whether or not the abnormality is a transient abnormality and the abnormality factor determination step, the abnormality is If it is determined that the sexual abnormalities, characterized in that a restart step of restarting the CPU module.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the restart number recording step for recording the number of times the CPU module is restarted by the restart step, and the restart number are predetermined. The CPU further includes a step of abnormally stopping the CPU module when the number of times exceeds the predetermined number .

  Note that the term “transient abnormality” used in the present specification refers to an abnormality that can be recovered not only by turning on the power again but also by restarting the CPU module. In other words, a “temporary abnormality” is not an abnormality caused by damage to each module or a module configuration abnormality, and therefore does not require module replacement, and power is turned on or rebooted (reset start). An abnormality that can be restored by

  The term “restart” used in this specification refers to restart of the CPU module, but restarting the CPU module restarts the entire PLC system including I / O. It is synonymous with.

  According to the present invention, when the CPU in the PLC CPU module detects an abnormality in a component in the PLC, the CPU can make a self-determination to restart the CPU module.

  Further, according to the present invention, the CPU can self-determine whether or not to restart the CPU module itself according to the type of abnormality in the components in the PLC.

  Furthermore, according to the present invention, by restarting the PLC in which an abnormality has been detected, the CPU module and system stop time can be reduced to a short time, and the operation can be quickly restored.

  Hereinafter, embodiments to which the present invention can be applied will be described in detail with reference to the drawings.

(Device configuration)
FIG. 1 is a block diagram illustrating a configuration of a PLC 100 including a CPU module 10 and an I / O module 40 according to an embodiment of the present invention.

  As shown in FIG. 1, the PLC 100 includes a CPU module 10 and an I / O module 40. The CPU module 10 includes the following components connected to each other via an internal system bus 19, and a programming loader (also referred to as a programming device or loader) 200 via a loader interface 30 provided in the CPU module 10 and a communication line 300. It is connected to the. The programming loader 200 is a tool that plays a role of creating and transferring a user program for the PLC 100. Further, the I / O module 40 is a digital and / or analog module that is added according to the type of the PLC or a control target device (not shown). Although only one I / O module 40 is shown in FIG. 1, a plurality of I / O modules 40 may be provided in the PLC 100. The I / O module 40 is connected to the PLC specific bus interface 14 in the CPU module via the PLC specific bus 14a, and is connected to the control target device via a communication line (not shown).

  The CPU module 10 operates with a system program stored in advance in a system program memory 15 described later as a base layer program. Further, the CPU module 10 stores a user program such as a sequence program transferred from the programming loader 200 in a user program memory 17 to be described later, and then executes and executes this sequence program to automatically sequence the external control target device. Take control. In the CPU module 10, the CPU 11, driver / receiver 13, system program memory 15, system work memory 16, user program memory 17, user data memory 18, and PLC specific bus interface 14 are connected to a common system bus 19. Has been.

  The CPU 11 controls the operation of each component in the CPU module 10 based on the system program stored in the system program memory 15 and executes or stops the sequence program stored in the user program memory 17. Control, communication command control such as transmission and monitoring of a sequence program from the programming loader 200, and recovery processing at the time of abnormality of the PLC 100 according to an embodiment of the present invention are performed.

  The driver / receiver 13 is connected to the programming loader 200 via the loader interface 30 and the communication line 300, and transmits and receives data between the CPU module 10 and the programming loader 200.

  The system program memory 15 stores a system program executed by the CPU 11. The system program memory 15 is usually a flash memory. This system program includes a program shown in the flowcharts of FIGS. 3 to 5 to be described later, including the above-described recovery processing when the PLC 100 is abnormal.

  The system work memory 16 stores temporary calculation results and various setting values necessary for execution of processing in the PLC 100 as work memory for system programs. The system work memory 16 is usually a RAM.

  The user program memory 17 stores a user program such as a sequence program transferred from the programming loader 200. A normal RAM is used for the user program memory 17.

  The user data memory 18 stores the calculation result of the sequence program stored in the user program memory 17 and various setting values of the control target device. As the user data memory 18, a normal RAM is used.

  The PLC specific bus interface 14 is connected to the I / O module 40 via the PLC specific bus 14a, and inputs and outputs information related to control of an external control target device. In this example, the connection to the I / O module 40 is described as being performed by the PLC specific bus interface 14, but it is necessary to connect by the special bus interface (14) or the specific bus (14 a) unique to the PLC. There is no need to be particular about it. Therefore, the PLC specific bus interface 14 can be simply an I / O interface unit, and the PLC specific bus 14a can be simply an I / O bus. Further, the I / O module 40 may be directly connected to the system bus 19.

  The I / O module 40 takes in a signal from a switch or a sensor and outputs a control signal to an actuator or the like.

  FIG. 2 is a block diagram showing a configuration in the system work memory 16 in the CPU module 10 in the PLC 100 according to the embodiment of the present invention.

  The system work memory 16 includes an operation state file 16A, a restart count recording file 16B, a restartable error factor file 16C, and an occurrence error factor information file 16D.

  The operation state file 16A indicates the operation state of the CPU module 10, and the operation state file 16A records three types of statuses: normal operation execution, normal operation stop, and abnormal operation stop.

  The restart count recording file 16B records the number of times the CPU module 10 is restarted due to a restartable error factor (for example, memory error, malfunction of built-in IC, PLC specific bus error, etc.).

  The restartable error factor file 16C is a record of n (n: natural number) restartable error factors such as memory error, malfunction of built-in IC, PLC specific bus error, I / O module error, etc. . The restartable abnormality factor file 16C may be registered in advance in the design stage, or may be registered or changed via the programming loader 200. The restartable abnormality factor file 16C is used in an abnormality factor determination process described later with reference to FIG.

  The occurrence abnormality factor information file 16D records the occurrence abnormality factor and a plurality of additional information associated with the occurrence abnormality factor when the CPU 11 detects the abnormality and executes the abnormality process.

When the occurrence abnormality factor is a restartable abnormality factor, for example, the following is recorded as the occurrence abnormality factor and additional information.
Cause of error occurrence: Memory error, additional information: error occurrence time, memory address, etc.
Cause of occurrence abnormality: malfunction of built-in IC, additional information: abnormality occurrence time, identifier of IC in which malfunction occurred, and the like.
Cause of occurrence abnormality: PLC specific bus error, additional information: error occurrence time, PLC specific bus identifier, and the like.
Cause of occurrence error: I / O module error, additional information: error occurrence time, error occurrence I / O module identification number, etc.

When the occurrence abnormality factor is an abnormality factor that cannot be restarted, for example, the following are recorded as the occurrence abnormality factor and additional information.
Cause of occurrence error: System configuration error (I / O module or communication module that cannot be connected is connected) Additional information: Error occurrence time, error occurrence module identification number, error module type, etc.
Cause of occurrence abnormality: Excessive number of I / O modules connected (I / O modules more than connectable number are connected) Additional information: Time of occurrence of abnormality, number of connected over, etc.

(Description of operation)
Next, the processing of the CPU 11 in the PLC 100 according to the embodiment of the present invention in the configuration shown in FIGS. 1 and 2 will be described.
FIG. 3 is a flow diagram illustrating processing performed by CPU 11 in accordance with one embodiment of the present invention.

  First, the process of the CPU 11 is started by turning on the power of the PLC 100. In S301, the CPU 11 clears the restart count recording file 16B in the system work memory 16 and sets the restart count to zero. Next, in S302, the CPU 11 refreshes the data contents of the contact information, records the operation state file A in the system work memory 16 as normal operation execution, and the recorded contents in the occurrence abnormality factor information file 16C in the system work memory 16 Perform initialization processing such as clearing. Next, in S <b> 303, the CPU 11 executes a self-diagnosis process for checking whether each component in the PLC 100 has an abnormality.

  Next, in S304, the CPU 11 executes various system processes. This system process includes a memory abnormality detection process for detecting a memory abnormality when the user program and user data stored in the user program memory 17 and the user data memory 18 are destroyed or lost. As a technique for detecting this memory abnormality, parity check or ECC (Error Checking and Correction), which is well known in the art, can be used. Alternatively, using a backup memory (not shown) in which data having the same contents as the user program and user data is stored, the user program and user data memory stored in the user program memory 17 and the user data memory 18, and the backup memory The user program and user data stored in the memory may be compared to determine whether there is a memory abnormality.

  Further, in this system process, when the occurrence abnormality factor is recorded in the occurrence abnormality factor information file 16D in the system work memory 16, the CPU 11 abnormally stops the operation state file 16A in the system work memory 16. As a recording process.

  When the CPU 11 receives an abnormal signal indicating that the devices such as various ICs and the PLC specific bus interface 14 are abnormal from the devices, the CPU 11 generates the above-described occurrence abnormality factor included in the abnormal signal as an interrupt process, A plurality of additional information accompanying the occurrence abnormality factor is recorded in the occurrence abnormality factor information file 16D in the system work memory 16.

  Next, in S305, the CPU 11 determines the operation state of the CPU module 10 by confirming the operation state file 16A in the system work memory 16 (operation state determination process).

  If the operation state is normal operation in S305, the process proceeds to S306, and the CPU 11 sends the signal input from the input module 40 to an I / O memory (not shown) in the user data memory 18 in the CPU module 10. In step S307, a logical operation is executed based on a user program (sequence program) registered in advance. In step S308, the operation execution result is written in the I / O memory and sent to the output module (output refresh). ).

  Next, in S311, the CPU 11 executes a loader process. This loader process includes a process in which the CPU 11 changes the operation state file 16A in the system work memory 16 to normal operation stop by a request from the loader or an external switch installed in the CPU module 10. Similarly, this loader process includes a process in which the CPU 11 changes the operation state file 16A in the system work memory 16 to normal operation execution by a request from the loader or an external switch installed in the CPU module 10. .

  Next, in S312, the CPU 11 executes various system processes similar to those in S304. This system process includes a memory abnormality detection process for detecting a memory abnormality when the user program and user data stored in the user program memory 17 and the user data memory 18 are destroyed or lost. As a technique for detecting this memory abnormality, parity check or ECC (Error Checking and Correction), which is well known in the art, can be used. Alternatively, a user program and user data stored in the user program memory 17 and the user data memory 18 and a backup memory storing data having the same contents as the user program and user data are stored in the backup memory. The user program and user data may be compared to determine whether there is a memory abnormality.

  Further, in this system process, when the occurrence abnormality factor is recorded in the occurrence abnormality factor information file 16D in the system work memory 16, the CPU 11 abnormally stops the operation state file 16A in the system work memory 16. As a recording process.

  When the CPU 11 receives an abnormal signal indicating that the devices such as various ICs and the PLC specific bus interface 14 are abnormal from the devices, the CPU 11 generates the above-described occurrence abnormality factor included in the abnormal signal as an interrupt process, A plurality of additional information accompanying the occurrence abnormality factor is recorded in the occurrence abnormality factor information file 16D in the system work memory 16.

  Here, it returns to S305 again and CPU11 performs a driving | running state determination process. In S305, when the operation state is a normal operation stop, the process proceeds to S309, and the CPU 11 stops the user program calculation process, confirms the wiring (input / output state; S309, S310), and sets the programming loader 200. Maintenance such as replacement of user programs can be performed safely.

  Next, in S311, after the operation state file 16A is changed to normal operation execution, some abnormality described above occurs, and the occurrence abnormality factor and additional information are recorded in the occurrence abnormality factor information file 16D in the system work memory 16. To do. Then, in S312, the CPU 11 changes the operation state file 16A to an abnormal operation stop, returns to S305 again, the CPU 11 executes an operation state determination process, determines that the operation state is an abnormal operation stop, The process proceeds to S313. In S313, the CPU 11 determines whether or not the occurrence abnormality factor is an abnormality that can be restarted (abnormal factor determination processing). The abnormality factor determination process will be described later in detail with reference to FIGS.

  In S313, when the occurrence abnormality factor is not an abnormality that can be restarted, the process proceeds to S311. At this time, the CPU 11 notifies a display device (not shown) that an abnormality that cannot be restarted has occurred, and displays that fact on the display device, so that a user such as a maintenance staff cannot restart the PLC 100. It is possible to recognize that a possible abnormality has occurred. In S <b> 311, the CPU 11 accepts an instruction or the like transmitted by the user via the programming loader 200 and performs processing according to the instruction. Although not shown, for example, if a memory dump instruction is received, the CPU 11 transmits data at a designated address to the loader 200 or receives an instruction to abnormally stop the CPU module 10, the CPU 11 The CPU module 10 can be abnormally stopped. On the other hand, if the occurrence abnormality factor is an error that can be restarted in S313, then in S314, the CPU 11 determines in advance the number of restarts recorded in the restart count recording file 16B in the system work memory 16. It is determined whether or not the number of times exceeded (restart number determination process). The predetermined number of times may be stored as a fixed number of times in the system program memory 15 or the like at the design stage, or may be registered or changed in the system work memory 16 via the programming loader 200. May be.

  If the number of restarts exceeds the predetermined number in S314, the process proceeds to S311. When the number of restarts exceeds a predetermined number, the cause of the abnormality that has occurred cannot be recovered by the restart process, and the restart is continuously performed. At this time, the CPU 11 notifies the display device that an abnormality that cannot be restarted has occurred, and displays the fact on the display device, so that a user such as a maintenance staff has an abnormality that cannot be restarted in the PLC 100. You can recognize what happened. In S <b> 311, the CPU 11 accepts an instruction or the like transmitted by the user via the programming loader 200 and performs processing according to the instruction. Although not shown, for example, if a memory dump instruction is received, the CPU 11 transmits data at a designated address to the loader 200 or receives an instruction to abnormally stop the CPU module 10, the CPU 11 The CPU module 10 can be abnormally stopped. On the other hand, if the number of restarts does not exceed the predetermined number in S314, then in S315, the CPU 11 sets the restart count recorded in the restart count recording file 16B in the system work memory 16 to 1. Increment. Next, the process returns to S302, and the above-described processing is repeated from the initialization processing. Note that the restart in this specification indicates returning from the restart count increment process in S315 to the initialization process in S302.

Next, the abnormality factor determination process in S313 of FIG. 3 will be described with reference to FIGS.
FIG. 4 is a flowchart showing an example of the abnormality factor determination process executed by the CPU 11 according to the embodiment of the present invention.

  This abnormality factor determination process is realized by the CPU 11 sequentially comparing n restartable abnormality factors, which are predetermined in the design stage and stored in the system program memory 15 or the like, with the abnormality factors that have occurred. Is done. That is, as shown in S401, the CPU 11 first determines whether or not the occurrence abnormality factor matches the predetermined restartable abnormality factor 1. If the occurrence abnormality factor matches the predetermined restartable abnormality factor 1, the process proceeds to S314 in FIG. On the other hand, if the occurrence abnormality factor and the predetermined restartable abnormality factor 1 do not match, the process proceeds to S402, and the CPU 11 matches the occurrence abnormality factor and the predetermined restartable abnormality factor 2. It is determined whether or not to do. The process proceeds in the same manner. Finally, if the CPU 11 determines that the occurrence abnormality factor and the predetermined restartable abnormality factor n do not match, the process proceeds to S311 in FIG.

  FIG. 5 is a flowchart showing another example of the abnormality factor determination process executed by the CPU 11 according to the embodiment of the present invention.

  In this abnormal factor determination process, in S501, the CPU 11 sequentially compares the n restartable abnormal factors recorded in the restartable abnormal factor file 16C in the system work memory 16 and the generated abnormal factors. To do. Next, in S502, the CPU 11 determines whether or not the same abnormality factor as the generated abnormality factor exists in the n restartable abnormality factors recorded in the restartable abnormality factor file 16C. . If the same abnormality factor exists, the process proceeds to S314 in FIG. On the other hand, if the same abnormality factor does not exist, the process proceeds to S311 in FIG.

As described above, according to the present invention, when the CPU in the PLC CPU module detects an abnormality in a component in the PLC, the CPU can make a self-determination to restart the CPU module. It becomes possible.
Further, according to the present invention, the CPU can self-determine whether or not to restart the CPU module itself according to the type of abnormality in the components in the PLC.
Furthermore, according to the present invention, by restarting the PLC in which an abnormality has been detected, the CPU module and system stop time can be reduced to a short time, and the operation can be quickly restored.

It is a block diagram which shows the structure of the programmable controller provided with the CPU module for programmable controllers and I / O module based on one Embodiment of this invention. It is a block diagram which shows the structure in the system work memory in the CPU module in the programmable controller which concerns on one Embodiment of this invention. FIG. 6 is a flowchart showing processing executed by a CPU according to an embodiment of the present invention. It is a flowchart which shows an example of the abnormality factor determination process which CPU performs according to one Embodiment of this invention. It is a flowchart which shows another example of the abnormal factor determination process which CPU performs according to one Embodiment of this invention.

Explanation of symbols

10 CPU module 11 CPU
13 Driver / receiver 14 Programmable controller (PLC) specific bus interface 15 System program memory 16 System work memory 16A Operation status file 16B Restart count record file 16C Restartable error factor file 16D Occurrence error factor information file 17 User program memory 18 User Data memory 19 System bus 30 Loader interface 40 I / O module 100 Programmable controller (PLC)
200 Programming loader

Claims (4)

At least including C PU module a CPU and various memories and I / O interface for the programmable controller, is connected via the I / O interface unit, chromatic and I / O module for controlling the external control target device A programmable controller that cyclically executes an input refresh process, a user program calculation process, and an output refresh process,
When an abnormality is detected in the CPU module or the I / O interface, an occurrence abnormality factor information file that records the cause of the abnormality,
A restartable error factor file that stores the cause of an abnormality that can restart the CPU module, and the error factor that can be restarted is set in advance or changeable via a programming device. A restartable error factor file,
State of the CPU module, and normal operation, normal stop, or abnormal stop determines the operating condition determining means for determining is either,
In the determination, an abnormality occurs in the CPU module or the I / O module, the cause of the abnormality is recorded in the occurrence abnormality factor information file, and it is determined that the state of the CPU module is abnormally stopped. In this case, the recorded abnormality factor is compared with a plurality of restartable abnormality factors recorded in the restartable abnormality factor file, and the abnormality is determined based on the comparison result. An abnormality factor determination means for determining whether or not the abnormality is a transient abnormality;
By the abnormal factor determination means, when the abnormality is determined to be abnormal transient, and restarting means for restarting the previous SL C PU module,
A programmable controller comprising: The restart means further comprises a restart number recording means for recording the number of times the CPU module is restarted ,
If it exceeds the number of times the number of restarts predetermined said CPU is programmable controller of claim 1, the pre-Symbol C PU module, characterized in that to hang. A CPU module including a CPU for a programmable controller, various memories, and an I / O interface unit; and an I / O module that is connected via the I / O interface unit and controls an external control target device; An error recovery method for a programmable controller that cyclically executes input refresh processing, user program calculation processing, and output refresh processing,
In the memory, when an abnormality is detected in the CPU module or the I / O interface, an occurrence abnormality factor information file that records the cause of the abnormality and a cause of the abnormality that can restart the CPU module are stored. A restartable abnormality factor file, wherein the restartable abnormality factor file includes a restartable abnormality factor file set in advance or changeable via a programming device. And
An operation state determination step for determining whether the state of the CPU module is normal operation, normal stop, or abnormal stop;
In the determination, an abnormality occurs in the CPU module or the I / O module, the cause of the abnormality is recorded in the occurrence abnormality factor information file, and it is determined that the state of the CPU module is abnormally stopped. In this case, the recorded abnormality factor is compared with a plurality of restartable abnormality factors recorded in the restartable abnormality factor file, and the abnormality is determined based on the comparison result. An abnormality factor determination step for determining whether or not the abnormality is a transient abnormality;
If the abnormality factor determination step determines that the abnormality is a transient abnormality, a restarting step of restarting the CPU module;
An abnormality recovery method for a programmable controller, comprising: A restart count recording step for recording the number of restarts of the CPU module by the restart step;
The method of claim 3, further comprising a step of abnormally stopping the CPU module when the number of restarts exceeds a predetermined number .

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