JP6780933B2 - 端子構造、端子構造の製造方法、及び配線基板 - Google Patents
端子構造、端子構造の製造方法、及び配線基板 Download PDFInfo
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- JP6780933B2 JP6780933B2 JP2015247602A JP2015247602A JP6780933B2 JP 6780933 B2 JP6780933 B2 JP 6780933B2 JP 2015247602 A JP2015247602 A JP 2015247602A JP 2015247602 A JP2015247602 A JP 2015247602A JP 6780933 B2 JP6780933 B2 JP 6780933B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 230000001681 protective effect Effects 0.000 claims description 72
- 229910045601 alloy Inorganic materials 0.000 claims description 40
- 239000000956 alloy Substances 0.000 claims description 40
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 29
- 239000010931 gold Substances 0.000 claims description 26
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 21
- 239000010949 copper Substances 0.000 claims description 21
- 238000007747 plating Methods 0.000 claims description 21
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 20
- 238000009713 electroplating Methods 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 9
- 229910052763 palladium Inorganic materials 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- 229910000597 tin-copper alloy Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 315
- 239000002335 surface treatment layer Substances 0.000 description 47
- 229910000679 solder Inorganic materials 0.000 description 23
- 239000000463 material Substances 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 14
- 229920005989 resin Polymers 0.000 description 13
- 239000011347 resin Substances 0.000 description 13
- 239000000758 substrate Substances 0.000 description 13
- 239000007788 liquid Substances 0.000 description 11
- 239000000243 solution Substances 0.000 description 9
- 238000007772 electroless plating Methods 0.000 description 8
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 239000004925 Acrylic resin Substances 0.000 description 4
- 229920000178 Acrylic resin Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229920003986 novolac Polymers 0.000 description 4
- 229920000106 Liquid crystal polymer Polymers 0.000 description 3
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 3
- 229910001128 Sn alloy Inorganic materials 0.000 description 3
- -1 and for example Substances 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 3
- 239000003054 catalyst Substances 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 239000004745 nonwoven fabric Substances 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 2
- 229910020888 Sn-Cu Inorganic materials 0.000 description 2
- 229910019204 Sn—Cu Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 239000004760 aramid Substances 0.000 description 2
- 229920003235 aromatic polyamide Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000012779 reinforcing material Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000002759 woven fabric Substances 0.000 description 2
- KAESVJOAVNADME-UHFFFAOYSA-N 1H-pyrrole Natural products C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- XLJMAIOERFSOGZ-UHFFFAOYSA-M cyanate Chemical compound [O-]C#N XLJMAIOERFSOGZ-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 150000002940 palladium Chemical class 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
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- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/08238—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a bonding area protruding from the surface of the item
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
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- H01L2924/14—Integrated circuits
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- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1437—Static random-access memory [SRAM]
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- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
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- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
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- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
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Description
なお、添付図面は、理解を容易にするために構成要素を拡大して示している場合がある。構成要素の寸法比率は実際のものと、または別の図面中のものと異なる場合がある。また、断面図では、理解を容易にするために、一部の構成要素のハッチングを省略している場合がある。
配線基板10の上面には、半導体素子100を実装するためのバンプ11が形成されている。半導体素子100は、はんだ101によりバンプ11に接続されている。はんだ101は、例えば半導体素子100に形成されたはんだバンプである。配線基板10と半導体素子100との間にはアンダーフィル樹脂102が充填されている。
図2(a)に示すように、配線基板10は、配線基板10の厚さ方向の中心付近に設けられた基板本体20を有している。
先ず、上記の配線基板10に対する比較例を説明する。なお、比較例の部材の材料は、本実施形態と同様のものである。
図4に示すように、まず、バンプ11(図2(a)参照)が形成される前段階の配線基板10を準備する。この配線基板10は、公知の製造方法により製造することが可能であるため、その概略について図4を参照しながら説明する。
図5(a)に示すように、配線層44の上面の一部は、保護絶縁層60に形成された開口部60Xにより露出している。
図6(c)に示すように、例えばフラッシュエッチング液を用いたエッチングにより、電解錫めっき層203をエッチングマスクとして電解錫めっき層203から露出するシード層201を除去する。フラッシュエッチング液としては、例えば硫酸系の溶液(例えば過硫酸アンモニウム水溶液)や過水硫酸系の溶液(硫酸に過酸化水素を混合した溶液)などを用いることができる。
(1)絶縁層43の上面には、配線層44の一部を被覆する保護絶縁層60が積層されている。保護絶縁層60には、配線層44の上面の一部を外部接続パッドP2として露出する開口部60Xが形成されている。最上層の配線層44の上には接続端子としてのバンプ11が形成されている。バンプ11は、保護絶縁層60の開口部60X内において、表面処理層71を介して配線層44と接続されている。バンプ11は、保護絶縁層60の開口部60X内に配置された基部11Aと、保護絶縁層60の上面60Aから上方に突出する接続部11Bとを有している。基部11Aの側面11Cと、保護絶縁層60の開口部60X壁面との間には隙間73が形成されている。
・上記実施形態に対し、各部材の形状、寸法等を適宜変更してもよい。
図7に示すように、配線層44の上面に凹部44Cが形成されている。凹部44Cの周縁部は、保護絶縁層60の下に配置されている。絶縁層43を覆う保護絶縁層60には開口部60Xが形成され、その開口部60Xの下端には内側に向かって突出する突出部60Tが形成されている。表面処理層71は、保護絶縁層60の突出部60Tと配線層44の凹部44Cとの間の隙間を埋めるように形成されている。このように、配線層44に形成した凹部44Cにより、配線層44と保護絶縁層60との間の隙間を埋めるように表面処理層71が形成されることにより、配線層44とバンプ11の間の接続強度を高めることができる。
図8(a)に示すように、保護絶縁層60に開口部60Xを形成する。この工程において、フォトリソグラフィの条件を設定することにより、開口部60Xの下端が裾をひくような形状となる。これにより、開口部60Xの下端に、内側に突出する突出部60Tを有する保護絶縁層60が形成される。次に、図8(b)に示すように、保護絶縁層60の開口部60Xを通して配線層44の上面をエッチングして凹部44Cを形成する。配線層44はたとえば銅または銅合金である場合、エッチング液として、塩化第二銅水溶液、又は塩化第二鉄水溶液などが用いられる。
・上記実施形態において、必要に応じて、図2(a)に示す開口部50Xから露出する配線層34(外部接続用パッドP1)上に表面処理層を形成するようにしてもよい。表面処理層の例としては、金(Au)層、ニッケル(Ni)層/Au層(Ni層とAu層をこの順番で積層した金属層)、Ni層/パラジウム(Pd)層/Au層(Ni層とPd層とAu層をこの順番で積層した金属層)などを挙げることができる。これらAu層、Ni層、Pd層としては、例えば、無電解めっき法により形成された金属層(無電解めっき金属層)を用いることができる。また、Au層はAu又はAu合金からなる金属層、Ni層はNi又はNi合金からなる金属層、Pd層はPd又はPd合金からなる金属層である。また、外部接続用パッドP1の表面に、OSP(Organic Solderability Preservative)処理などの酸化防止処理を施して表面処理層を形成するようにしてもよい。例えば、OSP処理を施した場合には、外部接続用パッドP1の表面に、アゾール化合物やイミダゾール化合物等の有機被膜による表面処理層が形成される。なお、開口部50Xから露出する配線層34(又は、配線層34上に表面処理層が形成されている場合には、その表面処理層)自体を、外部接続端子としてもよい。
11A 基部
11B 接続部
11C 側面
44 配線層
44C 凹部
60 保護絶縁層
60X 開口部
71 表面処理層
72 合金層
73 隙間
Claims (10)
- 配線層と、
前記配線層の一部を被覆し、前記配線層の上面の一部を露出する開口部を有する保護絶縁層と、
前記開口部内に露出する前記配線層上に設けられた金属層と、
前記金属層上に設けられた合金層と、
前記合金層上に設けられた接続端子と、
を有し、
前記金属層の側面は、前記開口部の壁面に接しており、
前記接続端子は、前記開口部内に形成された基部と、前記基部の上に形成され前記保護絶縁層の上面から突出する接続部とを有し、
前記合金層は、錫を含む前記接続端子を形成するために前記金属層の上面に形成されたシード層を形成する金属と前記錫とを含む合金であり、
前記基部の側面と前記開口部の壁面との間に隙間が形成されていること
を特徴とする端子構造。 - 前記金属層と前記基部との間に前記合金層が形成され、前記基部の側面には前記合金層が形成されていないことを特徴とする請求項1に記載の端子構造。
- 前記配線層の上面に凹部が形成され、
前記保護絶縁層は、前記開口部の下端に、内側に向かって突出する突出部を有し、
前記金属層は、前記保護絶縁層の前記突出部と前記配線層の前記凹部との間の隙間を埋めるように形成されたことを特徴とする請求項1又は2に記載の端子構造。 - 前記接続端子は錫を含み、前記配線層は銅または銅合金からなり、前記合金層は、錫−銅合金であることを特徴とする請求項1〜3のいずれか一項に記載の端子構造。
- 前記金属層は、ニッケル層/パラジウム層/金層、金層、又はニッケル層/金層であることを特徴とする請求項1〜4のいずれか一項に記載の端子構造。
- 請求項1〜5のいずれか一項に記載の端子構造を有する配線基板。
- 配線層の一部を被覆し、前記配線層の上面の一部を露出する開口部を有する保護絶縁層を形成する工程と、
前記開口部から露出する前記配線層の上面に、前記開口部の壁面に側面が接する金属層を形成する工程と、
前記金属層上と前記壁面を含む前記保護絶縁層の表面とにシード層を形成する工程と、
前記シード層の上に、前記開口部全体を露出するめっきマスクを形成する工程と、
前記シード層を給電電極とする電解めっき法により、前記めっきマスクから露出する前記シード層上に電解めっき層を形成する工程と、
前記めっきマスクを除去する工程と、
エッチングにより、前記電解めっき層から露出する前記シード層と、前記保護絶縁層と前記電解めっき層の間の前記シード層とを除去する工程と、
前記電解めっき層をリフロー処理して接続端子を形成する工程と、
を有し、
前記接続端子は、前記開口部内に形成された基部と、前記基部の上に形成され前記保護絶縁層の上面から突出する接続部とを有し、前記基部の側面と前記開口部の壁面との間に隙間が形成されていることを特徴とする端子構造の製造方法。 - 前記めっきマスクは、前記開口部内の前記シード層と、前記開口部の周囲の前記シード層を露出し、
前記電解めっき層は、前記開口部内の前記シード層と、前記開口部の周囲の前記シード層との上に形成されることを特徴とする請求項7に記載の端子構造の製造方法。 - 前記エッチングにより、前記開口部の前記壁面と前記電解めっき層との間の前記シード層を除去することを特徴とする請求項7又は8に記載の端子構造の製造方法。
- 前記開口部を形成する工程において、前記開口部の下端に、内側に突出する突出部を形成し、
前記金属層を形成する工程の前に、前記保護絶縁層の前記開口部を通して前記配線層の上面に凹部を形成する工程を有し、
前記金属層を形成する工程において、前記保護絶縁層の前記突出部と前記凹部との間の隙間を埋めるように前記金属層を形成すること、を特徴とする請求項7〜9のいずれか一項に記載の端子構造の製造方法。
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