JP6769322B2 - Semiconductor devices, power supplies and amplifiers - Google Patents

Description

The present invention relates to semiconductor devices, power supply devices and amplifiers.

Nitride semiconductors such as GaN, AlN, InN, and materials made of mixed crystals thereof have a wide bandgap and are used as high-power electronic devices, short-wavelength light emitting devices, and the like. For example, GaN, which is a nitride semiconductor, has a bandgap of 3.4 eV, which is larger than the bandgap of 1.1 eV for Si and 1.4 eV for GaAs.

Examples of such a high-power electronic device include a field effect transistor (FET), particularly a high electron mobility transistor (HEMT) (for example, Patent Document 1). HEMTs using nitride semiconductors are used in high-power, high-efficiency amplifiers, high-power switching devices, and the like. Specifically, in HEMTs in which AlGaN is used as an electron supply layer (barrier layer, for example, a layer made of a material having a smaller electron affinity and a larger bandgap than an electron traveling layer), and GaN is used as an electron traveling layer, AlGaN and GaN are used. Piezopolarization or the like occurs in AlGaN due to the strain due to the difference in lattice constants with, and high-concentration 2DEG (Two-Dimensional Electron Gas) is generated. These material systems can operate at high voltages and can be used for high-efficiency switching elements, high-voltage power devices for electric vehicles, and the like.

In ultra-high frequency devices using nitride semiconductors, in order to realize high output of the device, InAlN or InAlGaN having high spontaneous polarization is used instead of AlGaN as the electron supply layer. When InAlN or InAlGaN is used for the electron supply layer, it is attracting attention as a material having both high output and high frequency because it can induce a high concentration two-dimensional electron gas even if it is thin.

JP-A-2002-359256 Japanese Unexamined Patent Publication No. 2011-60950 JP-A-2010-192771

By the way, since InAlN and InAlGaN have a wide band gap, it is difficult to make ohmic contact, and since the ohmic contact resistance of the ohmic electrode formed on InAlN and InAlGaN is high, the current cannot be increased. Therefore, there is a method of injecting an impurity element such as Si into InAlN or InAlGaN in the region where the ohmic electrode is formed to lower the ohmic contact resistance in the region where the ohmic electrode is formed. However, in this method, for example, since the current is concentrated at the end of the drain electrode serving as the ohmic electrode, damage may occur in this portion, which may lead to a decrease in the reliability of the semiconductor device.

Therefore, in a semiconductor device using a nitride semiconductor, there is a demand for a highly reliable semiconductor device capable of passing a large amount of current.

According to one aspect of the present embodiment, the first semiconductor layer formed on the substrate, the second semiconductor layer formed on the first semiconductor layer, and the second semiconductor layer A drain electrode is formed in the gate electrode formed on the first semiconductor layer, the source electrode and the drain electrode formed on the first semiconductor layer or the second semiconductor layer, and the second semiconductor layer. In the first ion implantation region on the drain side formed in the region and the second on the drain side formed on the gate electrode side of the first ion implantation region on the drain side in the second semiconductor layer. It has an ion implantation region, and the first ion implantation region is doped with Si or Sn, and the second ion implantation region is doped with Ti or W, and the drain side. The drain electrode is formed on the first ion implantation region and the second ion implantation region on the drain side, and the carrier concentration in the first ion implantation region on the drain side is the drain side. It is characterized in that it is higher than the carrier concentration in the second ion implantation region of.

According to the disclosed semiconductor device, a large amount of current can flow, and a semiconductor device using a highly reliable nitride semiconductor can be obtained.

Structural diagram of a semiconductor device using InAlGaN for the electron supply layer (1) Structural diagram of a semiconductor device using InAlGaN for the electron supply layer (2) Structural diagram of the semiconductor device according to the first embodiment Correlation diagram between annealing temperature and contact resistance Explanatory drawing of concentration distribution of impurity element to be ion-implanted (1) Explanatory drawing of concentration distribution of impurity elements to be ion-implanted (2) Correlation diagram of drain voltage and drain current of the semiconductor device according to the first embodiment Correlation diagram of drain voltage and drain current of the semiconductor device shown in FIG. Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (1) Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (2) Process diagram of the method for manufacturing a semiconductor device according to the first embodiment (3) Process diagram (4) of the method for manufacturing a semiconductor device according to the first embodiment. Process diagram (5) of the method for manufacturing a semiconductor device according to the first embodiment. Process diagram (6) of the method for manufacturing a semiconductor device according to the first embodiment. Structural drawing of the semiconductor device of the modified example in the first embodiment Structural diagram of the semiconductor device according to the second embodiment Structural drawing of another semiconductor device according to the second embodiment Correlation diagram of drain voltage and drain current of the semiconductor device in the second embodiment Process diagram of the method for manufacturing a semiconductor device according to the second embodiment (1) Process diagram of a method for manufacturing a semiconductor device according to the second embodiment (2) Process diagram of the method for manufacturing a semiconductor device according to the second embodiment (3) Process diagram (4) of the method for manufacturing a semiconductor device according to the second embodiment. Process diagram (5) of the method for manufacturing a semiconductor device according to the second embodiment. Process diagram (6) of the method for manufacturing a semiconductor device according to the second embodiment. Structural diagram of the semiconductor device according to the third embodiment Correlation diagram of drain voltage and drain current of the semiconductor device according to the third embodiment Explanatory drawing of manufacturing method of semiconductor device in 3rd Embodiment Structural diagram of the semiconductor device according to the fourth embodiment Explanatory drawing of semiconductor device in 5th Embodiment Circuit diagram of the PFC circuit according to the fifth embodiment Circuit diagram of the power supply device according to the fifth embodiment Structural diagram of the high frequency amplifier according to the fifth embodiment

The embodiment for carrying out will be described below. The same members and the like are designated by the same reference numerals and the description thereof will be omitted.

[First Embodiment]
First, a semiconductor device using InAlGaN for the electron supply layer will be described with reference to FIG. As shown in FIG. 1, this semiconductor device is formed on a substrate 910 with a buffer layer (not shown), an electron traveling layer 921 formed of i-GaN, an intermediate layer 922 formed of AlN, and InAlGaN. The electron supply layer 923 is laminated. A gate electrode 931, a source electrode 932, and a drain electrode 933 are formed on the electron supply layer 923. A protective film 940 is formed by SiN or the like on the electron supply layer 923 excluding the region where the gate electrode 931, the source electrode 932, and the drain electrode 933 are formed. The substrate 910 is formed of a semi-insulating SiC substrate, and 2DEG921a is generated in the vicinity of the interface between the electronic traveling layer 921 and the intermediate layer 922 in the electronic traveling layer 921. In the semiconductor device having the structure shown in FIG. 1, since the band gap of InAlGaN forming the electron supply layer 923 is wide, the ohmic contact resistance between the source electrode 932 and the drain electrode 933 formed on the electron supply layer 923 is increased. It gets higher.

Therefore, as shown in FIG. 2, there is a method of ion-implanting an impurity element such as Si into the electron supply layer 923 or the like in the region where the source electrode 932 and the drain electrode 933 are formed to form the ion implantation regions 952 and 953. Conceivable. In this method, the source electrode 932 is formed on the ion implantation region 952 and the drain electrode 933 is formed on the ion implantation region 953, whereby the ohmic contact resistance in the source electrode 932 and the drain electrode 933 can be lowered. it can.

However, in this case, since the on-current concentrates on the end 933a on the gate electrode 931 side of the drain electrode 933 and the end 932a on the gate electrode 931 side of the source electrode 932, these portions are easily destroyed. Become. Further, since the source electrode 932 and the drain electrode 933 are formed by a method such as lift-off, the periphery of the formed source electrode 932 and the drain electrode 933 is not smooth and uneven. If the surroundings of the source electrode 932 and the drain electrode 933 are uneven in this way, for example, the current is concentrated (current concentration) in the region of the drain electrode 933 near the gate electrode 931 side, and damage occurs. Cheap. The fact that the circumference of the drain electrode 933 is uneven means that the end portion 933a of the drain electrode 933 on the gate electrode 931 side has a region close to the gate electrode 931 and a region away from the gate electrode 931 in the vertical direction of the paper surface. It means that you are doing it. In this case, at the end 933a of the drain electrode 933 on the gate electrode 931 side, the current is concentrated in the region close to the gate electrode 931 and damage is likely to occur.

Therefore, there is a demand for a highly reliable semiconductor device that can flow a large amount of current and does not have the above-mentioned current concentration.

(Semiconductor device)
Next, the semiconductor device according to the present embodiment will be described with reference to FIG. As shown in FIG. 3, the semiconductor device according to the present embodiment includes a buffer layer (not shown), an electron traveling layer 21 formed of i-GaN, an intermediate layer 22 formed of AlN, and InAlGaN on a substrate 10, as shown in FIG. The electron supply layer 23 formed by the above is laminated. The electron traveling layer 21 is formed of i-GaN having a thickness of about 1 μm, the intermediate layer 22 is formed of i-AlN having a thickness of about 1 nm, and the electron supply layer 23 has a thickness of about 1 nm. It is formed of 10 nm InAlGaN. A gate electrode 31, a source electrode 32, and a drain electrode 33 are formed on the electron supply layer 23. A protective film 40 is formed by SiN or the like on the electron supply layer 23 excluding the region where the gate electrode 31, the source electrode 32, and the drain electrode 33 are formed.

In the present embodiment, the substrate 10 is formed of a semi-insulating SiC substrate, and 2DEG21a is generated in the electron traveling layer 21 near the interface between the electron traveling layer 21 and the intermediate layer 22. Further, the electron supply layer 23 may be formed of i-In _0.17 Al _0.83 N or the like. In the present embodiment, the electron traveling layer 21 may be referred to as a first semiconductor layer, the electron supply layer 23 may be referred to as a second semiconductor layer, and the intermediate layer 22 may be referred to as a third semiconductor layer.

In the present embodiment, the first ion implantation region 52 and the second ion implantation region 62 are formed by ion-implanting an impurity element into the electron supply layer 23 and the intermediate layer 22 under the source electrode 32. ing. That is, each of the impurity elements is ion-implanted so that the ohmic contact resistance in the second ion implantation region 62 is higher than the ohmic contact resistance in the first ion implantation region 52. Specifically, an impurity element such as Si (silicon) is ion-implanted into the first ion implantation region 52, and an impurity element such as Ti (titanium) is ion-implanted into the second ion implantation region 62. It has been implanted. Therefore, an impurity element having a low ohmic contact resistance is ion-implanted into both the first ion implantation region 52 and the second ion implantation region 62, but the ion-implanted impurity element is the first ion implantation region. The 52 and the second ion implantation region 62 are different.

The second ion implantation region 62 is formed closer to the gate electrode 31 than the first ion implantation region 52. The second ion implantation region 62 is formed so that the end portion 32a of the source electrode 32 on the gate electrode 31 side is located above the second ion implantation region 62. Therefore, the first ion implantation region 52 is a region in which the source electrode 32 is formed, and is formed inside the end portion 32a of the source electrode 32 on the gate electrode 31 side. Therefore, the bottom surface 32b of the source electrode 32 is in contact with a part of the first ion implantation region 52 and the second ion implantation region 62.

Similarly, a first ion implantation region 53 and a second ion implantation region 63 are formed in the electron supply layer 23 and the intermediate layer 22 under the drain electrode 33 by ion implantation of an impurity element. That is, each of the impurity elements is ion-implanted so that the ohmic contact resistance in the second ion implantation region 63 is higher than the ohmic contact resistance in the first ion implantation region 53. Specifically, an impurity element such as Si is ion-implanted into the first ion implantation region 53, and an impurity element such as Ti is ion-implanted into the second ion implantation region 63. Therefore, an impurity element having a low ohmic contact resistance is ion-implanted into the first ion implantation region 53 and the second ion implantation region 63, but the impurity element to be ion-implanted together is the first ion implantation region. The 53 and the second ion implantation region 63 are different.

The second ion implantation region 63 is formed closer to the gate electrode 31 than the first ion implantation region 53. The second ion implantation region 63 is formed so that the end 33a of the drain electrode 33 on the gate electrode 31 side is located above the second ion implantation region 63. Therefore, the first ion implantation region 53 is a region in which the drain electrode 33 is formed, and is formed inside the end portion 33a of the drain electrode 33 on the gate electrode 31 side. Therefore, the bottom surface 33b of the drain electrode 33 is in contact with a part of the first ion implantation region 53 and the second ion implantation region 63.

Therefore, for example, the impurity elements are ion-implanted so that the carrier concentration in the first ion implantation regions 52 and 53 is higher than the carrier concentration in the second ion implantation regions 62 and 63. In the present application, the first ion implantation region 52 may be described as the first ion implantation region on the source side, and the second ion implantation region 62 may be described as the second ion implantation region on the source side. Further, the first ion implantation region 53 may be described as the first ion implantation region on the drain side, and the second ion implantation region 63 may be described as the second ion implantation region on the drain side.

Therefore, in the semiconductor device of the present embodiment, the current flowing from the drain electrode 33 to the first ion implantation region 53 is larger than the current flowing from the drain electrode 33 to the second ion implantation region 63. The boundary between the first ion implantation region 53 and the second ion implantation region 63 is a substantially straight line, is not uneven and is smooth, so that the current concentration is relaxed and a large current flows locally. Can be suppressed. Therefore, damage and the like are less likely to occur, and reliability can be improved.

Similarly, the current flowing from the first ion implantation region 52 to the source electrode 32 is larger than the current flowing from the second ion implantation region 62 to the source electrode 32. The boundary between the first ion implantation region 52 and the second ion implantation region 62 does not protrude or retract like the end portion 32a of the source electrode 32 on the gate electrode 31 side, so that the current concentration is relaxed. Therefore, it is possible to suppress the local flow of a large current. Therefore, damage and the like are less likely to occur, and reliability can be improved. Although the source electrode 32 side is less damaged by the electric field concentration than the drain electrode 33 side, the effect of this configuration can be expected.

In the semiconductor device of the present embodiment, since different impurity elements are implanted in the first ion implantation region 52 and the second ion implantation region 62, the first ion implantation region 52 and the second ion implantation region 52 and the second ion implantation region 52 are implanted. The boundary with the ion implantation region 62 is clear. Similarly, since different impurity elements are ion-implanted in the first ion implantation region 53 and the second ion implantation region 63, the boundary between the first ion implantation region 53 and the second ion implantation region 63. Is clear. Examples of the impurity element ion-implanted into the first ion-implanted regions 52 and 53 include Sn (tin) and the like, and the impurity element ion-implanted into the second ion-implanted regions 62 and 63. Examples thereof include W (tungsten) in addition to Ti.

FIG. 4 shows the annealing temperature and contact resistance _RC after ion implantation for a sample in which an ion implantation region was formed by ion implantation of an impurity element into the nitride semiconductor layer and an electrode was formed on the ion implantation region. The result of examining the relationship between is shown. Specifically, FIG. 4 shows the results of preparing a sample in which Si was implanted in the ion implantation region and a sample in which Ti was implanted, and examining the relationship between the annealing temperature after ion implantation and the contact resistance _RC. is there. When the impurity element to be injected was Si, a sample was prepared by changing the dose amount of Si to 5 × 10 ¹⁴ cm ^-2 , 1 × 10 ¹⁵ cm ^-2 , and 2 × 10 ¹⁵ cm ^-2 . When the impurity element to be injected was Ti, a sample was prepared with the dose amount of Ti set to 2 × 10 ¹⁵ cm- ² . The contact resistance _RC is, for example, a value corresponding to the resistance between the source electrode or drain electrode and 2DEG in the semiconductor device shown in FIGS. 2 and 3.

As a result, when the annealing temperature is about 850 ° C., the contact resistance _RC of the ion-implanted region where Si is implanted is 0.4 to 0.5 Ωmm, and the contact resistance R of the ion-implanted region where Ti is ion-implanted. _C was about 1.4 Ωmm. Therefore, the contact resistance _RC of the ion-implanted region in which Ti is ion-implanted is about 3 to 4 times the contact resistance _RC of the ion-implanted region in which Si is ion-implanted.

In the semiconductor device of the present embodiment, Si is ion-implanted into the first ion implantation regions 52 and 53, and Ti is ion-implanted into the second ion implantation regions 62 and 63. As a result, the contact resistance _{RC of} the second ion implantation regions 62 and 63 is higher than that of the first ion implantation regions 52 and 53. Since the first ion-implanted regions 52 and 53 and the second ion-implanted regions 62 and 63 are ion-implanted with impurity elements, the contact resistance is lower than that in the case where the ions are not implanted.

FIG. 5 shows the concentration distribution of the impurity element ion-implanted into the nitride semiconductor layer. FIG. 5A shows the concentration distribution of ion-implanted Si in the nitride semiconductor layer, and FIG. 5B shows the concentration distribution of ion-implanted Ti in the nitride semiconductor layer. The semiconductor device according to this embodiment is formed so that the concentration of impurity elements is highest on the surface or inside of the electron supply layer 23. Further, the source electrode 32 and the drain electrode 33 are preferably formed so as to be in contact with the region having the highest concentration of impurity elements in order to reduce the contact resistance.

In order to maximize the concentration of impurity elements at a desired depth on the surface or inside of the electron supply layer 23, a dielectric film 71 is formed on the electron supply layer 23 by SiN or the like. , Ion implantation of impurity elements is performed through this dielectric film 71. The dielectric film 71 is formed with a film thickness such that the peak depth of the concentration of the impurity element to be ion-implanted becomes a desired depth. By forming such a dielectric film 71, the concentration distribution of the impurity elements to be ion-implanted becomes the distribution as shown in FIG. FIG. 6A shows the concentration distribution when Si is ion-implanted into the nitride semiconductor layer under the conditions of an accelerating voltage of 3 KeV and a dose amount of 2 × 10 ¹⁵ cm- ² . FIG. 6B shows the concentration distribution when Ti is ion-implanted into the nitride semiconductor layer under the conditions of an accelerating voltage of 7 KeV and a dose amount of 2 × 10 ¹⁵ cm- ² .

Next, the relationship between the drain voltage Vds and the drain current Ids of the semiconductor device in the present embodiment will be described. FIG. 7 shows the relationship between the drain voltage Vds and the drain current Ids of the semiconductor device according to the present embodiment, and FIG. 8 shows the relationship between the drain voltage Vds and the drain current Ids of the semiconductor device having the structure shown in FIG. .. 7 and 8 show the relationship between the drain voltage Vds and the drain current Ids when the gate voltage Vg is changed by 1 V from -3V to + 2V. From FIGS. 7 and 8, when the same gate voltage Vg and the same drain voltage Vds are applied, the semiconductor device according to the present embodiment can flow a larger drain current Ids than the semiconductor device having the structure shown in FIG. ..

(Manufacturing method of semiconductor device)
Next, the method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 9 to 14. In the process diagram of this description, for convenience, the thickness and the like of each layer are described differently from those shown in FIG. 3 and the like, but they do not affect the content of the invention.

First, as shown in FIG. 9A, a buffer layer (not shown), an electron traveling layer 21, an intermediate layer 22, and an electron supply layer 23 are formed on a substrate 10 by epitaxial growth by MOVPE (Metal Organic Vapor Phase Epitaxy). Are sequentially laminated to form. In the present embodiment, the buffer layer (not shown), the electron traveling layer 21, the intermediate layer 22, and the electron supply layer 23 may be described as a nitride semiconductor layer. The electron traveling layer 21 is formed of i-GaN having a thickness of about 1 μm, the intermediate layer 22 is formed of i-AlN having a thickness of about 1 nm, and the electron supply layer 23 has a thickness of about 10 nm. It is formed of InAlGaN. As a result, 2DEG21a is generated in the electron traveling layer 21 near the interface between the electron traveling layer 21 and the intermediate layer 22. A semi-insulating SiC substrate is used for the substrate 10, and a buffer layer (not shown) is formed of GaN, AlGaN, or the like.

Next, as shown in FIG. 9B, the device separation region 70 is formed in the nitride semiconductor layer formed on the substrate 10. Specifically, by applying a photoresist on the electron supply layer 23 and performing exposure and development with an exposure apparatus, a resist pattern (not shown) having an opening in a region where the element separation region 70 is formed is formed. Form. After that, the device separation region 70 is formed by ion-implanting ions such as Ar into the nitride semiconductor layer at the opening of the resist pattern. When forming the element separation region 70, ions such as Ar may be injected into a part of the substrate 10. After that, the resist pattern (not shown) is removed with an organic solvent or the like.

Next, as shown in FIG. 9C, a dielectric film 71 is formed on the electron supply layer 23. The dielectric film 71 is formed so that the peak concentration of the impurity element ion-implanted into the nitride semiconductor layer has a desired depth. Therefore, even if the dielectric film 71 is not formed, it is not necessary to form the dielectric film 71 as long as the peak concentration of the impurity element to be ion-implanted reaches the desired depth of the nitride semiconductor layer. This step is unnecessary. In the present embodiment, the dielectric film 71 is formed by forming a SiN film having a film thickness of about 20 nm by plasma CVD (Chemical Vapor Deposition) using silane and ammonia or nitrogen as raw materials.

Next, as shown in FIG. 10A, a resist pattern 72 serving as an ion implantation mask for forming the first ion implantation regions 52 and 53 is formed on the dielectric film 71. Specifically, by applying a photoresist on the dielectric film 71 and performing exposure and development with an exposure apparatus, the openings 72a and 72b are formed in the regions where the first ion implantation regions 52 and 53 are formed. The resist pattern 72 having the above is formed.

Next, as shown in FIG. 10B, the first ion implantation region 52 is formed by ion-implanting Si into the nitride semiconductor layer under the conditions of an acceleration voltage of 3 KeV and a dose amount of 2 × 10 ¹⁵ cm- ^2. And 53 are formed. The first ion implantation regions 52 and 53 are formed by ion implantation so that the interface between the electron supply layer 23 and the dielectric film 71 becomes the peak of the Si concentration.

Next, as shown in FIG. 10C, after removing the resist pattern 72 with an organic solvent or the like, an ion implantation mask for forming the second ion implantation regions 62 and 63 on the dielectric film 71. The resist pattern 73 is formed. Specifically, by applying a photoresist on the dielectric film 71 and performing exposure and development with an exposure apparatus, the openings 73a and 73b are formed in the regions where the second ion implantation regions 62 and 63 are formed. The resist pattern 73 having the above is formed. The width of the openings 73a and 73b of the resist pattern 73 is about 0.5 μm.

Next, as shown in FIG. 11A, the second ion implantation region 62 is formed by ion-implanting Ti into the nitride semiconductor layer under the conditions of an accelerating voltage of 7 KeV and a dose amount of 2 × 10 ¹⁵ cm- ^2. And 63 are formed. The second ion implantation regions 62 and 63 are formed by ion implantation so that the concentration of Ti peaks at the interface between the electron supply layer 23 and the dielectric film 71. As a result, the second ion implantation region 62 is formed in contact with the first ion implantation region 52, and the second ion implantation region 63 is formed in contact with the first ion implantation region 53.

Next, as shown in FIG. 11B, the resist pattern 73 was removed with an organic solvent or the like, and then heat-treated at a temperature of 850 ° C. for 1 minute in an inert gas atmosphere to inject the impurity elements. Activates the ions of. As a result, donors are formed in the first ion implantation regions 52 and 53 and the second ion implantation regions 62 and 63, and the electron density increases. Although the case where the dielectric film 71 is used as a protective film for activation annealing has been described here, the dielectric film 71 is removed after ion implantation, and protection for activation annealing is performed again. After forming the film with SiN or the like, activation annealing may be performed.

Next, as shown in FIG. 11C, the dielectric film 71 is removed. Specifically, the dielectric film 71 formed of SiN or the like is removed by hydrofluoric acid or the like to expose the surface of the electron supply layer 23 or the like.

Next, as shown in FIG. 12A, a resist pattern 74 having openings 74a and 74b is formed on the electron supply layer 23 in the region where the source electrode 32 and the drain electrode 33 are formed. The resist pattern 74 is formed so that the regions where the source electrode 32 and the drain electrode 33 are formed are the openings 74a and 74b. That is, the resist pattern 74 is formed so that a part of the first ion implantation region 52 and the second ion implantation region 62 in which the source electrode 32 is formed becomes the opening 74a. Further, a part of the first ion implantation region 53 and the second ion implantation region 63 in which the drain electrode 33 is formed is formed so as to be an opening 74b.

Next, as shown in FIG. 12B, a source electrode 32 is formed on a part of the first ion implantation region 52 and the second ion implantation region 62, and the first ion implantation region 53 and the first ion implantation region 53 and the second ion implantation region 53 are formed. The drain electrode 33 is formed on a part of the ion implantation region 63 of 2. Specifically, a metal multilayer film made of Ti / Al is formed on the surface on which the resist pattern 74 is formed by vacuum deposition, and then immersed in an organic solvent or the like to be formed on the resist pattern 74. The metal multilayer film is removed together with the resist pattern 74 by lift-off. As a result, the source electrode 32 and the drain electrode 33 are formed by the metal multilayer film remaining in the region where the openings 74a and 74b of the resist pattern 74 were formed. After that, by performing heat treatment at a temperature of 550 ° C., an ohmic contact between the first ion implantation regions 52 and 53, a part of the second ion implantation regions 62 and 63, and the source electrode 32 and the drain electrode 33 is performed. To establish. The metal multilayer film formed in this step is a film in which a Ti film having a film thickness of about 20 nm and an Al film having a film thickness of about 200 nm are laminated in this order on a nitride semiconductor layer.

Next, as shown in FIG. 12C, a protective film 40 is formed on the electron supply layer 23, the source electrode 32, and the drain electrode 33. Specifically, it is formed by forming a SiN film having a film thickness of about 50 nm using silane and ammonia or nitrogen as raw materials by plasma CVD.

Next, as shown in FIG. 13A, a resist pattern 75 having an opening 75a is formed in the region where the gate electrode 31 is formed.

Next, as shown in FIG. 13B, the protective film 40 in the opening 75a of the resist pattern 75 is removed by dry etching using SF ₆ as an etching gas to form the opening 40a, and electrons are formed. The supply layer 23 is exposed. After that, the resist pattern 75 is removed with an organic solvent or the like.

Next, as shown in FIG. 13C, a resist pattern 76 for forming the gate electrode 31 is formed on the protective film 40. The resist pattern 76 is formed by three laminated electron beam resist layers, and has an opening 76a in a region where the gate electrode 31 is formed. Specifically, a three-layer electron beam resist layer is formed by repeatedly applying an electron beam resist or the like on the protective film 40, and drawing and development by an electron beam drawing apparatus are repeated to form the three layers. An opening 76a is formed in the electron beam resist layer. As a result, a resist pattern 76 having an opening 76a is formed.

Next, as shown in FIG. 14, the gate electrode 31 is formed on the electron supply layer 23 in the opening 40a of the protective film 40. Specifically, a metal multilayer film made of Ni / Au is formed on the surface on which the resist pattern 76 is formed by vacuum deposition, and then immersed in an organic solvent or the like to be formed on the resist pattern 76. The metal multilayer film is removed together with the resist pattern 76 by lift-off. As a result, the gate electrode 31 is formed by the metal multilayer film remaining in the region where the opening 76a of the resist pattern 76 was formed. The metal multilayer film formed in this step is a film in which a Ni film having a film thickness of about 10 nm and an Au film having a film thickness of about 300 nm are laminated in this order on a nitride semiconductor layer.

Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

(Modification example)
In this embodiment, as shown in FIG. 15, a second ion implantation region 63 is formed in the nitride semiconductor layer under the drain electrode 33, but the nitride semiconductor layer under the source electrode 32 is formed. May be a semiconductor device having a structure in which a second ion implantation region is not formed. Since a high voltage is applied to the drain electrode 33, an electric field is particularly likely to be concentrated on the end 33a of the drain electrode 33 on the gate electrode 31 side. Therefore, if the second ion implantation region 63 is formed in the nitride semiconductor layer under the end 33a on the gate electrode 31 side of the drain electrode 33, the electric field concentration can be relaxed. However, if current concentration is also taken into consideration, as shown in FIG. 3, a semiconductor device having a structure in which the second ion implantation region 62 is also provided on the source electrode 32 side is more reliable from the viewpoint of reliability. Is preferable.

[Second Embodiment]
Next, a second embodiment will be described. As shown in FIG. 16, the present embodiment has a structure in which a recess is formed by partially removing the electron supply layer 23 in the region where the source electrode 32 and the drain electrode 33 are formed and forming a recess. is there. By forming the recess and forming the source electrode 32 and the drain electrode 33 in this way, the contact resistance in the source electrode 32 and the drain electrode 33 can be lowered.

In a nitride semiconductor device using InAlGaN for the electron supply layer 23, the DEG 21a is generated by piezo polarization and spontaneous polarization. Therefore, even if the electron supply layer 23 is thinned, the 2DEG 21a generated in the electron traveling layer 21 is generated. , Can be maintained in a certain amount.

Further, by making the electron supply layer 23 thicker, it is possible to increase the amount of 2DEG21a generated in the electron traveling layer 21. Therefore, as shown in FIG. 17, the electron supply layer 23 is formed of InAlGaN having a thickness of about 15 nm, and the recess of the electron supply layer 23 where the source electrode 32 and the drain electrode 33 are formed has a depth of about 5 nm. May be formed. Also in this embodiment, the concentration of the impurity element in the first ion implantation regions 52 and 53 is ion-implanted so that the portion in contact with the source electrode 32 and the drain electrode 33 peaks.

In the present embodiment, the vicinity of the end 32a of the bottom surface 32b of the source electrode 32 on the gate electrode 31 side and the side surface 32c of the source electrode 32 are in contact with the second ion implantation region 62. Further, the bottom surface of the bottom surface 33b of the drain electrode 33 near the end 33a on the gate electrode 31 side and the side surface 33c of the drain electrode 33 are in contact with the second ion implantation region 63. Therefore, even if a recess is formed in the region where the source electrode 32 and the drain electrode 33 are formed, the electric field at the end 32a of the source electrode 32 on the gate electrode 31 side and the end 33a of the drain electrode 33 on the gate electrode 31 side. Concentration and current concentration can be suppressed.

Next, the relationship between the drain voltage Vds and the drain current Ids of the semiconductor device in the present embodiment will be described. FIG. 18 shows the relationship between the drain voltage Vds and the drain current Ids of the semiconductor device according to the present embodiment. FIG. 18 shows the relationship between the drain voltage Vds and the drain current Ids when the gate voltage Vg is changed by 1 V from -3V to + 2V. As shown in FIG. 18, when the same gate voltage Vg and the same drain voltage Vds are applied, the semiconductor device according to the present embodiment may have a larger drain current Ids than the semiconductor device having the structure shown in FIG. it can. Further, as compared with the semiconductor device according to the first embodiment shown in FIG. 7, when the same gate voltage Vg and the same drain voltage Vds are applied, the semiconductor device according to the present embodiment has a drain current Ids. You can shed a lot.

(Manufacturing method of semiconductor device)
Next, the method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 19 to 24. In the process diagram of this description, for convenience, the thickness and the like of each layer are described differently from those shown in FIGS. 16 and 17, but the contents of the invention are not affected.

First, as shown in FIG. 19A, a buffer layer (not shown), an electron traveling layer 21, an intermediate layer 22, and an electron supply layer 23 are sequentially laminated on the substrate 10 by epitaxial growth by MOVPE. ..

Next, as shown in FIG. 19B, the element separation region 70 is formed in the nitride semiconductor layer formed on the substrate 10.

Next, as shown in FIG. 19C, a dielectric film 71 is formed on the electron supply layer 23. The dielectric film 71 is formed so that the peak concentration of the impurity element ion-implanted into the nitride semiconductor layer has a desired depth.

Next, as shown in FIG. 20A, a resist pattern 72 serving as an ion implantation mask for forming the first ion implantation regions 52 and 53 is formed on the dielectric film 71.

Next, as shown in FIG. 20B, the first ion implantation region 52 is formed by ion-implanting Si into the nitride semiconductor layer under the conditions of an acceleration voltage of 3 KeV and a dose amount of 2 × 10 ¹⁵ cm- ^2. And 53 are formed.

Next, as shown in FIG. 20C, after removing the resist pattern 72 with an organic solvent or the like, an ion implantation mask for forming the second ion implantation regions 62 and 63 on the dielectric film 71. The resist pattern 73 is formed.

Next, as shown in FIG. 21 (a), the second ion implantation region 62 is formed by ion-implanting Ti into the nitride semiconductor layer under the conditions of an acceleration voltage of 7 KeV and a dose amount of 2 × 10 ¹⁵ cm- ^2. And 63 are formed.

Next, as shown in FIG. 21B, the resist pattern 73 was removed with an organic solvent or the like, and then heat-treated at a temperature of 850 ° C. for 1 minute in an inert gas atmosphere to inject the impurity elements. Activates the ions of.

Next, as shown in FIG. 21 (c), the dielectric film 71 is removed. Specifically, the dielectric film 71 formed of SiN or the like is removed by hydrofluoric acid or the like to expose the surface of the electron supply layer 23 or the like.

Next, as shown in FIG. 22A, a resist pattern 74 having openings 74a and 74b is formed on the electron supply layer 23 in the region where the source electrode 32 and the drain electrode 33 are formed, and the recess 132 is formed. 133 is formed. In the resist pattern 74, the regions where the source electrode 32 and the drain electrode 33 are formed, that is, the first ion implantation regions 52 and 53 and a part of the second ion implantation regions 62 and 63 are the openings 74a and 74b. It is formed so as to be. The recesses 132 and 133 are formed by removing the electron supply layer 23 in the openings 74a and 74b of the resist pattern 74 by RIE or the like so as to have a depth of, for example, about 5 nm. The recess 132 is formed in a part of the first ion implantation region 52 and the second ion implantation region 62 in which the source electrode 32 is formed, and the recess 133 is formed in the first ion implantation region 53 in which the drain electrode 33 is formed. It is formed in a part of the second ion implantation region 63.

Next, as shown in FIG. 22B, the source electrode 32 and the drain electrode 33 are formed by lift-off. As a result, the source electrode 32 is formed on a part of the first ion implantation region 52 and the second ion implantation region 62 in which the recess 132 is formed. Similarly, the drain electrode 33 is formed on a part of the first ion implantation region 53 and the second ion implantation region 63 in which the recess 133 is formed.

Next, as shown in FIG. 22C, a protective film 40 is formed on the electron supply layer 23, the source electrode 32, and the drain electrode 33.

Next, as shown in FIG. 23A, a resist pattern 75 having an opening 75a is formed in the region where the gate electrode 31 is formed.

Next, as shown in FIG. 23 (b), the opening 40a is formed by removing the protective film 40 in the opening 75a of the resist pattern 75 by dry etching using SF ₆ as an etching gas, and electrons are formed. The supply layer 23 is exposed.

Next, as shown in FIG. 23C, a resist pattern 76 for forming the gate electrode 31 is formed on the protective film 40.

Next, as shown in FIG. 24, the gate electrode 31 is formed by lift-off on the electron supply layer 23 in the opening 40a of the protective film 40.

Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

The contents other than the above are the same as those in the first embodiment.

[Third Embodiment]
Next, a third embodiment will be described. As shown in FIG. 25, the present embodiment is a semiconductor device having a structure in which a gate recess is formed by forming a recess in a region where the gate electrode 31 is formed, and the gate electrode 31 is formed. In this way, the thickness of the electron supply layer 23 is increased in order to increase the density of 2DEG21a by forming the gate recess in the region where the gate electrode 31 is formed and forming the gate electrode 31 in the region where the gate recess is formed. Even if the thickness is increased, it is possible to suppress the deterioration of the frequency characteristics.

Next, the relationship between the drain voltage Vds and the drain current Ids of the semiconductor device in the present embodiment will be described. FIG. 26 shows the relationship between the drain voltage Vds and the drain current Ids of the semiconductor device according to the present embodiment. FIG. 26 shows the relationship between the drain voltage Vds and the drain current Ids when the gate voltage Vg is changed by 1 V from -3V to + 2V. As shown in FIG. 26, when the same gate voltage Vg and the same drain voltage Vds are applied, the semiconductor device according to the present embodiment may have a larger drain current Ids than the semiconductor device having the structure shown in FIG. it can.

(Manufacturing method of semiconductor device)
Next, a method of manufacturing the semiconductor device according to the present embodiment will be described. Since the steps shown in FIGS. 19 (a) to 23 (a) of the method of manufacturing the semiconductor device of the second embodiment are the same as the method of manufacturing the semiconductor device in the present embodiment, the description thereof will be omitted. The steps after FIG. 23A will be described. In the process diagram of this description, for convenience, the thickness and the like of each layer are described differently from those shown in FIG. 25 and the like, but they do not affect the content of the invention.

After the step shown in FIG. 23 (a), as shown in FIG. 27 (a), the protective film 40 in the opening 75a of the resist pattern 75 is removed to form the opening 40a, and further, the electron supply layer 23 is formed. The gate recess 131 is formed by removing a part of the above. After that, the resist pattern 75 is removed with an organic solvent or the like.

Next, as shown in FIG. 27 (b), a resist pattern 76 for forming the gate electrode 31 is formed on the protective film 40.

Next, as shown in FIG. 27 (c), the gate electrode 31 is formed by lift-off on the electron supply layer 23 on which the gate recess 131 is formed in the opening 40a of the protective film 40.

Through the above steps, the semiconductor device according to the present embodiment can be manufactured.

The contents other than the above are the same as those in the second embodiment.

[Fourth Embodiment]
Next, a fourth embodiment will be described. In this embodiment, as shown in FIG. 28, the impurity elements ion-implanted into the first ion-implanted regions 152 and 153 and the second ion-implanted regions 162 and 163 are the same but have different concentrations. is there. When the concentration of ions to be implanted is changed, the contact resistance also changes. Therefore, Ti is ion-implanted into the first ion implantation regions 152 and 153 under the conditions of an accelerating voltage of 7 KeV and a dose amount of 5 × 10 ¹⁵ cm- ² . Further, Ti is ion-implanted into the second ion implantation regions 162 and 163 under the conditions of an acceleration voltage of 7 KeV and a dose amount of 2 × 10 ¹⁵ cm- ² . In general, the higher the impurity concentration in the nitride semiconductor layer, the lower the contact resistance. Therefore, the ions are implanted so that the impurity concentration of Ti, which is an impurity element, is lower in the second ion implantation regions 162 and 163 than in the first ion implantation regions 152 and 153.

The contents other than the above are the same as those in the first embodiment.

[Fifth Embodiment]
Next, a fifth embodiment will be described. The present embodiment is a semiconductor device, a power supply device, and a high frequency amplifier.

(Semiconductor device)
The semiconductor device according to the present embodiment is a discrete package of the semiconductor devices according to the first to fourth embodiments, and the semiconductor device discretely packaged in this way will be described with reference to FIG. 29. Note that FIG. 29 schematically shows the inside of the discretely packaged semiconductor device, and the arrangement of the electrodes and the like are different from those shown in the first to fourth embodiments. There is.

First, a HEMT semiconductor chip 410 made of a GaN-based semiconductor material is formed by cutting the semiconductor device manufactured in the first to fourth embodiments by dicing or the like. The semiconductor chip 410 is fixed on the lead frame 420 with a die-attaching agent 430 such as solder. The semiconductor chip 410 corresponds to the semiconductor device according to the first to fourth embodiments.

Next, the gate electrode 411 is connected to the gate lead 421 by the bonding wire 431, the source electrode 421 is connected to the source lead 422 by the bonding wire 432, and the drain electrode 413 is connected to the drain lead 423 by the bonding wire 433. The bonding wires 431, 432, and 433 are made of a metal material such as Al. Further, in the present embodiment, the gate electrode 411 is a kind of gate electrode pad and is connected to the gate electrode 31 of the semiconductor device according to the first to fourth embodiments. Further, the source electrode 412 is a kind of source electrode pad, and is connected to the source electrode 32 of the semiconductor device according to the first to fourth embodiments. Further, the drain electrode 413 is a kind of drain electrode pad, and is connected to the drain electrode 33 of the semiconductor device according to the first to fourth embodiments.

Next, the resin is sealed with the mold resin 440 by the transfer molding method. In this way, a discretely packaged semiconductor device of HEMT using a GaN-based semiconductor material can be manufactured.

(PFC circuit, power supply and high frequency amplifier)
Next, the PFC circuit, the power supply device, and the high frequency amplifier in the present embodiment will be described. The PFC circuit, power supply device, and high-frequency amplifier in the present embodiment are a power supply device and a high-frequency amplifier using any of the semiconductor devices in the first to fourth embodiments.

(PFC circuit)
Next, the PFC (Power Factor Correction) circuit in the present embodiment will be described. The PFC circuit according to the present embodiment includes the semiconductor device according to the first to fourth embodiments.

The PFC circuit according to the present embodiment will be described with reference to FIG. The PFC circuit 450 in this embodiment includes a switch element (transistor) 451, a diode 452, a choke coil 453, capacitors 454 and 455, a diode bridge 456, and an AC power supply (not shown). As the switch element 451, HEMT, which is a semiconductor device according to the first to fourth embodiments, is used.

In the PFC circuit 450, the drain electrode of the switch element 451, the anode terminal of the diode 452, and one terminal of the choke coil 453 are connected. Further, the source electrode of the switch element 451 and one terminal of the capacitor 454 and one terminal of the capacitor 455 are connected, and the other terminal of the capacitor 454 and the other terminal of the choke coil 453 are connected. The other terminal of the capacitor 455 and the cathode terminal of the diode 452 are connected, and an AC power supply (not shown) is connected between both terminals of the capacitor 454 via a diode bridge 456. In such a PFC circuit 450, direct current (DC) is output from both terminals of the capacitor 455.

(Power supply)
Next, the power supply device according to the present embodiment will be described. The power supply device according to the present embodiment is a power supply device having a HEMT which is a semiconductor device according to the first to fourth embodiments.

The power supply device according to the present embodiment will be described with reference to FIG. 31. The power supply device according to the present embodiment has a structure including the PFC circuit 450 according to the above-described embodiment.

The power supply device according to the present embodiment has a high-voltage primary side circuit 461 and a low-voltage secondary side circuit 462, and a transformer 463 arranged between the primary side circuit 461 and the secondary side circuit 462. There is.

The primary side circuit 461 has an inverter circuit connected between the terminals of both the PFC circuit 450 and the capacitor 455 of the PFC circuit 450 according to the present embodiment described above, for example, the full bridge inverter circuit 460. The full-bridge inverter circuit 460 has a plurality of (four in this case) switch elements 464a, 464b, 464c, and 464d. Further, the secondary side circuit 462 has a plurality of (three in this case) switch elements 465a, 465b, and 465c. An AC power supply 457 is connected to the diode bridge 456.

In the present embodiment, in the switch element 451 of the PFC circuit 450 in the primary side circuit 461, the HEMT which is the semiconductor device in the first to fourth embodiments is used. Further, in the switch elements 464a, 464b, 464c, and 464d in the full bridge inverter circuit 460, HEMT, which is a semiconductor device according to the first to fourth embodiments, is used. On the other hand, as the switch elements 465a, 465b, and 465c of the secondary side circuit 462, FETs having a normal MIS structure using silicon or the like are used.

(High frequency amplifier)
Next, the high frequency amplifier in this embodiment will be described. The high-frequency amplifier in the present embodiment has a structure in which HEMT, which is a semiconductor device in the first to fourth embodiments, is used.

A high frequency amplifier according to the present embodiment will be described with reference to FIG. 32. The high frequency amplifier 470 in this embodiment includes a digital predistortion circuit 471, mixers 472a and 472b, a power amplifier 473, and a directional coupler 474.

The digital pre-distortion circuit 471 compensates for the non-linear distortion of the input signal. The mixer 472a mixes the input signal and the AC signal in which the non-linear distortion is compensated. The power amplifier 473 amplifies the input signal mixed with the AC signal, and has HEMT which is a semiconductor device according to the first to fourth embodiments. The directional coupler 474 monitors the input signal and the output signal. In FIG. 32, for example, by switching the switch, the output side signal can be mixed with the AC signal by the mixer 472b and transmitted to the digital predistortion circuit 471.

Although the embodiments have been described in detail above, the embodiments are not limited to the specific embodiments, and various modifications and changes can be made within the scope of the claims.

Regarding the above explanation, the following additional notes are further disclosed.
(Appendix 1)
The first semiconductor layer formed on the substrate and
A second semiconductor layer formed on the first semiconductor layer and
The gate electrode formed on the second semiconductor layer and
A source electrode and a drain electrode formed on the first semiconductor layer or the second semiconductor layer,
In the second semiconductor layer, a first ion implantation region on the drain side formed in a region where a drain electrode is formed, and a first ion implantation region on the drain side.
In the second semiconductor layer, a second ion implantation region on the drain side formed on the gate electrode side of the first ion implantation region on the drain side, and
Have,
The drain electrode is formed on the first ion implantation region on the drain side and the second ion implantation region on the drain side.
A semiconductor device characterized in that the carrier concentration in the first ion implantation region on the drain side is higher than the carrier concentration in the second ion implantation region on the drain side.
(Appendix 2)
The semiconductor device according to Appendix 1, wherein the end of the drain electrode on the gate electrode side is located above the second ion implantation region on the drain side.
(Appendix 3)
A recess is formed in the second semiconductor layer in the region where the drain electrode is formed.
The semiconductor device according to Appendix 1 or 2, wherein the side surface of the drain electrode on the gate electrode side is in contact with the second ion implantation region on the drain side.
(Appendix 4)
In the second semiconductor layer, the first ion implantation region on the source side formed in the region where the source electrode is formed, and
In the second semiconductor layer, a second ion implantation region on the source side formed on the gate electrode side of the first ion implantation region on the source side, and
Have,
The source electrode is formed on the first ion implantation region on the source side and the second ion implantation region on the source side.
The semiconductor device according to any one of Supplementary note 1 to 3, wherein the carrier concentration in the first ion implantation region on the source side is higher than the carrier concentration in the second ion implantation region on the source side.
(Appendix 5)
The semiconductor device according to Appendix 4, wherein the end of the source electrode on the gate electrode side is located above the second ion implantation region on the source side.
(Appendix 6)
A recess is formed in the second semiconductor layer in the region where the source electrode is formed.
The semiconductor device according to Appendix 4 or 5, wherein the side surface of the source electrode on the gate electrode side is in contact with the second ion implantation region on the source side.
(Appendix 7)
The semiconductor device according to any one of Supplementary note 1 to 6, wherein the first semiconductor layer and the second semiconductor layer are formed of a nitride semiconductor.
(Appendix 8)
The first semiconductor layer is formed of a material containing InAlN or InAlGaN.
The semiconductor device according to any one of Appendix 1 to 6, wherein the second semiconductor layer is formed of a material containing GaN.
(Appendix 9)
The first ion implantation region is doped with Si or Sn.
The semiconductor device according to any one of Supplementary note 1 to 8, wherein the second ion implantation region is doped with Ti or W.
(Appendix 10)
A gate recess is formed in the region of the second semiconductor layer where the gate electrode is formed by removing a part of the second semiconductor layer.
The semiconductor device according to any one of Appendix 1 to 9, wherein the gate electrode is formed on the second semiconductor layer of the gate recess.
(Appendix 11)
A power supply device comprising the semiconductor device according to any one of Appendix 1 to 10.
(Appendix 12)
An amplifier comprising the semiconductor device according to any one of Appendix 1 to 10.

10 Substrate 21 Electronic traveling layer (first semiconductor layer)
21a 2DEG
22 Intermediate layer (third semiconductor layer)
23 Electronic supply layer (second semiconductor layer)
31 Gate electrode 32 Source electrode 32a Gate electrode side end 32b Bottom surface 32c Side surface 33 Drain electrode 33a Gate electrode side end 33b Bottom surface 33c Side surface 40 Protective film 52 First ion implantation region (first ion implantation on the source side) region)
53 First ion implantation region (first ion implantation region on the drain side)
62 Second ion implantation region (second ion implantation region on the source side)
63 Second ion implantation region (second ion implantation region on the drain side)

Claims (9)

The first semiconductor layer formed on the substrate and
A second semiconductor layer formed on the first semiconductor layer and
The gate electrode formed on the second semiconductor layer and
A source electrode and a drain electrode formed on the first semiconductor layer or the second semiconductor layer,
In the second semiconductor layer, the first ion implantation region on the drain side formed in the region where the drain electrode is formed, and the first ion implantation region on the drain side.
In the second semiconductor layer, a second ion implantation region on the drain side formed on the gate electrode side of the first ion implantation region on the drain side, and
Have,
The first ion implantation region is doped with Si or Sn.
The second ion implantation region is doped with Ti or W.
The drain electrode is formed on the first ion implantation region on the drain side and the second ion implantation region on the drain side.
A semiconductor device characterized in that the carrier concentration in the first ion implantation region on the drain side is higher than the carrier concentration in the second ion implantation region on the drain side. The semiconductor device according to claim 1, wherein the end of the drain electrode on the gate electrode side is located above the second ion implantation region on the drain side. A recess is formed in the second semiconductor layer in the region where the drain electrode is formed.
The semiconductor device according to claim 1 or 2, wherein the side surface of the drain electrode on the gate electrode side is in contact with the second ion implantation region on the drain side. In the second semiconductor layer, the first ion implantation region on the source side formed in the region where the source electrode is formed, and
In the second semiconductor layer, a second ion implantation region on the source side formed on the gate electrode side of the first ion implantation region on the source side, and
Have,
The source electrode is formed on the first ion implantation region on the source side and the second ion implantation region on the source side.
The semiconductor device according to any one of claims 1 to 3, wherein the carrier concentration in the first ion implantation region on the source side is higher than the carrier concentration in the second ion implantation region on the source side. The semiconductor device according to claim 4, wherein the end of the source electrode on the gate electrode side is located above the second ion implantation region on the source side. A recess is formed in the second semiconductor layer in the region where the source electrode is formed.
The semiconductor device according to claim 4 or 5, wherein the side surface of the source electrode on the gate electrode side is in contact with the second ion implantation region on the source side. The second semiconductor layer is formed of a material containing InAlN or InAlGaN.
The semiconductor device according to any one of claims 1 to 6, wherein the first semiconductor layer is formed of a material containing GaN. A power supply device comprising the semiconductor device according to any one of claims 1 to 7 . An amplifier comprising the semiconductor device according to any one of claims 1 to 7 .

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