JP6763716B2 - Load current detection circuit - Google Patents

Description

The present invention relates to a load current detection circuit that detects a load current of a load drive circuit that drives a load.

As the load current detection circuit for detecting the load current of the load drive circuit that drives the load, the circuit shown in FIG. 5 (FIG. 6 of Patent Document 1 and FIG. 1 of Patent Document 2) is generally used. Further, as a circuit using a depletion type transistor as a constant current source, the circuit shown in FIG. 6 (FIG. 2 of Patent Document 1) is known.

In the load current detection circuit 20A shown in FIG. 5, 21 is a load drive control circuit, 22 is a voltage VDD power supply terminal, 23 is a ground terminal, 24 is an output terminal, 25 is a load, 26 is a determination circuit (not shown), and the like. Is a load current detection terminal to which is connected, 27 is a current source, and 28 is an operational amplifier. Further, M21, M22, M23, M24, and M25 are enhancement type NMOS transistors.

In the transistor M21 whose ON / OFF control is controlled by the load drive control circuit 21, the drain is connected to the power supply terminal 22 and the source is connected to the output terminal 24. A load 25 is connected between the output terminal 24 and the ground terminal 23. That is, the transistor M21 constitutes a load drive circuit.

Like the transistor M21, the transistor M22 is also ON / OFF controlled by the load drive control circuit 21, the drain is connected to the power supply terminal 22, and the source is connected to the drain of the transistor M23. The gate of the transistor M23 is connected to the output terminal of the operational amplifier 28, the non-inverting input terminal of the operational amplifier 28 is connected to the node N1 which is the drain of the transistor M23, and the inverting input terminal is connected to the output terminal 24. Further, the source of the transistor M23 is connected to the drain and the gate of the transistor M24 and the gate of the transistor M25. Further, a current source 27 is connected between the drain of the transistor M25 and the power supply terminal 22, and a load current detection terminal 26 is connected to the drain of the transistor M25.

In the load current detection circuit 20A, when the size ratio of the transistors M22 and M21 is set to, for example, 1: 1000, the transistor M21 is controlled to be ON by the load drive control circuit 22 and a voltage is supplied to the load 25. The transistor M22 is also controlled to be ON at the same time, and a current 1/1000 of the drain current of the transistor M21 flows through the drain. The voltage Vs of the node N1 at the common connection point between the source of the transistor M22 and the drain of the transistor M23 is controlled so as to match the voltage Vout of the output terminal 24 by the feedback operation of the operational amplifier 28 and the transistor M23.

Then, the current Id25 flowing through the drain of the transistor M25 due to the voltage Vs of the node N1 when the voltage Vout of the output terminal 24 is a normal value is set in advance so that I27> Id25 with respect to the current I27 of the current source 27. Then, when the load current flowing through the load 25 is normal, the voltage Vout = Vs shows a normal value, so that the relationship of I27> Id25 is maintained and the logic of the load current detection terminal 26 becomes “H”.

However, when the load current flowing through the load 25 increases, the voltage Vout = Vs increases, and the drain current Id25 of the transistor M25 increases. When I27 <Id25, the logic of the load current detection terminal 26 becomes “L”, indicating that an overcurrent has occurred in the load 25.

On the other hand, in the load current detection circuit 20B shown in FIG. 6, a detection resistor R2 is connected between the source of the transistor M22 of the load current detection circuit 20A described in FIG. 5 and the output terminal 24. Then, the depletion type NMOS transistors M28 and M29, in which the gate and the source are commonly connected, are used as a constant current source, and their drains are connected to the power supply terminal 22, and the source of the transistor M28 is the gate, drain, and enhancement of the enhancement type NMOS transistor M26. It is connected to the gate of the type transistor M27. Further, the source of the transistor M29 and the drain of the transistor M27 are connected to the load current detection terminal 26. Further, the source of the transistor M26 is connected to the source of the transistor M22, and the source of the transistor M27 is connected to the output terminal 24.

In this load current detection circuit 20B, even if the size ratio of the transistors M26 and M27 is set to 1: 1 and a voltage is generated in the detection resistor R2 when the voltage Vout of the output terminal 24 is a normal value, the transistor M26 , M27 is made to operate almost as a current mirror circuit. At this time, if the drain current Id27 of the transistor M27 is set to have a relationship of Id27 <Id29 with respect to the source current Id29 of the transistor M29, the logic of the load current detection terminal 26 becomes “H”.

However, when the load current flowing through the load 25 increases, the current flowing through the detection resistor R2 also increases, the gate-source voltage of the transistor M27 becomes sufficiently larger than the gate-source voltage of the transistor M26, and the drain of the transistor M27 The current Id27 becomes larger than that in the normal state. Then, when Id27> Id29, the logic of the load current detection terminal 26 becomes “L”, indicating that an overcurrent has occurred in the load 25.

Japanese Unexamined Patent Publication No. 2005-039573 Japanese Unexamined Patent Publication No. 06-180332

However, in the load current detection circuit 20A described with reference to FIG. 5, when the load 25 is short-circuited, that is, when the output terminal 24 and the ground terminal 23 are short-circuited, the source of the transistor M21 becomes the ground potential, but the node N1 of the source of the transistor M22. Since the transistors M23 and M24 are inserted, the potential becomes higher than the potential of the ground terminal 23, and the relationship in which the transistors M21 and M22 operate at the same control voltage does not hold, and the transistor M22 is connected to the transistor M21. The current cannot flow according to the size ratio. That is, there is a problem that the load current is not detected normally when the output terminal 24 is short-circuited to the ground terminal 23. Further, since the operational amplifier 28 is used, there is a problem that the circuit scale of the load current detection circuit 20A becomes large.

Further, in order for the load current detection circuit 20B described with reference to FIG. 6 to operate normally, at least the voltage between the drain and source of the deflection type transistor M28, the voltage between the gate and source of the transistor M26, and the detection resistor R2 are used. A voltage corresponding to the sum of the resulting voltage drops needs to occur between the drain and source of the transistor M21. Therefore, in order to suppress the power loss of the load current detection circuit 20B and supply the current from the power supply terminal 22 to the load 25 with high efficiency, it is required to use an element having a small drain-source resistance as the transistor M21. However, it becomes difficult to meet this demand.

Further, in the load current detection circuit 20B, even when the load 25 is not driven, that is, even when the transistors M21 and M22 are turned off, the current generated by the deformation type transistor M29 is regarded as an invalid current from the load current detection terminal 26. Since the current flows out, in order to take out the current that accurately corresponds to the current flowing through the load 25, it is necessary to provide a correction circuit that cancels the invalid current portion after the load current detection terminal 26.

The present invention solves the above problems, can detect the load current normally even when a load short circuit occurs, has a small circuit scale, and can use an element with a small source-drain resistance for the load driving transistor. Another object of the present invention is to provide a load current detection circuit in which an invalid current is not output to the load current detection terminal.

In order to achieve the above object, in the invention according to claim 1, the output terminal and the ground terminal are connected by a first conductive type first transistor in which a drain is connected to a first power supply terminal and a source is connected to an output terminal. A first load current detection circuit that detects the load current of the load drive circuit that drives the load connected between them, and is controlled by the same control voltage as the first transistor and the drain is connected to the first power supply terminal. It is a conduction type second transistor, a detection resistor connected between the source of the first transistor and the source of the second transistor, and a depletion type in which the drain is connected to the second power supply terminal and the gate and source are commonly connected. A first conductive type third transistor, a depletion type first conductive type fourth transistor in which the detection resistor is connected between the gate and source and a drain is connected to the source of the third transistor, and the third transistor. A second conductive type fifth transistor in which a gate and a drain are connected to a common connection point between the source and the drain of the fourth transistor and the source is connected to the second power supply terminal, and a gate at the gate of the fifth transistor. The second transistor is provided with a second conductive type sixth transistor connected, the source is connected to the second power supply terminal, and the drain is connected to the load current detection terminal, and the second transistor is set to have a smaller size ratio than the first transistor. The third and fourth transistors are set to have the same structure and the same size ratio, the voltage of the second power supply terminal is set to a voltage higher than the voltage of the first power supply terminal, and the voltage generated across the detection resistor is It is characterized in that it is set smaller than the absolute value of the threshold voltage of the third and fourth transistors.

According to the second aspect of the present invention, in the load current detection circuit according to the first aspect, the voltage of the second power supply terminal is set to a voltage at which the third transistor and the fourth transistor operate in a saturated state. It is characterized by that.

In the invention according to claim 3, in the load current detection circuit according to claim 1 or 2, a load drive control circuit for simultaneously driving the first transistor and the second transistor is provided, and the load drive control circuit is charged. It operates at a voltage generated by the pump circuit, and is characterized in that another voltage generated by the charge pump circuit is applied to the second power supply terminal.

According to a fourth aspect of the present invention, in the load current detection circuit according to the first, second or third aspect, a diode or a diode-connected transistor is provided between the drain of the fourth transistor and the drain of the fifth transistor. It is characterized in that one or two or more are connected in series and inserted.

The invention according to claim 5 is the first conductive type in which the drain and the gate are short-circuited between the drain of the fourth transistor and the drain of the fifth transistor in the load current detection circuit according to claim 1, 2 or 3. Alternatively, a second conductive type tenth transistor is inserted, the source of the second conductive type 11th transistor is connected to the drain of the sixth transistor, and the gate of the eleventh transistor is connected to the drain of the fourth transistor. , The drain is connected to the load current detection terminal.

According to the load current detection circuit of the present invention, the load current can be normally detected even when the output terminal is short-circuited to the ground terminal. Moreover, since an operational amplifier is not required, the circuit scale can be reduced. Further, since the load current can be detected even when the potential difference between the first power supply terminal and the output terminal is small, a transistor having a small drain-source resistance can be used as the first transistor for load driving, and a high current can be applied to the load. It can be supplied efficiently. In addition, since the reactive current is not output from the load current detection terminal in the standby state when the load is not driven, the detection current that accurately corresponds to the current flowing through the load is output even if a correction circuit that cancels the reactive current is not provided. can do. Furthermore, if another voltage generated by the charge pump circuit that supplies the voltage to the load drive control circuit is used as the power supply for the second power supply terminal of the load current detection circuit, the charge pump circuit is in a standby state in which it is stopped. It is possible to realize a load current detection circuit that does not consume current.

It is a circuit diagram of the load current detection circuit of 1st Example of this invention. It is a circuit diagram of the load current detection circuit of the 2nd Example of this invention. It is a circuit diagram of the load current detection circuit of the 3rd Example of this invention. It is a circuit diagram of the load current detection circuit of the 4th Example of this invention. It is a circuit diagram of the conventional load current detection circuit. It is a circuit diagram of another conventional load current detection circuit.

<First Example>
FIG. 1 shows the load current detection circuit 10A of the first embodiment of the present invention. 1 is a charge pump circuit for voltage generation, 2 is a load drive control circuit to which power is supplied from the charge pump circuit 1, 3 is a first power supply terminal having a voltage of VDD1, and 4 is a first power terminal having a voltage of VDD2 (VDD2> VDD1). 2 power supply terminal, 5 is a ground terminal, 6 is an output terminal, 7 is a load, and 8 is a load current detection terminal to which a determination circuit (not shown) or the like is connected. Further, M1 and M2 are enhancement type NMOS transistors, M3 and M4 are depletion type NMOS transistors, and M5 and M6 are enhancement type MOSFET transistors. R1 is a detection resistor.

The transistor M1 is a transistor constituting a load drive circuit, and drives a load 7 connected between the output terminal 6 and the ground terminal 5. The transistor M2 is a detection transistor having a structural similarity similar to that of the transistor M1. The drains of the transistors M1 and M2 are connected to the first power supply terminal 3, and the gate is ON / OFF controlled by the same control signal output from the load drive control circuit 2. A detection resistor R1 is connected between the sources of the transistors M1 and M2.

Since the transistors M1 and M2 are similar in structure, if the gate-source voltage and the drain-source voltage are equal, a current corresponding to the relative ratio with the transistor M1 flows through the transistor M2. For example, if the relative ratio of the transistors M2 and M1 is 1: 10000, when a current of 10 A flows through the transistor M1, a current of 1 mA flows through the transistor M2.

However, since the detection resistor R1 is actually connected between the transistor M2 and the source of the transistor M1, the voltage between the drain and the source of the transistor M2 depends on the product of the drain current of the transistor M2 and the resistance value of the detection resistor R1. The voltage Vr drops lower than the drain-source current of the transistor M1, and an error occurs in the relative ratio of the drain currents of the transistors M1 and M2.

Therefore, the relative ratio between the transistor M1 and the transistor M2 is set as large as possible, and the resistance value of the detection resistor R1 is set as small as possible so that even at the maximum current at which overcurrent protection works, both ends of the detection resistor R1 are used. The generated voltage Vr is set to about 0.3V.

The gate of the transistor M4 is connected to both ends of the detection resistor R1 on the source side of the transistor M2, and the source of the transistor M4 is connected to the source side of the transistor M1. The gate and source of the transistor M3 having the same structure and the same dimensions as the transistor M4 are connected to the drain of the transistor M4, and the drain of the transistor M3 is connected to the second power supply terminal 4.

The voltage VDD2 of the second power supply terminal 4 is higher than the voltage VDD1 of the first power supply terminal 3, and the voltage at which both the transistors M3 and the transistor M4 operate in the saturated state, that is, the potential difference between the voltage VDD1 and the voltage VDD2. Is set to a voltage higher than the saturation voltage (VDsat) of the transistors M3 and M4.

The gate of the transistors M5 and M6 constituting the current mirror circuit and the drain of the transistor M5 are connected to the drain of the transistor M4. The source of the transistors M5 and M6 is connected to the second power supply terminal 4, and the drain of the transistor M6 is connected to the load current detection terminal 8.

By the way, in the standby state where the transistor M1 is not driving the load, the source current of the transistor M1 is 0A and the source current of the transistor M2 is also 0A, so that the voltage Vr across the detection resistor R1 is 0V. Therefore, the gate-source voltage of the transistor M4 becomes 0V like the gate-source voltage of the transistor M3, the saturation currents of the transistor M4 and the transistor M3 become equal, and the gate currents of M5 and M6 constituting the current mirror are the same. No current flows and no current flows through the load current detection terminal 8.

In the load current detection circuit 20B described with reference to FIG. 6, even when the transistors M21 and M22 are turned off and the load 25 is not driven, an invalid current flows through the transistor M29, so that the detection accurately corresponds to the current flowing through the load 25. In order to obtain the current, it was necessary to provide a correction circuit for canceling the invalid current in the load current detection terminal 26, but in the load current detection circuit 10A of this embodiment, when the load 7 is not driven, the load is loaded. Since no current flows through the current detection terminal 8, a highly accurate detection current that is exactly proportional to the current flowing through the load 7 can be output from the load current detection terminal 8 without the need for a correction circuit.

Next, in a state where the transistor M1 is turned on and the load is driven, a current flows from the first power supply terminal 3 to the load 7 via the transistor M1 and the output terminal 6, and the transistor M2 also has the transistor M1. A current corresponding to the relative ratio flows, and this current flows to the output terminal 6 via the detection resistor R1.

The voltage generated across the detection resistor R1, that is, the gate-source voltage of the transistor M4 is Vr, and if the threshold voltage of the transistors M3 and M4 is Vt, the drain current Id3 of the transistor M3 in the saturated state is
Id3 = (β / 2) ・ Vt ・ Vt (1)
Can be expressed as. Here, β can be expressed as β = (W / L) · μ · C by using the channel length of the transistor M3 as L, the channel width as W, the electron mobility as μ, and the oxide film capacity C per unit area. It is a coefficient. The drain current Id4 of the transistor M4 is
Id4 = (β / 2) · (Vr-Vt) · (Vr-Vt) (2)
Can be expressed as.

Therefore, the difference between the drain currents of the transistor M4 and the transistor M3 is
Id4-Id3 = (β / 2) · Vr · (Vr-2Vt) (3)
Will be. The current of the difference between the currents Id4 and Id3 represented by the equation 3 flows into the drain of the transistor M4 as the drain current of the transistor M5, and the transistors M5 and the transistors M6 constituting the current mirror also have the transistors M5 and M6. If the current mirror ratio is 1: N, the drain current Id6 is N times that of the transistor M5.
Id6 = (Id4-Id3) · N (4)
Flows.

Assuming that Equation 3 is substituted into this Equation 4 and the drain current of the transistor M2 is Id2, since Vr = R1 and Id2, the drain current Id6 of the transistor M6, which is the detection current flowing through the load current detection terminal 8, is
Id6 = (β / 2), R1, Id2, (R1, Id2-2Vt), N (5)
Therefore, as the detection current Id6, a current proportional to the quadratic equation of the current Id2 flowing through the detection transistor M2 is obtained.

Equation 5 is a quadratic equation for the drain current Id12 of the transistor M2, but the threshold voltage Vt of the transistors M3 and M4 is
−Vt >> (R1 ・ Id2) (6)
In the case of,
R1 · Id2-2Vt ≒ -2Vt (7)
Since it can be approximated to, equation (5) is
Id6 ≒ −β ・ R1, Id2 ・ Vt ・ N (8)
Can be transformed into.

That is, if the resistance value of the detection resistor R1 and the current flowing through the transistor M2, that is, the size ratio of the transistors M1 and M2 are appropriately selected, the load current is detected by the detection current Id6 which is substantially linearly proportional to the drain current Id2 of the transistor M2. It can be obtained from terminal 8.

In the load current detection circuit 10A of this embodiment, even if the output terminal 6 is short-circuited to the ground terminal 5, the load 7 is connected to the output terminal 6 described above so that the transistor M1 and the transistor M2 operate at the same control voltage. Since it is the same as the case where the current flows, the overcurrent generated by the short circuit can be output from the load current detection terminal 8 as the detection current.

Therefore, by providing a determination circuit (not shown) for comparing the detected current with the reference current corresponding to the overcurrent in the subsequent stage of the load current detection terminal 8, whether the overcurrent has flowed due to the short circuit of the load 7. Whether or not it can be accurately determined.

<Second Example>
FIG. 2 shows the load current detection circuit 10B according to the second embodiment of the present invention. In FIG. 2, the second power supply terminal 4 is connected to the charge pump circuit 1 so that the voltage VDD2 of the second power supply terminal 4 in FIG. 1 can be supplied from the charge pump circuit 1 that supplies the voltage to the load drive control circuit 2. It is a thing.

With this configuration, when the load 7 is not driven, the charge pump circuit 1 is stopped, power is not supplied to the load drive control circuit 2, and the voltage VDD2 is not generated at the second power supply terminal 4. Therefore, no current flows through the transistors M3, M4, M5, and M6, and the current consumption by the load current detection circuit 10B during the standby of load drive is 0A. Other operating principles are the same as in the first embodiment.

<Third Example>
FIG. 3 shows the load current detection circuit 10C of the third embodiment of the present invention. FIG. 3 shows a series connection circuit of enhancement type MOSFET transistors M7, M8, and M9 in which the drain and the gate are short-circuited and diode-connected between the drain of the transistor M5 and the drain of the transistor M4 in FIG. .. In FIG. 3, three transistors are connected in series and inserted, but the number of transistors to be inserted is not limited.

When a current flows through the load 7, a current corresponding to the difference (Id4-Id3) between the drain currents of the transistors M4 and M3 represented by the equation 3 flows as the drain current of the transistors M5, and this current flows through the transistors Q7 to M9. A voltage drop occurs when flowing.

The voltage drop, which is the gate-source voltage Vgs, is assumed to be β2 for the current amplification factor per transistor and Vt2 for the threshold voltage.
Vgs = √ {2 · (Id4-Id3) / β2} + Vt2 (9)
The drain voltage Vd4 of the transistor M4 is determined by inserting the transistors M7 to M9. As a result, the difference between the drain and source voltages of the transistors M3 and M4 can be reduced, so that the influence of the effect of channel length modulation can be reduced and the accuracy of load current detection can be improved.

Therefore, the number of transistors inserted between the drain of the transistor M5 and the drain of the transistor M4 is such that the drain voltage Vd4 of the transistor M4 is near the midpoint between the voltage VDD2 of the second power supply terminal 4 and the voltage VDD1 of the first power supply terminal 3. Voltage Vd4 = (VDD2 + VDD1) / 2 (10)
It is desirable to set so as to be.

In FIG. 3, the MOSFET transistors M7 to M9 having the gate and source connected in common are inserted, but these MOSFET transistors can be replaced with the NMOS transistors or diodes. When replacing with a diode, the anode of the diode may be connected to the drain side of the transistor M5, and the cathode may be connected to the drain side of the transistor M4. Other operating principles are the same as in the first embodiment.

<Fourth Example>
FIG. 4 shows the load current detection circuit 10D of the fourth embodiment of the present invention. In this embodiment, an enhancement type epitaxial transistor M10 in which a drain and a gate are short-circuited is inserted between the drain of the transistor M5 and the drain of the transistor M4 in the load current detection circuit 10A of FIG. 1, and a buffer is further inserted in the drain of the transistor M6. The source of the enhancement type epitaxial transistor M11 is connected, the gate of the transistor M11 is connected to the drain of the transistor M4, and the drain of the transistor M11 is connected to the load current detection terminal 8.

With this configuration, the source-gate voltage of the transistor M10 and the source-gate voltage of the transistor M11 are matched, and the drain-source voltage of the transistors M5 and M6 constituting the current mirror is made comparable. Therefore, the drain currents of the transistors M5 and M6 are similarly affected by the channel length modulation. Therefore, the effective current mirror ratio of the transistors M5 and M6 does not fluctuate depending on the voltage VDD2 of the second power supply terminal 4 and the potential of the connection destination of the load current detection terminal 8, and accurate load current detection is performed. Can be done. The MPLS transistor M10 can be replaced with an NMOS transistor in which a gate and a drain are commonly connected, provided that a source-gate voltage similar to that of the source-gate voltage of the transistor M11 can be obtained. Other operating principles are the same as in the first embodiment.

10A, 10B, 10C, 10D, 20A, 20B: Load current detection circuit 1: Charge pump circuit 2: Load drive control circuit 3: 1st power supply terminal 4: 2nd power supply terminal 5: Ground terminal, 6: Output terminal, 7: Load, 8: Load current detection terminal 21: Load drive control circuit, 22: Power supply terminal, 23: Ground terminal, 24: Output terminal, 25: Load, 26: Load current detection terminal, 27: Current source , 28: Optotype

Claims (5)

The load current of the load drive circuit that drives the load connected between the output terminal and the ground terminal by the first conductive type first transistor in which the drain is connected to the first power supply terminal and the source is connected to the output terminal. It is a load current detection circuit to detect
A first conductive type second transistor controlled by the same control voltage as the first transistor and having a drain connected to the first power supply terminal, and a source of the first transistor and a source of the second transistor were connected to each other. The detection resistor, the depletion type first conductive type third transistor in which the drain is connected to the second power supply terminal and the gate and source are commonly connected, and the detection resistor is connected between the gate and source to form the third transistor. The gate and drain are connected to the common connection point between the depletion type first conductive type fourth transistor in which the drain is connected to the source and the source of the third transistor and the drain of the fourth transistor, and the source is the second power supply. The second conductive type fifth transistor connected to the terminal and the second conductive type in which the gate is connected to the gate of the fifth transistor, the source is connected to the second power supply terminal, and the drain is connected to the load current detection terminal. Equipped with the 6th transistor of
The size ratio of the second transistor is set to be smaller than that of the first transistor, the third and fourth transistors are set to the same structure and the same size ratio, and the voltage of the second power supply terminal is smaller than the voltage of the first power supply terminal. A load current detection circuit characterized in that the voltage is set to a high voltage and the voltage generated across the detection resistor is set to be smaller than the absolute value of the threshold voltage of the third and fourth transistors. In the load current detection circuit according to claim 1,
The load current detection circuit, wherein the voltage of the second power supply terminal is set to a voltage at which the third transistor and the fourth transistor operate in a saturated state. In the load current detection circuit according to claim 1 or 2.
A load drive control circuit for simultaneously driving the first transistor and the second transistor is provided, the load drive control circuit operates at a voltage generated by the charge pump circuit, and the second power supply terminal is connected to the charge pump circuit. A load current detection circuit characterized in that another generated voltage is applied. In the load current detection circuit according to claim 1, 2 or 3,
A load current detection circuit, characterized in that a diode or a diode-connected transistor is connected in series with one or more in series between the drain of the fourth transistor and the drain of the fifth transistor. In the load current detection circuit according to claim 1, 2 or 3,
A first conductive type or second conductive type tenth transistor having a drain and a gate short-circuited between the drain of the fourth transistor and the drain of the fifth transistor is inserted, and the second conductive type is inserted into the drain of the sixth transistor. A load current detection circuit comprising connecting the source of the eleventh transistor, connecting the gate of the eleventh transistor to the drain of the fourth transistor, and connecting the drain to the load current detection terminal.

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