JP6763715B2 - Timing controller, its control method, electronic equipment using it - Google Patents

Description

The present invention relates to a timing controller that receives image data from a graphic controller and transmits information to a gate driver and a source driver.

FIG. 1 is a block diagram of an image display system. The image display system 100 includes a display panel 102 such as a liquid crystal panel or an organic EL panel, a gate driver 104, a source driver 106, a graphic controller 110, and a timing controller 200. The graphic controller 110 generates image data to be displayed on the display panel 102. The pixel (RGB) data included in the image data is transmitted to the timing controller 200 in a serial format. The cable may be detachable at the connector 112.

The timing controller 200 receives image data and generates various control signals and timing signals (synchronization signals). The gate timing signal is transmitted to the gate driver 104. The gate driver 104, in synchronization with the gate timing signal for selecting the scanning line L _S of the display panel 102 in this order. The RGB data is supplied to the source driver 106 for driving the data line L _D should output it.

FIG. 2 is a block diagram of the timing controller 200r of FIG. The timing controller 200r includes an input interface (receiver) circuit 202, a logic circuit 204, an SDRAM (Synchronous Dynamic Random Access Memory) 206, and an output interface circuit (transmitter) 208. The input interface circuit 202 receives video input data (RGB data) serially transmitted from the graphic controller 110. The RGB data is transmitted in synchronization with the pixel clock CK _P. The pixel clock CK _P may be transmitted via the clock line or may be embedded in RGB data. The timing controller 200 operates in synchronization with the pixel clock CK _P received by the input interface circuit 202.

The RGB data received by the input interface circuit 202 is stored in the SDRAM 206 as frame data or line data (hereinafter referred to as image data). The logic circuit 204 receives the image data stored in the SDRAM 206 and performs necessary signal processing. The image data that has undergone signal processing is transmitted to the source driver 106 by the output interface circuit 208.

Japanese Unexamined Patent Publication No. 2000-78027 JP-A-2007-96903

3 (a) and 3 (b) are diagrams showing data reading from SDRAM. When the logic circuit 204 reads and accesses the SDRAM 206, the SDRAM 206 generates the data DQ and the data strobe signal DQS in synchronization with the clock CK given by the logic circuit 204.

FIG. 3A shows normal operation. Logic circuit 204, a data strobe signal DQS by a predetermined time _{T a} delay, generates a read clock _{CK READ,} at the timing of the edge of the read clock _{CK READ,} captures data DQ (latch), and generates the read data.

However, due to sudden frequency fluctuations, external factors such as temperature and humidity, and variations in the delay time Ta, _a situation may occur in which the data DQ cannot be captured correctly. FIG. 3B shows how the frequencies (cycles) of the data DQ and the data strobe signal DQS generated by the SDRAM 206 fluctuate, and the edge of the read clock CK _READ is located in the first half of the data DQ section. Therefore, the setup is violated, and the read data does not match the data DQ from the SDRAM 206.

The present invention has been made in view of such a situation, and one of an exemplary purpose of the embodiment is to provide a timing controller capable of reliably capturing data stored in a memory.

One aspect of the present invention relates to a timing controller. The timing controller includes a receiver that receives the pixel data that constitutes the image data and the pixel clock that accompanies it from the graphic controller, a memory that holds the pixel data received by the receiver, a memory read circuit that reads the pixel data from the memory, and a memory. It includes a logic circuit that performs signal processing on the pixel data read by the read circuit, and a transmitter that transmits the pixel data that has undergone signal processing by the logic circuit to the source driver. The memory read circuit has a multi-phase clock generator that generates a multi-phase clock based on a pixel clock, and a multi-phase clock that reads and accesses the memory during the automatic adjustment period and captures the data strobe signal from the memory using the multi-phase clock. One of the phase clocks located substantially in the center of the high section of the data strobe signal is the first read clock for the high section, and another of the polyphase clocks located substantially in the center of the low section of the data strobe signal. It includes an automatic adjustment circuit in which one is used as a second read clock for a low section, and a latch circuit that takes in data from a memory by using a first read clock and a second read clock in a normal period. Burst read may be used for read access during the automatic adjustment period.

According to this aspect, since the read clock located at the center of each of the high section and the low section of the data strobe signal DQS can be generated, data can be reliably captured.

The polyphase clock may include a first phase clock to an N phase clock (N is an integer of 2 or more). When the interval between the phase i clock and the phase j clock is the high section of the data strobe signal, the automatic adjustment circuit may use the central clock of the phase i clock and the phase j clock as the first read clock. ..

Further, when the interval between the k-phase clock and the l-phase clock is a low section, the automatic adjustment circuit may use the central clock of the k-phase clock and the l-phase clock as the second read clock.
By adjusting the read clocks of the high section and the low section independently, the optimum read clock can be generated even when the duty ratio of the data strobe signal DQS deviates from 50%.

In the automatic adjustment circuit, a clock shifted by a predetermined phase with respect to the first read clock may be used as the second read clock. This simplifies the circuit.

The automatic adjustment circuit includes the first-phase clock to the N-phase clock (N is an integer of 2 or more), and when the interval between the k-phase clock and the l-phase clock is a low interval, the k-phase clock and the th-phase clock are included. The central clock of the l-phase clock may be used as the second read clock. The automatic adjustment circuit may use a clock that is shifted by a predetermined phase with respect to the second read clock as the first read clock.

The automatic adjustment period may be inserted in a blank section of one frame. As a result, the read clock timing can be adjusted without interrupting the display during the image display.

The automatic adjustment period may occur every frame. This makes it possible to follow fluctuations in frequency, temperature, humidity, etc. on a short time scale.

The automatic adjustment circuit may determine that the data strobe signal is abnormal when at least one of the high section and the low section of the data strobe signal is less than a predetermined width. This makes it possible to detect abnormalities in the memory.

If the automatic adjustment circuit determines that it is abnormal, the memory may be initialized. If the error is caused by the memory, the timing controller can be restored to normal by initializing the memory.

When a low section having a predetermined width or less occurs in the high section, the automatic adjustment circuit may ignore the low section. When a high section having a predetermined width or less occurs in the low section, the automatic adjustment circuit may ignore the high section. By masking the short low section or high section as noise, the accuracy of automatic adjustment can be improved.

The polyphase clock may be any of 8, 12, 16, 24, and 32 phases.

The timing controller may be integrally integrated on one semiconductor substrate.
"Integrated integration" includes cases where all the components of a circuit are formed on a semiconductor substrate or cases where the main components of a circuit are integrated integrally, and some of them are used for adjusting circuit constants. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

Another aspect of the invention relates to electronic devices. The electronic device includes any of the timing controllers described above.

Another aspect of the invention relates to a display device. The display device includes any of the timing controllers described above.

It should be noted that an arbitrary combination of the above components or a conversion of the expression of the present invention between methods, devices and the like is also effective as an aspect of the present invention.

According to an aspect of the present invention, the data stored in the memory can be reliably captured.

It is a block diagram of an image display system. It is a block diagram of the timing controller of FIG. 3 (a) and 3 (b) are diagrams showing data reading from SDRAM. It is a block diagram of the timing controller which concerns on embodiment. It is a waveform diagram which shows a data strobe signal and a polymorphic clock. It is a figure which shows the structural example of the automatic adjustment circuit. FIG. 7A is an operation waveform diagram of the automatic adjustment period of the timing controller, and FIG. 7B is an operation waveform diagram of the normal period of the timing controller. FIG. 8A is an operation waveform diagram of the first modification, and FIG. 8B is an operation waveform diagram of the second modification. It is a figure which shows the electronic device.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, and the member A and the member B are electrically connected. It also includes the case of being indirectly connected via another member that does not affect the connection state or interfere with the function.
Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and also electrically. It also includes the case of being indirectly connected via another member that does not affect the connection state or interfere with the function.

FIG. 4 is a block diagram of the timing controller 200 according to the embodiment. The timing controller 200 is used in the image display system 100 shown in FIG. 1, receives pixel (RGB) data constituting the image data and a pixel clock CK _P associated therewith from the graphic controller 110, and receives data driver (not shown). ) Is output. For example, pixel data is transmitted in differential serial format.

The timing controller 300 includes a receiver 302, a memory 304, a logic circuit 306, a transmitter 308, and a memory read circuit 310, and is a functional IC (Integrated Circuit) integrally integrated on one semiconductor substrate.

The receiver 302 receives the pixel data constituting the image data and the pixel clock CK _P associated therewith from the graphic controller 110. For example, the receiver 302 may be a differential interface such as LVDS (Low Voltage Differential Signaling).

The memory 304 holds the pixel data received by the receiver 302. SDRAM is suitable for the memory 304, but this is not the case. The memory 304 may be a line memory that holds pixel data over one or a plurality of lines, or a frame memory that holds pixel data for one frame.

The memory read circuit 310 reads pixel data from the memory 304. The logic circuit 306 performs signal processing on the pixel data read by the memory read circuit 310. The signal processing of the logic circuit 306 is not particularly limited, and a known technique may be used, and examples thereof include γ (gamma) correction, FRC (Frame Rate Control) processing, and RGB mapping.

The transmitter 308 transmits the pixel data that has undergone signal processing by the logic circuit 306 to the source driver 106.

The memory read circuit 310 includes a multi-phase clock generator 312, an automatic adjustment circuit 314, and a latch circuit 316. The multi-phase clock generator 312 generates a multi-phase clock based on the pixel clock CK _P. The multi-phase (N-phase) clock CK includes a first-phase clock CK ₁ to an N-phase clock CK _N whose phases are shifted by 360 ° / N. FIG. 5 is a waveform diagram showing the data strobe signal DQS and the polyphase clocks CK _{1 to} CK _N. However, N is an integer of 2 or more, and in this embodiment, N = 32. Note that N is not particularly limited, and may have another value such as 4, 8, 12, 16, 24, 48, or 64. The configuration of the multi-phase clock generator 312 is not particularly limited, and a known technique may be used.

Return to FIG. The automatic adjustment circuit 314 reads and accesses the memory 304 during the automatic adjustment period. Burst read can be used for read access during the automatic adjustment period. In response to this, the data strobe signal DQS is output from the memory 304. The automatic adjustment circuit 314 takes in the data strobe signal DQS using the multi-phase clock CK, and determines the high section and the low section. Then, among the polyphase clocks CK _{1 to} CK _N , one CK _H located substantially in the center of the high section of the data strobe signal DQS is set as the first read clock for the high section, and among the polyphase clocks CK _{1 to} CK _N. another one substantially located in the center of the low period of the data strobe signal DQS and the second read clock CK _L for low period.

In the normal period, the latch circuit 316 takes in the data DQ (data generated in the output of the memory) from the memory 304 by using the first read clock CK _H and the second read clock CK _L.

FIG. 6 is a diagram showing a configuration example of the automatic adjustment circuit 314. 6, only the portion (314H) are shown to be associated with the occurrence of the first read clock CK _H. The automatic adjustment circuit 314 includes a plurality of flip-flops FF _{1 to} FF ₃₂ corresponding to the N phase, a phase determination device 320, and a multiplexer (selector) 322. The plurality of flip-flops FF _{1 to} FF ₃₂ use the corresponding clocks CK ₁ to CK ₃₂ to capture the data strobe signal DQS. The phase determiner 320 receives the outputs Q _{1 to} Q ₃₂ of a plurality of flip-flops FF _{1 to} FF ₃₂ , compares each of them with the expected value (1 to determine the high interval, that is, high), and determines match or mismatch. To do. Then, when the continuous Q _{i to} Q _j match the expected value, it is indicated that the period between the phase _i clock CK _i and the phase j clock CK _j is the high section of the data strobe signal DQS. The phase determination device 320 calculates the midpoint by numerical calculation based on i and j, and generates a phase select (PHASE_SEL) signal indicating the midpoint. The selector 322 selects one of the plurality of clocks CK _{1 to} CK ₃₂ indicated by the PHASE_SEL signal, and sets the central clock of the phase _i clock CK _i and the phase j clock CK _j as the first read clock CK _H. To do.

The portion (314L) related to the generation of the second read clock CK _L can also be generated by the same configuration. Specifically, the expected value in the phase determination device 320 may be set to 0 (low). When the continuous Q _{k to} Q _l match the expected value, it indicates that the section between the k-phase clock CK _k and the l-phase clock CK _l is the low interval of the data strobe signal DQS. The phase determination device 320 calculates the midpoint by numerical calculation based on k and l, and generates a phase select (PHASE_SEL) signal indicating the midpoint. The selector 322 selects one of the plurality of clocks CK _{1 to} CK ₃₂ indicated by the PHASE_SEL signal, and sets the central clock of the k-phase clock CK _k and the l-phase clock CK _l as the second read clock CK _L. To do. The circuits 314H and 314L may be configured by sharing some hardware.

The above is the configuration of the timing controller 300. Subsequently, the operation of the timing controller 300 of FIG. 4 will be described.

FIG. 7A is an operation waveform diagram of the timing controller 300 during the automatic adjustment period. The automatic adjustment period is inserted in the blank section in the frame. By using the blank period, it is possible to adjust the read clock timing without interrupting the display during the image display. The automatic adjustment can be executed every predetermined number of frames or every predetermined time.

On platforms with large frequency fluctuations and jitter fluctuations on a short time scale, it is advisable to perform automatic adjustment in a short cycle, for example, in a cycle of 1 to 3 frames. This makes it possible to deal with short-term fluctuations. On the contrary, on a platform having a long fluctuation time scale, it is preferable to reduce the frequency of automatic adjustment, and for example, automatic adjustment may be performed once every several tens to several hundreds of frames, that is, about once every few seconds. In this case, power consumption can be reduced. The automatic adjustment period may be executed once for each activation of the timing controller 300.

7 shows the data strobe signal DQS, the decision result in the high side of the data _Q 1 _{to Q 32,} the determination result of the first read clock CK _H, the low side of the data _{Q 1 ~Q 32 (Judge Result)} , second lead The clock CK _L is shown. In the judgment result, ◯ indicates a match and × indicates a disagreement.

Focusing on the high side, Q ₆ to Q ₂₁ is shows a match, it can be seen that during the sixth phase, second 21 phase is the high period. That is, i = 6, j = 21. The thirteenth phase is selected as the midpoint among them, and the clock CK ₁₃ becomes the first read clock CK _H.

Focusing on the low side, it can be seen that Q _{22 to} Q ₅ show agreement, and that there is a low section between the 22nd phase and the 5th phase. That is, k = 22, l = 5. The 29th phase is selected as the midpoint among them, and the clock CK ₂₉ becomes the second read clock CK _L.

FIG. 7B is an operation waveform diagram of the timing controller 300 during a normal period. The latch circuit 316 uses the first read clock CK _H and uses the second read clock CK _L to capture the data DQ (D ₀ , D ₂ , D ₄ ...) Located in the high section of the data strobe signal DQS. Data strobe signal Data DQ (D ₁ , D ₃ , D ₅ ...) located in the low section of the DQS is taken in.

The above is the operation of the timing controller 300.
According to the timing controller 300, the read clocks CK _H and CK _L located at the center of each of the high section and the low section of the data strobe signal DQS can be generated, so that the data DQ can be reliably captured, and the frequency fluctuation and the power supply voltage can be obtained. It can increase resistance to fluctuations and fluctuations in temperature and humidity.

Further, as shown in FIG. 7 (a), by adjusting the read clocks in the high section and the low section independently, the optimum read clock is obtained even when the duty ratio of the data strobe signal DQS deviates from 50%. CK _H and CK _L can be generated.

The present invention has been described above based on the embodiments. This embodiment is an example, and there may be various variations in each of these components, each processing process, and their combination. Hereinafter, such a modification will be described.

(First modification)
The automatic adjustment circuit 314 may determine that it is abnormal when at least one of the high section and the low section of the data strobe signal DQS is less than a predetermined width (predetermined number of phases). For example, when N = 32 and the high section or the low section is less than three phases, it may be determined as abnormal. The threshold value (predetermined number of phases) can be arbitrarily set.

FIG. 8A is an operation waveform diagram of the first modification. If the memory is operating normally, the duty ratio of the data strobe signal DQS will be 50% or a value close to it, so that the high section will be around 16 phases. However, when an abnormality occurs in the memory, the duty ratio deviates from 50% and the high section (or low section) becomes extremely short. In FIG. 8A, since the high section is for three phases from the 9th phase to the 11th phase, it is determined to be abnormal.

Further, the automatic adjustment circuit 314 initializes the memory 304 when it determines that it is abnormal. If the abnormality is caused by the memory 304, the timing controller 300 can be restored to normal by initializing the memory 304.

When the automatic adjustment circuit 314 determines that there is an abnormality, the automatic adjustment circuit 314 may notify the abnormality to the outside of the timing controller 300.

(Second modification)
When a low section having a predetermined width (for example, one or two phases) or less occurs in the high section, the automatic adjustment circuit 314 ignores the low section. Further, when a high section (for example, one or two phases) having a predetermined width or less occurs in the low section, the automatic adjustment circuit 314 ignores the high section.

FIG. 8B is an operation waveform diagram of the second modification. The data strobe signal DQS is in the high section from the 4th phase to the 19th phase. It is assumed that the determination of the sixth phase is erroneously detected as a mismatch due to the influence of noise. At this time, if the 7th to 19th phases are set as the high section, the clock CK ₁₃ of the 13th phase becomes the read clock CK _H , but this deviates from the center of the true high section.

In the second modification, since the low section (that is, the mismatch) in the sixth phase is ignored, the fourth to 19th phases can be correctly determined as the high section. As a result, the clock CK ₁₁ located at the center of the true high section can be selected as the lead clock CK _H.

(Third modification example)
In the embodiment, the phases of both the first read clock CK _H and the second read clock CK _L are automatically adjusted independently, but the phase is not limited to this, and one may be subordinate to the other. The read clock CK _H may be automatically adjusted only for one (for example, the high section), and a clock shifted by a predetermined phase from the automatically adjusted clock CK _H may be used for the other (for example, the low section). For example, when N = 32 phases, a clock shifted by about 15 to 17 phases with respect to the clock CK _H can be used as the second read clock CK _L. If N = 16, a clock shifted by about 7 to 9 phases with respect to the clock CK _H can be used as the second read clock CK _L.

In this case, a first mode in which the first read clock CK _H and the second read clock CK _L are automatically adjusted independently and a second mode in which one is automatically adjusted and the other is subordinate may be selectable.

(Fourth modification)
The automatic adjustment circuit 314 may measure the high section and the low section over a plurality of cycles of the data strobe signal DQS, and may determine the read clocks CK _H and CK _L based on the average of the plurality of measurements.

Finally, the use of the timing controller 200 will be described.
FIG. 9 is a diagram showing an electronic device 500. The electronic device 500 of FIG. 9 can be a laptop computer, a tablet terminal, a smartphone, a portable game machine, an audio player, or the like. The electronic device 500 includes a graphic controller 110, a display panel 102, a gate driver 104, and a source driver 106 built in the housing 502. A transmission device 120 including a differential transmitter, a transmission line, and a differential receiver may be provided between the timing controller 300 and the graphic controller 110.

In addition to the electronic device 500, the timing controller 300 can also be used for an in-vehicle display embedded in a console of an automobile, a medical device, and the like.

Although the present invention has been described using specific terms and phrases based on the embodiments, the embodiments merely indicate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangement changes are permitted without departing from the ideas of the present invention.

100 ... image display system, 102 ... display panel, 104 ... gate driver, 106 ... source driver, 110 ... graphic controller, 200, 300 ... timing controller, 302 ... receiver, 304 ... memory, 306 ... logic circuit, 308 ... transmitter, 310 ... Memory read circuit, 312 ... Multiphase clock generator, 314 ... Automatic adjustment circuit, 316 ... Latch circuit, 320 ... Phase judge, 322 ... Selector, DQ ... Data, DQS ... Data strobe signal, 500 ... Electronic equipment.

Claims (16)

A receiver that receives the pixel data that makes up the image data and the pixel clock that accompanies it from the graphic controller.
An SDRAM (Synchronous Dynamic Random Access Memory) that holds the pixel data received by the receiver, and
A memory read circuit that supplies a clock signal based on the pixel clock to the SDRAM and reads the pixel data from the SDRAM .
A logic circuit that performs signal processing on the pixel data read by the memory read circuit, and
A transmitter that transmits the pixel data that has undergone signal processing by the logic circuit to the source driver,
With
The memory read circuit is
A multi-phase clock generator that generates a multi-phase clock including a first-phase clock to an N-phase clock whose phase is shifted by 360 ° / N (N is an integer of 2 or more) based on the pixel clock.
During the automatic adjustment period, the clock signal based on the pixel clock is used to read-access the SDRAM, and the data strobe signal from the SDRAM is captured by using the polyphase clock. (I) Of the polyphase clocks rising or falling edge is substantially the one located at the center and the first read clock for high period, (ii) a rising or falling edge of the multiphase clock high period of the data strobe signal However, there is an automatic adjustment circuit that uses another one located substantially in the center of the low section of the data strobe signal as the second read clock for the low section.
A latch circuit that takes in data from the SDRAM during a normal period by using the first read clock and the second read clock.
Only including,
The automatic adjustment circuit
The data strobe signal is high among the first phase clock to the N phase clock based on N data obtained by latching the data strobe signal based on the first phase clock to the N phase clock. A first-phase determiner that generates a first-phase select signal indicating one that is located substantially in the center of the section,
A first multiplexer that receives the first-phase clock to the N-phase clock, selects one according to the first-phase select signal, and outputs it as the first read clock.
A timing controller characterized by including . The timing controller according to claim 1, wherein a burst read is used for the read access during the automatic adjustment period. When the data latched by the phase i clock to the phase j clock of the data strobe signal is continuously high, the first phase select signal is the central clock of the phase i clock and the phase j clock. the timing controller of claim 1 or 2, characterized in that it presents a. The automatic adjustment circuit is characterized in that, among the first-phase clocks to the N-phase clocks, a clock that is predeterminedly shifted with respect to the clock selected as the first read clock is used as the second read clock. Item 3. The timing controller according to item 3. The automatic adjustment circuit
Of the first phase clock to the N phase clock, the row of the data strobe signal is based on N data obtained by latching the data strobe signal based on the first phase clock to the N phase clock. A second phase determiner that generates a second phase select signal indicating one that is located substantially in the center of the section,
A second multiplexer that receives the first-phase clock to the N-phase clock, selects one according to the second phase select signal, and outputs it as the second read clock.
Including
When the data in which the data strobe signal is latched from the k-phase clock to the l-phase clock is continuously low, the second-phase select signal is the central clock of the k-phase clock and the l-phase clock. the timing controller as claimed in any one of 3 claims 1, wherein the indicating. A receiver that receives the pixel data that makes up the image data and the pixel clock that accompanies it from the graphic controller.
An SDRAM (Synchronous Dynamic Random Access Memory) that holds the pixel data received by the receiver, and
A memory read circuit that supplies a clock signal based on the pixel clock to the SDRAM and reads the pixel data from the SDRAM.
A logic circuit that performs signal processing on the pixel data read by the memory read circuit, and
A transmitter that transmits the pixel data that has undergone signal processing by the logic circuit to the source driver,
With
The memory read circuit is
A multi-phase clock generator that generates a multi-phase clock including a first-phase clock to an N-phase clock whose phase is shifted by 360 ° / N (N is an integer of 2 or more) based on the pixel clock.
During the automatic adjustment period, read access is performed to the SDRAM, and the data strobe signal from the SDRAM is captured by using the polyphase clock. (I) The rising edge or falling edge of the polyphase clock is the data strobe signal. One located substantially in the center of the high section of is used as the first read clock for the high section, and (ii) the rising edge or falling edge of the polyphase clock is substantially the low section of the data strobe signal. An automatic adjustment circuit that uses another one located in the center as the second read clock for the low section,
A latch circuit that takes in data from the SDRAM during a normal period by using the first read clock and the second read clock.
Including
The automatic adjustment circuit
The data strobe signal is low among the first phase clock to the N phase clock based on N data obtained by latching the data strobe signal based on the first phase clock to the N phase clock. A second phase determiner that generates a second phase select signal indicating one that is located substantially in the center of the section,
A second multiplexer that receives the first-phase clock to the N-phase clock, selects one according to the second phase select signal, and outputs it as the second read clock.
A timing controller characterized by including. The automatic adjustment circuit is characterized in that, among the first-phase clocks to the N-phase clocks, a clock that is predeterminedly shifted with respect to a clock selected as the second read clock is used as the first read clock. Item 6. The timing controller according to item 6. The timing controller according to any one of claims 1 to 7, wherein the automatic adjustment period is inserted in a blank section of one frame. The timing controller according to claim 8, wherein the automatic adjustment period occurs every frame. The timing according to any one of claims 1 to 9, wherein the automatic adjustment circuit determines that an abnormality occurs when at least one of the high section and the low section of the data strobe signal is less than a predetermined width. controller. The timing controller according to claim 10, wherein the automatic adjustment circuit initializes the SDRAM when it is determined to be abnormal. The automatic adjustment circuit ignores the low section when a low section having a predetermined width or less occurs in the high section, and ignores the low section when a high section having a predetermined width or less occurs in the low section. The timing controller according to any one of claims 1 to 11, wherein the timing controller is ignored. The timing controller according to any one of claims 1 to 12, wherein the polyphase clock is any of 8, 12, 16, 24, and 32 phases. The timing controller according to any one of claims 1 to 13, wherein the timing controller is integrally integrated on one semiconductor substrate. An electronic device comprising the timing controller according to any one of claims 1 to 14. It is a control method of the timing controller.
The step of receiving the pixel data that composes the image data and the pixel clock that accompanies it from the graphic controller, and
The step of holding the pixel data in SDRAM (Synchronous Dynamic Random Access Memory) and
A step of generating a multi- phase clock including a first-phase clock to an N-phase clock whose phase is shifted by 360 ° / N (N is an integer of 2 or more) based on the pixel clock.
During the automatic adjustment period, the clock signal based on the pixel clock is used to read-access the SDRAM, and the data strobe signal from the SDRAM is captured by the polyphase clock. (I) Rise of the polyphase clock. One of the edge or falling edge located substantially in the center of the high section of the data strobe signal is selected as the first read clock for the high section , and (ii) the rising edge or falling edge of the polyphase clock. The step of selecting another one whose edge is substantially centered in the low section of the data strobe signal as the second read clock for the low section.
In a normal period, a step of taking in data from the SDRAM by using the first read clock and the second read clock and performing signal processing, and
The step of transmitting the pixel data that has undergone signal processing to the source driver, and
Bei to give a,
The step selected as the first read clock is
A step of latching the data strobe signal based on the first-phase clock to the N-phase clock, and
A first phase select signal indicating one of the first phase clock to the N phase clock in which the data strobe signal is located substantially in the center of the high section, based on the N data obtained in the latching step. And the steps to generate
A step of selecting one of the first phase clock to the N phase clock corresponding to the first phase select signal as the first read clock, and
A control method characterized by including .

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