JP2009168705A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correctly determine the existence of a skew between differential signals without using an inspection apparatus. <P>SOLUTION: A semiconductor device 10 is provided with a self-test connection selecting circuit 16, an error detecting circuit 17, and a test control circuit 18. The connection selecting circuit 16 connects a subsequent stage of an arbitrary differential signal driver and a previous stage of an arbitrary differential signal receiver, and loops back a signal input to the former. The error detecting circuit 17 determines whether the signal before the loop back is matched with the signal after the loop back. The test control circuit 18 controls the connection selecting circuit 16, and sequentially switches one of the differential signal drivers 13a-13d and the differential signal receivers 14a-14d, and connects it to arbitrary one of the other. Each time a connection of the connection selecting circuit 16 is switched, it determines the existence of the skew between the differential signals output from the differential signal drivers and the existence of the skew between the differential signals input to the differential signal receivers based on a result of a comparison implemented by the error detecting circuit 17. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention converts a serial signal output from a parallel-serial conversion circuit into a differential signal and outputs the differential signal to the outside, and converts the differential signal input from the outside into a serial signal. The present invention relates to a semiconductor device including a plurality of differential signal input circuits that output to a serial / parallel conversion circuit.

  For example, a digital camera is provided with a differential interface in order to transmit a data signal of a captured image captured by an image sensor at high speed to an image processing circuit or the like. The differential interface includes a semiconductor device for inputting and outputting differential signals.

  As shown in FIG. 10, a semiconductor device 100 includes a parallel / serial conversion circuit (hereinafter simply referred to as a P / S conversion circuit) 101, a differential signal driver 102, a differential signal receiver 103, and a serial / parallel conversion circuit (hereinafter referred to as “P / S conversion circuit”). , Simply referred to as an S / P conversion circuit) 104.

  The P / S conversion circuit 101 converts a parallel signal into a serial signal in synchronization with a clock signal input from a PLL (phase synchronization circuit) 106. The differential signal driver 102 converts serial signals and clock signals output from the P / S conversion circuit 101 and the PLL 106 into differential signals. The differential signal converted by the differential signal driver 102 is output from the differential output terminal 109 via the output differential pair wiring 108.

  The differential signal receiver 103 converts a differential signal input from the differential input terminal 110 via the input differential pair wiring 111 into a serial signal and a clock signal, respectively, and converts each converted signal into an S / P conversion circuit. To 104. The S / P conversion circuit 104 converts the serial signal into a parallel signal in synchronization with the input clock signal and outputs the parallel signal to the internal circuit.

Such an inspection of the semiconductor device 100 is performed using an inspection device 112 such as an LSI tester (see Patent Documents 1 to 3). The differential signal output from the differential output terminal 109 of the semiconductor device 100 is input to the differential signal receiver 116 of the inspection device 112 and inspected via the interface 114 including a probe card and a socket. Further, when the input of the differential signal to the semiconductor device 100 is inspected, the differential signal output from the differential signal driver 117 of the inspection device 112 is the differential signal of the semiconductor device 100 via the interface 114 described above. The inspection is performed by inputting to the input terminal 110.
JP 2007-78643 A JP 2000-171524 A Japanese Patent Laid-Open No. 2003-167034

  Incidentally, input / output of each differential signal between the semiconductor device 100 and the inspection device 112 is performed via the interface 114. For this reason, when a difference occurs in the line length or wiring capacity of the transmission path of each interface 114, the skew (delay) between the differential signals input from the semiconductor device 100 to the inspection device 112, or from the inspection device 112. Skew between differential signals input to the semiconductor device 100 occurs, which causes generation of common mode noise. As a result, even if the inspection device 112 performs the inspection, the skew between the differential signals output from each differential signal driver 102 of the semiconductor device 100 and the difference between the differential signals input to each differential signal receiver 116. It is difficult to accurately determine the presence or absence of skew. Such a problem also occurs in the inspection methods described in Patent Documents 1 to 3.

  In recent years, in order to cope with higher speeds of semiconductor devices, for example, higher data rates of serial signals transmitted by semiconductor devices, inspections have been performed using high-speed inspection devices. Since the device is expensive, there is a problem that the inspection cost increases.

  The present invention has been made to solve the above problem, and without using an expensive inspection device, the skew between differential signals output from each differential signal driver and the input to each differential signal receiver. An object of the present invention is to provide a semiconductor device that can accurately determine the presence or absence of skew between differential signals.

  In order to solve the above problems, the present invention converts a parallel-serial conversion circuit, a serial-parallel conversion circuit, a serial signal input from the parallel-serial conversion circuit into a differential signal, and outputs the converted differential signal to the outside A plurality of differential signal output circuits, and a plurality of differential signal input circuits for converting a differential signal input from the outside into a serial signal and outputting the converted serial signal to the serial-parallel conversion circuit A connection selection circuit capable of selectively connecting a subsequent stage of the arbitrary differential signal output circuit and a front stage of the arbitrary differential signal input circuit, and the differential connected via the connection selection circuit A serial signal inputted to the former of the signal output circuit and the differential signal input circuit, and a serial signal outputted from the latter to which the differential signal from the former is inputted There characterized in that it comprises a determination circuit for determining whether they match.

  A drive circuit that drives the connection selection circuit to sequentially switch and connect one of the differential signal output circuits and one of the differential signal input circuits to the other one circuit; and the determination circuit Performs the determination every time the connection of the connection selection circuit is switched, and based on the determination result of the determination circuit, between the differential signals that transmit the differential pair wiring that connects each of the one circuit and the external terminal It is preferable to determine whether or not there is any skew.

  The determination circuit includes a strobe signal input circuit for inputting a strobe signal, and the determination circuit is synchronized with the strobe signal input from the strobe signal input circuit, and the serial signal input from the former and the latter It is preferable to determine whether or not the output serial signal matches.

  The strobe signal input circuit preferably changes the timing of determination by the determination circuit by changing a phase of the strobe signal input to the determination circuit.

  The semiconductor device of the present invention is connected via a connection selection circuit, a connection selection circuit capable of selectively connecting a subsequent stage of an arbitrary differential signal output circuit and a previous stage of the arbitrary differential signal input circuit. Since the differential signal output circuit and the differential signal input circuit are provided with a determination circuit for determining whether or not the serial signal input to the former and the serial signal output from the latter coincide with each other, it is expensive. The presence or absence of skew between differential signals output from each differential signal driver and differential signals input to each differential signal receiver using only a semiconductor device without using a simple inspection device Can do. In particular, since the test can be performed without using an interface composed of a probe card, a socket, etc., it is not necessary to consider the difference in the line length of the interface transmission line and the difference in wiring capacity, and the presence or absence of skew can be accurately determined. Further, since it is not necessary to use an expensive inspection device, the inspection cost can be suppressed.

  A semiconductor device 10 shown in FIG. 1 constitutes a differential interface provided in an electronic device such as a digital camera, and is used for transmission / reception of various data signals. The semiconductor device 10 includes a PLL (phase synchronization circuit) 11, a P / S conversion circuit 12, differential signal drivers (differential signal output circuits) 13a to 13d, differential signal receivers (differential signal input circuits) 14a to 14d, An S / P conversion circuit 15, a connection selection circuit 16, an error detection circuit 17, and a test control circuit (drive circuit) 18 are provided.

  The PLL 11 outputs the clock signals Tx_clk and PLL_clk whose phases are synchronized with the clock signal Clk to the differential signal driver 13d and the error detection circuit 17, respectively, according to the internal clock signal Clk input from the internal circuit of the digital camera. . The PLL 11 also inputs a clock signal to the P / S conversion circuit 12. In this embodiment, since the 8-bit parallel signal is converted into a 1-bit serial signal in the P / S conversion circuit 12, the frequency of the clock signal output from the PLL 11 is adjusted to 8 times the internal clock signal Clk. Is done.

  As shown in FIG. 2A, the P / S conversion circuit 12 receives 8-bit parallel signals D0 (D0 <0> to D0 <7>) and D1 (D1 <0) from an internal circuit of the digital camera, for example. > To D1 <7>) and D2 (D2 <0> to D2 <7>) are input. As shown in FIG. 2 (B), the P / S conversion circuit 12 synchronizes the parallel signals D0 to D2 with serial signals Tx0, Tx1, Tx2 having an eight times higher frequency rate in synchronization with the clock signal input from the PLL 11. Convert to

  Returning to FIG. 1, the serial signals Tx0 to Tx2 output from the P / S conversion circuit 12 and the clock signal Tx_clk output from the PLL 11 are input to the differential signal drivers 13a to 13d, respectively. The differential signal drivers 13a to 13d convert the input serial signals Tx0 to Tx2 and the clock signal Tx_clk into positive (+) differential signals Tx0 +, Tx1 +, Tx2 +, Tx_clk + and negative (−) differential signals Tx0−. , Tx1-, Tx2-, and Tx_clk-. Since a method for converting a serial signal or the like into a differential signal is well known, the description thereof is omitted here. The differential signals converted by the differential signal drivers 13 a to 13 d are output to the outside from the differential output terminal 21 via the output differential pair wiring 20.

  The differential signal receivers 14a to 14d include positive differential signals Rx0 + to Rx2 + and Rx_clk + input from the differential input terminals 23 via the input differential pair wiring 24, and negative differential signals Rx0− to Rx2. − And Rx_clk− are converted into serial signals Rx0 to Rx2 and a clock signal Rx_clk, respectively. Note that a method for converting a differential signal into a data signal is also well known, and a description thereof will be omitted. The serial signals Rx0 to Rx2 and the clock signal Rx_clk output from the differential signal receivers 14a to 14d are input to the S / P conversion circuit 15, respectively.

  The S / P conversion circuit 15 converts the serial signals Rx0 to Rx2 into 8-bit parallel signals D0, D1, and D2, respectively, in synchronization with the clock signal Rx_clk (see FIG. 2B) (FIG. 2A). reference). The parallel signals D0 to D2 converted by the S / P conversion circuit 15 are input to an internal circuit of the digital camera.

  The connection selection circuit 16, the error detection circuit 17, and the test control circuit 18 include a skew between differential signals output from the differential signal drivers 13a to 13d and a difference input to the differential signal receivers 14a to 14d. It is a self-test circuit for determining the presence or absence of skew between motion signals. The skew is a difference in the time constant of the differential signal or a delay in the delay time. For example, the skew is caused by a difference in wiring length between the output differential pair wiring 20 and the input differential pair wiring 24 or a wiring capacitance difference. To do.

  As shown in FIGS. 3A and 3B, the connection selection circuit 16 includes an input terminal IN0 ± and an input terminal IN1 connected to the output differential pair wiring 20 at the subsequent stage of the differential signal drivers 13a to 13d, respectively. Four input terminal pairs each including ±, input terminal IN2 ±, and input terminal IN3 ± are provided. The connection selection circuit 16 includes an output terminal OUT0 ±, an output terminal OUT1 ±, an output terminal OUT2 ±, and an output terminal OUT3 ± connected to the input differential pair wiring 24 in the previous stage of the differential signal receivers 14a to 14d. There are four output terminal pairs. Note that the signal RTx in the figure indicates a looped back signal.

  The connection selection circuit 16 selectively connects an arbitrary input terminal pair and an arbitrary output terminal pair based on the selection signal Ch_select input from the test control circuit 18. 3A and 3B show examples of connections, and combinations of connections other than those shown are possible. In addition, any one of the output terminals and the input terminals can be sequentially switched and connected to the other one terminal.

  Returning to FIG. 1, serial signals and clock signals input to the differential signal drivers 13 a to 13 d are differentially transmitted via the output differential pair wiring 20, the connection selection circuit 16, and the input differential pair wiring 24. It is output from any of the signal receivers 14a to 14d. That is, the serial signal and the clock signal are looped back in the semiconductor device 10. Accordingly, the connection selection circuit 16 forms a loopback path for the serial signal and the clock signal, and the loopback path for the serial signal and the clock signal is switched by switching the connection of the input / output terminals.

  The error detection circuit 17 is a serial signal or clock signal input to the former (differential signal driver) when an arbitrary differential signal driver and an arbitrary differential signal receiver are connected via the connection selection circuit 16 or the like. And whether the serial signal or clock signal output from the latter (differential signal receiver) is matched with the loopback is determined.

  As shown in FIG. 4, the error detection circuit 17 is roughly composed of a first selection circuit 27, a second selection circuit 28, and a determination circuit 29. The first selection circuit 27 includes four input terminals IN0 to IN3 respectively connected to the respective previous wirings of the differential signal drivers 13a to 13d, and one output terminal OUT connected to the determination circuit 29. Yes. The first selection circuit 27 alternatively inputs the serial signals Tx0 to Tx2 and the clock signal Tx_clk input from the respective wirings to the determination circuit 29 based on the selection signal Sig_sel1 input from the test control circuit 18.

  The second selection circuit 28 includes four input terminals IN <b> 0 to IN <b> 3 connected to the respective wirings subsequent to the differential signal receivers 14 a to 14 d and one output terminal OUT connected to the determination circuit 29. Yes. The second selection circuit 28 alternatively determines the serial signal RTx0 to RTx2 or the clock signal RTx_clk looped back via the connection selection circuit 16 or the like based on the selection signal Sig_sel2 input from the test control circuit 18. To enter. The selection signal Sig_sel2 controls the second selection circuit 28 so that a signal obtained by looping back the signal input from the first selection circuit 27 to the determination circuit 29 is input to the determination circuit 29.

  The determination circuit 29 receives from the first and second selection circuits 27 and 28 a serial signal and clock signal Tx before loop back (hereinafter simply referred to as a signal before loop back) Tx and a serial signal and clock signal that have been looped back. RTx (hereinafter simply referred to as a signal after loopback) is input. The signal RTx after the loopback is composed of serial signals RTx0 to RTx2 and a clock signal RTx_clk.

  The determination circuit 29 determines whether the signals before and after the loopback match. As shown in FIG. 5, the determination circuit 29 includes a strobe generation circuit 31 (strobe signal input circuit) and a comparison circuit 32. The strobe generation circuit 31 generates a strobe signal (strobe: refer to FIG. 6) for setting the timing of the comparison operation by the comparison circuit 32 based on the clock signal PLL_clk and the trigger signal (Trigger) input from the test control circuit 18. To do.

  The strobe signal corresponds to the signal components Dn <0> to Dn <7> (n = 0 to 2) included in the signals Tx and RTx before and after the loopback in synchronization with the rising and falling edges of the clock signal PLL_clk. (See FIG. 6). Then, for example, by varying the trigger signal input from the test control circuit 18, various conditions such as the frequency and phase of the strobe signal are varied. The strobe signal generated by the strobe generation circuit 31 is input to the comparison circuit 32.

  The comparison circuit 32 is connected to the first selection circuit 27, the second selection circuit 28, and the strobe generation circuit 31, respectively. A signal Tx before the loopback and a signal RTx after the loopback are output from the circuits 27, 28, and 31, respectively. The strobe signal is input. As shown in FIG. 6, the comparison circuit 32 synchronizes with the rising edge of the strobe signal so that the signal components Dn <0> to Dn <7> of the signals Tx and RTx before and after the loopback are “0” or “ 1 ”is detected.

  As shown in FIG. 7, the comparison circuit 32 compares the detection results for each of the signal components Dn <0> to Dn <7> of the signals Tx and RTx before and after the loopback, and the detection results are compared. If they match, the error signal (Error) is set to “0”, and if the detection results do not match, the error signal is set to “1”. In FIG. 7, serial signals Tx0 and RTx0 are illustrated as examples of the pre-loopback signal Tx and the post-loopback signal RTx, respectively, but other signals are compared in the same manner. When the error signals in all the signal components Dn <0> to Dn <7> are set to “0”, it is determined that the signals Tx and RTx before and after the loopback match.

  In contrast, when the error signal in any one of the signal components Dn <0> to Dn <7> is set to “1”, it is determined that the signals Tx and RTx before and after the loopback do not match. Then, an error signal is output from the comparison circuit 32 to the test control circuit 18. The error signal output to the test control circuit 18 includes information on signal components whose detection results do not match.

  Note that the comparison between the signals Tx and RTx before and after the loopback is performed in synchronization with the rising edge of the strobe signal. Therefore, as shown in FIG. 6 described above, each signal Tx depends on the phase of the strobe signal, even if the rise of the signal RTx after the loopback is delayed with respect to the signal Tx before the loopback. , RTx signal components Dn <0> to Dn <7> may all coincide with each other. In this case, it is determined that the signals Tx and RTx before and after the loopback match.

  Therefore, the test control circuit 18 adjusts the trigger signal or the like input to the strobe generation circuit 31 and shifts the phase of the strobe signal input to the comparison circuit 32 in the direction in which the time is advanced (rightward in FIG. 6). Let As a result, as shown in FIGS. 8 and 9, the detection results of the signal components D0 <1>, D0 <5>, and D0 <7> corresponding to the rising edges of the signals Tx and RTx before and after the loopback are different. , Each error signal is set to “1”. As a result, it can be determined that the rises of the signals Tx and RTx before and after the loopback do not match.

  In addition, even when the rise of the signal RTx after the loopback is earlier than the signal Tx before the loopback, the signals Tx and RTx before and after the loopback are shifted by shifting the phase of the strobe signal in the same direction. It can be determined that the rising edges of the two do not match. Further, when there is a deviation in the falling of the signals Tx and RTx before and after the loopback, for example, by shifting the phase of the strobe signal in a direction in which the time is delayed, the falling of both signals Tx and RTx is caused. It can be determined that they do not match.

  In this way, when the comparison circuit 32 compares the signals Tx and RTx before and after the loopback, by appropriately shifting the phase of the strobe signal, it is possible to accurately determine whether the signals Tx and RTx before and after the loopback match. Can be determined.

  Returning to FIG. 1, the test control circuit 18 controls the connection selection circuit 16 and the error detection circuit 17 to skew between the differential signals output from the differential signal drivers 13 a to 13 d and the differential signals. A self test is performed to determine the presence or absence of skew between differential signals input to the receivers 14a to 14d. Hereinafter, an example of the self-test procedure will be described.

  The test control circuit 18 starts by determining whether or not there is a skew between the differential signals output from the differential signal drivers 13a to 13d. The test control circuit 18 inputs the selection signal Ch_select to the connection selection circuit 16 and connects only the input terminal IN0 ± and the output terminal OUT0 ± of the connection selection circuit 16. As a result, the differential pair wiring for output 20 at the rear stage of the differential signal driver 13a and the differential pair wiring for input 24 at the front stage of the differential signal receiver 14a are connected.

  Further, the test control circuit 18 inputs the selection signals Sig_sel1, Sig_sel2 to the first and second selection circuits 27, 28 (see FIG. 4) of the error detection circuit 17, respectively, and the input terminals IN0 of both selection circuits 27, 28. Are connected to the output terminal OUT (see FIG. 4). When these connections are completed, the test control circuit 18 inputs a test start signal to the internal circuit of the digital camera and inputs a trigger signal to the strobe generation circuit 31 of the error detection circuit 17 (determination circuit 29).

  Based on the test start signal from the test control circuit 18, the internal clock signal Clk is input to the PLL 11 from the internal circuit of the digital camera, and the parallel signals D 0 to D 2 are input to the P / S conversion circuit 12. As a result, the clock signals Tx_clk and PLL_clk are input from the PLL 11 to the differential signal driver 13d and the error detection circuit 17, respectively. Furthermore, the PLL 11 also inputs a clock signal to the P / S conversion circuit 12.

  The P / S conversion circuit 12 converts each parallel signal D0 to D2 into a serial signal Tx0 to Tx2 having a frequency rate of 8 times in synchronization with the clock signal input from the PLL 11, and the converted serial signal is a differential signal. Each is input to the drivers 13a to 13c. The differential signal drivers 13a to 13d convert the input serial signals Tx0 to Tx2 and the clock signal Tx_clk into differential signals, respectively, and output the differential signals to the output differential pair wiring 20.

  Of the differential signals output from the differential signal drivers 13a to 13d, only the differential signal output from the differential signal driver 13a is input to the differential signal receiver 14a via the connection selection circuit 16. . As a result, only the serial signal Tx0 input to the differential signal driver 13a is looped back and output as the serial signal RTx0 from the differential signal receiver 14a.

  The serial signal Tx0 before the loopback and the serial signal RTx0 after the loopback are input to the comparison circuit 32 via the first and second selection circuits 27 and 28, respectively. The strobe generation circuit 31 generates a strobe signal based on the clock signal PLL_clk input from the PLL 11 and the trigger signal input from the test control circuit 18 and inputs the strobe signal to the comparison circuit 32.

  The comparison circuit 32 detects whether the signal components D0 <0> to D0 <7> of the serial signals Tx0 and RTx0 are “0” or “1” in synchronization with the rising edge of the strobe signal. Then, it is compared whether or not the detection results of the respective signal components D0 <0> to D0 <7> match (see FIGS. 6 and 7). Then, the comparison circuit 32 determines that the serial signals Tx0 and RTx0 match when the detection results of all the signal components D0 <0> to D0 <7> match.

  The comparison circuit 32 also sends an error signal to the test control circuit 18 if any one of the detection results of the signal components D0 <0> to D0 <7> of the serial signals Tx0 and RTx0 does not match. input. The test control circuit 18 stores the error signal input from the comparison circuit 32 in a memory or the like (not shown). As described above, since the error signal includes information on the signal components whose detection results do not match, the test control circuit 18 determines which signal components of the serial signals Tx0 and RTx0 do not match. I can grasp it.

  When the first comparison process by the comparison circuit 32 is completed, the test control circuit 18 shifts the phase of the strobe signal input from the strobe generation circuit 31 to the comparison circuit 32. The comparison circuit 32 performs the above-described comparison process again based on the strobe signal whose phase has been shifted.

  Similarly, the test control circuit 18 shifts the phase of the strobe signal input from the strobe generation circuit 31 to the comparison circuit 32, and the comparison circuit 32 performs the above-described operation based on the strobe signal whose phase is shifted. Perform the comparison process. Note that the number of phase shifts, the shift direction, and the shift amount of the strobe signal may be appropriately determined. Thus, by appropriately shifting the phase of the strobe signal, it can be accurately determined whether or not the serial signals Tx0 and RTx0 match.

  When all the comparison processing of the serial signals Tx0 and RTx0 is completed, the test control circuit 18 inputs the selection signal Ch_select to the connection selection circuit 16, and connects the subsequent stage of the differential signal driver 13b to the previous stage of the differential signal receiver 14a. To do. As a result, only the serial signal Tx1 input to the differential signal driver 13b is looped back and output as the serial signal RTx1 from the differential signal receiver 14a.

  Further, the test control circuit 18 inputs a new selection signal Sig_sel1 to the first selection circuit 27 and connects the input terminal IN1 and the output terminal OUT of the first selection circuit 27. As a result, the serial signal Tx1 before the loopback and the serial signal RTx1 after the loopback are input to the comparison circuit 32 via the first and second selection circuits 27 and 28, respectively. The comparison circuit 32 compares the serial signal Tx1 and the serial signal RTx1 in the same manner as the comparison process described above.

  Similarly, the subsequent stages of the differential signal drivers 13c and 13d are sequentially connected to the previous stage of the differential signal receiver 14a, and the serial signal Tx2 and the clock signal Tx_clk respectively input to the differential signal drivers 13c and 13d are looped. Back. Then, the comparison circuit 32 compares the serial signal Tx2 and the clock signal Tx_clk before the loopback with the serial signal RTx2 and the clock signal RTx_clk after the loopback, respectively.

  When all of these comparison processes are completed, the test control circuit 18 refers to the result of each comparison process and determines whether or not there is a skew between the differential signals output from the differential signal drivers 13a to 13d. Specifically, all the differential signals output from the differential signal drivers 13a to 13d are input to one differential signal receiver 14a (any of 14b to 14d) via the connection selection circuit 16. The For this reason, when no skew occurs between the differential signals output from the differential signal drivers 13a to 13d, the results of the comparison processes are all the same.

  For example, when it is determined that the serial signal Tx0 and the serial signal RTx0 match, it is determined that other comparison results also match. Further, for example, when it is determined that the serial signal Tx0 and the serial signal RTx0 do not match, it is determined that the other does not match, and the position of the signal component that does not match (for example, the rise or rise of the signal). (Fall) becomes the same.

  On the contrary, when skew is generated between the differential signals output from the differential signal drivers 13a to 13d, the results of the above comparison processes are not all the same. Specifically, signals that match before and after the loopback are mixed and signals that do not match. Even when it is determined that the results of the respective comparison processes do not all match, the positions of the signal components that do not match differ.

  The test control circuit 18 determines whether or not there is a skew between the differential signals output from the differential signal drivers 13a to 13d by referring to the result of each comparison process performed in the comparison circuit 32 in this way. . When this determination is completed, the test control circuit 18 starts determining whether or not there is a skew between the differential signals input to the differential signal receivers 14a to 14d.

  The test control circuit 18 controls the connection selection circuit 16 to sequentially switch, for example, the subsequent stage of the differential motion signal driver 13a (any of 13b to 13d) to the previous stage of the differential signal receivers 14a to 14d. . Thus, the serial signal Tx0 input to the differential signal driver 13a can be looped back and output from each of the differential signal receivers 14a to 14d. The comparison circuit 32 compares the serial signal Tx0 with the RTx0 output from each of the differential signal receivers 14a to 14d in the same manner as in the skew determination described above.

  When all these comparison processes are completed, the test control circuit 18 refers to the result of each comparison process to determine whether or not there is a skew between the differential signals input to the differential signal receivers 14a to 14d. Since this determination method is the same as that in the skew determination described above, description thereof is omitted.

  When it is determined that the skew between the differential signals output from the differential signal drivers 13a to 13d is not generated by the previously performed skew determination, the comparison by the comparison circuit 32 is performed by a different method. It can be performed. Specifically, the subsequent stage of each differential signal driver 13a-13d is connected to the previous stage of each differential signal receiver 14a-14d (see FIG. 3A). Then, only the first and second selection circuits 27 and 28 are switched, and the signals Tx0 to Tx2 and Tx_clk before the loopback are compared with the signals RTx0 to RTx2 and RTx_clk after the loopback, respectively.

  Since there is no skew between the differential signals output from the differential signal drivers 13a to 13d, the differential signal receivers 14a to 14a are based on whether the comparison results by the comparison circuit 32 are all the same. Whether or not there is a skew between the differential signals output from 14d can be determined. In this case, since it is not necessary to switch the connection selection circuit 16, the time required for skew determination can be reduced.

  As described above, the self-test for determining the skew between the differential signals output from the differential signal drivers 13a to 13d and the skew between the differential signals input to the differential signal receivers 14a to 14d is performed. Complete.

  As described above, the semiconductor device 10 of the present invention includes the self-test circuit including the connection selection circuit 16, the error detection circuit 17, and the test control circuit 18, and therefore includes the above-described inspection apparatus and interface (see FIG. 10). Without using, it is possible to determine the skew between the differential signals output from the differential signal drivers 13a to 13d and the presence or absence of the skew between the differential signals input to the differential signal receivers 14a to 14d. . In particular, since a test can be performed without going through an interface, the presence or absence of skew can be accurately determined. Further, since it is not necessary to use an expensive inspection device, the inspection cost can be reduced.

  In the above embodiment, after determining whether or not there is skew between the differential signals output from the differential signal drivers 13a to 13d, between the differential signals input to the differential signal receivers 14a to 14d. However, the present invention is not limited to this, and the order may be reversed.

  In the above embodiment, the case where the comparison circuit 32 compares the signals before and after the loopback in synchronization with the rising edge of the strobe signal input from the strobe generation circuit 31 has been described as an example. The present invention is not limited to this, and the signals before and after the loopback may be compared within the signal width of the strobe signal.

  In the above embodiment, the semiconductor device constituting the differential interface provided in the digital camera has been described as an example. However, the present invention is not limited to this. For example, the present invention can be applied to a semiconductor device that constitutes a differential interface provided in various electronic devices (devices) such as a differential interface that connects a probe of a measuring device (such as an oscilloscope) and a device body for various measurements. it can.

It is explanatory drawing for demonstrating schematically the structure of the semiconductor device of this invention. It is explanatory drawing for demonstrating the parallel serial conversion process and serial parallel conversion process by a semiconductor device. It is explanatory drawing for demonstrating operation | movement of a connection selection circuit. It is explanatory drawing for demonstrating schematically the structure of an error detection circuit. It is explanatory drawing for demonstrating schematically the structure of a determination circuit. It is explanatory drawing for demonstrating the comparison process of the signal before and behind the loopback performed by a determination circuit synchronizing with the rising edge of a strobe signal. It is explanatory drawing for demonstrating the result of the comparison process of FIG. It is explanatory drawing for demonstrating the comparison process by the comparison circuit when the phase of a strobe signal is shifted. It is explanatory drawing for demonstrating the result of the comparison process of FIG. It is explanatory drawing for demonstrating schematically the structure of the conventional semiconductor device.

Explanation of symbols

10 Semiconductor Device 11 PLL (Phase Synchronization Circuit)
12 parallel-serial conversion circuit 13 differential signal driver 14 differential signal receiver 15 serial-parallel conversion circuit 16 connection selection circuit 17 error detection circuit 18 test control circuit 20 differential pair wiring for output 24 differential pair wiring for input 27 first selection Circuit 28 Second selection circuit 29 Determination circuit 31 Strobe generation circuit 32 Comparison circuit

Claims (4)

A parallel-serial conversion circuit, a serial-parallel conversion circuit, a plurality of differential signal output circuits for converting a serial signal input from the parallel-serial conversion circuit into a differential signal, and outputting the converted differential signal to the outside; In a semiconductor device comprising a plurality of differential signal input circuits that convert a differential signal input from a serial signal and output the converted serial signal to the serial-parallel conversion circuit,
A connection selection circuit capable of selectively connecting a subsequent stage of any of the differential signal output circuits and a preceding stage of any of the differential signal input circuits;
Serial signal input to the former of the differential signal output circuit and the differential signal input circuit connected via the connection selection circuit, and serial output from the latter to which the differential signal from the former is input A semiconductor device comprising: a determination circuit that determines whether or not the signal matches. A drive circuit for driving the connection selection circuit to sequentially switch and connect one of the differential signal output circuits and one of the differential signal input circuits to the other one circuit; and the determination circuit Performs the determination every time the connection of the connection selection circuit is switched,
2. The presence / absence of skew between differential signals transmitted through a differential pair wiring connecting each of the one circuit and an external terminal is determined based on a determination result of the determination circuit. Semiconductor device. A strobe signal input circuit for inputting a strobe signal to the determination circuit;
The determination circuit determines whether the serial signal input from the former and the serial signal output from the latter coincide with each other in synchronization with the strobe signal input from the strobe signal input circuit. The semiconductor device according to claim 1, wherein:   4. The semiconductor device according to claim 3, wherein the strobe signal input circuit changes a timing of determination by the determination circuit by changing a phase of the strobe signal input to the determination circuit.

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