JP6752639B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6752639B2 JP6752639B2 JP2016126447A JP2016126447A JP6752639B2 JP 6752639 B2 JP6752639 B2 JP 6752639B2 JP 2016126447 A JP2016126447 A JP 2016126447A JP 2016126447 A JP2016126447 A JP 2016126447A JP 6752639 B2 JP6752639 B2 JP 6752639B2
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- plating layer
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- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 238000007747 plating Methods 0.000 claims description 172
- 229920005989 resin Polymers 0.000 claims description 122
- 239000011347 resin Substances 0.000 claims description 122
- 238000007789 sealing Methods 0.000 claims description 116
- 239000000463 material Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 21
- 229910000679 solder Inorganic materials 0.000 claims description 14
- 238000007772 electroless plating Methods 0.000 claims description 11
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- 238000005520 cutting process Methods 0.000 description 16
- 229910045601 alloy Inorganic materials 0.000 description 2
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- 229910052802 copper Inorganic materials 0.000 description 1
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- 239000003822 epoxy resin Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
- H01L2924/15747—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/183—Connection portion, e.g. seal
- H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
1 :第1リード
2 :第2リード
3 :第3リード
4 :半導体素子
6 :封止樹脂
10 :リードフレーム
40 :素子本体
41 :第1電極
42 :第2電極
43 :第3電極
49 :導電性接合材
51 :第1ワイヤ
52 :第2ワイヤ
61 :封止樹脂主面
62 :封止樹脂裏面
63 :封止樹脂側面
81 :切断線
101 :第1主面
102 :第1裏面
103 :リードフレーム
110 :第1端子部
111 :第1端子端面
112 :第1端子裏面
113 :第1端子側面
114 :第1端子主面
120 :第1連結部
121 :第1連結端面
180 :第1裏面側凹部
191 :第1表層めっき層
201 :第2主面
202 :第2裏面
210 :第2端子部
211 :第2端子端面
212 :第2端子裏面
213 :第2端子側面
214 :第2端子主面
220 :第2連結部
221 :第2連結端面
230 :第2ワイヤボンディング部
232 :第2ワイヤボンディング裏面
280 :第2裏面側凹部
291 :第2表層めっき層
301 :第3主面
302 :第3裏面
310 :第3端子部
311 :第3端子端面
312 :第3端子裏面
313 :第3端子側面
314 :第3端子主面
320 :第3連結部
321 :第3連結端面
322 :第3連結裏面
323 :第3連結側面
324 :第3連結主面
330 :素子ボンディング部
332 :素子ボンディング裏面
380 :第3裏面側凹部
391 :第3表層めっき層
392 :第3中層めっき層
631 :第1部
632 :第2部
801 :スリット
802,803:切断線
1010 :主面
1020 :裏面
3000 :リード母材イオン
3910 :表層めっきイオン
Claims (10)
- 各々が厚さ方向において互いに反対側を向く主面および裏面を有するリードフレームを用意する工程と、
前記リードフレームの主面に半導体素子を搭載する工程と、
前記リードフレームの一部および前記半導体素子を覆う封止樹脂を形成する工程と、
前記リードフレームのうち前記封止樹脂から露出した部分の少なくとも一部に、置換型の無電解めっきにより表層めっき層を形成する工程と、
を備え、
前記封止樹脂を形成する工程の後であって、前記表層めっき層を形成する工程の前に、前記封止樹脂および前記リードフレームの前記裏面に少なくとも開口するスリットを形成する工程を備え、
前記表層めっき層を形成する工程においては、前記リードフレームのうち前記スリットから露出した部位に、前記表層めっき層を形成することを特徴とする、半導体装置の製造方法。 - 前記表層めっき層は、前記リードフレームの母材よりもはんだ濡れ性が高い材質からなる、請求項1に記載の半導体装置の製造方法。
- 前記リードフレームの前記母材は、Cuである、請求項2に記載の半導体装置の製造方法。
- 前記表層めっき層は、Auからなる、請求項3に記載の半導体装置の製造方法。
- 前記表層めっき層を形成する工程においては、前記表層めっき層を前記リードフレームのうち前記封止樹脂から露出するすべての部分に形成する、請求項1ないし4のいずれかに記載の半導体装置の製造方法。
- 前記表層めっき層を形成する工程においては、前記表層めっき層の少なくとも一部を、前記リードフレームの母材に直接形成する、請求項1ないし5のいずれかに記載の半導体装置の製造方法。
- 前記表層めっき層を形成する工程の前に、中層めっき層を形成する工程を備える、請求項6に記載の半導体装置の製造方法。
- 前記表層めっき層を形成する工程においては、前記表層めっき層から前記中層めっき層を露出させる、請求項7に記載の半導体装置の製造方法。
- 前記中層めっき層を形成する工程においては、前記主面および前記裏面に前記中層めっき層を形成する、請求項7または8に記載の半導体装置の製造方法。
- 前記表層めっき層を形成する工程においては、前記表層めっき層のすべてを、前記リードフレームの前記母材に直接形成する、請求項6に記載の半導体装置の製造方法。
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US15/496,800 US10388616B2 (en) | 2016-05-02 | 2017-04-25 | Semiconductor device and method for manufacturing the same |
US16/509,159 US10658317B2 (en) | 2016-05-02 | 2019-07-11 | Semiconductor device and method for manufacturing the same |
US16/853,252 US11133276B2 (en) | 2016-05-02 | 2020-04-20 | Semiconductor device and method for manufacturing the same |
US17/459,604 US11728298B2 (en) | 2016-05-02 | 2021-08-27 | Semiconductor device and method for manufacturing the same |
US18/342,449 US20230343735A1 (en) | 2016-05-02 | 2023-06-27 | Semiconductor device and method for manufacturing the same |
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JP7144112B2 (ja) * | 2018-09-19 | 2022-09-29 | ローム株式会社 | 半導体装置 |
CN113424311B (zh) * | 2019-02-15 | 2024-08-30 | 罗姆股份有限公司 | 半导体器件和半导体器件的制造方法 |
DE112020003122T5 (de) * | 2019-06-28 | 2022-05-05 | Rohm Co., Ltd. | Elektronikbauteil und elektronikbauteil-montagestruktur |
JP1695980S (ja) * | 2021-03-09 | 2021-09-27 | ||
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Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3988518A (en) | 1975-08-15 | 1976-10-26 | Sprague Electric Company | Batch plating of a long lead frame strip |
JP2858197B2 (ja) * | 1993-04-16 | 1999-02-17 | 株式会社三井ハイテック | 半導体装置用リードフレーム |
US6201292B1 (en) | 1997-04-02 | 2001-03-13 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member used therefor |
US6756658B1 (en) * | 2001-04-06 | 2004-06-29 | Amkor Technology, Inc. | Making two lead surface mounting high power microleadframe semiconductor packages |
TW498443B (en) | 2001-06-21 | 2002-08-11 | Advanced Semiconductor Eng | Singulation method for manufacturing multiple lead-free semiconductor packages |
US6879034B1 (en) | 2003-05-01 | 2005-04-12 | Amkor Technology, Inc. | Semiconductor package including low temperature co-fired ceramic substrate |
JP2005191240A (ja) | 2003-12-25 | 2005-07-14 | Renesas Technology Corp | 半導体装置及びその製造方法 |
JP4658481B2 (ja) * | 2004-01-16 | 2011-03-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2005209770A (ja) * | 2004-01-21 | 2005-08-04 | Renesas Technology Corp | 半導体装置 |
US7125747B2 (en) | 2004-06-23 | 2006-10-24 | Advanced Semiconductor Engineering, Inc. | Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe |
JP2006049341A (ja) * | 2004-07-30 | 2006-02-16 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2006179760A (ja) | 2004-12-24 | 2006-07-06 | Yamaha Corp | 半導体パッケージ、および、これに使用するリードフレーム |
US7932587B2 (en) | 2007-09-07 | 2011-04-26 | Infineon Technologies Ag | Singulated semiconductor package |
JP5025394B2 (ja) | 2007-09-13 | 2012-09-12 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP4887346B2 (ja) * | 2008-11-20 | 2012-02-29 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置 |
JPWO2011121756A1 (ja) * | 2010-03-31 | 2013-07-04 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP5762081B2 (ja) | 2011-03-29 | 2015-08-12 | 新光電気工業株式会社 | リードフレーム及び半導体装置 |
JP2014072236A (ja) * | 2012-09-27 | 2014-04-21 | Renesas Electronics Corp | 半導体装置の製造方法 |
US9076891B2 (en) * | 2013-01-30 | 2015-07-07 | Texas Instruments Incorporation | Integrated circuit (“IC”) assembly includes an IC die with a top metallization layer and a conductive epoxy layer applied to the top metallization layer |
US9576932B2 (en) | 2013-03-09 | 2017-02-21 | Adventive Ipbank | Universal surface-mount semiconductor package |
JP6352009B2 (ja) * | 2013-04-16 | 2018-07-04 | ローム株式会社 | 半導体装置 |
US9012268B2 (en) | 2013-06-28 | 2015-04-21 | Stmicroelectronics, Inc. | Leadless packages and method of manufacturing same |
US9059185B2 (en) | 2013-07-11 | 2015-06-16 | Texas Instruments Incorporated | Copper leadframe finish for copper wire bonding |
US20150076675A1 (en) | 2013-09-16 | 2015-03-19 | Stmicroelectronics, Inc. | Leadframe package with wettable sides and method of manufacturing same |
JP6244147B2 (ja) | 2013-09-18 | 2017-12-06 | エスアイアイ・セミコンダクタ株式会社 | 半導体装置の製造方法 |
EP3128539B1 (en) | 2014-03-27 | 2020-01-08 | Renesas Electronics Corporation | Semiconductor device manufacturing method and semiconductor device |
JP6535509B2 (ja) * | 2014-05-12 | 2019-06-26 | ローム株式会社 | 半導体装置 |
US9590158B2 (en) | 2014-12-22 | 2017-03-07 | Nichia Corporation | Light emitting device |
-
2016
- 2016-06-27 JP JP2016126447A patent/JP6752639B2/ja active Active
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