JP6631209B2 - Mounting structure of semiconductor element on printed wiring board, semiconductor element, inductor setting method, and processor - Google Patents

Description

  The present invention relates to a mounting structure of a semiconductor element on a printed wiring board, a semiconductor element forming an inductor by the mounting structure, a method of setting the inductance of the inductor, and a processor including the inductor.

  An IPD (Integrated Passive Device) that integrally forms a thin-film inductor and the like on a semiconductor substrate by a thin-film process is useful as, for example, a composite passive component for a mobile terminal because it is small and thin.

  A semiconductor device in which an inductor pattern is formed in a redistribution layer of a semiconductor element is disclosed in, for example, Japanese Patent Application Laid-Open No. H11-163,837.

JP 2010-50136 A

  In general, a redistribution layer of a semiconductor element has a small thickness, and thus it is difficult to obtain a predetermined high inductance. Further, since the pattern formed on the rewiring layer is a pattern formed by a thin film process, it is difficult to form an inductor having a high Q value.

  Further, since the inductor is formed on the redistribution layer by a thin film process, the characteristics of the inductor cannot be changed after the inductor is formed. Therefore, for example, when it is necessary to configure a circuit having a plurality of inductors having different inductances, it is necessary to prepare in advance a plurality of types of semiconductor elements having inductors having a predetermined inductance. Therefore, the productivity is low, which is a factor of increasing the manufacturing cost.

  An object of the present invention is to solve the above-mentioned problems and provide an inductor having a predetermined high inductance or an inductor having a predetermined high Q value, and providing a mounting structure of a semiconductor element on a printed wiring board. is there. Another object of the present invention is to provide a semiconductor device, a method for setting the inductor, and a processor including the inductor.

  A further object of the present invention is to make it possible to change the characteristics of the inductor during or after the formation of the inductor.

(1) The mounting structure of the semiconductor element on the printed wiring board of the present invention is as follows.
A printed wiring board, comprising a semiconductor element mounted on the printed wiring board,
The semiconductor element has a plurality of first layer conductors formed on a first layer, a plurality of terminals formed on a mounting surface, and a plurality of interlayer conductors connecting the first layer conductor and the plurality of terminals. And
The printed wiring board includes a plurality of second layer conductors formed on a second layer, and a plurality of pads formed on a mounting surface and electrically connected to the plurality of second layer conductors,
A pad of the printed wiring board and a terminal of the semiconductor element are connected by a connecting material, and a meander is provided by the plurality of first-layer conductors, the plurality of second-layer conductors, the plurality of interlayer conductors, and the plurality of connecting materials. It is characterized by including a conductor pattern formed in a shape.

  According to the above configuration, the inductor is configured by a conductor pattern formed in a meandering shape. Since a part of the conductor pattern is the second layer conductor formed on the printed wiring board, the inductor or the inductor having a predetermined high inductance is provided. , An inductor having a predetermined high Q value is obtained. That is, since the conductor pattern formed on the printed wiring board has lower resistance than the conductor pattern formed on the semiconductor element, an inductor having a high Q value can be obtained. Further, since a meandering conductor pattern is formed including the conductor pattern formed on the printed wiring board, a predetermined high inductance can be obtained.

(2) The second-layer conductor or the pad may be configured to determine a connection position of the second-layer conductor to the interlayer conductor and determine a characteristic of the inductor by the conductor pattern. This makes it possible to obtain a predetermined inductance or Q value among a plurality of types of inductances or Q values determined by the connection position of the second layer conductor to the interlayer conductor. That is, when the inductor is formed, the characteristics of the inductor can be set.

(3) In the above (1) or (2), at least a part of the conductor pattern may be spiral in a plan view from a direction perpendicular to the first layer and the second layer. Thereby, the self-inductance works effectively, and an inductor having a predetermined inductance can be formed in a limited occupied area.

(4) In any one of the above items (1) to (3), the semiconductor element includes a semiconductor substrate and a redistribution layer formed on the semiconductor substrate, wherein the first layer conductor and the interlayer conductor are the same. A coil-shaped conductor pattern may be formed in the redistribution layer and including the interlayer conductor or conducting to the interlayer conductor inside the redistribution layer. Thereby, a predetermined large inductance can be obtained even if the number of terminals and pads for forming the meandering conductor pattern is small.

(5) The semiconductor device of the present invention comprises:
A plurality of first layer conductors formed on a first layer, a plurality of terminals formed on a mounting surface, and a plurality of interlayer conductors connecting the plurality of first layer conductors and the plurality of terminals; By connecting a predetermined terminal of the plurality of terminals with a connecting material, a pad, and a plurality of second layer conductors formed on a printed wiring board, the plurality of first layer conductors and the plurality of second layer conductors are connected. A conductor, an element constituting a meandering conductor pattern by the plurality of interlayer conductors and the plurality of connecting members,
The first layer conductor is provided below a redistribution layer formed on a surface of a semiconductor substrate, the interlayer conductor is formed inside the redistribution layer, and the terminal is formed on a surface of the redistribution layer. It is characterized by having.

  By mounting the semiconductor element on a printed wiring board on which a connecting material, pads and a plurality of second-layer conductors are formed, an inductor with a conductor pattern formed in a meander shape is formed, and a predetermined high inductance is obtained. Or an inductor having a predetermined high Q value.

(6) In the above (5), a terminal connected to a pad (independent from the conductor pattern ) formed on the printed wiring board and different from the conductor pattern may be formed on the surface of the rewiring layer. . Thus, it can be used as a semiconductor element having a semiconductor circuit including an inductor simply by mounting it on a printed wiring board.

(7) The inductor setting method of the present invention includes:
A semiconductor element having a plurality of first layer conductors formed on a first layer, a plurality of terminals formed on a mounting surface, and a plurality of interlayer conductors connecting the first layer conductor and the plurality of terminals;
Preparing a printed wiring board having a plurality of second layer conductors formed on a second layer and a plurality of pads formed on a mounting surface and electrically connected to the plurality of second layer conductors,
A pad of the printed wiring board and a terminal of the semiconductor element are connected by a connecting material, and a meander is provided by the plurality of first-layer conductors, the plurality of second-layer conductors, the plurality of interlayer conductors, and the plurality of connecting materials. And a shape of the conductor pattern is determined by a pattern of the second layer conductor or a position of the pad.

  With the above configuration, a predetermined inductance or Q value can be obtained from a plurality of types of inductances or Q values determined by the position of the pattern or pad of the second layer conductor on the interlayer conductor. That is, when the inductor is formed, the characteristics of the inductor can be set.

(8) In the above (7), the interval between the interlayer conductors through which a current flows among the plurality of interlayer conductors may be determined by the pattern of the second layer conductor or the position of the pad. This makes it possible to select a self-inductance or a mutual inductance generated at a position close to the interlayer conductors through which a current flows.

(9) In the above (7) or (8), a current path in which a current in the same direction flows to an adjacent interlayer conductor among the plurality of interlayer conductors depending on the pattern of the second layer conductor or the position of the pad. The configuration may be such that the polarity of the coupling between the adjacent interlayer conductors is determined depending on whether a current path in which a current flows in the opposite direction through the adjacent interlayer conductors. As a result, it is possible to adjust the self-inductance or the mutual inductance generated at a position close to the interlayer conductors through which current flows.

(10) In the above (7) to (9), the shape of the conductor pattern may be changed by trimming a part of the plurality of second layer conductors. This makes it possible to change the characteristics (inductance or Q value) of the inductor after forming the semiconductor element and the printed wiring board, and further after mounting the semiconductor element on the printed wiring board, for example.

(11) A processor of the present invention includes a processor integrated circuit including a switching circuit of a switching power supply circuit, and a printed wiring board on which the processor integrated circuit is mounted.
The processor integrated circuit includes a plurality of first-layer conductors formed on a first layer, a plurality of terminals formed on a mounting surface, and a plurality of layers connecting the plurality of first-layer conductors and the plurality of terminals. And a conductor,
The printed wiring board includes a plurality of second layer conductors formed on a second layer, and a plurality of pads formed on a mounting surface and electrically connected to the plurality of second layer conductors,
A pad of the printed wiring board and a terminal of the processor integrated circuit are connected by a connecting material, and the plurality of first-layer conductors, the plurality of second-layer conductors, the plurality of interlayer conductors, and the plurality of connecting materials are provided. And a meandering conductor pattern connected to the switching circuit.

  With the above configuration, by mounting the processor integrated circuit on the printed wiring board, a miniaturized processor including the switching power supply circuit and the inductor connected thereto is obtained.

  ADVANTAGE OF THE INVENTION According to this invention, the mounting structure of the semiconductor element to a printed wiring board in which the inductor which has predetermined high inductance or the inductor which has predetermined high Q value is obtained. Further, a semiconductor device applied to the mounting structure, a method for setting the inductor, and a processor including the inductor can be obtained.

  Further, the characteristics of the inductor can be changed during or after the formation of the inductor.

FIG. 1 is a cross-sectional view illustrating a mounting structure of a semiconductor element according to the first embodiment. FIG. 2 is a perspective view of the semiconductor element 10. 3A, 3B, and 3C are cross-sectional views each showing a mounting structure of a semiconductor device according to the second embodiment. FIG. 4A is a partial plan view of a conductor pattern formed on a rewiring layer of the semiconductor device according to the third embodiment, and FIG. 4B shows an example of a direction of a current flowing in each interlayer conductor. FIG. FIG. 5A is a partial plan view of a conductor pattern formed on a rewiring layer of another semiconductor device according to the third embodiment, and FIG. 5B is an example of a direction of a current flowing in each interlayer conductor. FIG. FIGS. 6A, 6B, and 6C are cross-sectional views each showing a mounting structure of a semiconductor device according to the fourth embodiment. 7A and 7B are cross-sectional views illustrating a mounting structure of a semiconductor device according to the fifth embodiment. FIG. 8 is a partial perspective view showing the internal structure of the redistribution layer of the semiconductor device according to the sixth embodiment. FIG. 9 is a plan view showing a mounting structure of a semiconductor element according to the seventh embodiment. FIGS. 10A and 10B are plan views of the semiconductor device according to the eighth embodiment as viewed from the terminal formation surface. FIG. 11 is a schematic configuration diagram of a processor 201 according to the ninth embodiment. FIG. 12 is a circuit diagram showing a connection relationship of the smoothing circuit to the DC / DC converter 19. FIG. 13 is a circuit diagram of a power supply circuit portion of another processor according to the ninth embodiment.

<< 1st Embodiment >>
FIG. 1 is a cross-sectional view illustrating a mounting structure of a semiconductor device according to the first embodiment.

  The semiconductor element mounting structure 101 includes a printed wiring board 2 and a semiconductor element 10 mounted on the printed wiring board 2. The semiconductor element 10 includes a semiconductor substrate 1 and a redistribution layer 3 formed on the semiconductor substrate 1.

  A plurality of first layer conductors 11 are formed in a layer inside the redistribution layer 3. A plurality of terminals 13 and 14 are formed on the surface of the redistribution layer 3 (the mounting surface of the semiconductor element 10). Further, a plurality of interlayer conductors 12 connecting the first layer conductor 11 and the plurality of terminals 13 are formed inside the rewiring layer. The layer inside the redistribution layer 3 on which the plurality of first layer conductors 11 are formed is an example of the “first layer La1” according to the present invention.

  The printed wiring board 2 has a plurality of second layer conductors 21 formed on the mounting surface, and a plurality of pads 23 formed on the mounting surface and electrically connected to the plurality of second layer conductors 21. The mounting surface on which the plurality of second layer conductors 21 are formed is an example of the “second layer La2” according to the present invention.

  The terminals 13 and 14 of the semiconductor element 10 are electrically connected to the pads 23 and 24 of the printed wiring board 2 via the solder 31, so that the semiconductor element 20 is surface-mounted on the printed wiring board. The solder 31 is an example of the “connecting material” according to the present invention.

  In a state where the semiconductor element 10 is mounted on the printed wiring board 2, a conductor formed in a meander shape by the plurality of first layer conductors 11, the plurality of second layer conductors 21, the plurality of interlayer conductors 12, and the plurality of solders 31. The pattern MP is formed. The conductor pattern MP formed in a meandering shape is an inductor.

  FIG. 2 is a perspective view of the semiconductor element 10. FIG. 2 shows the mounting surface up. However, the rewiring layer 3 is shown by seeing through the conductor and the electrode. In FIG. 2, the second-layer conductor 21 formed on the printed wiring board is also represented by a virtual line. The pads 23 and 24 and the solder 31 of the printed wiring board are not shown. FIG. 1 is a sectional view taken along a plane passing between two pads 24-24 in FIG.

  A plurality of first layer conductors 11 are formed on the surface of the semiconductor element 10. The first ends of the plurality of interlayer conductors 12 are electrically connected to the first layer conductors 11. As shown in FIG. 1, the second ends of the interlayer conductors 12 are electrically connected to the second layer conductors 21 via the pads 23 and 24 and the solder 31.

  In the example shown in FIG. 2, the pad 23a of the printed wiring board is the first end of the inductor formed by the conductor pattern MP, and the pad 23b is the second end of the inductor. The conductor pattern MP has a rectangular spiral shape when viewed from the Z-axis direction (in a plan view). The conductor pattern MP has a meandering shape when viewed from the X-axis direction and the Y-axis direction.

  An integrated circuit is formed on the semiconductor substrate 1 of the semiconductor element 10. Terminals 14 shown in FIG. 1 are input / output terminals connected to the integrated circuit.

  By mounting the semiconductor element 10 on the printed wiring board 2 in this manner, a meandering conductor pattern formed by the plurality of first-layer conductors 11, the plurality of second-layer conductors 21, the plurality of interlayer conductors 12, and the plurality of solders 31 is formed. MP constitutes an inductor. Further, an integrated circuit configured in the semiconductor element 10 is connected to the printed wiring board 2.

  If the size of a general semiconductor element is used, the inductor having the meandering conductor pattern is an inductor having an inductance of 1 nH or more and 50 nH or less. Therefore, it is particularly suitable for applications requiring inductors on the order of nH.

<< 2nd Embodiment >>
In the second embodiment, an example will be described in which inductors having different characteristics are formed by conductor patterns formed on a printed wiring board.

  3A, 3B, and 3C are cross-sectional views each showing a mounting structure of a semiconductor device according to the second embodiment.

  The basic configuration of the mounting structure 101A shown in FIG. 3A is the same as the mounting structure 101 shown in the first embodiment. In the example shown in FIGS. 3B and 3C, a second-layer conductor 21M and an interlayer conductor 22 connecting between the second-layer conductor 21M and the pad 23 are formed inside the printed wiring board 2. ing. In this example, the second-layer conductor 21 is also formed on the upper surface (mounting surface) of the printed wiring board 2. 3A, 3B, and 3C, the configuration of the semiconductor element 10 is the same.

  According to the present embodiment, since the second layer conductor 21M and the interlayer conductor 22 are formed in the inner layer of the printed wiring board 2, the current path of the meandering conductor pattern becomes longer. Therefore, an inductor having a larger inductance can be configured in a limited occupied area. Alternatively, the formation range of the inductor having the predetermined inductance can be reduced.

  Further, according to the present embodiment, the obtained inductance differs depending on the shape and presence or absence of the second-layer conductors 21 and 21M and the interlayer conductor 22 formed on the printed wiring board 2 while using the same semiconductor element 10. Therefore, by determining the shape and presence / absence of the second layer conductors 21 and 21M and the interlayer conductor 22 formed on the printed wiring board 2, an inductor having a predetermined inductance can be formed without changing the semiconductor element.

<< 3rd Embodiment >>
In the third embodiment, depending on the position of the pattern or pad of the second layer conductor of the printed wiring board, a current path in which current flows in the same direction to an adjacent interlayer conductor among a plurality of interlayer conductors of the semiconductor element, An example is shown in which the polarity of the coupling between adjacent interlayer conductors is determined depending on whether a current path in which a current flows in the opposite direction flows between adjacent interlayer conductors.

  FIG. 4A is a partial plan view of a conductor pattern formed on a rewiring layer of the semiconductor device according to the third embodiment, and FIG. 4B shows an example of a direction of a current flowing in each interlayer conductor. FIG. FIG. 5A is a partial plan view of a conductor pattern formed on a redistribution layer of another semiconductor device according to the third embodiment, and FIG. 5B is a diagram showing a direction of a current flowing in each interlayer conductor. It is a figure showing the example of.

  In the example shown in FIGS. 4A and 4B, a current path including the interlayer conductors 12a, 12b, 12c, and 12d and a current path including the interlayer conductors 12e, 12f, 12g, and 12h are arranged in parallel. As is clear from FIG. 4B, the current direction is the same for each pair of interlayer conductors 12a-12e, 12b-12f, 12c-12g, and 12d-12h adjacent to each other. Inductance occurs.

  On the other hand, in the example shown in FIGS. 5A and 5B, the current path including the interlayer conductors 12a, 12b, 12c, and 12d and the current path including the interlayer conductors 12m, 12n, 12o, and 12p are arranged in parallel. I have. As apparent from FIG. 5 (B), since the current direction is opposite in each of the interlayer conductors 12a-12m, 12b-12n, 12c-12o, and 12d-12p adjacent to each other, a negative self-inductance occurs. .

  Accordingly, the inductance generated in the path shown in FIGS. 4A and 4B is larger than the inductance generated in the path shown in FIGS. 5A and 5B. In this way, the path shown in FIGS. 4A and 4B or the path shown in FIGS. 5A and 5B is selected according to the pattern of the pad 23 and the second layer conductor 21 formed on the printed wiring board. By doing so, the inductance of the inductor may be determined appropriately.

  In the examples shown in FIGS. 4A and 4B and FIGS. 5A and 5B, a predetermined inductance is obtained by determining (selecting) the direction of the current flowing in the adjacent interlayer conductor. However, the predetermined inductance may be determined by determining (selecting) the interval between adjacent interlayer conductors.

  Also, in the examples shown in FIGS. 4A and 4B and FIGS. 5A and 5B, an example is shown in which the arrangement pitches of adjacent interlayer conductors are juxtaposed in the same phase. The pitch may be different, or the phase of the pitch may be different. The self-inductance may be determined by the phase of the pitch.

<< 4th Embodiment >>
In the fourth embodiment, an example of a mounting structure of a semiconductor element on a printed wiring board having a parallel connection part in a part of a meandering conductor pattern will be described. In the fourth embodiment, an example of a mounting structure in which a second-layer conductor is formed on the lower surface of a printed wiring board will be described. Further, in the fourth embodiment, an example in which the second-layer conductor is trimmed on the lower surface of the printed wiring board will be described.

  FIGS. 6A, 6B, and 6C are cross-sectional views each showing a mounting structure of a semiconductor device according to the fourth embodiment.

  Each of the mounting structures 104A, 104B, and 104C shown in FIGS. 6A, 6B, and 6C is the same as each of the above-described embodiments in that the printed wiring board 2 and the semiconductor element 10 are provided. In the fourth embodiment, the second-layer conductor 21B is formed on the lower surface of the printed wiring board 2 (the surface opposite to the surface on which the semiconductor element 10 is mounted). A second-layer conductor 21B and an interlayer conductor 22 connecting between the second-layer conductor 21B and the pad 23 are formed in an inner layer of the printed wiring board. 6A, 6B, and 6C, the configuration of the semiconductor element 10 is the same.

  In the mounting structure 104A shown in FIG. 6A, the parallel connection part of the second layer conductor 21 formed on the upper surface of the printed wiring board 2, the second layer conductor 21B formed on the lower surface, and the interlayer conductor 22 is partially formed. Have. According to this structure, the inductance of the parallel connection part is smaller than the other parts. Therefore, the inductance of the inductor can be determined by forming the parallel connection portion. In addition, the resistance value of the parallel connection part is small, and an inductor having a large Q value is configured accordingly.

  6B is an example in which the second-layer conductor 21 is not formed in advance from the state shown in FIG. 6A, or is removed before the semiconductor element 10 is mounted. . The mounting structure 104C shown in FIG. 6C is an example in which a part of the second layer conductor 21B is not formed in advance from the state shown in FIG. This is an example of removal after mounting.

  In the mounting structure 104B shown in FIG. 6B, the current path of the meandering conductor pattern is long. Therefore, an inductor having a large inductance can be formed in a limited occupied area. Alternatively, the formation range of the inductor having the predetermined inductance can be reduced.

  In the mounting structure 104C shown in FIG. 6C, the current path of the meandering conductor pattern is shorter than that of the mounting structure 104B, and thus the obtained inductor has a smaller inductance than that of the mounting structure 104B.

  Note that, in the present embodiment, since the electrode 25 that conducts to a predetermined position of the inductor is formed on the lower surface of the printed wiring board 2, a circuit using the inductor on the printed wiring board or a circuit connected to the inductor is formed. Can be provided.

<< 5th Embodiment >>
In the fifth embodiment, an example of a mounting structure of a semiconductor element on a printed wiring board including a current path bypass in a part of a meandering conductor pattern will be described. In the fifth embodiment, an example of a mounting structure in which a second-layer conductor is formed inside and on a lower surface of a printed wiring board will be described.

  7A and 7B are cross-sectional views illustrating a mounting structure of a semiconductor device according to the fifth embodiment.

  Each of the mounting structures 105A and 105B shown in FIGS. 7A and 7B is the same as each of the above-described embodiments in that it includes the printed wiring board 2 and the semiconductor element 10. In the mounting structures 105A and 105B, the second layer conductor 21M is formed on the inner layer of the printed wiring board 2, and the second layer conductor 21B is formed on the lower surface of the printed wiring board 2. Further, an interlayer conductor 22 that connects between the second-layer conductors 21M and 21B and the pad 23 is formed inside the printed wiring board. A second layer conductor 21 is formed on the upper surface of the printed wiring board 2 of the mounting structure 105A. 7A and 7B, the configuration of the semiconductor element 10 is the same.

  In the mounting structure 105A shown in FIG. 7A, a current path including the second layer conductor 21B and a current path including the second layer conductor 21M exist. The current path including the second layer conductor 21M is a bypass path. In the mounting structure 105B shown in FIG. 7B, since the second layer conductor 21 is not provided, there is no bypass path.

  According to the present embodiment, the inductance of the inductor can be switched depending on whether or not the bypass path is formed.

<< Sixth Embodiment >>
The sixth embodiment shows an example in which a coil-shaped conductor pattern is formed inside a redistribution layer of a semiconductor element.

  FIG. 8 is a partial perspective view showing the internal structure of the redistribution layer of the semiconductor device according to the sixth embodiment. However, only the conductor portion is shown except for the insulator portion of the rewiring layer. A first layer conductor 11 is formed below the redistribution layer of the semiconductor element. A second-layer conductor 21 is formed above the rewiring layer. A coil-shaped conductor pattern 15 is formed in an intermediate layer of the rewiring layer. Then, inside the rewiring layer, an interlayer conductor 12A connected between the first-layer conductor 11 and the coil-shaped conductor pattern 15 and a connection between the second-layer conductor 21 and the coil-shaped conductor pattern 15 are formed. An interlayer conductor 12B is formed.

  According to the present embodiment, since the coil-shaped conductor formed of the interlayer conductor is formed between the first-layer conductor 11 and the second-layer conductor 21, the number of terminals and pads for forming the meander-shaped conductor pattern is increased. , A predetermined large inductance can be obtained.

  In the same manner, a coil-shaped conductor pattern composed of two or more conductor patterns may be formed in the rewiring layer of the semiconductor element.

<< Seventh Embodiment >>
In the seventh embodiment, an example in which a part of the second layer conductor formed on the printed wiring board is trimmed will be described.

  FIG. 9 is a plan view showing a mounting structure of a semiconductor element according to the seventh embodiment. The semiconductor element 10 is mounted on the printed wiring board 2. A plurality of second layer conductors 21 are formed in a mounting region of the semiconductor element 10 on the printed wiring board 2. Further, a second-layer conductor 21p for trimming, which extends from the second-layer conductor 21, is formed outside the mounting region of the semiconductor element 10.

  The arrangement of the second layer conductor 21 is basically the same as that shown in FIG. 2 in the first embodiment. The second layer conductor 21p for trimming is a path that bypasses a part of the current path. Therefore, the inductance of the inductor can be determined by the presence or absence of trimming of the second-layer conductor 21p for trimming or the number of trimmed portions.

<< Eighth Embodiment >>
In the eighth embodiment, an example in which the invention is applied to a semiconductor device having a large number of grid array type terminals will be described.

  FIGS. 10A and 10B are plan views of the semiconductor device according to the eighth embodiment as viewed from the terminal formation surface. Each of the semiconductor element 10A shown in FIG. 10A and the semiconductor element 10B shown in FIG. 10B has a large number of terminals 14 which are electrically connected to an integrated circuit formed inside the semiconductor element. These terminals 14 are arranged in a grid array.

  In the example shown in FIG. 10A, a terminal 13 for forming an inductor is disposed in a predetermined region between adjacent terminals 14. Therefore, the inductor forming terminals 13 can be provided without enlarging the arrangement region of the terminals 14 electrically connected to the integrated circuit.

  In the example shown in FIG. 10B, the terminals 13 for forming inductors are arranged in the arrangement region LZ of the terminals 13 for forming inductors. In this example, since the pitch of the terminals 13 is smaller than the pitch of the terminals 14, the inductor is formed in a relatively narrow region. Further, the terminal 13 does not affect the region where the terminals 14 are arranged.

  In any of the semiconductor elements 10A and 10B, the terminals 13 and 14 may be connected to the printed wiring board via solder balls, but may be electrically connected to the printed wiring board via, for example, PGA (Pin Grid Array) pins. May be connected. In that case, the PGA pin functions as the “connecting material” according to the present invention.

<< 9th Embodiment >>
In the ninth embodiment, an example of a processor according to the present invention will be described.

FIG. 11 is a schematic configuration diagram of a processor 201 according to the ninth embodiment. The processor 201 is configured with the semiconductor element 10 mounted on the printed wiring board 2. An integrated circuit as a processor and a DC / DC converter 19 are formed on the semiconductor substrate 1 of the semiconductor element 10. The integrated circuit as a processor includes, for example, a terminal for an I ² C interface, a clock terminal, a terminal for high-frequency communication, and the like. DC / DC converter 19 includes a switching element and its switching control circuit.

  A smoothing capacitor C is mounted on the printed wiring board 2. In a state where the semiconductor element 10 is mounted on the printed wiring board 2, the inductor L is configured. The inductor L is an inductor having a meandering conductor pattern as described in each embodiment.

  FIG. 12 is a circuit diagram showing a connection relationship of the smoothing circuit to the DC / DC converter 19. The inductor L and the capacitor C form a smoothing circuit.

  FIG. 13 is a circuit diagram of a power supply circuit portion of another processor of the present embodiment. In this example, a plurality of inductors L1 to L5 and a capacitor C form a smoothing circuit. A circuit for a plurality of channels is configured in the DC / DC converter 19, and inductors L1 to L5 are respectively connected.

  When a plurality of inductors are provided in this manner, the meandering conductor pattern shown in each of the above-described embodiments may be provided for the required inductors. Further, the respective inductors may be magnetically coupled to generate a mutual inductance. Then, as already described in each embodiment, the mutual inductance may be determined according to the setting of the current path by the conductor pattern formed on the printed wiring board.

  In the present embodiment, the inductor having the meandering conductor pattern is applied to the switching power supply circuit. However, the inductor according to the present invention is applied to various signal processing circuits such as a filter and a phase shifter in addition to the power supply circuit. You can also.

  Finally, the description of the above embodiments is illustrative in all respects and is not restrictive. Modifications and changes can be made by those skilled in the art as appropriate. The scope of the present invention is defined by the terms of the claims, rather than the embodiments described above. Further, the scope of the present invention includes modifications from the embodiments within the scope equivalent to the scope of the claims.

C ... Capacitors L, L1 to L5 ... Inductor La1 ... First layer La2 ... Second layer LZ ... Placement area MP for terminals for forming inductors ... Conductor pattern 1 ... Semiconductor substrate 2 ... Printed wiring board 3 ... Rewiring layer 10, 10A, 10B: semiconductor element 11: first layer conductors 12a, 12b, 12c, 12d: interlayer conductors 12e, 12f, 12g, 12h: interlayer conductors 12m, 12n, 12o, 12p: interlayer conductors 12, 12A, 12B: interlayer conductor 13, 14 ... Terminal 15 ... Coiled conductor pattern 19 ... DC / DC converter 20 ... Semiconductor elements 21, 21p ... Second layer conductors 21M, 21B ... Second layer conductor 22 ... Interlayer conductors 23, 23a, 23b, 24 ... Pad 25 ... electrodes 101, 101A ... mounting structures 104A, 104B, 104C ... mounting structures 105A, 105B ... mounting structures 201 ... processor

Claims (11)

A printed wiring board, comprising a semiconductor element mounted on the printed wiring board, in the mounting structure of the semiconductor element on the printed wiring board,
The semiconductor element has a plurality of first layer conductors formed on a first layer, a plurality of terminals formed on a mounting surface, and a plurality of interlayer conductors connecting the first layer conductor and the plurality of terminals. And
The printed wiring board includes a plurality of second layer conductors formed on a second layer, and a plurality of pads formed on a mounting surface and electrically connected to the plurality of second layer conductors,
A pad of the printed wiring board and a terminal of the semiconductor element are connected by a connecting material, and a meander is provided by the plurality of first-layer conductors, the plurality of second-layer conductors, the plurality of interlayer conductors, and the plurality of connecting materials. A mounting structure of a semiconductor element on a printed wiring board, comprising a conductor pattern formed in a shape.   2. The semiconductor element mounting structure according to claim 1, wherein the second-layer conductor or the pad determines a connection position of the second-layer conductor to the interlayer conductor, and determines characteristics of the inductor by the conductor pattern. 3.   The mounting structure of the semiconductor element according to claim 1, wherein at least a part of the conductor pattern has a spiral shape in a plan view from a direction perpendicular to the first layer and the second layer. The semiconductor element includes a semiconductor substrate, and a redistribution layer formed on the semiconductor substrate,
The first layer conductor and the interlayer conductor are formed in the rewiring layer,
4. The semiconductor element mounting structure according to claim 1, wherein a coil-shaped conductor pattern including the interlayer conductor or conducting to the interlayer conductor is formed inside the rewiring layer. 5. A plurality of first layer conductors formed on a first layer, a plurality of terminals formed on a mounting surface, and a plurality of interlayer conductors connecting the plurality of first layer conductors and the plurality of terminals; By connecting a predetermined terminal of the plurality of terminals with a connecting material, a pad, and a plurality of second layer conductors formed on a printed wiring board, the plurality of first layer conductors and the plurality of second layer conductors are connected. A conductor, an element constituting a meandering conductor pattern by the plurality of interlayer conductors and the plurality of connecting members,
The first layer conductor is provided below a redistribution layer formed on a surface of a semiconductor substrate, the interlayer conductor is formed inside the redistribution layer, and the terminal is formed on a surface of the redistribution layer. A semiconductor device, characterized in that: 6. The semiconductor device according to claim 5, wherein a terminal formed on the printed wiring board and connected to a pad different from the conductor pattern is formed on a surface of the rewiring layer. A semiconductor element having a plurality of first layer conductors formed on a first layer, a plurality of terminals formed on a mounting surface, and a plurality of interlayer conductors connecting the first layer conductor and the plurality of terminals;
Preparing a printed wiring board having a plurality of second layer conductors formed on a second layer and a plurality of pads formed on a mounting surface and electrically connected to the plurality of second layer conductors,
A pad of the printed wiring board and a terminal of the semiconductor element are connected by a connecting material, and a meander is provided by the plurality of first-layer conductors, the plurality of second-layer conductors, the plurality of interlayer conductors, and the plurality of connecting materials. A method of setting an inductor, comprising: forming a conductor pattern in a shape of a circle; and determining a shape of the conductor pattern by a position of the pattern of the second layer conductor or the position of the pad.   8. The inductor setting method according to claim 7, wherein an interval between current-carrying interlayer conductors among the plurality of interlayer conductors is determined by a pattern of the second-layer conductor or a position of the pad. 9.   Depending on the pattern of the second layer conductor or the position of the pad, a current path in which current flows in the same direction between adjacent interlayer conductors among the plurality of interlayer conductors, or a current flows in the opposite direction through adjacent interlayer conductors 9. The inductor setting method according to claim 7, wherein the polarity of the coupling between the adjacent interlayer conductors is determined depending on whether the current path is used.   10. The inductor setting method according to claim 7, wherein a shape of the conductor pattern is changed by trimming a part of the plurality of second layer conductors. A processor including a processor integrated circuit including a switching circuit of a switching power supply circuit, and a printed wiring board on which the processor integrated circuit is mounted,
The processor integrated circuit includes a plurality of first-layer conductors formed on a first layer, a plurality of terminals formed on a mounting surface, and a plurality of layers connecting the plurality of first-layer conductors and the plurality of terminals. And a conductor,
The printed wiring board includes a plurality of second layer conductors formed on a second layer, and a plurality of pads formed on a mounting surface and electrically connected to the plurality of second layer conductors,
A pad of the printed wiring board and a terminal of the processor integrated circuit are connected by a connecting material, and the plurality of first-layer conductors, the plurality of second-layer conductors, the plurality of interlayer conductors, and the plurality of connecting materials are provided. A meandering conductor pattern connected to the switching circuit.

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