JP6545954B2 - Semiconductor device - Google Patents

Description

  The present invention relates to an object, a method, or a method of manufacturing. Alternatively, the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. The transistor and the semiconductor circuit are one embodiment of a semiconductor device. In addition, an arithmetic device, a memory device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like), and an electronic device may include a semiconductor device.

  A technique for forming a transistor using a semiconductor material has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Although silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have attracted attention as other materials.

  For example, a technique for manufacturing a transistor using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).

  Further, in recent years, with the advancement of performance, miniaturization, and weight reduction of electronic devices, there is an increasing demand for integrated circuits in which semiconductor elements such as miniaturized transistors are integrated at high density.

Unexamined-Japanese-Patent No. 2007-123861 JP 2007-96055 A

  An object of one embodiment of the present invention is to provide a semiconductor device suitable for miniaturization. Another object is to provide a semiconductor device with a reduced circuit area.

  Another object is to provide a highly reliable semiconductor device. Another object is to provide semiconductor devices with favorable electrical characteristics. Another object is to provide a semiconductor device having a memory element with favorable retention characteristics. Another object is to provide a semiconductor device having a novel structure.

  Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, it is not necessary to solve all of these problems. In addition, problems other than these are naturally apparent from the description of the specification, drawings, claims and the like, and it is possible to extract the problems other than these from the description of the specification, drawings, claims and the like. It is.

  One embodiment of the present invention includes a capacitor and a first transistor, the first transistor includes a first semiconductor layer, and the first semiconductor layer is located above the capacitor, the capacitor The element is a semiconductor device having a first electrode electrically connected to the first transistor. In the above structure, the capacitor includes the m-layer (m is a natural number of 3 or more) conductive layer and the n-layer (n is a natural number) insulating film, and the first insulating film includes the first conductive layer and the first conductive layer. The second conductive film is preferably sandwiched between the second conductive layer and the third conductive layer, and the first conductive layer is preferably electrically connected to the third conductive layer.

  Alternatively, one embodiment of the present invention includes a capacitor, a first transistor, and a second transistor, the first transistor includes a first semiconductor layer, and the capacitor includes n layers (n Has a natural number insulating film and a k layer (k is a natural number of 2 or more) conductive layers, and each of the n insulating films is sandwiched by at least two conductive layers, and the first transistor Is located above the second transistor, the first semiconductor layer is located above the capacitive element, and the n-layer (n is a natural number) insulating film included in the capacitive element is the first transistor and the second transistor. And a capacitive element is a semiconductor device having a first electrode connected to either the source or the drain of the first transistor.

  In the above configuration, the insulating film of the n layer preferably has a function of blocking at least one of hydrogen, water, and oxygen. In the above structure, the insulating film of the n layer is at least one of silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, and hafnium oxide nitride. It is preferable to include one.

  In the above structure, the capacitor and the first transistor preferably overlap with each other.

  In the above structure, it is preferable that in the first transistor, the first opening be provided in the first semiconductor layer and the first electrode be in contact with the first opening.

  In the above structure, the first transistor has a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer are in contact with the first semiconductor layer, and the first transistor It is preferable that an opening be provided in the first semiconductor layer and the first conductive layer which the semiconductor device has, and the first electrode be in contact with the opening provided in the first semiconductor layer and the first conductive layer.

  According to one embodiment of the present invention, a semiconductor device suitable for miniaturization can be provided. In addition, a semiconductor device with a reduced circuit area can be provided.

  In addition, a highly reliable semiconductor device can be provided. Further, favorable electrical characteristics can be given to the semiconductor device. Further, a semiconductor device having a memory element with favorable holding characteristics can be provided. In addition, a semiconductor device with a novel configuration can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these are naturally apparent from the description of the specification, drawings, claims and the like, and other effects can be extracted from the descriptions of the specification, drawings, claims and the like. It is.

FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. 7A and 7B are a circuit diagram and a top view of a transistor, according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7D illustrate a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. 5A and 5B illustrate a band structure of part of a transistor according to one embodiment of the present invention, and a diagram illustrating a current path when conducting. Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. 5A and 5B show a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus. A figure showing an example of structural analysis by transmission electron diffraction measurement, and a plane TEM image. The circuit diagram which concerns on embodiment. The structural example of RF tag concerning an embodiment. 11 shows a configuration example of a CPU according to an embodiment. FIG. 16 is a circuit diagram of a memory element of one embodiment. 5A and 5B are a top view and a circuit diagram of a display device of an embodiment. Electronic device according to an embodiment. The example of use of RF tag concerning an embodiment. FIG. 16 is a circuit diagram illustrating an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 shows a semiconductor device. FIG. 18 is a top view illustrating an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. FIG. 7 illustrates an example of a semiconductor device according to one embodiment of the present invention. Cs-corrected high-resolution TEM image of a cross section of a CAAC-OS, and a cross-sectional schematic view of the CAAC-OS. Cs corrected high resolution TEM image in the plane of CAAC-OS. FIG. 16 illustrates structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD. The figure which shows the electron diffraction pattern of CAAC-OS. FIG. 18 shows change in crystal parts of an In-Ga-Zn oxide due to electron irradiation. The schematic diagram explaining the film-forming model of CAAC-OS and nc-OS. FIG. 16 illustrates crystals of InGaZnO ₄ and pellets. The schematic diagram explaining the film-forming model of CAAC-OS.

  Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated. In addition, when referring to the same function, the hatch pattern may be the same and no reference numeral may be given.

  Note that in the drawings described herein, the size of each component, the thickness of a layer, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.

  Note that ordinal numbers such as “first”, “second” and the like in the present specification and the like are attached to avoid confusion of constituent elements, and are not limited numerically.

  Even when the term "semiconductor" is used, for example, in the case where the conductivity is sufficiently low, it may have characteristics as an "insulator". In addition, “semiconductor” and “insulator” may have vague boundaries and may not be distinguishable from each other. Thus, the "semiconductor" described herein may be rephrased as an "insulator". Similarly, the "insulator" described herein may be paraphrased as a "semiconductor".

  Moreover, even when it describes as a "semiconductor", when electroconductivity is high enough, for example, it may have the characteristic as a "conductor." In addition, the boundaries between the "semiconductor" and the "conductor" may be vague and indistinguishable in some cases. Therefore, the "semiconductor" described in this specification may be rephrased as "conductor". Similarly, "conductor" described herein may be rephrased as "semiconductor".

  A transistor is a type of semiconductor element and can realize amplification of current or voltage, switching operation to control conduction or non-conduction, and the like. The transistor in the present specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

  In the present specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Moreover, "generally parallel" means the state by which two straight lines are arrange | positioned by the angle of -30 degrees or more and 30 degrees or less. Also, "vertical" means that two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Moreover, "generally perpendicular" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

  In the present specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

Embodiment 1
[Configuration example of laminated structure]
Hereinafter, an example of a stack structure which can be applied to the semiconductor device of one embodiment of the present invention will be described with reference to FIG.

  The stacked structure illustrated in FIG. 1A includes a transistor 100 and a capacitor 150. The transistor 100 is located above the capacitive element 150. In addition, the capacitor 150 is electrically connected to the transistor 100.

The semiconductor layer 101 of the transistor 100 may have a low resistance region 171 a and a low resistance region 171 b. The low resistance region 171a and the low resistance region 171b preferably function as a source region or a drain region. The low resistance region 171a and the low resistance region 171b may be doped with an impurity. By adding an impurity, the resistance of the semiconductor layer 101 can be reduced. As impurities to be added, for example, argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium, zirconium, niobium It is preferable to add one or more selected from molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum and tungsten. The low-resistance region 171 a and the low-resistance region 171 b may be, for example, 5 × 10 ¹⁹ atoms / cm ³ or more, preferably 1 × 10 ²⁰ atoms / cm ³ or more, more preferably 2 × in the semiconductor layer 101. It is a region containing 10 ²⁰ atoms / cm ³ or more, more preferably 5 × 10 ²⁰ atoms / cm ³ or more.

  The stacked structure illustrated in FIG. 1A may include the transistor 130. In addition, a barrier film 111 is preferably provided between the transistor 100 and the transistor 130. The capacitor 150 includes a conductive layer 151 and a conductive layer 152, and has a structure in which the barrier film 111 is sandwiched between the conductive layer 151 and the conductive layer 152.

  Here, FIG. 1B illustrates a cross section along dashed-dotted line A-B illustrated in FIG. Here, the cross section along the alternate long and short dash line A-B is, for example, a cross section approximately perpendicular to the cross section shown in FIG. 1A, passing the alternate long and short dash line AB. Note that although there are places where reference numerals are omitted in FIG. 1B, for example, the same hatches as those in FIG. 1A may be referred to, for example, FIG. 1A.

  The transistor 130 is configured to include the first semiconductor material. In addition, the transistor 100 includes the second semiconductor material. The first semiconductor material and the second semiconductor material may be the same material, but are preferably different semiconductor materials.

  Examples of the semiconductor that can be used as the first semiconductor material or the second semiconductor material include semiconductor materials such as silicon, germanium, gallium and arsenic, and compound semiconductor materials having silicon, germanium, gallium, arsenic, aluminum, and the like. Organic semiconductor materials or oxide semiconductor materials can be mentioned.

  Here, a case where single crystal silicon is used as the first semiconductor material and an oxide semiconductor is used as the second semiconductor material will be described.

  The transistor 100 includes a semiconductor layer 101 formed of a second semiconductor material, a gate insulating film 102, a gate electrode 103, a plug 121, and a plug 122. The insulating film 112 and the insulating film 113 are formed to cover the transistor 100. The plug 121 is in contact with an opening portion provided in the insulating film 113, the insulating film 112, and the semiconductor layer 101, and is connected to the capacitor 150. That is, the plug 121 is formed to penetrate the insulating film 113, the insulating film 112, and the semiconductor layer 101.

  The barrier film 111 is a layer having a function of suppressing the diffusion of water and hydrogen from the lower layer to the upper layer. The barrier film 111 preferably has low oxygen permeability. In addition, the barrier film 111 may have an opening or a plug for electrically connecting an electrode or a wiring provided thereabove and an electrode or a wiring provided below it. For example, as illustrated in FIG. 1, the plug 121 electrically connects the plug 121 and the conductive layer 151. Here, suppressing the diffusion of water and hydrogen indicates that water and hydrogen are less likely to diffuse or have low permeability, as compared with, for example, silicon oxide generally used as an insulating film. In addition, low oxygen permeability means that oxygen permeability is low compared to silicon oxide or the like generally used as an insulating film.

  Similar to the barrier film 111, the insulating film 112 is preferably made of a material to which water or hydrogen does not easily diffuse. In particular, a material which hardly transmits oxygen is preferably used as the insulating film 112. Note that the insulating film 112 may have a stacked structure of two or more layers. In that case, for example, the insulating film 112 has a stacked structure of two layers, and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used in the lower layer. Just do it. In the upper layer, it is preferable to use a material to which water or hydrogen does not easily diffuse as in the barrier film 111. The insulating film provided in the lower layer may be configured to supply oxygen also from the upper side of the semiconductor layer 101 through the gate insulating film 102 as an insulating film from which oxygen is released by heating, as in the case of the insulating film 114.

  By covering the semiconductor layer 101 with the insulating film 112 containing a material which does not easily transmit oxygen, release of oxygen from the semiconductor layer 101 above the insulating film 112 can be suppressed. Further, oxygen released from the insulating film 114 can be confined below the insulating film 112, whereby the amount of oxygen which can be supplied to the semiconductor layer 101 can be increased.

  In addition, the insulating film 112 which hardly transmits water and hydrogen can suppress entry of water and hydrogen which are impurities for the oxide semiconductor from the outside, which can suppress variation in electric characteristics of the transistor 100 and has high reliability. A transistor can be realized.

  Note that an insulating film similar to the insulating film 114 from which oxygen is released by heating is provided below the insulating film 112, and oxygen is also supplied from the upper side of the semiconductor layer 101 through the gate insulating film 102. It is also good.

  The capacitor 150 is preferably formed to overlap with the transistor 100. By increasing the overlapping region of the capacitor 150 and the transistor 100, the area of the semiconductor device can be reduced.

  The semiconductor device illustrated in FIG. 1 includes the insulating film 114 between the transistor 100 and the capacitor 150. The insulating film 114 preferably contains an oxide. In particular, it is preferable to include an oxide material from which part of oxygen is released by heating. Preferably, it is preferable to use an oxide containing more oxygen than the stoichiometric composition. In the case where an oxide semiconductor is used as the second semiconductor material, oxygen released from the insulating film 114 is supplied to the oxide semiconductor, and oxygen vacancies in the oxide semiconductor can be reduced. As a result, fluctuations in the electrical characteristics of the second transistor can be suppressed and the reliability can be improved.

  Here, in the lower layer than the barrier film 111, it is preferable to reduce hydrogen, water and the like as much as possible. Alternatively, it is preferable to suppress the desorbed gas. Hydrogen or water can be a factor that causes variation in electrical characteristics of an oxide semiconductor. Further, although hydrogen and water diffused from the lower layer to the upper layer through the barrier film 111 can be suppressed by the barrier film 111, hydrogen and water diffuse into the upper layer through an opening or a plug provided in the barrier film 111. There is a possibility that

  In order to reduce hydrogen and water contained in each layer located below the barrier film 111 or to suppress desorption gas, before forming the barrier film 111 or forming a conductive layer or the like on the barrier film 111 Immediately after the opening is formed, heat treatment is preferably performed to remove hydrogen and water contained in the lower layer than the barrier film 111 or to suppress desorption gas. The heat treatment temperature is preferably as high as possible, as long as the heat resistance of a conductive film or the like included in the semiconductor device and the electrical characteristics of the transistor are not deteriorated. Specifically, the temperature may be, for example, 450 ° C. or more, preferably 490 ° C. or more, more preferably 530 ° C. or more, but it may be 650 ° C. or more. Heat treatment is preferably performed for 1 hour or more, preferably 5 hours or more, more preferably 10 hours or more under an inert gas atmosphere or a reduced pressure atmosphere. It may be determined in consideration of the heat resistance of the material of the wiring or the electrode located below the barrier film 111. For example, when the heat resistance of the material is low, the temperature is 550 ° C. or less, 600 ° C. or less, or 650 The temperature may be lower than or equal to 0 ° C., or lower than or equal to 800 ° C. Such heat treatment may be performed at least once or more, but is more preferably performed plural times.

  The insulating film provided below the barrier film 111 has a desorption amount of hydrogen molecules at a substrate surface temperature of 400 ° C. of 300 ° C., which is measured by thermal desorption spectroscopy analysis (also referred to as TDS analysis). It is preferable that it is 130% or less, preferably 110% or less of the amount of desorption of hydrogen molecules. Alternatively, it is preferable that the desorption amount of hydrogen molecules at a substrate surface temperature of 450 ° C. is 130% or less, preferably 110% or less of the desorption amount at 350 ° C. according to TDS analysis.

Further, it is preferable that water and hydrogen contained in the barrier film 111 itself are also reduced. Alternatively, it is preferable that the desorbed gas be suppressed. For example, as the barrier film 111, the desorption amount of hydrogen molecules (M / z = 2) in a substrate surface temperature range of 20 ° C. to 600 ° C. by TDS analysis is less than 2 × 10 ¹⁵ / cm ² , preferably 1 × It is preferable to use a material which is less than 10 ¹⁵ pieces / cm ² , more preferably less than 5 × 10 ¹⁴ pieces / cm ² for the barrier film 111. Alternatively, the desorption amount of water molecules (M / z = 18) in the substrate surface temperature range of 20 ° C. to 600 ° C. is less than 1 × 10 ¹⁶ / cm ² , preferably 5 × 10 ¹⁵ / cm ² according to TDS analysis. It is preferable to use a material which is less than cm ² , more preferably less than 2 × 10 ¹² pieces / cm ² for the barrier film 111.

  In the case where single crystal silicon is used for the semiconductor layer of the transistor 130, the heat treatment is a treatment (also referred to as hydrogenation treatment) of terminating unpaired silicon bonds (also referred to as dangling bonds) with hydrogen. It can double as well. Part of hydrogen contained in the gate insulating film of the transistor 130 and the other insulating film formed under the barrier film 111 is removed by hydrogenation treatment, and is diffused into the semiconductor layer of the first transistor to be contained in silicon. By terminating the dangling bond, the reliability of the first transistor can be improved.

As materials that can be used for the barrier film 111, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr) TiO ₃ (BST) can be used. Etc.) can be used in a single layer or a stack. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, tungsten oxide, yttrium oxide, zirconium oxide, or gallium oxide may be added to these insulating films. Alternatively, these insulating films may be nitrided to form an oxynitride film. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulating film. In particular, aluminum oxide is preferable because of its excellent barrier property to water and hydrogen.

  The barrier film 111 may be formed by stacking a layer containing another insulating material in addition to a layer of a material which is not easily permeable to water or hydrogen. For example, a layer containing silicon oxide or silicon oxynitride, a layer containing a metal oxide, or the like may be stacked.

  In addition, it is preferable that the barrier film 111 be made of a material which hardly transmits oxygen. The above-mentioned materials are materials excellent in barrier properties against hydrogen and water as well as oxygen. By using such a material, oxygen released when the insulating film 114 is heated can be prevented from diffusing to a lower layer than the barrier film 111. As a result, the amount of oxygen which is released from the insulating film 114 and can be supplied to the semiconductor layer of the transistor 100 can be increased.

As described above, the concentration of hydrogen or water contained in each layer positioned lower than the barrier film 111 is reduced, or hydrogen or water is removed, or desorption gas is suppressed, and the hydrogen or water is further reduced by the barrier film 111. Can be prevented from diffusing into the transistor 100. Therefore, the contents of hydrogen and water in the insulating film 114 and the layers included in the transistor 100 can be extremely low. For example, the hydrogen concentration in the insulating film 114, the semiconductor layer 101 of the transistor 100, or the gate insulating film 102 is less than 5 × 10 ¹⁸ cm ⁻³ , preferably less than 1 × 10 ¹⁸ cm ⁻³ , more preferably 3 × 10 It can be reduced to less than ¹⁷ cm- ³ .

  With the above-described structure, high reliability can be compatible in any of the first transistor and the second transistor, and a highly reliable semiconductor device can be realized.

  Note that the conductive layer 152 may be arranged to overlap with the channel region of the transistor 100. An example in that case is shown in FIGS. 34 (A) and 34 (B). FIG. 34B is a cross section along dashed-dotted line A-B in FIG. 34A. Note that the conductive layer 152 can also function as a gate electrode of the transistor 100. For example, the threshold voltage of the transistor 100 can be controlled by supplying a constant potential to the gate electrode.

  Further, an example of a stack structure which can be applied to the semiconductor device of one embodiment of the present invention is shown in FIGS. 2, 3, 4A, and 4B. As shown in FIG. 2, the capacitor 150 may be formed by stacking three or more conductive layers. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are electrically connected to each other through the plug 121, the plug 126, and the plug 127, and one electrode of the capacitor 150 is formed. Although not shown, the conductive layer 152, the conductive layer 154a, and the conductive layer 154c are electrically connected to form the other electrode of the capacitor 150.

  Further, as shown in FIG. 3, conductive layers may be formed on both sides of the plug 126 and the plug 127. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are electrically connected to each other through the plug 121, the plug 126, and the plug 127, and one electrode of the capacitor 150 is formed. Although not illustrated, the conductive layer 152, the conductive layer 152b, the conductive layer 154a, the conductive layer 154b, the conductive layer 154c, and the conductive layer 154d are electrically connected to form the other electrode of the capacitor 150.

  Further, as illustrated in FIG. 4A, the transistor 100 may include a conductive layer 104 a and a conductive layer 104 b in contact with the semiconductor layer 101. 4B is a cross section taken along dashed-dotted line A-B in FIG. 4A. The conductive layer 104a and the conductive layer 104b function as a source electrode or a drain electrode. The transistor 100 may also have a conductive layer 105. The conductive layer 105 may function as a second gate of the transistor 100. A voltage lower or higher than that of the source electrode may be applied to the conductive layer 105, and the threshold voltage of the transistor may be changed in the positive direction or the negative direction. For example, by varying the threshold voltage of the transistor in the positive direction, there may be a case where normally-off can be realized in which the transistor is turned off (off) even when the gate voltage is 0 V. Note that the voltage applied to the conductive layer 105 may be variable or fixed. In the case where the voltage applied to the conductive layer 105 is variable, a circuit for controlling the voltage may be connected to the conductive layer 105.

  In addition, the conductive layer 105 may be connected to the gate electrode 103.

[Example of configuration]
FIG. 5A is an example of a circuit diagram of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG. 5A includes the transistor 100, the transistor 130, the capacitor 150, the wiring BL, the wiring WL, and the wiring CL.

  In the transistor 130, one of the source and the drain is electrically connected to the wiring BL, the other is electrically connected to the wiring SL, and a gate is electrically connected to one of the source or the drain of the transistor 100 and one electrode of the capacitor 150. Connect. In the transistor 100, the other of the source and the drain is electrically connected to the wiring BL, and the gate is electrically connected to the wiring WL. The other electrode of the capacitor 150 is electrically connected to the wiring CL. The wiring BG is electrically connected to the second gate of the transistor 100. Note that a node between the gate of the transistor 130, one of the source or the drain of the transistor 100, and one of the electrodes of the capacitor 150 is referred to as a node FN.

  The semiconductor device illustrated in FIG. 5A applies a potential corresponding to the potential of the wiring BL to the node FN when the transistor 100 is in a conductive state (on state). In addition, the transistor 100 has a function of holding the potential of the node FN when the transistor 100 is nonconductive (off). That is, the semiconductor device illustrated in FIG. 5A functions as a memory cell of a memory device. Note that in the case of including a display element such as a liquid crystal element or an organic EL (Electroluminescence) element electrically connected to the node FN, the semiconductor device in FIG. 5A can also function as a pixel of the display device.

  The selection of the conductive state or the non-conductive state of the transistor 100 can be controlled by the potential applied to the wiring WL or the wiring BG. The threshold voltage of the transistor 100 can be controlled by the potential supplied to the wiring WL or the wiring BG. With the use of a transistor with low off current as the transistor 100, the potential of the node FN in the non-conductive state can be held for a long time. Therefore, since the refresh frequency of the semiconductor device can be reduced, a semiconductor device with low power consumption can be realized. Note that a transistor using an oxide semiconductor can be given as an example of a transistor with low off current.

  Note that the wiring CL is supplied with a constant potential such as a reference potential, a ground potential, or any fixed potential. At this time, the apparent threshold voltage of the transistor 100 is changed by the potential of the node FN. Information that the potential of the node FN is held can be read as data using changes in the conductive state and the nonconductive state of the transistor 130 due to changes in the apparent threshold voltage.

Note that in order to maintain the potential held at the node FN for 10 years (3.15 × 10 ⁸ seconds) at 85 ° C., the value of the off current per 1 μm channel width of the transistor is 4.3 yA per 1 fF of capacitance. It is preferred that the Yct A: 1yA is less than 10 ^-24 A). At this time, it is preferable that the fluctuation of the potential of the acceptable node FN is within 0.5V. Or, preferably, at 95 ° C., the off current is less than 1.5 yA. The semiconductor device of one embodiment of the present invention has a sufficiently low hydrogen concentration in the lower layer than the barrier film, and as a result, the transistor using the oxide semiconductor in the upper layer has extremely low off-state current as described above. It can be realized.

  Further, by increasing the capacitance, the potential can be held longer at the node FN. That is, the holding time can be extended.

  A memory device (memory cell array) can be formed by arranging the semiconductor devices illustrated in FIG. 5A in a matrix.

  6A and 6B show an example of a cross-sectional configuration of a semiconductor device capable of realizing the circuit shown in FIG. 5A. FIG. 6B is a cross section taken along dashed-dotted line A-B in FIG.

  The semiconductor device illustrated in FIGS. 6A and 6B includes the transistor 130, the transistor 100, and the capacitor 150. The transistor 100 is provided above the transistor 130, and at least one or more barrier films are provided between the transistor 130 and the transistor 100. In addition, the semiconductor device may form a plurality of barrier films. 6A and 6B illustrate an example in which the semiconductor device includes the barrier films 111a to 111e. A top view of the transistor 100 is illustrated in FIG. A cross section taken along a broken line X-X 'illustrated in FIG. 5B is illustrated as the transistor 100 in FIG. A cross section taken along a broken line Y-Y 'in FIG. 5B is illustrated as the transistor 100 in FIG.

[First transistor]
The transistor 130 is provided over the semiconductor substrate 131, and includes a semiconductor layer 132 formed of part of the semiconductor substrate 131, a gate insulating film 134, a gate electrode 135, and a low resistance layer 133a and a low resistance layer 133b functioning as a source region or a drain region. Have. The semiconductor device illustrated in FIG. 6 may include the transistor 160. The transistor 160 is provided on the semiconductor substrate 131 together with the transistor 130.

  The transistor 130 may be either a p-channel transistor or an n-channel transistor, but an appropriate transistor may be used depending on the circuit configuration and the driving method.

  A semiconductor such as a silicon-based semiconductor is preferably included in a region where the channel of the semiconductor layer 132 is formed or a region in the vicinity thereof, and the low resistance layer 133a and the low resistance layer 133b serving as a source region or a drain region. It is preferred to include silicon. Alternatively, it may be formed using a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide) or the like. A configuration in which silicon having distortion in a crystal lattice is used may be used. Alternatively, the transistor 130 may be a HEMT (High Electron Mobility Transistor) by using GaAs and AlGaAs or the like.

  In addition, the transistor 130 may include a region 176 a and a region 176 b which are LDD (lightly doped drain) regions.

  In addition to the semiconductor material applied to the semiconductor layer 132, the low-resistance layer 133a and the low-resistance layer 133b may be an element imparting n-type conductivity such as phosphorus or an element imparting p-type conductivity such as boron. Including.

  The gate electrode 135 is a semiconductor material such as silicon containing an element imparting n-type conductivity such as phosphorus or an element imparting p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material And the like can be used. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten.

  Here, instead of the transistor 130 and the transistor 160, a transistor 190 and a transistor 191 as shown in FIG. 16 may be used. The cross section shown to dashed-dotted line AB of FIG. 16 (A) is shown to FIG. 16 (B). In the transistor 190 and the transistor 191, the semiconductor layer 132 (part of the semiconductor substrate) in which a channel is formed has a convex shape, and the gate insulating film 134 and the gate electrode 135 are provided along the side surface and the top surface. Such a transistor 190 and a transistor 191 are also referred to as a FIN type transistor because they use the convex portion of the semiconductor substrate. Note that an insulating film which functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Further, although the case where the semiconductor substrate is partially processed to form the convex portion is shown here, the SOI substrate may be processed to form a semiconductor layer having a convex shape.

  An insulating film 136, an insulating film 137, and an insulating film 138 are sequentially stacked and provided to cover the transistor 130.

  The insulating film 136 functions as a protective film in activating a conductive element added to the low resistance layer 133 a and the low resistance layer 133 b in the manufacturing process of the semiconductor device. The insulating film 136 may not be provided if unnecessary.

  In the case where a silicon-based semiconductor material is used for the semiconductor layer 132, the insulating film 137 preferably contains an insulating material containing hydrogen. By providing the insulating film 137 containing hydrogen over the transistor 130 and performing heat treatment, dangling bonds in the semiconductor layer 132 are terminated by hydrogen in the insulating film 137; thus, the reliability of the transistor 130 can be improved.

  The insulating film 138 functions as a planarization layer which planarizes a step difference generated by a transistor 130 or the like provided in the lower layer. The upper surface of the insulating film 138 may be planarized by planarization treatment using a CMP (Chemical Mechanical Polishing) method or the like in order to improve the planarity of the upper surface.

  The insulating film 136, the insulating film 137, and the insulating film 138 have a plug 140 electrically connected to the low resistance layer 133a, the low resistance layer 133b, and the like, a plug 139 electrically connected to the gate electrode 135 of the transistor 130, and the like. It may be embedded.

[Capacitance element]
A barrier film 111 is provided between the transistor 130 and the transistor 100. The barrier film may be a single layer or a plurality of layers as shown in FIG. Here, in the example of the semiconductor device illustrated in FIG. 6A, five barrier films including the barrier films 111a to 111e are provided. When the barrier film is used as the insulating film of the capacitor, the capacitance can be increased by reducing the film thickness. On the other hand, there is a possibility that the barrier property may be reduced by thinning. Therefore, by stacking a plurality of thin barrier films, the capacitance can be further increased and the barrier property can be improved, and the characteristics of the transistor 100 and the transistor 130 can be improved.

  The conductive layer 151, the conductive layer 152, the conductive layer 153a, the conductive layer 153b, and the conductive layers 154a to 154e are provided to sandwich the barrier film, and the capacitor 150 is formed. The plug 121, the plug 126 and the plug 127 are electrically connected. The plug 126 is formed in an opening provided in the barrier film 111b, the insulating film 115b, and the barrier film 111c. The conductive layer 151, the conductive layer 153a, and the conductive layer 153b are electrically connected to the conductive layer 104a of the transistor 100 through the plug 127, the plug 126, and the plug 121. The conductive layer 151 is formed to be embedded in the opening provided in the insulating film 115 a. Similarly, the conductive layers 154a and 154b are provided in the insulating film 115b, the conductive layer 153a is provided in the insulating film 115c, the conductive layer 154c and the conductive layer 154d are provided in the insulating film 115d, and the conductive layer 153b is provided in the insulating film 115e. It is formed to be embedded in the opening.

  7 shows a cross section taken along dashed-dotted line C-D in FIG. The conductive layer 154 e is electrically connected to the plug 128. The conductive layer 154 b and the conductive layer 154 d are electrically connected to the plug 128 through the plugs 129 a to 129 d. The plug 128 is connected to the wiring 142 through the plug 141.

  An insulating film 114 is provided to cover the barrier film 111, the conductive layer 152, the conductive layer 154e, and the like.

  The upper surface of the insulating film 114 is preferably planarized by the above-described planarization process.

  As the insulating film 114, it is preferable to use an oxide material from which part of oxygen is released by heating.

As an oxide material from which oxygen is released by heating, an oxide containing oxygen at a higher proportion than the stoichiometric composition is preferably used. In an oxide film containing more oxygen than the stoichiometric composition, part of the oxygen is released by heating. The oxide film containing more oxygen than the stoichiometric composition has an amount of released oxygen in terms of oxygen atoms in thermal desorption spectroscopy (TDS) analysis. The oxide film is an oxide film of 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, metal oxides can also be used. As the metal oxide, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. In the present specification, silicon oxynitride refers to a material having a higher content of oxygen than nitrogen as its composition, and silicon nitride oxide is a material having a higher content of nitrogen than oxygen as its composition. Indicates

[Second transistor]
The semiconductor layer 101 of the transistor 100 is provided over the insulating film 114.

  The transistor 100 includes a semiconductor layer 101 in contact with the top surface of the insulating film 114, a conductive layer 104a and a conductive layer 104b, a gate insulating film 102 over the semiconductor layer 101, and a gate electrode overlapping with the semiconductor layer 101 with the gate insulating film 102 interposed therebetween. And 103. In addition, the insulating film 112, the insulating film 113, and the insulating film 116 are provided to cover the transistor 100. In addition, the transistor 100 may include the conductive layer 105 which functions as a second gate electrode.

  Note that the semiconductor layer 101 may be formed as a single layer, and is preferably formed to have a stacked structure of the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c as in the transistor 100 illustrated in FIG. . The transistor 100 illustrated in FIG. 6 includes a semiconductor layer 101a, a semiconductor layer 101b in contact with the top surface of the semiconductor layer 101a, and a conductive layer 104a and a conductive layer 104b in contact with the top surface of the semiconductor layer 101b and separated in a region overlapping with the semiconductor layer 101b. The semiconductor layer 101c is in contact with the top surface of the semiconductor layer 101b, the gate insulating film 102 over the semiconductor layer 101c, and the gate electrode 103 overlapping with the semiconductor layer 101b with the gate insulating film 102 and the semiconductor layer 101c interposed therebetween. In addition, the transistor 100 illustrated in FIG. 6 includes the conductive layer 105 which functions as a second gate electrode. The conductive layer 105 may be formed at the same time as the conductive layer 152 which forms a part of the capacitor 150. The semiconductor layer 101a is provided between the insulating film 114 and the semiconductor layer 101b. The semiconductor layer 101 c is provided between the semiconductor layer 101 b and the gate insulating film 102. The conductive layers 104a and 104b are in contact with the top surface of the semiconductor layer 101b and in contact with the bottom surface of the semiconductor layer 101c.

  In addition, the insulating film 112, the insulating film 113, and the insulating film 116 are provided to cover the transistor 100.

  As illustrated in FIG. 6A, the side surface of the semiconductor layer 101b is in contact with the conductive layer 104a and the conductive layer 104b. Further, the semiconductor layer 101b can be electrically surrounded by the electric field of the gate electrode 103 (a structure of a transistor which electrically surrounds a semiconductor by the electric field of a conductor is referred to as a surrounded channel (s-channel) structure). . Therefore, a channel may be formed in the whole (bulk) of the semiconductor layer 101b. In the s-channel structure, a large current can flow between the source and the drain of the transistor, and the current (on-state current) when conducting can be increased.

  The s-channel structure can be said to be a structure suitable for miniaturized transistors because high on-state current can be obtained. Since the transistor can be miniaturized, a semiconductor device including the transistor can be a highly integrated semiconductor device with high density. For example, the transistor has a channel length of preferably 40 nm or less, more preferably 30 nm or less, more preferably 20 nm or less, and the transistor preferably has a channel width of 40 nm or less, more preferably 30 nm or less, more Preferably, it has a region of 20 nm or less.

  Note that the channel length is, for example, a region where a semiconductor (or a portion through which current flows in the semiconductor when the transistor is on) and a gate electrode overlap in a top view of the transistor, or a region where a channel is formed. , Source (source region or source electrode) and drain (drain region or drain electrode). Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be determined to one value. Therefore, in the present specification, the channel length is any one value, maximum value, minimum value or average value in the region where the channel is formed.

  The channel width is, for example, a region where a semiconductor (or a portion through which current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other or a region in which a channel is formed and the source and the drain face each other. Say the length of the part Note that in one transistor, the channel width may not be the same in all regions. That is, the channel width of one transistor may not be determined to one value. Therefore, in the present specification, the channel width is set to any one value, maximum value, minimum value or average value in the region where the channel is formed.

  Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, referred to as effective channel width) and the channel width shown in the top view of the transistor (hereinafter, apparent channel width) And) may be different. For example, in a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a minute and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the top surface of the semiconductor. In that case, the effective channel width actually formed by the channel is larger than the apparent channel width shown in the top view.

  By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width unless the shape of the semiconductor is accurately known.

  Therefore, in this specification, in the top view of the transistor, the apparent channel width, which is the length of the portion where the source and the drain face each other in the region where the semiconductor and the gate electrode overlap, Sometimes referred to as “surrounded channel width)”. Also, in the present specification, the term “channel width only” may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, the term “channel width” may refer to an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. can be determined by acquiring a cross-sectional TEM image etc. and analyzing the image etc. it can.

  Note that in the case where electric field mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, the value may be different from that calculated using the effective channel width.

  Note that at least part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is a surface, a side surface, a top surface, and a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). And / or provided on at least a part (or all) of the lower surface.

  Alternatively, at least part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is a surface, a side surface, a top surface, and a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). And / or contacts at least a part (or all) of the lower surface. Alternatively, at least a portion (or all) of the conductive layer 104a (and / or the conductive layer 104b) is at least a portion (or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). , In contact.

  Alternatively, at least part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is a surface, a side surface, a top surface, and a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). And / or electrically connected to at least part (or all) of the lower surface. Alternatively, at least a portion (or all) of the conductive layer 104a (and / or the conductive layer 104b) is at least a portion (or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). , Electrically connected.

  Alternatively, at least part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is a surface, a side surface, a top surface, and a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). And / or disposed close to at least a part (or all) of the lower surface. Alternatively, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is at least a part (or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). , Placed in close proximity.

  Alternatively, at least part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is a surface, a side surface, a top surface, and a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). And / or is disposed on the side of at least part (or all) of the lower surface. Alternatively, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is at least a part (or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). It is placed on the side.

  Alternatively, at least part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is a surface, a side surface, a top surface, and a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). And / or is disposed diagonally above at least a part (or all) of the lower surface. Alternatively, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is at least a part (or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). It is arranged diagonally above.

  Alternatively, at least part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is a surface, a side surface, a top surface, and a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). And / or is disposed on the upper side of at least a part (or all) of the lower surface. Alternatively, at least a part (or all) of the conductive layer 104a (and / or the conductive layer 104b) is at least a part (or all) of a semiconductor layer such as the semiconductor layer 101b (and / or the semiconductor layer 101a). It is arranged on the upper side.

  The semiconductor layer 101 may include a semiconductor such as a silicon-based semiconductor in a region where a channel is formed. In particular, the semiconductor layer 101 preferably includes a semiconductor having a larger band gap than silicon. Preferably, the semiconductor layer 101 includes an oxide semiconductor. It is preferable to use a semiconductor material having a wider band gap and a lower carrier density than silicon because current in the off state of the transistor can be reduced.

  By using such a material as the semiconductor layer, variation in electrical characteristics can be suppressed and a highly reliable transistor can be realized.

  Note that a preferable embodiment of an oxide semiconductor which can be applied to the semiconductor layer and a formation method thereof will be described in detail in a later embodiment.

Note that in the present specification and the like, when substantially intrinsic, the carrier density of the oxide semiconductor layer is less than 1 × 10 ¹⁷ / cm ^3, less than 1 × 10 ¹⁵ / cm ³ , or less than 1 × 10 ¹³ / cm ³ , Particularly preferably less than 8 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹¹ / cm ³ , still more preferably less than 1 × 10 ¹⁰ / cm ³ and 1 × 10 ⁻⁹ / cm ³ or more Point to By making the oxide semiconductor layer highly intrinsic, stable electric characteristics can be given to the transistor.

  For example, in the case of using an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 1: 1: 1 or 3: 1: 2 as the semiconductor layer 101b, the semiconductor layer 101a or the semiconductor layer 101c can be obtained. For example, In: Ga: Zn = 1: 3: 2, 1: 3: 4, 1: 3: 6, 1: 6: 4, 1: 6: 8, 1: 6: 10, or 1: 9: 6 etc. An In-Ga-Zn-based oxide having an atomic ratio of can be used. Note that the atomic ratio of the semiconductor layer 101b, the semiconductor layer 101a, and the semiconductor layer 101c includes a variation of plus or minus 20% of the atomic ratio described above as an error. In addition, the semiconductor layer 101a and the semiconductor layer 101c may use materials having the same composition, or materials having different compositions may be used.

In the case where an In-M-Zn-based oxide is used as the semiconductor layer 101b, a target used for forming a semiconductor film to be the semiconductor layer 101b has an atomic ratio of metal elements contained in the target of In: When M: Zn = x ₁ : y ₁ : z ₁ , the value of x ₁ / y ₁ is 1/3 or more and 6 or less, preferably 1 or more and 6 or less, and z ₁ / y ₁ is 1/3 It is preferable to use an oxide having an atomic ratio of 6 or more, preferably 1 or more and 6 or less. Note that setting z ₁ / y ₁ to 6 or less facilitates formation of a CAAC-OS film described later. As a representative example of the atomic ratio of metal elements of the target, there are In: M: Zn = 1: 1: 1, 3: 1: 2, and the like.

In the case where an In-M-Zn-based oxide is used for the semiconductor layer 101a and the semiconductor layer 101c, a target used for forming a semiconductor film to be the semiconductor layer 101a and the semiconductor layer 101c is a metal contained in the target. When the atomic ratio of the elements is In: M: Zn = x ₂ : y ₂ : z ₂ , x ₂ / y ₂ <x ₁ / y ₁ and the value of z ₂ / y ₂ is 1/3 It is preferable to use an oxide having an atomic ratio of 6 or more, preferably 1 or more and 6 or less. Note that setting z ₂ / y ₂ to 6 or less facilitates formation of a CAAC-OS film described later. In: M: Zn = 1: 3: 4, 1: 3: 6, 1: 3: 8 etc. are representative examples of the atomic ratio of the metal element of the target.

  In the case where an oxide semiconductor is formed by sputtering, a film with an atomic ratio different from that of the target may be formed. In particular, zinc may make the atomic ratio of the film smaller than the atomic ratio of the target. Specifically, it may be about 40 atomic% or more and about 90 atomic% or less of the atomic ratio of zinc contained in the target.

  One of the conductive layer 104 a and the conductive layer 104 b functions as a source electrode, and the other functions as a drain electrode.

  The plug 121 is electrically connected to the conductive layer 151 through an opening provided in the conductive layer 104 a, the semiconductor layer 101 a, the semiconductor layer 101 b, the semiconductor layer 101 c, the insulating film 114, and the barrier film 111. The conductive layer 104 a is electrically connected to the conductive layer 151 via the plug 121.

  The conductive layer 104 a and the conductive layer 104 b each have a single-layer structure or a stacked structure of a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing such a metal as a main component. Used as For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked on a titanium film, a two-layer structure in which an aluminum film is stacked on a tungsten film, a copper film on a copper-magnesium-aluminum alloy film Two-layer structure to be stacked, two-layer structure in which a copper film is stacked on a titanium film, two-layer structure in which a copper film is stacked on a tungsten film, a titanium film or titanium nitride film, and the titanium film or titanium nitride film A three-layer structure in which an aluminum film or a copper film is laminated and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or a molybdenum nitride film, and an aluminum film or copper stacked on the molybdenum film or the molybdenum nitride film There is a three-layer structure or the like in which a film is stacked and a molybdenum film or a molybdenum nitride film is formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

  The gate insulating film 102 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn-based metal oxide, silicon nitride, or the like, and is provided as a stacked layer or a single layer.

In addition, as the gate insulating film 102, hafnium silicate (HfSiO _x ), hafnium silicate to which nitrogen is added (HfSi _x O _y N _z ), hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z ), yttrium oxide And the like may be used.

  In addition, as the gate insulating film 102, an oxide insulating film of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like The insulating film can be formed using a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide, or a film obtained by mixing the above materials.

  Further, as the gate insulating film 102, as in the case of the insulating film 114, an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition is preferably used.

  Note that when a specific material is used for the gate insulating film, electrons can be captured by the gate insulating film under specific conditions to increase the threshold voltage. For example, as in a laminated film of silicon oxide and hafnium oxide, a material having many electron capture states such as hafnium oxide, aluminum oxide, or tantalum oxide is used for part of the gate insulating film, and a higher temperature (use of semiconductor device The potential of the gate electrode is higher than the potential of the source electrode or the drain electrode at a temperature higher than the temperature or the storage temperature, or 125 ° C. to 450 ° C., typically 150 ° C. to 300 ° C.); By maintaining for 1 second or more, typically 1 minute or more, electrons move from the semiconductor layer to the gate electrode, and some of them are trapped in the electron capture level.

  As described above, in the transistor in which the amount of electrons necessary for the electron trap level is captured, the threshold voltage is shifted to the positive side. By controlling the voltage of the gate electrode, it is possible to control the amount of captured electrons and, accordingly, the threshold voltage can be controlled. In addition, a process for capturing electrons may be performed in the process of manufacturing a transistor.

  For example, after formation of a wiring metal connected to a source electrode or drain electrode of a transistor, or after completion of a previous process (wafer processing), or after a wafer dicing process, after packaging, or before factory shipment. Good to do. In any case, it is preferable not to be exposed to the temperature of 125 ° C. or more for one hour or more after that.

  The gate electrode 103 is formed using, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described metal, or an alloy combining the above-described metals. Can. In addition, a metal selected from one or more of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus or a silicide such as nickel silicide may be used. The gate electrode 103 may have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which an aluminum film is stacked on a titanium film and a titanium film, and a titanium film is formed thereon is there. Alternatively, an alloy film or nitride film in which one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined with aluminum may be used.

  In addition, the gate electrode 103 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, the light-transmitting conductive material can have a stacked structure of the above-described metal.

  In addition, an In—Ga—Zn-based oxynitride semiconductor film, an In—Sn-based oxynitride semiconductor film, an In—Ga-based oxynitride semiconductor film, and an In—Zn-based film are formed between the gate electrode 103 and the gate insulating film 102. An oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a metal nitride film (InN, ZnN or the like), or the like may be provided. These films have a work function of 5 eV or more, preferably 5.5 eV or more, which is larger than the electron affinity of the oxide semiconductor, and thus shift the threshold voltage of the transistor including the oxide semiconductor to a positive value. Thus, a switching element having a so-called normally-off characteristic can be realized. For example, in the case of using an In-Ga-Zn-based oxynitride semiconductor film, an In-Ga-Zn-based oxynitride semiconductor film which has a nitrogen concentration higher than that of the semiconductor layer 101, specifically, 7 atomic% or more is used.

  Like the barrier film 111, the insulating film 112 is preferably made of a material to which water or hydrogen does not easily diffuse. In particular, a material which hardly transmits oxygen is preferably used as the insulating film 112.

  By covering the semiconductor layer 101 with the insulating film 112 containing a material which does not easily transmit oxygen, release of oxygen from the semiconductor layer 101 above the insulating film 112 can be suppressed. Further, oxygen released from the insulating film 114 can be confined below the insulating film 112, whereby the amount of oxygen which can be supplied to the semiconductor layer 101 can be increased.

  In addition, the insulating film 112 which hardly transmits water and hydrogen can suppress entry of water and hydrogen which are impurities for the oxide semiconductor from the outside, which can suppress variation in electric characteristics of the transistor 100 and has high reliability. A transistor can be realized.

  Note that an insulating film similar to the insulating film 114 from which oxygen is released by heating is provided below the insulating film 112, and oxygen is also supplied from the upper side of the semiconductor layer 101 through the gate insulating film 102. It is also good.

  Further, as shown in FIG. 6B, the gate electrode 103 is provided so as to face the upper surface and the side surface of the semiconductor layer 101b in the cross section in the channel width direction of the transistor. A channel is formed near the side surface, the effective channel width can be increased, and the current in the on state (on current) can be increased. In particular, in the case where the width of the semiconductor layer 101b is extremely small (for example, 50 nm or less, preferably 30 nm or less, more preferably 20 nm or less), the region in which the channel is formed expands to the inside of the semiconductor layer 101b, so miniaturization is achieved. The contribution to the on current increases.

  17A and 17B illustrate an example of the transistor 100 included in the semiconductor device. The transistor 100 illustrated in FIGS. 17A and 17B is mainly different from the transistor 100 illustrated in FIG. 6 in that the semiconductor layer 101c is provided in contact with the lower surfaces of the conductive layer 104a and the conductive layer 104b. It is different. Here, FIG. 17B is a cross section along dashed-dotted line A-B in FIG. 17A.

  With such a structure, films can be formed continuously without being exposed to the air at the time of film formation of the respective films forming the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c. Interface defects can be reduced.

  Further, the transistor 100 may have a structure shown in FIG. In FIG. 35A, after the semiconductor layers 101a and 101b are formed, the semiconductor layer 101c is formed, and the side surfaces of the semiconductor layers 101a and 101b are covered with the semiconductor layer 101c. In addition, the transistor 100 may have a structure illustrated in FIG. 35B is different from FIG. 35A in that the gate electrode 103 and the conductive layer 104a, and the gate electrode 103 and the conductive layer 104b overlap in FIG. 35A. Then, the gate electrode 103 and the conductive layer 104a and the conductive layer 104b do not overlap in the cross section shown in FIG.

  In FIGS. 6A, 6B, 17A, and 17B, the structure in which the semiconductor layer 101a and the semiconductor layer 101c are provided in contact with the semiconductor layer 101b is described. However, the semiconductor layer 101a or the semiconductor layer is described. Alternatively, one or both of 101c may not be provided.

  The structure shown in FIG. 6B is processed so that the end portions of the gate insulating film 102 and the semiconductor layer 101c are substantially aligned, and the gate electrode 103 is processed so as to be positioned inside the gate insulating film. Although an example is shown, as in the example of the transistor 100 illustrated in FIG. 17C, the end portions of the gate insulating film 102, the semiconductor layer 101c, and the gate electrode 103 may be roughly aligned. Alternatively, as in the example of the transistor 100 illustrated in FIG. 17D, the end portions of the gate insulating film 102, the semiconductor layer 101c, and the gate electrode may be processed so as not to coincide with each other.

  The above is the description of the transistor 100.

  The insulating film 116 which covers the transistor 100 functions as a planarization layer which covers the underlying uneven shape. In addition, the insulating film 113 may have a function as a protective film in forming the insulating film 116. The insulating film 113 may not be provided if unnecessary.

  In the insulating film 112, the insulating film 113, and the insulating film 116, a plug 123, a plug 122, and the like which are electrically connected to the conductive layer 104b are embedded.

  Over the insulating film 116, a wiring 124 electrically connected to the plug 123 and the like are provided.

  Here, the wiring 124 illustrated in FIG. 6A corresponds to the wiring BL illustrated in FIG. Similarly, the wiring 166 illustrated in FIG. 6B corresponds to the wiring BG, and the wiring 142 illustrated in FIG. 7 corresponds to the wiring CL. Although not shown, a wire connected to the gate electrode 103 in FIG. 6 corresponds to the wire WL. The low resistance layer 133 b of the transistor 130 corresponds to the wiring SL. A node including the gate electrode 135 of the transistor 130, the plug 121 functioning as the first electrode of the capacitor 150, and the conductive layer 104a of the transistor 100 corresponds to the node FN illustrated in FIG. 5A.

  Further, in FIG. 6, as the insulating film 137 provided over the insulating film 136 containing hydrogen, the insulating film 137 containing a material similar to the barrier film 111 is preferably provided. With such a configuration, diffusion of water and hydrogen remaining in the insulating film 136 containing hydrogen can be effectively suppressed. In this case, heat treatment for removing water and hydrogen is performed twice or more in total before forming the insulating film 137 and after forming the insulating film 137 and before forming the barrier film 111. It is also good.

  For the wirings such as the wiring 124, the wiring 142, and the wiring 166, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used as a material. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten.

  A conductive layer such as the conductive layer 125, the conductive layer 151, the conductive layer 152, the conductive layer 153a, the conductive layer 153b, the conductive layers 154a to 154e, the plug 121 to the plug 123, the plug 126 to the plug 128, the plug 129a to For plugs such as the plug 129 d, the plug 139 to the plug 141, the plug 164, and the plug 165, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used as a material. In particular, it is preferable to use a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity, and it is particularly preferable to use tungsten. In addition, materials such as titanium nitride and titanium may be stacked with other materials. For example, by using titanium nitride or titanium, adhesion to the opening can be improved. In addition, conductive layers such as the conductive layer 125, the conductive layer 151, the conductive layer 152, the conductive layer 153a, the conductive layer 153b, and the conductive layers 154a to 154e, the plugs 121 to 123, the plugs 126 to 128, and the plugs 129a to 129d. The plugs 139 to 141, the plug 164, the plug 165, and the like are provided so as to be embedded in the insulating film, and the upper surface of each is preferably planarized.

  Here, the plug 121 is in contact with the semiconductor layer 101, the conductive layer 104 a, and the conductive layer 151 of the transistor 100. First, by being in contact with the semiconductor layer 101 and the conductive layer 104 a of the transistor 100, the wiring functions as a wiring connected to the source region or the drain region of the transistor 100. In addition, by being in contact with the conductive layer 151, the wiring functions as a wiring connected to one electrode of the capacitor 150. The plug 121 penetrates the transistor 100 and reaches the conductive layer 151 which is one electrode of the capacitor 150, whereby one electrode connects the electrode of the capacitor 150 and the source or drain region of the transistor 100 It can double as wiring.

  Similarly, the plug 122 is in contact with the semiconductor layer 101, the conductive layer 104 b, and the conductive layer 125 of the transistor 100. First, by being in contact with the semiconductor layer 101 and the conductive layer 104 b of the transistor 100, the wiring functions as a wiring connected to the source region or the drain region of the transistor 100. Further, by being in contact with the conductive layer 125, the wiring functions as a wiring connected to the source region or the drain region of the transistor 130. The plug 122 penetrates the transistor 100 and reaches the conductive layer 125 so that one plug serves as a wiring connected to the source or drain region of the transistor 130 and a wiring connected to the source or drain electrode of the transistor 100. be able to.

  Next, an example in which the circuit area can be reduced by using the plug 121 and the plug 122 will be described with reference to FIG. Further, the configuration shown in FIG. 31 shows an example in which the plug 121 and the plug 122 are not used. For the barrier film 211a, the description of the barrier film 111 is referred to. For the insulating film 215a, the description of the insulating film 115a is referred to. The contact 221 between the conductive layer 104a and the capacitor 150 is formed outside the semiconductor layer 101b, which causes an increase in the element area. Similarly, the contact 222 between the conductive layer 104 b and the conductive layer connected to the source region or the drain region of the transistor 130 is formed outside the semiconductor layer 101 b, which causes an increase in the element area.

  In the configuration example shown in FIG. 30A, a plug 121 which penetrates the transistor 100 and is connected to one electrode of the capacitor 150 and electrically connected to a source electrode or a drain region of the transistor 130 which penetrates the transistor 100 An example in which the plug 122 connected to the conductive layer 251a is used is shown. For the barrier films 211 a to 211 f, the description of the barrier film 111 is referred to. For the insulating films 215a to 215f, the description of the insulating film 115a is referred to. For the conductive layer 251, the description of the conductive layer 151 is referred to. For the conductive layer 251 a, the description of the conductive layer 125 is referred to. 30B is a diagram in which two configurations shown in FIG. 30A are arranged. Although FIG. 30 shows an example in which the conductive layer 104 a and the conductive layer 104 b are not provided, they may be provided.

  While two contacts of the contact 221 of the conductive layer 104a and the capacitor 150 and the contact 223 of the plug 321 and the conductive layer 104a are provided in FIG. 31, the two contacts are shown in FIG. The role of the plug 121 can be played. Similarly, in FIG. 31, two contacts of the contact 222 of the conductive layer 104b and the conductive layer 251a and the contact 224 of the plug 322 and the conductive layer 104b are provided, while in FIG. The role of the two contacts can be played by the plug 122. As described above, by using the plug 121 and the plug 122, the capacitor 150 can be manufactured to have a width similar to that of the transistor 100 in the structure illustrated in FIG. 30, and the area occupied by the element can be reduced.

  Next, in the cross-sectional view in FIG. 30, top views of the layers 281 to 287 are illustrated in FIG. In addition, in the cross-sectional view in FIG. 31, top views of the layers 291 to 295 are illustrated in FIG. Each top view shows the minimum structural unit of the memory cell. By using the structure of FIG. 30, it can be seen that the area can be reduced to about half compared to FIG.

  Alternatively, as in the cross section of the semiconductor device illustrated in FIG. 33, the plug 121 and the plug 122 may be formed after the insulating film 261 for planarization is provided.

  The semiconductor device of one embodiment of the present invention includes the transistor 130 and the transistor 100 located above the first transistor 130; therefore, the area occupied by the element can be reduced by stacking them. In addition, by providing the plug 121 and the plug 122, the area occupied by the element can be reduced. Thus, a semiconductor device having a small circuit area and excellent characteristics can be provided. In addition, when one embodiment of the present invention is used for a semiconductor device including, for example, a memory or the like, a memory capacity can be increased even with a small circuit area, and a semiconductor device having a memory with favorable retention characteristics can be provided. Further, the barrier film 111 provided between the transistor 130 and the transistor 100 can suppress diffusion of an impurity such as water or hydrogen in the lower layer below the transistor 100 to the transistor 100 side. Further, a wiring whose part functions as a first electrode and a wiring whose part functions as a second electrode are provided with the barrier film 111 interposed therebetween, and the capacitor 150 is formed. The capacitive element 150 can be easily manufactured without separately adding a process for manufacturing.

  The above is the description of the configuration example.

[Example of production method]
Hereinafter, an example of a method for manufacturing the semiconductor device described in the above configuration example will be described with reference to the cross-sectional views of FIGS.

  First, the semiconductor substrate 131 is prepared. As the semiconductor substrate 131, for example, a single crystal silicon substrate (including a p-type semiconductor substrate or an n-type semiconductor substrate), a compound semiconductor substrate made of silicon carbide or gallium nitride, or the like can be used. Alternatively, an SOI substrate may be used as the semiconductor substrate 131. Hereinafter, the case where single crystal silicon is used as the semiconductor substrate 131 will be described.

  Subsequently, an element isolation layer (not shown) is formed on the semiconductor substrate 131. The element isolation layer may be formed using a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.

  In the case where a p-type transistor and an n-type transistor are formed over the same substrate, an n well or a p well may be formed in part of the semiconductor substrate 131. For example, even if an impurity element such as boron which imparts p-type conductivity is added to the n-type semiconductor substrate 131 to form a p-well, an n-type transistor and a p-type transistor may be formed over the same substrate. Good.

  Subsequently, an insulating film to be the gate insulating film 134 is formed over the semiconductor substrate 131. For example, the surface of the semiconductor substrate 131 is oxidized to form a silicon oxide film. Alternatively, after a silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film may be nitrided to form a layered structure of a silicon oxide film and a silicon oxynitride film. Alternatively, silicon oxide, silicon oxynitride, tantalum oxide which is a high dielectric constant substance (also referred to as high-k material), hafnium oxide, hafnium oxide silicate, zirconium oxide, aluminum oxide, metal oxide such as titanium oxide, or oxidation A rare earth oxide such as lanthanum may be used.

  The insulating film can be formed by a sputtering method, a chemical vapor deposition (CVD) method (including a thermal CVD method, a metal organic CVD (MOCVD) method, a plasma enhanced CVD (PECVD) method), a molecular beam epitaxy (MBE) method, It may be formed by film formation by an atomic layer deposition method, a PLD (pulsed laser deposition) method, or the like.

  Subsequently, a conductive film to be the gate electrode 135 is formed. As the conductive film, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium or the like, or an alloy material or a compound material containing these metals as a main component. Alternatively, polycrystalline silicon to which an impurity such as phosphorus is added can be used. Alternatively, a stacked structure of a metal nitride film and the above metal film may be used. As the metal nitride, tungsten nitride, molybdenum nitride, or titanium nitride can be used. By providing the metal nitride film, the adhesion of the metal film can be improved and peeling can be prevented.

  The conductive film can be formed by a sputtering method, an evaporation method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, and the like), or the like. Further, in order to reduce the plasma damage, a thermal CVD method, an MOCVD method or an ALD method is preferable.

  Subsequently, a resist mask is formed over the conductive film by a lithography method or the like, and unnecessary portions of the conductive film are removed. After that, the gate electrode 135 can be formed by removing the resist mask.

  Here, the processing method of a to-be-processed film | membrane is demonstrated. In the case of finely processing the film to be processed, various microprocessing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a photolithography method or the like may be used. Alternatively, a dummy pattern may be formed by photolithography or the like, a sidewall may be formed on the dummy pattern, and then the dummy pattern may be removed, and the remaining film may be etched using the remaining sidewall as a resist mask. In order to realize a high aspect ratio, it is preferable to use anisotropic dry etching as etching of a film to be processed. Alternatively, a hard mask made of an inorganic film or a metal film may be used.

  As light used for forming a resist mask, for example, i-ray (wavelength 365 nm), g-ray (wavelength 436 nm), h-ray (wavelength 405 nm), or a mixture of these can be used. Besides, ultraviolet light, KrF laser light, ArF laser light or the like can also be used. Further, the exposure may be performed by the immersion exposure technique. Further, as light used for exposure, extreme ultraviolet (EUV: Extreme Ultra-violet) or X-rays may be used. Also, instead of light used for exposure, an electron beam can be used. The use of extreme ultraviolet light, X-rays or electron beams is preferable because extremely fine processing is possible. In the case where exposure is performed by scanning a beam such as an electron beam, a photomask is not necessary.

  In addition, before forming a resist film to be a resist mask, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed. The organic resin film can be formed, for example, by spin coating or the like so as to cover the step in the lower layer and planarize the surface, and the thickness variation of the resist mask provided on the upper layer of the organic resin film Can be reduced. In the case of particularly fine processing, it is preferable to use, as the organic resin film, a material that functions as an antireflective film to light used for exposure. As an organic resin film which has such a function, there is a BARC (Bottom Anti-Reflection Coating) film etc., for example. The organic resin film may be removed simultaneously with the removal of the resist mask, or may be removed after removing the resist mask.

  After the gate electrode 135 is formed, a sidewall covering the side surface of the gate electrode 135 may be formed. The sidewalls can be formed by forming an insulating film thicker than the thickness of the gate electrode 135 and then anisotropically etching the insulating film so that only the side portions of the gate electrode 135 remain.

  Although FIG. 8A shows an example in which etching of the gate insulating film is not performed at the time of formation of the sidewall, an insulating film to be the gate insulating film 134 may be etched at the same time of formation of the sidewall. In this case, the gate insulating film 134 is formed under the gate electrode 135 and the side wall.

  Subsequently, an element imparting n-type conductivity such as phosphorus or an element imparting p-type conductivity such as boron is added to a region of the semiconductor substrate 131 where the gate electrode 135 (and the sidewall) is not provided. Do. A schematic cross-sectional view at this stage corresponds to FIG.

  Subsequently, after the insulating film 136 is formed, the above-described first heat treatment for activating the element imparting conductivity is performed.

  The insulating film 136 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like, and is provided as a stacked layer or a single layer. The insulating film 136 can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because coverage can be improved. Further, in order to reduce the plasma damage, a thermal CVD method, an MOCVD method or an ALD method is preferable.

  The first heat treatment can be performed, for example, at a temperature higher than or equal to 400 ° C. and lower than the strain point of the substrate in an inert gas atmosphere such as a rare gas or a nitrogen gas, or in a reduced pressure atmosphere.

  At this stage, the transistor 130 is formed. Alternatively, the transistor 160 may be formed in the same manner as the transistor 130 is formed.

  Subsequently, the insulating film 137 and the insulating film 138 are formed.

  The insulating film 137 is preferably formed using a silicon nitride (SiNOH) containing oxygen and hydrogen in addition to a material which can be used for the insulating film 136 because the amount of hydrogen desorbed by heating can be increased. In addition, the insulating film 138 is a step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate), silane or the like with oxygen or nitrous oxide or the like in addition to the material which can be used for the insulating film 136. It is preferable to use good silicon oxide.

  The insulating film 137 and the insulating film 138 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because coverage can be improved. Further, in order to reduce the plasma damage, a thermal CVD method, an MOCVD method or an ALD method is preferable.

  Subsequently, the upper surface of the insulating film 138 is planarized using a CMP method or the like. Alternatively, a planarization film may be used as the insulating film 138. In that case, planarization may not necessarily be performed by a CMP method or the like. For the formation of the planarizing film, for example, an atmospheric pressure CVD method or a coating method can be used. Examples of the film that can be formed using the normal pressure CVD method include BPSG (Boron Phosphorus Silicate Glass). Moreover, as a film | membrane which can be formed using the apply | coating method, HSQ (hydrogen silsesquioxane) etc. are mentioned, for example.

  After that, second heat treatment is performed to terminate dangling bonds in the semiconductor layer 132 with hydrogen released from the insulating film 137. In addition, the content of water or hydrogen can be reduced by removing water or hydrogen contained in each layer by the second heat treatment.

  The second heat treatment can be performed under the conditions exemplified in the description of the above laminated structure. For example, the conditions described in the first heat treatment can be used.

  Subsequently, an opening reaching the low resistance layer 133a, the low resistance layer 133b, the gate electrode 135, and the like is formed in the insulating film 136, the insulating film 137, and the insulating film 138 (see FIG. 8B). After that, a conductive film 181 to be the plug 139 or the like is formed so as to fill the opening (see FIG. 8C). After that, the conductive film 181 is planarized so that the top surface of the insulating film 138 is exposed, whereby the plug 139, the plug 140, and the like are formed (see FIG. 8D). The conductive film 181 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like.

  Subsequently, the insulating film 115 e is formed over the insulating film 138 to form an opening. After that, a conductive film is formed to fill the opening, and the conductive film is planarized to expose the top surface of the insulating film 115e, whereby the conductive layer 144, the conductive layer 153b, and the like are formed (FIG. 8). See (E). In the example illustrated in FIG. 6, the conductive layer 153b functions as an electrode of a capacitor.

  Subsequently, a barrier film 111e is formed, and then an insulating film 115d is formed (see FIG. 9A). Next, an opening is formed in the insulating film 115d. After that, a conductive film is formed to fill the opening, and the conductive film is planarized to expose the top surface of the insulating film 115e, whereby the conductive layer 154d, the conductive layer 154e, and the like are formed (FIG. 9). (B) see). In the example illustrated in FIG. 6, the conductive layer 154d and the conductive layer 154e function as electrodes of a capacitor. Thereafter, the barrier film 111d is formed (see FIG. 9C).

  Subsequently, openings are formed in the barrier film 111d, the insulating film 115d, and the barrier film 111e. After that, a conductive film to be the plug 127 or the like is formed so as to fill the opening, and the conductive film is planarized to form the plug 127, the plug 145, or the like so that the upper surface of the barrier film 111d is exposed. (Refer to FIG. 9 (D).).

  Subsequently, an insulating film 115c is formed (see FIG. 10A). Next, an opening is formed in the insulating film 115c. After that, a conductive film is formed so as to fill the opening, and the conductive film is planarized to expose the top surface of the insulating film 115c, whereby the conductive layer 146, the conductive layer 153a, and the like are formed (FIG. 10). (B) see). The conductive layer 153 a functions as an electrode of a capacitor.

  Next, the conductive layer 154a, the conductive layer 154b, the plug 126, and the plug 147 are manufactured using a method similar to that shown in FIG. 9, and then the barrier film 111a is formed, and the conductive layer 143 of the barrier film 111a is formed. After an opening is provided in a region in contact with the conductive film, a conductive film is formed. After that, a resist mask is formed, and unnecessary portions of the conductive film are removed by etching. After that, the resist mask is removed, whereby the conductive layer 152, the conductive layer 154e, and the conductive layer 105 functioning as a second gate electrode can be formed (see FIG. 10C).

  Here, in FIG. 9D, the barrier film 111d is subjected to planarization. As shown in FIGS. 9 to 10, the barrier film 111d may be used as it is as an insulating film of a capacitor. Alternatively, the steps of FIGS. 9D to 10C may be replaced with the steps of FIGS. 13A to 14B shown below, for example. Film formation may be performed again after the barrier film 111d is removed once. The example is shown in FIG. 13 to FIG. For example, when the planarization process is performed by a CMP method or the like, damage or the like sometimes occurs on the surface of the film or the like. In that case, as described below, the capacitance characteristic can be further improved by removing the damaged film or the surface area of the film and then forming the insulating film used for the capacitor element again. it can.

  FIG. 13A shows a state in which the conductive film to be the barrier film 111d, the plug 127, and the like is planarized as described with reference to FIG. 9D. Thereafter, as shown in FIG. 13B, the barrier film 111d is removed by etching or the like. Thereafter, the barrier film 111f is formed. Next, a resist mask is formed and etching is performed to form an opening portion in the barrier film 111f over the plug such as the plug 127 and the plug 145 in the barrier film 111f. After that, the resist mask is removed (see FIG. 13C).

  Next, the insulating film 115c is formed. After that, a resist mask is formed and etching is performed to form an opening in the insulating film 115c. Next, the conductive layer 146, the conductive layer 153a, and the like are formed so as to fill the opening (see FIG. 14A).

  Next, the barrier film 111c is formed, and then the insulating film 115b is formed. After that, conductive layer 154a, conductive layer 154b, barrier film 111g, plug 126 and plug 147 are formed using the same method as forming conductive layer 154c, conductive layer 154d, barrier film 111f, plug 127 and plug 145. Do.

  Next, the insulating film 115a is formed. After that, the conductive layer 125 and the conductive layer 151 are formed by using the same method as the conductive layer 146 and the conductive layer 153a. Thereafter, the barrier film 111a is formed. After that, an opening is provided in the barrier film 111a, a conductive film is formed, and the conductive layer 105, the conductive layer 152, and the conductive layer 154e are formed using a resist mask or the like (see FIG. 14B). The above is the description in the case where the steps of FIGS. 9D to 10C are replaced with the steps of FIGS. 13A to 14B.

  The insulating films 115a to 115e can be formed using the same material and method as the insulating film 136 and the like.

  The barrier films 111a to 111g can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because coverage can be improved. Further, in order to reduce the plasma damage, a thermal CVD method, an MOCVD method or an ALD method is preferable. For materials that can be used for the barrier films 111a to 111g, the description of the barrier film 111 can be referred to.

  After the insulating film 115 e is formed, third heat treatment is preferably performed. By the third heat treatment, the content of water or hydrogen can be reduced by desorbing water or hydrogen contained in each layer. A third heat treatment is performed immediately before the barrier film 111e is formed to thoroughly remove hydrogen and water contained in the lower layer than the barrier film 111e, and then the barrier film 111e is formed, whereby a barrier in a later step is obtained. It is possible to suppress the re-diffusion of water and hydrogen to the lower layer side of the film 111e.

  The third heat treatment can be performed under the conditions exemplified in the description of the above laminated structure. For example, the conditions described in the first heat treatment can be used. Note that similar heat treatment may be performed after the formation of the insulating films 115 a to 115 d after the formation of the respective insulating films.

  At this stage, the capacitive element 150 is formed. The capacitor 150 includes a conductive layer 152 and a conductive layer 154a to a conductive layer 154e, part of which functions as a first electrode, and a conductive layer 151, a conductive layer 153a, and a conductive layer 153b, part of which functions as a second electrode. And the barrier films 111a to 111e sandwiching them.

  Next, the insulating film 114 is formed. The insulating film 114 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because coverage can be improved. Further, in order to reduce the plasma damage, a thermal CVD method, an MOCVD method or an ALD method is preferable.

  In order to make the insulating film 114 contain oxygen in excess, for example, the insulating film 114 may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the insulating film 114 after film formation to form a region containing excess oxygen, or both of the methods may be combined.

  For example, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the insulating film 114 after film formation to form a region containing excess oxygen. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

  An oxygen-containing gas can be used for the oxygen introduction process. As the gas containing oxygen, oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, carbon monoxide and the like can be used. In addition, in the oxygen introduction process, a gas containing oxygen may contain a rare gas. Alternatively, hydrogen or the like may be included. For example, a mixed gas of carbon dioxide, hydrogen and argon may be used.

  In addition, after the insulating film 114 is formed, planarization treatment using a CMP method or the like may be performed in order to improve the planarity of the top surface.

  Next, a semiconductor film to be the semiconductor layer 101 a and a semiconductor film to be the semiconductor layer 101 b are sequentially formed. It is preferable that the semiconductor film be formed successively without being exposed to the air. The semiconductor to be the semiconductor layer 101a and the semiconductor to be the semiconductor layer 101b may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Note that when an In—Ga—Zn oxide layer is formed by MOCVD as a semiconductor to be the semiconductor layer 101a and a semiconductor to be the semiconductor layer 101b, trimethylindium, trimethylgallium, dimethylzinc, or the like can be used as a source gas. Good. In addition, it is not limited to the combination of the said source gas, It may replace with a trimethyl indium and a triethyl indium etc. may be used. Further, triethyl gallium or the like may be used instead of trimethyl gallium. Also, diethylzinc or the like may be used instead of dimethylzinc.

  After the semiconductor film is formed, fourth heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or reduced pressure. The heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas to compensate for the released oxygen after the heat treatment in an inert gas atmosphere. The heat treatment may be performed immediately after the formation of the semiconductor film, or may be performed after the semiconductor film is processed to form the island-shaped semiconductor layers 101a and 101b. By heat treatment, oxygen is supplied from the insulating film 114 or the oxide film to the semiconductor film, so that oxygen vacancies in the semiconductor film can be reduced.

  After that, a resist mask is formed, and unnecessary portions are removed by etching. After that, the resist mask is removed, whereby a stacked-layer structure of the island-shaped semiconductor layer 101a and the island-shaped semiconductor layer 101b can be formed (see FIG. 11A). Note that when the semiconductor film is etched, part of the insulating film 114 is etched, which may result in thinning of the insulating film 114 in a region which is not covered with the semiconductor layer 101 a and the semiconductor layer 101 b. Therefore, it is preferable to form the insulating film 114 thick beforehand so that the insulating film 114 does not disappear by the etching.

  After that, the conductive film 104 is formed (see FIG. 11B). The conductive film 104 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because coverage can be improved. Further, in order to reduce the plasma damage, a thermal CVD method, an MOCVD method or an ALD method is preferable.

  Next, a resist mask is formed, and unnecessary portions of the conductive film 104 are removed by etching. After that, the resist mask is removed, and conductive layers 104a and 104b are formed. Here, when the conductive film is etched, part of the top of the semiconductor layer 101b or the insulating film 114 may be etched, and a portion which does not overlap with the conductive layer 104a or the conductive layer 104b may be thinned. Therefore, it is preferable that the thickness of the semiconductor film or the like to be the semiconductor layer 101 b be formed in advance in consideration of the depth to be etched.

  Next, the gate insulating film 102 and the semiconductor layer 101c are formed, a resist mask is formed, and the resist mask is processed by etching. Thereafter, the resist mask is removed. Next, a conductive film to be the gate electrode 103 is formed (see FIG. 12A). After that, a resist mask is formed, the conductive film is processed by etching, and then the resist mask is removed to form the gate electrode 103. The semiconductor to be the semiconductor layer 101c may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Note that in the case where an In—Ga—Zn oxide layer is formed by MOCVD as a semiconductor to be the semiconductor layer 101c, trimethyl indium, trimethyl gallium, dimethyl zinc, or the like may be used as a source gas. In addition, it is not limited to the combination of the said source gas, It may replace with a trimethyl indium and a triethyl indium etc. may be used. Further, triethyl gallium or the like may be used instead of trimethyl gallium. Also, diethylzinc or the like may be used instead of dimethylzinc.

  At this stage, the transistor 100 is formed.

  Next, the insulating film 112 is formed. The insulating film 112 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because coverage can be improved. Further, in order to reduce the plasma damage, a thermal CVD method, an MOCVD method or an ALD method is preferable.

  After the formation of the insulating film 112, fifth heat treatment is preferably performed. By heat treatment, oxygen can be supplied from the insulating film 114 or the like to the semiconductor layer 101, so that oxygen vacancies in the semiconductor layer 101 can be reduced. At this time, since the oxygen desorbed from the insulating film 114 is blocked by the barrier film 111 and the insulating film 112 and is not diffused in the lower layer and the upper layer of the barrier film 111, the oxygen is effectively removed. It can be locked up. Therefore, the amount of oxygen which can be supplied to the semiconductor layer 101 can be increased, and oxygen vacancies in the semiconductor layer 101 can be effectively reduced.

  Further, the insulating film 112 may have a stacked structure of two or more layers. In that case, for example, the insulating film 112 has a stacked structure of two layers, and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used in the lower layer. Just do it. In the upper layer, it is preferable to use a material to which water or hydrogen does not easily diffuse as in the barrier film 111. The insulating film provided in the lower layer may be configured to supply oxygen also from the upper side of the semiconductor layer 101 through the gate insulating film 102 as an insulating film from which oxygen is released by heating, as in the case of the insulating film 114.

  Subsequently, the insulating film 113 is formed. The insulating film 113 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like, and is provided as a stacked layer or a single layer. The insulating film 113 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In particular, film formation by a CVD method, preferably plasma CVD method, is preferable because coverage can be improved. Further, in order to reduce the plasma damage, a thermal CVD method, an MOCVD method or an ALD method is preferable.

  Subsequently, as illustrated in FIG. 12B, an opening is provided in the insulating film 113, the insulating film 112, the gate insulating film 102, the conductive layer 104a, the conductive layer 104b, the semiconductor layer 101b, the semiconductor layer 101a, and the insulating film 114. . Next, a conductive film is formed so as to fill the opening, and then an unnecessary portion is removed using a resist mask, and the resist mask is removed to form a plug 121 and a plug 122. Here, the plug 121 is formed to penetrate the insulating film 113, the insulating film 112, the gate insulating film 102, the semiconductor layer 101c, the conductive layer 104a, the semiconductor layer 101b, the semiconductor layer 101a, the insulating film 114, and the barrier film 111a. Connect with the layer 151. Here, the plug 121 and the conductive layer 104 a are connected by being in contact with the side surface of the plug 121. Similarly, the plug 122 is formed to penetrate the insulating film 113, the insulating film 112, the gate insulating film 102, the semiconductor layer 101c, the conductive layer 104b, the semiconductor layer 101b, the semiconductor layer 101a, the insulating film 114, and the barrier film 111a. The conductive layer 104 b is connected by being in contact with the side surface of the plug 122.

  Subsequently, the insulating film 116 is formed. The insulating film 116 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like, and is provided as a stacked layer or a single layer. The insulating film 116 can be formed by, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like. In the case of using an organic insulating material such as an organic resin as the insulating film 116, a coating method such as a spin coating method may be used. After the insulating film 116 is formed, planarization treatment is preferably performed on the top surface thereof. Alternatively, as the insulating film 116, a material or a formation method shown in the insulating film 138 may be used.

  Subsequently, the plug 123 and the like reaching the plug 122 are formed in the insulating film 116 by the same method as described above.

  Subsequently, a conductive film is formed over the insulating film 116. Thereafter, a resist mask is formed by the same method as described above, and unnecessary portions of the conductive film are removed by etching. After that, the wiring 124 and the like can be formed by removing the resist mask (see FIG. 12B).

  Through the above steps, the semiconductor device of one embodiment of the present invention can be manufactured.

  Note that in forming the semiconductor layer 101a and the semiconductor layer 101b, the conductive film 104 is formed and then a resist mask is formed, and after the conductive film 104 is etched, the semiconductor layer to be the semiconductor layer 101a and the semiconductor layer 101b are formed. The semiconductor layer may be formed by etching to have a structure illustrated in FIG. After that, the conductive film 104 is processed again to form a conductive layer 104a and a conductive layer 104b. Through the steps shown in FIGS. 12 to 13, the transistor 100 can have a structure as shown in FIG.

  Further, as an example of a method for manufacturing the transistor 100 having a structure different from that of the transistor 100 illustrated in FIG. 15B, an example of a method for manufacturing the transistor 100 in FIG. 1 is briefly described.

  First, a semiconductor film to be the semiconductor layer 101 is formed over the insulating film 114, a resist mask or the like is formed, and etching is performed to form the semiconductor layer 101. Next, an insulating film to be the gate insulating film 102 and a conductive film to be the gate electrode 103 are formed, a resist mask or the like is formed, and etching is performed to form the gate electrode 103 and the gate insulating film 102.

  Next, the low resistance region 171a and the low resistance region 171b are formed. The semiconductor layer with high carrier density has low resistance. Examples of methods for increasing the carrier density include the addition of impurities, the formation of oxygen vacancies, and the like. For example, as a method for increasing the carrier density, elements may be added using ion implantation. As an element which can be used, for example, argon, boron, carbon, magnesium, aluminum, silicon, phosphorus, calcium, scandium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, gallium, germanium, arsenic, yttrium, zirconium It is preferable to add one or more selected from niobium, molybdenum, indium, tin, lanthanum, cerium, neodymium, hafnium, tantalum and tungsten.

  In such a low resistance region, for example, unnecessary hydrogen may be able to be trapped. By trapping unnecessary hydrogen in the low resistance layer, the hydrogen concentration in the channel region can be lowered and good transistor characteristics can be obtained.

  Next, the insulating film 112 and the insulating film 113 are formed. Thereafter, the plug 121 and the plug 122 are formed by the method described above. Through the above steps, the transistor 100 illustrated in FIG. 1 can be manufactured.

Second Embodiment
In this embodiment, an oxide semiconductor which can be preferably used for the transistor 100 described in Embodiment 1 will be described.

  Here, as shown as an example in FIG. 6, an example in which three layers of a semiconductor layer 101a, a semiconductor layer 101b, and a semiconductor layer 101c are stacked and used as an oxide semiconductor is described; however, an oxide semiconductor that can be used for the transistor 100 May be a single layer. Alternatively, one or both of the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c may be omitted.

  The semiconductor layer 101 b is, for example, an oxide semiconductor containing indium. When the semiconductor layer 101 b contains, for example, indium, the carrier mobility (electron mobility) becomes high. The semiconductor layer 101 b preferably contains the element M. The element M is preferably aluminum, gallium, yttrium or tin. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and the like. However, as the element M, a plurality of the aforementioned elements may be combined in some cases. The element M is, for example, an element having a high binding energy to oxygen. For example, it is an element whose binding energy to oxygen is higher than that of indium. Alternatively, the element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. The semiconductor layer 101 b preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.

  However, the semiconductor layer 101 b is not limited to an oxide semiconductor containing indium. The semiconductor layer 101b may be, for example, an oxide semiconductor not containing indium but containing zinc, an oxide semiconductor containing gallium, an oxide semiconductor containing tin, or the like, such as zinc tin oxide or gallium tin oxide. .

  For example, an oxide with a large energy gap is used for the semiconductor layer 101b. The energy gap of the semiconductor layer 101b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more and 3.5 eV or less.

  For example, the semiconductor layer 101a and the semiconductor layer 101c are oxide semiconductors including one or more elements or two or more elements other than oxygen included in the semiconductor layer 101b. Since the semiconductor layer 101a and the semiconductor layer 101c are formed of one or more elements or two or more elements other than oxygen constituting the semiconductor layer 101b, the interface between the semiconductor layer 101a and the semiconductor layer 101b, and the semiconductor layer 101b and the semiconductor layer 101c An interface state is less likely to be formed at the interface with the

  The semiconductor layers 101a, 101b, and 101c preferably contain at least indium. Note that when the sum of In and M is 100 atomic% when the semiconductor layer 101a is an In-M-Zn oxide, preferably In is less than 50 atomic%, M is 50 atomic% or more, and more preferably In is less than 25 atomic%. , M is 75 atomic% or more. When the semiconductor layer 101 b is an In—M—Zn oxide, the sum of In and M is 100 atomic%, preferably 25 atomic% or more of In and less than 75 atomic% of M, more preferably 34 atomic% or more of In. , M is less than 66 atomic%. When the semiconductor layer 101c is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, preferably In is less than 50 atomic%, M is 50 atomic% or more, and more preferably In is less than 25 atomic%. , M is 75 atomic% or more. Note that an oxide of the same type as the semiconductor layer 101 a may be used for the semiconductor layer 101 c.

  The semiconductor layer 101 b uses an oxide having a larger electron affinity than the semiconductor layer 101 a and the semiconductor layer 101 c. For example, as the semiconductor layer 101b, the semiconductor layer 101a and the semiconductor layer 101c have an electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less Use large oxides. The electron affinity is the difference between the vacuum level and the energy at the lower end of the conduction band.

  Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the semiconductor layer 101 c contain indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

  At this time, when an electric field is applied to the gate electrode, a channel is formed in the semiconductor layer 101b having high electron affinity among the semiconductor layers 101a, 101b, and 101c.

  Here, a band structure is shown in FIG. FIG. 18A shows the vacuum level (denoted as vacuum level), the energy at the lower end of the conduction band of each layer (denoted Ec), and the energy at the upper end of the valence band (denoted Ev).

  Here, a mixed region of the semiconductor layer 101a and the semiconductor layer 101b may be provided between the semiconductor layer 101a and the semiconductor layer 101b. In addition, a mixed region of the semiconductor layer 101b and the semiconductor layer 101c may be provided between the semiconductor layer 101b and the semiconductor layer 101c. The mixed region has a low interface state density. Therefore, a stack of the semiconductor layer 101a, the semiconductor layer 101b, and the semiconductor layer 101c has a band structure in which energy changes continuously (also referred to as a continuous junction) in the vicinity of each interface.

  Although FIG. 18A shows the case where the Ec of the semiconductor layer 101a and the second semiconductor layer 101c are the same, they may be different. For example, Ec of the semiconductor layer 101c may have higher energy than the semiconductor layer 101a.

  At this time, electrons move mainly in the semiconductor layer 101b, not in the semiconductor layer 101a and the semiconductor layer 101c (see FIG. 18B). As described above, by lowering the interface state density at the interface between the semiconductor layer 101a and the semiconductor layer 101b and the interface state density at the interface between the semiconductor layer 101b and the semiconductor layer 101c, electrons move in the semiconductor layer 101b. It is less disturbed, and the on current of the transistor can be increased.

  Note that when the transistor has an s-channel structure, a channel is formed in the entire semiconductor layer 101 b. Therefore, the thicker the semiconductor layer 101b, the larger the channel region. That is, as the semiconductor layer 101 b is thicker, the on-state current of the transistor can be increased. For example, the semiconductor layer 101b may have a region with a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, more preferably 100 nm or more. However, since the productivity of the semiconductor device may be reduced, for example, the semiconductor layer 101b may have a region with a thickness of 300 nm or less, preferably 200 nm or less, more preferably 150 nm or less.

  In order to increase the on current of the transistor, the smaller the thickness of the semiconductor layer 101c, the better. For example, the semiconductor layer 101c may have a region of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less. On the other hand, the semiconductor layer 101c has a function of blocking entry of an element (such as hydrogen or silicon) other than oxygen which forms an adjacent insulator into the semiconductor layer 101b in which a channel is formed. Therefore, the semiconductor layer 101 c preferably has a certain thickness. For example, the semiconductor layer 101c may have a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more. The semiconductor layer 101 c preferably has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulating film 102 or the like.

  Further, in order to increase the reliability, it is preferable that the semiconductor layer 101 a be thick and the semiconductor layer 101 c be thin. For example, the semiconductor layer 101a may have a region with a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, more preferably 60 nm or more. By increasing the thickness of the semiconductor layer 101a, the distance from the interface between the adjacent insulator and the semiconductor layer 101a to the semiconductor layer 101b in which a channel is formed can be increased. However, since the productivity of the semiconductor device may be reduced, for example, the semiconductor layer 101a may have a region with a thickness of 200 nm or less, preferably 120 nm or less, more preferably 80 nm or less.

  When the oxide semiconductor film contains a large amount of hydrogen, part of the hydrogen serves as a donor by bonding with the oxide semiconductor, and an electron which is a carrier is generated. Thus, the threshold voltage of the transistor is shifted in the negative direction. Therefore, after formation of the oxide semiconductor film, dehydration treatment (dehydrogenation treatment) is performed to remove hydrogen or moisture from the oxide semiconductor film and to highly purify the oxide semiconductor film so that impurities are not contained as much as possible. preferable.

  Note that oxygen may also be reduced from the oxide semiconductor film at the same time due to dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film. Therefore, in order to compensate for oxygen vacancies increased by dehydration treatment (dehydrogenation treatment) of the oxide semiconductor film, treatment for adding oxygen to the oxide is preferably performed. In this specification and the like, the case where oxygen is supplied to the oxide semiconductor film may be referred to as an oxygenation treatment, or the case where the amount of oxygen contained in the oxide semiconductor film is greater than the stoichiometric composition is described. It may be referred to as peroxygenation treatment.

Thus, the oxide semiconductor film is i-type (intrinsic) or i-type by removing hydrogen or moisture by dehydration treatment (dehydrogenation treatment) and compensating oxygen deficiency by oxygenation treatment. An oxide semiconductor film that is substantially i-type (intrinsic) can be formed as close as possible. Note that substantially intrinsic means that the number of carriers derived from donors in the oxide semiconductor film is very small (near zero), the carrier density is 1 × 10 ¹⁷ / cm ³ or less, 1 × 10 ¹⁶ / cm ³ or less, It is 1 × 10 ¹⁵ / cm ³ or less, 1 × 10 ¹⁴ / cm ³ or less, 1 × 10 ¹³ / cm ³ or less, particularly preferably 8 × 10 ¹¹ / cm ^{3 or} less, more preferably 1 × 10 ¹¹ / cm ³ It is less than 1 × 10 ¹⁰ / cm ³ and preferably 1 × 10 ⁻⁹ / cm ³ or more.

Further, as described above, the transistor including the i-type or substantially i-type oxide semiconductor film can achieve extremely excellent off-state current characteristics. For example, the drain current when the transistor including the oxide semiconductor film is off is 1 × 10 ⁻¹⁸ A or less, preferably 1 × 10 ⁻²¹ A or less, more preferably 1 at room temperature (approximately 25 ° C.). × ^{10 -24} a or less, or 1 × ^{10 -15} a or less at 85 ° C., preferably 1 × ^{10 -18} a or less, more preferably to less 1 × ^{10 -21} a. Note that, in the case of an n-channel transistor, the off state of the transistor refers to a state in which the gate voltage is sufficiently smaller than the threshold voltage. Specifically, when the gate voltage is smaller than the threshold voltage by 1 V or more, 2 V or more, or 3 V or more, the transistor is turned off.

  The structure of the oxide semiconductor film is described below.

  The oxide semiconductor film can be divided into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. Alternatively, an oxide semiconductor can be divided into, for example, a crystalline oxide semiconductor and an amorphous oxide semiconductor. The non-single-crystal oxide semiconductor film includes a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like. In addition, as a crystalline oxide semiconductor, a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, or the like can be given.

  First, a CAAC-OS film is described. Note that the CAAC-OS can also be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals).

  The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis-oriented crystal parts (also referred to as pellets).

  When a composite analysis image (also referred to as a high resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed by a transmission electron microscope (TEM) on a CAAC-OS film, a plurality of pellets are confirmed can do. On the other hand, in the high resolution TEM image, the boundaries between the pellets, that is, the grain boundaries (also referred to as grain boundaries) can not be clearly identified. Therefore, it can be said that the CAAC-OS film is unlikely to cause a decrease in electron mobility due to crystal grain boundaries.

  When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape (also referred to as a formation surface) on which the CAAC-OS film is to be formed (also referred to as a formation surface) or a shape reflecting the unevenness of the top surface, and is arranged parallel to the formation surface or top surface of the CAAC-OS film .

  On the other hand, when the CAAC-OS film is observed by a TEM in a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in a crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

  FIG. 19A is a cross-sectional TEM image of the CAAC-OS film. FIG. 19 (b) is a cross-sectional TEM image obtained by further enlarging FIG. 19 (a), and the atomic arrangement is highlighted to facilitate understanding.

  FIG. 19C is a local Fourier transform image of a circled area (about 4 nm in diameter) between AO and A ′ in FIG. From FIG. 19 (c), c-axis alignment can be confirmed in each region. In addition, the directions of the c-axis are different between A-O and O-A ', which suggests different grains. In addition, it can be seen that, between A and O, the angle of the c-axis continuously changes little by little, such as 14.3 °, 16.6 °, and 26.4 °. Similarly, it can be seen that the angle of the c-axis continuously changes little by little, such as -18.3 °, -17.6 °, and -15.9 °, between O-A '.

  Note that when electron diffraction is performed on the CAAC-OS film, spots (bright spots) showing orientation are observed. For example, when electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam of, for example, 1 nm to 30 nm is performed on the top surface of the CAAC-OS film, spots are observed (see FIG. 20A).

  From the cross-sectional TEM observation and the planar TEM observation, it is found that the crystal part of the CAAC-OS film has orientation.

Note that most of the crystal parts included in the CAAC-OS film each fit inside a cube whose one side is less than 100 nm. Therefore, the crystal part included in the CAAC-OS film is also included in the case where the side is smaller than 10 nm, smaller than 5 nm, or smaller than 3 nm. However, a plurality of crystal parts included in the CAAC-OS film may be connected to form one large crystal region. For example, in a planar TEM image, a crystalline region with a size of 2500 nm ² or more, 5 μm ² or more, or 1000 μm ² or more may be observed.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis points in a direction substantially perpendicular to the formation surface or the top surface. It can be confirmed that

On the other hand, in the analysis by the in-plane method in which X-rays are incident on the CAAC-OS film in a direction substantially perpendicular to the c-axis, a peak may appear in the vicinity of 56 ° in 2θ. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of an InGaZnO ₄ single crystal oxide semiconductor film, analysis (φ scan) is performed while fixing 2θ at around 56 ° and rotating the sample with the normal vector of the sample surface as the axis (φ axis), Six peaks attributed to crystal planes equivalent to the 110) plane are observed. On the other hand, in the case of the CAAC-OS film, a clear peak does not appear even when φ scan is performed with 2θ fixed at around 56 °.

  From the above, in the CAAC-OS film, the orientation of the a-axis and the b-axis is irregular between different crystal parts, but the c-axis has c-axis orientation and the c-axis is a normal to the formation surface or the top surface It turns out that it is pointing in the direction parallel to the vector. Therefore, each layer of the metal atoms arranged in a layer, which is confirmed by the above-mentioned cross-sectional TEM observation, is a plane parallel to the ab plane of the crystal.

  Note that the crystal part is formed when a CAAC-OS film is formed or when crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formation surface or the top surface of the CAAC-OS film.

  In the CAAC-OS film, distribution of c-axis aligned crystal parts is not necessarily uniform. For example, in the case where a crystal part of a CAAC-OS film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, the ratio of c-axis aligned regions in the region near the top surface is higher than the region near the formation surface Can be high. Further, in the case of the CAAC-OS film to which the impurity is added, the region to which the impurity is added may be altered to form a region in which the ratio of crystal parts in which c-axis alignment is partially different is different.

Note that in the analysis by a out-of-plane method of a CAAC-OS film having an InGaZnO ₄ crystal, in addition to the peak at 2θ of around 31 °, the peak may also appear at around 36 ° of 2θ. The peak at 2θ of around 36 ° indicates that a part of the CAAC-OS film contains a crystal having no c-axis alignment. It is preferable that the CAAC-OS film has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

  The CAAC-OS film is an oxide semiconductor film with low impurity concentration. The impurity is an element other than the main components of the oxide semiconductor film such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon having a stronger bonding force with oxygen than a metal element constituting the oxide semiconductor film disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, thereby causing crystallinity Cause a decrease in In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radius (or molecular radius), and therefore, if contained within the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed and crystallinity Cause a decrease in Note that an impurity contained in the oxide semiconductor film may be a carrier trap or a carrier generation source.

  The CAAC-OS film is an oxide semiconductor film with low density of defect states. For example, oxygen vacancies in the oxide semiconductor film may be carrier traps or may be a carrier generation source by capturing hydrogen.

  A low impurity concentration and a low density of defect levels (less oxygen vacancies) are referred to as high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film can reduce carrier density because there are few carriers. Thus, a transistor including the oxide semiconductor film rarely has negative threshold voltage (also referred to as normally on). In addition, the highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Thus, the transistor including the oxide semiconductor film has small variation in electrical characteristics and is highly reliable. Note that the charge trapped in the carrier trap in the oxide semiconductor film may take a long time to be released and behave as if it were fixed charge. Therefore, in the transistor including the oxide semiconductor film, which has a high impurity concentration and a high density of defect states, electrical characteristics may be unstable.

  In addition, a transistor including the CAAC-OS film has less variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

FIG. 36A shows a high-resolution TEM image of a cross section of a CAAC-OS observed from a direction substantially parallel to the sample surface. A spherical aberration correction function was used to observe a high resolution TEM image. A high resolution TEM image using a spherical aberration correction function is particularly called a Cs corrected high resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained, for example, by an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL.

A Cs corrected high resolution TEM image obtained by enlarging the region (1) of FIG. 36 (A) is shown in FIG. 36 (B). From FIG. 36 (B), it can be confirmed in the pellet that the metal atoms are arranged in layers. The arrangement of metal atoms in each layer reflects the unevenness of the surface (also referred to as a formation surface) or the top surface of the CAAC-OS film, which is parallel to the formation surface or the top surface of the CAAC-OS.

As shown in FIG. 36B, the CAAC-OS has a characteristic atomic arrangement. FIG. 36C shows a characteristic atomic arrangement by auxiliary lines. From FIG. 36 (B) and FIG. 36 (C), it is understood that the size of one pellet is about 1 nm or more and 3 nm or less, and the size of the gap generated by the inclination of the pellet and the pellet is about 0.8 nm. Therefore, the pellet can also be called nanocrystal (nc: nanocrystal).

Here, the arrangement of pellets 5100 of CAAC-OS on the substrate 5120 is schematically shown based on a Cs-corrected high-resolution TEM image, resulting in a structure in which bricks or blocks are stacked (FIG. 36D). reference.). The portion where inclination occurs between the pellet and the pellet observed in FIG. 36C corresponds to a region 5161 shown in FIG. 36D.

FIG. 37A shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface. 37 (B), 37 (C) and 37 (D) respectively show enlarged Cs-corrected high-resolution TEM images of region (1), region (2) and region (3) of FIG. 37 (A). Show. From FIG. 37 (B), FIG. 37 (C) and FIG. 37 (D), it can be confirmed that in the pellet, metal atoms are arranged in a triangular shape, a square shape or a hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when structural analysis by an out-of-plane method is performed on a CAAC-OS having an InGaZnO ₄ crystal, a peak appears in the vicinity of 31 ° of the diffraction angle (2θ) as shown in FIG. 38A. There is. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis points in a direction substantially perpendicular to the formation surface or upper surface Can be confirmed.

Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when 2θ is around 36 °, in addition to the peak at 2θ of around 31 °. The peak at 2θ of around 36 ° indicates that a part of the CAAC-OS contains a crystal having no c-axis alignment. More preferable CAAC-OS shows a peak at 2θ of around 31 ° and no peak at 2θ of around 36 ° in structural analysis by the out-of-plane method.

On the other hand, when structural analysis by an in-plane method in which X-rays are incident on the CAAC-OS in a direction substantially perpendicular to the c-axis, a peak appears at around 56 ° in 2θ. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of CAAC-OS, even if analysis (φ scan) is performed while rotating the sample with the 2θ fixed at around 56 ° and the normal vector of the sample surface as the axis (φ axis), FIG. No clear peaks appear as shown. On the other hand, in the case of a single crystal oxide semiconductor of InGaZnO ₄ , when 2θ is fixed at around 56 ° and φ scan is performed, as shown in FIG. 38C, it belongs to a crystal plane equivalent to the (110) plane. 6 peaks are observed. Therefore, from structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular alignment in the a-axis and b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident in parallel to the sample surface with respect to a CAAC-OS having a crystal of InGaZnO ₄ , a diffraction pattern as shown in FIG. Say) may appear. The diffraction pattern includes spots originating from the (009) plane of the InGaZnO ₄ crystal. Therefore, it is also understood by electron diffraction that the pellets contained in the CAAC-OS have c-axis alignment, and the c-axis points in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 39 (B) shows a diffraction pattern when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 39 (B), a ring-like diffraction pattern is confirmed. Therefore, it is also understood by electron diffraction that the a-axis and b-axis of the pellet contained in the CAAC-OS have no orientation. Note that the first ring in FIG. 39B is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO ₄ crystal. The second ring in FIG. 39B is considered to be derived from the (110) plane and the like.

  Next, a polycrystalline oxide semiconductor film is described.

  In the polycrystalline oxide semiconductor film, crystal grains can be confirmed by an observation image by TEM. For example, a crystal grain included in the polycrystalline oxide semiconductor film often has a particle diameter of 2 nm to 300 nm, 3 nm to 100 nm, or 5 nm to 50 nm in an observation image by TEM. In addition, in a polycrystalline oxide semiconductor film, crystal grain boundaries may be confirmed in some cases by an observation image by TEM.

The polycrystalline oxide semiconductor film may have a plurality of crystal grains, and the crystal orientation may be different between the plurality of crystal grains. Further, when structural analysis is performed on the polycrystalline oxide semiconductor film using an XRD apparatus, for example, in the analysis of the polycrystalline oxide semiconductor film having an InGaZnO ₄ crystal by an out-of-plane method, 2θ is 31 °. A nearby peak, a peak at 2θ of around 36 °, or another peak may appear.

  Since a polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Thus, a transistor including a polycrystalline oxide semiconductor film has high field-effect mobility. However, in the polycrystalline oxide semiconductor film, impurities may be segregated at grain boundaries. In addition, crystal grain boundaries in the polycrystalline oxide semiconductor film become defect states. A crystal grain boundary may be a carrier trap or a carrier generation source in a polycrystalline oxide semiconductor film; therefore, a transistor using a polycrystalline oxide semiconductor film is more electrically than a transistor using a CAAC-OS film. In some cases, the transistor has a large fluctuation in characteristics and low reliability.

  Next, a microcrystalline oxide semiconductor film is described.

  In a microcrystalline oxide semiconductor film, in some cases, a crystal part can not be clearly confirmed in an observation image by TEM. The crystal part included in the microcrystalline oxide semiconductor film often has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having a nanocrystal (nc: nanocrystal) which is a fine crystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline oxide semiconductor) film. In addition, in the case of an nc-OS film, for example, an observation image by TEM may not clearly confirm the grain boundaries. Note that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, the crystal part of nc-OS may be called a pellet below.

  The nc-OS film has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, in the nc-OS film, regularity is not observed in crystal orientation between different crystal parts. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS film may not be distinguished from the amorphous oxide semiconductor film depending on the analysis method. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus using an X-ray having a diameter larger than that of a crystal part (pellet), a peak showing a crystal plane is an analysis by an out-of-plane method. Not detected. In addition, when electron diffraction (also referred to as limited field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the pellet is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Ru. On the other hand, spots are observed when nanobeam electron diffraction is performed on the nc-OS film using an electron beam with a probe diameter close to or smaller than the pellet size. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance (in a ring shape) may be observed in a circular manner (in a ring shape). Furthermore, a plurality of spots may be observed in the ring-shaped region (see FIG. 20B).

Thus, nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals) or NANC (Non-Aligned nanocrystals) because crystal orientation does not have regularity among pellets (nanocrystals). It can also be called an oxide semiconductor.

  The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than an amorphous oxide semiconductor film. However, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

  Therefore, the carrier density of the nc-OS film may be higher than that of the CAAC-OS film. In the case of an oxide semiconductor film with high carrier density, electron mobility may be high. Thus, a transistor using an nc-OS film may have high field-effect mobility. In addition, since the nc-OS film has a higher density of defect states than the CAAC-OS film, carrier traps may be increased. Therefore, a transistor using an nc-OS film has a large variation in electrical characteristics and low reliability as compared to a transistor using a CAAC-OS film. However, since the nc-OS film can be formed even if it contains a relatively large amount of impurities, it can be more easily formed than the CAAC-OS film, and may be suitably used depending on the application. Therefore, a semiconductor device including a transistor using an nc-OS film may be manufactured with high productivity.

  Next, an amorphous oxide semiconductor film is described.

  The amorphous oxide semiconductor film is an oxide semiconductor film in which the atomic arrangement in the film is irregular and does not have a crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

  In the case of an amorphous oxide semiconductor film, a crystal part can not be confirmed by an observation image by TEM.

  When structural analysis is performed on an amorphous oxide semiconductor film using an XRD apparatus, a peak indicating a crystal plane is not detected in analysis by the out-of-plane method. In addition, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. In addition, when nanobeam electron diffraction is performed on the amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

  The amorphous oxide semiconductor film is an oxide semiconductor film containing an impurity such as hydrogen at a high concentration. The amorphous oxide semiconductor film is an oxide semiconductor film with a high density of defect states.

  An oxide semiconductor film which has a high impurity concentration and a high density of defect states is an oxide semiconductor film which has many carrier traps and a plurality of carrier generation sources.

  Therefore, the carrier density of the amorphous oxide semiconductor film may be higher than that of the nc-OS film. Therefore, a transistor including an amorphous oxide semiconductor film is likely to be normally on. Therefore, it may be suitably used for a transistor for which normally-on electrical characteristics are required. Since the amorphous oxide semiconductor film has a high density of defect states, carrier traps may be increased. Accordingly, a transistor including an amorphous oxide semiconductor film has large variation in electrical characteristics and low reliability as compared to a transistor including a CAAC-OS film or an nc-OS film.

  Note that the oxide semiconductor film may have a structure which shows physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film.

  In the a-like OS film, wrinkles (also referred to as voids) may be observed in a high resolution TEM image. Further, the high resolution TEM image has a region where the crystal part can be clearly confirmed and a region where the crystal part can not be confirmed. The a-like OS film may undergo crystallization due to a slight amount of electron irradiation as observed by TEM, and growth of a crystal part may be observed. On the other hand, in the case of a high-quality nc-OS film, crystallization by a slight amount of electron irradiation for observation by TEM is hardly observed.

Note that the size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high resolution TEM image. For example, the crystal of InGaZnO ₄ has a layered structure, and has two Ga—Zn—O layers between the In—O layers. The unit cell of the InGaZnO ₄ crystal has a structure in which nine layers of three In—O layers and six Ga—Zn—O layers are layered in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) in the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice in the high resolution TEM image, each lattice corresponds to the a-b plane of the InGaZnO ₄ crystal in a portion where the lattice spacing is 0.28 nm or more and 0.30 nm or less.

Because it has wrinkles, a-like OS is an unstable structure. In the following, a change in structure due to electron irradiation is shown to indicate that the a-like OS has an unstable structure compared to the CAAC-OS and the nc-OS.

As samples to be subjected to electron irradiation, a-like OS (denoted as sample A), nc-OS (denoted as sample B), and CAAC-OS (denoted as sample C) are prepared. All samples are In-Ga-Zn oxides.

First, a high resolution cross-sectional TEM image of each sample is acquired. The high-resolution cross-sectional TEM image shows that each sample has a crystal part.

Note that which part is regarded as one crystal part may be determined as follows. For example, the unit cell of the InGaZnO ₄ crystal has a structure in which a total of nine layers are layered in the c-axis direction, having three In—O layers and six Ga—Zn—O layers. Are known. The distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) in the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, a portion where the lattice spacing is 0.28 nm or more and 0.30 nm or less can be regarded as the InGaZnO ₄ crystal part. The checkered pattern corresponds to the a-b plane of the InGaZnO ₄ crystal.

FIG. 40 shows an example in which the average size of crystal parts (at 22 points to 45 points) of each sample was investigated. However, the length of the checkered pattern described above is the size of the crystal part. From FIG. 40, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative irradiation dose of electrons. Specifically, as shown by (1) in FIG. 40, a crystal part (also referred to as an initial nucleus) having a size of about 1.2 nm at the initial stage of observation by TEM has a cumulative irradiation amount of 4.2. It can be seen that the crystal is grown to a size of about 2.6 nm at 10 ⁸ e ⁻ / nm ² . On the other hand, in the nc-OS and CAAC-OS, no change in the size of the crystal part is observed in the range of the cumulative irradiation dose of electrons from the start of the electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ² I understand. Specifically, as shown by (2) and (3) in FIG. 40, the size of the crystal part of nc-OS and CAAC-OS is about 1.4 nm regardless of the cumulative irradiation dose of electrons. And about 2.1 nm.

Thus, in the a-like OS, crystal growth may be observed due to electron irradiation. On the other hand, it can be seen that in the nc-OS and the CAAC-OS, almost no growth of crystal parts due to electron irradiation is observed. That is, it can be seen that the a-like OS has an unstable structure as compared to the nc-OS and the CAAC-OS.

In addition, because of having wrinkles, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition. Further, the density of nc-OS and the density of CAAC-OS are 92.3% to less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor which is less than 78% of the density of a single crystal.

  In addition, the density of the oxide semiconductor film may be different depending on the structure. For example, when the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparison with the density of single crystals in the same composition as the composition. For example, the density of the a-like OS film is 78.6% to less than 92.3% with respect to the density of single crystals. Further, for example, the density of the nc-OS film and the density of the CAAC-OS film are greater than or equal to 92.3% and less than 100% with respect to the density of single crystals. Note that it is difficult to form an oxide semiconductor film whose density is less than 78% of the density of single crystals.

The above will be described using a specific example. For example, in the oxide semiconductor film which satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral crystal structure is 6.357 g / cm ³ . Thus, for example, In: Ga: Zn = 1 : 1: 1 in the oxide semiconductor film which satisfies the atomic ratio, the density of a-like OS film 5.0 g / cm ³ or more 5.9 g / cm less than ³ It becomes. For example, in the case of an oxide semiconductor film with an atomic ratio of In: Ga: Zn = 1: 1: 1, the density of the nc-OS film and the density of the CAAC-OS film are 5.9 g / cm ³ or more. Less than ³ g / cm ³ .

  In addition, the single crystal of the same composition may not exist. In that case, the density corresponding to the single crystal of a desired composition can be calculated by combining single crystals having different compositions at an arbitrary ratio. The density of single crystals having a desired composition may be calculated using a weighted average with respect to the ratio of combining single crystals having different compositions. However, it is preferable to calculate the density by combining as few types of single crystals as possible.

  Next, a single crystal oxide semiconductor film is described.

  The single crystal oxide semiconductor film is an oxide semiconductor film which has a low impurity concentration and a low density of defect states (there are few oxygen vacancies). Therefore, the carrier density can be lowered. Therefore, a transistor including a single crystal oxide semiconductor film rarely has an electrical characteristic of normally on. Further, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, carrier traps may be reduced in some cases. Therefore, a transistor including a single crystal oxide semiconductor film has small variation in electrical characteristics and is highly reliable.

  Note that the density of the oxide semiconductor film increases as the number of defects decreases. Further, the oxide semiconductor film has a high density when the crystallinity is high. Further, the density of the oxide semiconductor film is increased when the concentration of impurities such as hydrogen is low. The single crystal oxide semiconductor film has a higher density than the CAAC-OS film. In addition, the CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. In addition, the polycrystalline oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. Further, the microcrystalline oxide semiconductor film has a higher density than the amorphous oxide semiconductor film.

  Note that the oxide semiconductor film may be, for example, a stacked film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film.

<Film formation model>
Hereinafter, an example of a deposition model of a CAAC-OS and an nc-OS will be described.

FIG. 41A is a schematic view of a deposition chamber, which shows a CAAC-OS film formed by a sputtering method.

The target 5130 is bonded to the backing plate. A plurality of magnets are disposed at positions facing the target 5130 via the backing plate. A magnetic field is generated by the plurality of magnets. The sputtering method for increasing the deposition rate using the magnetic field of the magnet is called magnetron sputtering.

The substrate 5120 is disposed to face the target 5130, and the distance d (also referred to as target-substrate distance (distance between T and S)) is 0.01 m to 1 m, preferably 0.02 m to 0 .5 m or less. Most of the deposition chamber is filled with a deposition gas (for example, oxygen, argon, or a mixed gas containing 5% by volume or more of oxygen), and is 0.01 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less Controlled by Here, discharge is started by applying a predetermined voltage or more to the target 5130, and a plasma is confirmed. A high density plasma region is formed in the vicinity of the target 5130 by the magnetic field. In the high density plasma region, the film formation gas is ionized to generate ions 5101. The ion 5101 is, for example, a cation of oxygen (O ⁺ ) or a cation of argon (Ar ⁺ ).

Here, the target 5130 has a polycrystalline structure having a plurality of crystal grains, and one of the crystal grains includes a cleavage plane. FIG. 42A shows, as an example, a structure of an InGaZnO ₄ crystal included in the target 5130. FIG. 42A shows a structure when the InGaZnO ₄ crystal is observed from the direction parallel to the b-axis. From FIG. 42 (A), it can be seen that oxygen atoms in each of the two adjacent Ga—Zn—O layers are arranged in a short distance. And, since the oxygen atom has a negative charge, a repulsive force is generated between two adjacent Ga-Zn-O layers. As a result, the InGaZnO ₄ crystal has a cleavage plane between two adjacent Ga—Zn—O layers.

The ions 5101 generated in the high density plasma region are accelerated to the target 5130 side by the electric field and eventually collide with the target 5130. At this time, pellets 5100 a and pellets 5100 b which are flat plate-like or pellet-like sputtered particles are peeled off from the cleavage plane and struck out. The pellets 5100 a and 5100 b may be distorted in structure due to the impact of the collision of the ions 5101.

The pellet 5100a is a flat or pellet-like sputtered particle having a triangle, for example, a plane of an equilateral triangle. The pellet 5100 b is a flat plate-like or pellet-like sputtered particle having a hexagonal, for example, a regular hexagonal plane. Note that flat-plate-like or pellet-like sputtered particles such as pellets 5100 a and pellets 5100 b are collectively referred to as pellets 5100. The shape of the plane of the pellet 5100 is not limited to a triangle or a hexagon, for example, it may be a shape in which a plurality of triangles are combined. For example, it may be a quadrangle (e.g., a rhombus) in which two triangles (e.g., an equilateral triangle) are combined.

The thickness of the pellet 5100 is determined according to the type of deposition gas and the like. Although the reason will be described later, the thickness of the pellet 5100 is preferably uniform. In addition, it is preferable that the sputtered particles be in the form of a thin pellet rather than in the form of a thick die. For example, the pellet 5100 has a thickness of 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. Further, for example, the pellet 5100 has a width of 1 nm to 3 nm, preferably 1.2 nm to 2.5 nm. The pellet 5100 corresponds to the initial nucleus described in (1) in FIG. 40 described above. For example, when an ion 5101 is made to collide with a target 5130 having an In—Ga—Zn oxide, as shown in FIG. 42B, the Ga—Zn—O layer, the In—O layer, and the Ga—Zn—O layer The pellet 5100 having three layers peels off. FIG. 42C shows a structure in which the peeled pellet 5100 is observed from the direction parallel to the c-axis. The pellet 5100 can also be referred to as a nano-sized sandwich structure having two Ga-Zn-O layers (pans) and an In-O layer (instrument).

The pellet 5100 may be negatively or positively charged on its side when passing through the plasma. The pellet 5100 may, for example, be negatively charged with oxygen atoms located on the side. When the side surfaces have charges of the same polarity, repulsion between the charges occurs and it becomes possible to maintain a flat or pellet shape. Note that in the case where the CAAC-OS is an In—Ga—Zn oxide, an oxygen atom bonded to an indium atom may be negatively charged. Alternatively, an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom may be negatively charged. In addition, the pellet 5100 may grow by being bonded to an indium atom, a gallium atom, a zinc atom, an oxygen atom, or the like in plasma when passing through the plasma. The difference between the sizes of (2) and (1) in FIG. 40 described above corresponds to the growth in plasma. Here, when the substrate 5120 is at about room temperature, growth of the pellet 5100 on the substrate 5120 is difficult to occur, and thus nc-OS is obtained (see FIG. 41B). Since deposition can be performed at around room temperature, deposition of nc-OS is possible even when the substrate 5120 has a large area. Note that in order to grow the pellet 5100 in plasma, it is effective to increase deposition power in the sputtering method. By increasing the deposition power, the structure of the pellet 5100 can be stabilized.

As shown in FIGS. 41 (A) and 41 (B), for example, the pellet 5100 flies in the plasma like a scoop and flutters up onto the substrate 5120. Since the pellet 5100 is charged, repulsion occurs when the area where other pellets 5100 have already been deposited approaches. Here, on the top surface of the substrate 5120, a magnetic field (also referred to as a horizontal magnetic field) parallel to the top surface of the substrate 5120 is generated. Further, since a potential difference is given between the substrate 5120 and the target 5130, a current flows in a direction from the substrate 5120 toward the target 5130. Therefore, the pellet 5100 receives force (Lorentz force) on the upper surface of the substrate 5120 by the action of the magnetic field and the current. This can be understood by Fleming's left-hand rule.

The pellet 5100 has a large mass compared to one atom. Therefore, in order to move the upper surface of the substrate 5120, it is important to apply some kind of force from the outside. One of the forces may be the force generated by the action of the magnetic field and the current. Note that in order to give the pellet 5100 sufficient force to move the upper surface of the substrate 5120, the magnetic field parallel to the upper surface of the substrate 5120 on the upper surface of the substrate 5120 is 10 G or more, preferably 20 G or more, more preferably It is preferable to provide a region of 30 G or more, more preferably 50 G or more. Alternatively, on the upper surface of the substrate 5120, the magnetic field in the direction parallel to the upper surface of the substrate 5120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more the magnetic field in the direction perpendicular to the upper surface of the substrate 5120. It is preferable to provide a region which is more preferably five times or more.

At this time, the orientation of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change due to relative movement or rotation of the magnet and the substrate 5120. Thus, on the top surface of the substrate 5120, the pellets 5100 can receive force from various directions and move in various directions.

When the substrate 5120 is heated as shown in FIG. 41A, the resistance due to friction or the like is small between the pellet 5100 and the substrate 5120. As a result, the pellet 5100 moves to glide on the top surface of the substrate 5120. The movement of the pellet 5100 occurs with the flat surface facing the substrate 5120. After that, when the side surfaces of the other pellets 5100 already deposited are reached, the side surfaces are bonded to each other. At this time, oxygen atoms at the side of the pellet 5100 are released. Since oxygen vacancies in the CAAC-OS may be filled with the released oxygen atom, the CAAC-OS with a low density of defect states is obtained. Note that the temperature of the top surface of the substrate 5120 may be, for example, 100 ° C. or more and less than 500 ° C., 150 ° C. or more and less than 450 ° C., or 170 ° C. or more and less than 400 ° C. Therefore, deposition of a CAAC-OS is possible even when the substrate 5120 has a large area.

In addition, the pellet 5100 is heated on the substrate 5120 to rearrange atoms, and the distortion of the structure caused by the collision of the ions 5101 is alleviated. The strain-relieved pellet 5100 is almost single crystal. Since the pellets 5100 are almost single crystals, expansion and contraction of the pellets 5100 itself can hardly occur even if the pellets 5100 are combined and then heated. Therefore, a defect such as a grain boundary is formed by widening the gap between the pellets 5100, and the crevice formation does not occur.

In addition, in the CAAC-OS, a single crystal oxide semiconductor is not formed like a single plate, but an array of pellets 5100 (nanocrystals) is arranged as if bricks or blocks are stacked. In addition, there is no grain boundary between the pellets 5100. Therefore, even when deformation such as contraction occurs in the CAAC-OS by heating during film formation, heating or bending after film formation, or the like, local stress can be relieved or strain can be released. Therefore, the structure is suitable for use in a flexible semiconductor device. Note that nc-OS has an arrangement in which pellets 5100 (nanocrystals) are randomly stacked.

When the target 5130 is sputtered with the ions 5101, not only the pellet 5100 but also zinc oxide or the like may be peeled off. Since zinc oxide is lighter than the pellet 5100, it first reaches the top surface of the substrate 5120. Then, a zinc oxide layer 5102 having a thickness of 0.1 nm to 10 nm, 0.2 nm to 5 nm, or 0.5 nm to 2 nm is formed. FIG. 43 shows a schematic cross-sectional view.

As shown in FIG. 43 (A), pellets 5105 a and pellets 5105 b are deposited on the zinc oxide layer 5102. Here, the pellet 5105 a and the pellet 5105 b are disposed such that the side surfaces are in contact with each other. In addition, the pellet 5105 c deposits on the pellet 5105 b and then slides on the pellet 5105 b. In addition, on another side surface of the pellet 5105 a, a plurality of particles 5103 separated from the target together with zinc oxide are crystallized by heating from the substrate 5120 to form a region 5105 a 1. Note that the plurality of particles 5103 may contain oxygen, zinc, indium, gallium, and the like.

Then, as shown in FIG. 43B, the region 5105a1 is integrated with the pellet 5105a to form a pellet 5105a2. In addition, the pellet 5105 c is disposed so that the side surface thereof is in contact with another side surface of the pellet 5105 b.

Next, as shown in FIG. 43C, the pellet 5105d is further deposited on the pellet 5105a2 and the pellet 5105b, and then moved so as to slide on the pellet 5105a2 and the pellet 5105b. Also, toward the other side of the pellet 5105c, the pellet 5105e further slides on the zinc oxide layer 5102.

Then, as shown in FIG. 43D, the pellet 5105 d is disposed such that the side surface thereof is in contact with the side surface of the pellet 5105 a 2. In addition, the pellet 5105 e is disposed such that the side surface of the pellet 5105 e is in contact with another side surface of the pellet 5105 c. In addition, in another side surface of the pellet 5105 d, a plurality of particles 5103 separated from the target 5130 together with zinc oxide are crystallized by heating from the substrate 5120 to form a region 5105 d 1.

As described above, the deposited pellets are arranged to be in contact with each other, and growth occurs on the side surfaces of the pellets, whereby a CAAC-OS is formed over the substrate 5120. Therefore, CAAC-OS has larger pellets than nc-OS. The difference in size between (3) and (2) in FIG. 40 described above corresponds to the growth after deposition.

In addition, when the gap between the pellets is extremely small, one large pellet may be formed. One large pellet has a single crystal structure. For example, the size of the pellet may be 10 nm to 200 nm, 15 nm to 100 nm, or 20 nm to 50 nm as viewed from the top. At this time, in an oxide semiconductor used for a minute transistor, a channel formation region may be contained in one large pellet. That is, a region having a single crystal structure can be used as a channel formation region. In addition, when the pellet is enlarged, a region having a single crystal structure may be used as a channel formation region, a source region, and a drain region of the transistor in some cases.

As described above, when the channel formation region of the transistor or the like is formed in the region having a single crystal structure, the frequency characteristics of the transistor can be increased in some cases.

It is considered that the pellet 5100 is deposited on the substrate 5120 according to the model as described above. Even in the case where the formation surface does not have a crystal structure, deposition of a CAAC-OS is possible, which indicates that the growth mechanism is different from epitaxial growth. In addition, CAAC-OS does not require laser crystallization, and uniform film formation is possible even with a large-area glass substrate or the like. For example, even when the structure of the top surface (the formation surface) of the substrate 5120 is an amorphous structure (for example, amorphous silicon oxide), CAAC-OS can be deposited.

In addition, even in the case where the top surface of the substrate 5120 which is the formation surface of the CAAC-OS has unevenness, it can be seen that the pellets 5100 are arrayed along the shape. For example, in the case where the top surface of the substrate 5120 is flat at the atomic level, the pellets 5100 are juxtaposed with a flat surface parallel to the ab plane facing downward. When the thickness of the pellet 5100 is uniform, a layer having uniform thickness, flatness, and high crystallinity is formed. Then, CAAC-OS can be obtained by stacking n layers (n is a natural number) of the layers.

On the other hand, even in the case where the top surface of the substrate 5120 has unevenness, the CAAC-OS has a structure in which n layers (n is a natural number) in which pellets 5100 are juxtaposed along the unevenness are stacked. In the case of the CAAC-OS, a gap may be easily generated between the pellets 5100 because the substrate 5120 has unevenness. However, even in this case, an intermolecular force works between the pellets 5100, and even if there is unevenness, the gaps between the pellets are arranged as small as possible. Therefore, the CAAC-OS can have high crystallinity even with unevenness.

Since a CAAC-OS is formed into a film by such a model, it is preferable that the sputtered particles be in the form of pellets having a small thickness. In the case where the sputtered particles are in the form of a dice having a large thickness, the surface to be directed onto the substrate 5120 may not be constant, and the thickness and the orientation of crystals may not be uniform.

According to the film formation model described above, a CAAC-OS having high crystallinity can be obtained even on a formation surface having an amorphous structure.

  In the case where the oxide semiconductor film has a plurality of structures, structural analysis may be possible by using nanobeam electron diffraction.

  In FIG. 20C, an electron gun chamber 610, an optical system 612 under the electron gun chamber 610, a sample chamber 614 under the optical system 612, an optical system 616 under the sample chamber 614, and an optical system 616. The transmission electron diffraction measurement apparatus is shown to have a lower observation room 620, a camera 618 installed in the observation room 620, and a film room 622 below the observation room 620. The camera 618 is installed toward the inside of the observation room 620. Note that the film chamber 622 may not be provided.

  Further, FIG. 20 (D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. 20 (C). Inside the transmission electron diffraction measurement apparatus, electrons emitted from the electron gun installed in the electron gun chamber 610 are irradiated to the substance 628 disposed in the sample chamber 614 via the optical system 612. Electrons having passed through the substance 628 enter a fluorescent plate 632 disposed inside the observation chamber 620 via the optical system 616. In the fluorescent plate 632, a transmission electron diffraction pattern can be measured by the appearance of a pattern corresponding to the intensity of the incident electron.

  The camera 618 is installed facing the fluorescent plate 632 and can capture a pattern appearing on the fluorescent plate 632. The angle between the center of the lens of the camera 618 and the straight line passing through the center of the fluorescent plate 632 and the upper surface of the fluorescent plate 632 is, for example, 15 ° to 80 °, 30 ° to 75 °, or 45 ° to 70 °. It is assumed that The smaller the angle, the larger the distortion of the transmitted electron diffraction pattern captured by the camera 618. However, if the angle is known in advance, it is also possible to correct distortion of the obtained transmission electron diffraction pattern. The camera 618 may be installed in the film chamber 622 in some cases. For example, the camera 618 may be installed in the film chamber 622 so as to face the incident direction of the electrons 624. In this case, a transmission electron diffraction pattern with less distortion can be photographed from the back surface of the fluorescent plate 632.

  The sample chamber 614 is provided with a holder for fixing a substance 628 which is a sample. The holder is structured to transmit electrons passing through the substance 628. The holder may have, for example, a function of moving the substance 628 to the X axis, the Y axis, the Z axis, or the like. The moving function of the holder may have an accuracy of moving in a range of, for example, 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm or the like. These ranges may be set as optimum depending on the structure of the substance 628.

  Next, a method of measuring a transmission electron diffraction pattern of a substance using the above-described transmission electron diffraction measurement apparatus will be described.

  For example, as shown in FIG. 20D, by changing (scanning) the irradiation position of the electron 624 which is a nano beam in the substance, it is possible to confirm that the structure of the substance is changing. At this time, when the substance 628 is a CAAC-OS film, a diffraction pattern as shown in FIG. 20A is observed. Alternatively, when the substance 628 is an nc-OS film, a diffraction pattern as shown in FIG. 20B is observed.

  By the way, even when the substance 628 is a CAAC-OS film, a diffraction pattern similar to that of an nc-OS film or the like may be partially observed. Therefore, the quality of the CAAC-OS film may be expressed by the ratio of a region where the diffraction pattern of the CAAC-OS film is observed in a certain range (also referred to as a CAAC conversion ratio). For example, in the case of a high-quality CAAC-OS film, the CAAC conversion rate is 50% or more, preferably 80% or more, more preferably 90% or more, and more preferably 95% or more. Note that the ratio of a region where a diffraction pattern different from that of the CAAC-OS film is observed is referred to as a non-CAAC conversion ratio.

  As an example, transmission electron diffraction patterns were obtained while scanning the upper surface of each sample having a CAAC-OS film immediately after deposition (denoted as as-sputtered) or after heating at 450 ° C. in an atmosphere containing oxygen. . Here, the CAAC conversion ratio was derived by observing the diffraction pattern while scanning at a speed of 5 nm / sec for 60 seconds and converting the observed diffraction pattern to a still image every 0.5 seconds. As the electron beam, a nanobeam electron beam with a probe diameter of 1 nm was used. The same measurement was performed on six samples. And the average value in six samples was used for calculation of a CAAC conversion rate.

  The CAAC conversion rate in each sample is shown in FIG. The CAAC conversion rate of the CAAC-OS film immediately after film formation was 75.7% (the non-CAAC conversion rate was 24.3%). In addition, the CAAC conversion rate of the CAAC-OS film after the heat treatment at 450 ° C. was 85.3% (the non-CAAC conversion rate was 14.7%). It can be seen that the CAAC conversion rate after the heat treatment at 450 ° C. is higher than that immediately after the film formation. That is, it is found that the heat treatment at a high temperature (eg, 400 ° C. or higher) lowers the non-CAAC conversion rate (increases the CAAC conversion rate). In addition, it can be seen that a CAAC-OS film having a high CAAC conversion rate can be obtained even with heat treatment at less than 500 ° C.

  Here, most of the diffraction patterns different from the CAAC-OS film were diffraction patterns similar to the nc-OS film. In addition, the amorphous oxide semiconductor film could not be confirmed in the measurement region. Therefore, it is suggested that the heat treatment causes a region having a structure similar to that of the nc-OS film to be rearranged and CAAC-ized under the influence of the structure of the adjacent region.

  21B and 21C are planar TEM images of the CAAC-OS film immediately after film formation and after heat treatment at 450 ° C. FIG. By comparing FIG. 21B and FIG. 21C, it is found that the quality of the CAAC-OS film after the heat treatment at 450 ° C. is more homogeneous. That is, it is found that the heat treatment at a high temperature improves the film quality of the CAAC-OS film.

  With such a measurement method, structural analysis of an oxide semiconductor film having a plurality of structures may be possible.

  The CAAC-OS film can be formed, for example, by the following method.

  The CAAC-OS film is formed, for example, by sputtering using a polycrystalline oxide semiconductor sputtering target. As a sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, or the like can be used. Further, in order to improve the uniformity of the film thickness distribution, the film composition distribution, or the crystallinity distribution of the oxide semiconductor film, it is more preferable to use the DC sputtering method or the AC sputtering method than the RF sputtering method.

  By raising the substrate temperature at the time of film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the film is formed at a substrate temperature of 100 ° C. to 740 ° C., preferably 200 ° C. to 500 ° C. By raising the substrate temperature at the time of film formation, when the sputtered particles reach the substrate, migration occurs on the substrate and the flat surface of the sputtered particles adheres to the substrate. At this time, since the sputtered particles are positively charged, the sputtered particles adhere to each other while repelling each other, so that the sputtered particles are not unevenly overlapped and a CAAC-OS film having a uniform thickness is formed. It can be membrane.

  By reducing the mixing of impurities at the time of film formation, it is possible to suppress that the crystal state is broken by the impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) in the film formation chamber may be reduced. Further, the concentration of impurities in the deposition gas may be reduced. Specifically, a deposition gas whose dew point is lower than or equal to -80.degree. C., preferably lower than or equal to -100.degree. C. is used.

  Further, it is preferable to reduce plasma damage at the time of film formation by increasing the proportion of oxygen in the film formation gas and optimizing the power. The proportion of oxygen in the deposition gas is 30% by volume or more, preferably 100% by volume.

  Alternatively, the CAAC-OS film is formed by the following method.

  First, a first oxide semiconductor film is formed to a thickness of greater than or equal to 1 nm and less than 10 nm. The first oxide semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100 ° C. to 500 ° C., preferably 150 ° C. to 450 ° C., and the film formation gas is formed with an oxygen ratio of 30 vol% or more, preferably 100 vol%.

  Next, heat treatment is performed to form the first oxide semiconductor film as a first CAAC-OS film with high crystallinity. The temperature of the heat treatment is 350 ° C to 740 ° C, preferably 450 ° C to 650 ° C. The heat treatment time is 1 minute to 24 hours, preferably 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, after the heat treatment is performed in an inert atmosphere, the heat treatment is performed in an oxidizing atmosphere. By heat treatment in an inert atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies may be generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In that case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. The heat treatment may be performed under reduced pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the first oxide semiconductor film can be further reduced in a short time.

  When the thickness of the first oxide semiconductor film is greater than or equal to 1 nm and less than 10 nm, the first oxide semiconductor film can be easily crystallized by heat treatment as compared to the case where the thickness is greater than or equal to 10 nm.

  Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm to 50 nm. The second oxide semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100 ° C. to 500 ° C., preferably 150 ° C. to 450 ° C., and the film formation gas is formed with an oxygen ratio of 30 vol% or more, preferably 100 vol%.

  Next, heat treatment is performed to solid-phase grow the second oxide semiconductor film from the first CAAC-OS film, whereby the second CAAC-OS film having high crystallinity is formed. The temperature of the heat treatment is 350 ° C to 740 ° C, preferably 450 ° C to 650 ° C. The heat treatment time is 1 minute to 24 hours, preferably 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, after the heat treatment is performed in an inert atmosphere, the heat treatment is performed in an oxidizing atmosphere. By heat treatment in an inert atmosphere, the impurity concentration of the second oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies may be generated in the second oxide semiconductor film by heat treatment in an inert atmosphere. In that case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. The heat treatment may be performed under reduced pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration of the second oxide semiconductor film can be further reduced in a short time.

  As described above, a CAAC-OS film with a total thickness of 10 nm or more can be formed.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Third Embodiment
In this embodiment, an example of a circuit using a transistor of one embodiment of the present invention will be described with reference to the drawings.

[Circuit configuration example]
In the structure described in Embodiment 1, various circuits can be formed by changing connection structures of transistors, wirings, and electrodes. Hereinafter, examples of circuit configurations which can be realized by using the semiconductor device of one embodiment of the present invention will be described.

[CMOS circuit]
The circuit diagram shown in FIG. 22A shows a configuration of a so-called CMOS circuit in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected. Note that in the drawing, the transistor to which the second semiconductor material is applied is shown with the symbol “OS”.

[Analog switch]
The circuit diagram in FIG. 22B illustrates a structure in which the source and the drain of each of the transistor 2100 and the transistor 2200 are connected. With such a configuration, it can function as a so-called analog switch.

[Example of storage device]
An example of a semiconductor device (memory device) which uses a transistor which is one embodiment of the present invention and which can hold stored data even in a situation where power is not supplied and which has no limitation on the number of times of writing is illustrated in FIG.

  The semiconductor device illustrated in FIG. 22C includes a transistor 3200 using a first semiconductor material, a transistor 3300 using a second semiconductor material, and a capacitor 3400. Note that as the transistor 3300, any of the transistors described in the above embodiments can be used.

  In this embodiment, an example in which a channel is formed in a semiconductor layer including an oxide semiconductor is described as the transistor 3300. Since the transistor 3300 has low off-state current, stored data can be held for a long time by using this. In other words, power consumption can be sufficiently reduced because a semiconductor memory device which does not require a refresh operation or has a very low refresh operation frequency can be provided.

  In FIG. 22C, the first wiring 3001 is electrically connected to the source electrode of the transistor 3200, and the second wiring 3002 is electrically connected to the drain electrode of the transistor 3200. In addition, the third wiring 3003 is electrically connected to one of the source electrode and the drain electrode of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate electrode of the transistor 3300. The other of the gate electrode of the transistor 3200 and the other of the source and drain electrodes of the transistor 3300 is electrically connected to one of the electrodes of the capacitor 3400, and the fifth wiring 3005 is electrically connected to the other of the electrodes of the capacitor 3400. Connected.

  In the semiconductor device illustrated in FIG. 22C, writing, holding, and reading of data can be performed as follows by utilizing the feature that the potential of the gate electrode of the transistor 3200 can be held.

  The writing and holding of information will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, whereby the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the gate electrode of the transistor 3200 and the capacitor 3400. That is, predetermined charge is given to the gate electrode of the transistor 3200 (writing). Here, it is assumed that one of charges (hereinafter referred to as low level charge and high level charge) giving two different potential levels is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, and the transistor 3300 is turned off, whereby the charge given to the gate electrode of the transistor 3200 is held (holding).

  Since the off-state current of the transistor 3300 is extremely small, the charge of the gate electrode of the transistor 3200 is held for a long time.

Next, reading of information will be described. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, a charge amount stored in the gate electrode of the transistor 3200 is applied. , And the second wiring 3002 have different potentials. In general, when the transistor 3200 is an n-channel transistor, the apparent threshold value V th — _H when the high level charge is given to the gate electrode of the transistor 3200 is that the low level charge is given to the gate electrode of the transistor 3200 This is because it is lower than the apparent threshold value V _{th_L} of the case. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 which is necessary to turn on the transistor 3200. Therefore, by _setting the potential of the fifth wiring 3005 to the potential V ₀ between V _{th — H} and V th — _L , the charge applied to the gate electrode of the transistor 3200 can be determined. For example, in the case where high level charge is given in writing, the transistor 3200 is turned on when the potential of the fifth wiring 3005 is V ₀ (> V th — _H ). When low level charge is applied, the transistor 3200 remains in the “off state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V th — _{L 2} ). Therefore, by determining the potential of the second wiring 3002, the held information can be read.

Note that in the case where memory cells are arrayed to be used, it is necessary to be able to read only information of a desired memory cell. In the case where information is not read out in this manner, a potential which causes the transistor 3200 to be in the “off state” regardless of the state of the gate electrode, that is, a potential smaller than V th — _H may be _supplied to the fifth wiring 3005. _{Alternatively} , the fifth wiring 3005 may be _{supplied with a} potential at which the transistor 3200 is turned “on” regardless of the state of the gate electrode, that is, a potential higher than V th — _L.

  The semiconductor device illustrated in FIG. 22D is mainly different from FIG. 22C in that the transistor 3200 is not provided. Also in this case, the operation of writing and holding information is possible by the same operation as described above.

  Next, reading of information will be described. When the transistor 3300 is turned on, the third wiring 3003 in a floating state and the capacitor 3400 are electrically connected, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 is changed. The amount of change in the potential of the third wiring 3003 varies depending on the potential of one of the electrodes of the capacitor 3400 (or the charge stored in the capacitor 3400).

  For example, the potential of one of the electrodes of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge is redistributed Assuming that the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, assuming that the potential of one of the electrodes of capacitive element 3400 has two states of V1 and V0 (V1> V0) as the state of the memory cell, the potential of third wiring 3003 in the case of holding potential V1. (= (CB × VB0 + C × V1) / (CB + C)) is higher than the potential (= (CB × VB0 + C × V0) / (CB + C)) of the third wiring 3003 in the case where the potential V0 is held. I understand that.

  Then, the information can be read out by comparing the potential of the third wiring 3003 with a predetermined potential.

  In this case, a transistor to which the first semiconductor material is applied is used as a driver circuit for driving a memory cell, and a transistor to which a second semiconductor material is applied as the transistor 3300 is stacked over the driver circuit. And it is sufficient.

  In the semiconductor device described in this embodiment, stored data can be held for an extremely long time by applying a transistor with extremely low off-state current in which an oxide semiconductor is used for a channel formation region. That is, since the refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, the power consumption can be sufficiently reduced. In addition, even when power is not supplied (however, the potential is preferably fixed), stored data can be held for a long time.

  Further, in the semiconductor device described in this embodiment, a high voltage is not required for writing information, and there is no problem of element deterioration. For example, unlike the conventional non-volatile memory, it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, so there is no problem such as deterioration of the gate insulating film. That is, in the semiconductor device according to the disclosed invention, there is no limitation on the number of times of rewriting which is a problem in the conventional nonvolatile memory, and the reliability is dramatically improved. In addition, since information is written according to the on state and the off state of the transistor, high-speed operation can be easily realized.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Embodiment 4
In this embodiment, an example of a semiconductor device using a transistor which is an embodiment of the present invention will be described with reference to drawings. FIG. 29 is an example of a circuit diagram of a semiconductor device according to one embodiment of the present invention.

  The semiconductor device illustrated in FIG. 29 includes a capacitor 660a, a capacitor 660b, a transistor 661a, a transistor 661b, a transistor 662a, a transistor 662b, an inverter 663a, an inverter 663b, a wiring BL, and a wiring BLB. A wiring WL, a wiring CL, and a wiring GL are provided.

  The semiconductor device illustrated in FIG. 29 is a memory cell in which a flip flop is formed by ring connection of an inverter 663a and an inverter 663b. A node to which an output signal of the inverter 663b is output is referred to as a node VN1, and a node to which an output signal of the inverter 663a is output is referred to as a node VN2. Note that a memory device (memory cell array) can be formed by arranging the memory cells in a matrix.

  One of the source and the drain of the transistor 662a is electrically connected to the wiring BL, the other of the source and the drain is electrically connected to the node VN1, and the gate is electrically connected to the wiring WL. One of the source and the drain of the transistor 662b is electrically connected to the node VN2, the other of the source and the drain is electrically connected to the wiring BLB, and the gate is electrically connected to the wiring WL.

  One of the source and the drain of the transistor 661a is electrically connected to the node VN1, the other of the source and the drain is electrically connected to one electrode of the capacitor 660a, and the gate is electrically connected to the wiring GL. Here, a node between the other of the source and the drain of the transistor 661a and one electrode of the capacitor 660a is a node NVN1. One of the source and the drain of the transistor 661b is electrically connected to the node VN2, the other of the source and the drain is electrically connected to one electrode of the capacitor 660b, and the gate is electrically connected to the wiring GL. Here, a node between the other of the source and the drain of the transistor 661b and one electrode of the capacitor 660b is a node NVN2.

  The other electrode of the capacitor 660 a is electrically connected to the wiring CL. The other electrode of the capacitor 660 b is electrically connected to the wiring CL.

  The conductive state and non-conductive state of the transistors 662a and 662b can be selected by the potential applied to the wiring WL. The conductive state and non-conductive state of the transistors 661a and 661b can be selected by the potential applied to the wiring GL.

  The writing, holding and reading of the memory cell shown in FIG. 29 will be described below.

  At the time of writing, first, a potential corresponding to data 0 or data 1 is applied to the wiring BL and the wiring BLB.

  For example, in the case where data 1 is to be written, the wiring BL is set to a high level power supply potential (VDD) and the wiring BLB is set to a ground potential. Next, a potential (VH) higher than or equal to the sum of VDD and the threshold voltage of the transistors 662 a and 662 b is applied to the wiring WL.

  Next, the potential of the wiring WL is set to be lower than the threshold voltage of the transistors 662 a and 662 b, whereby the data 1 written to the flip-flop is held.

  At the time of reading, the wiring BL and the wiring BLB are set to VDD in advance. Next, by applying VH to the wiring WL, the wiring BL remains unchanged at VDD, but the wiring BLB is discharged through the transistor 662a and the inverter 663a and becomes a ground potential. Data 1 held can be read out by amplifying the potential difference between the wiring BL and the wiring BLB with a sense amplifier (not shown).

  Note that in the case where data 0 is to be written, the wiring BL may be at the ground potential, the wiring BLB may be VDD, and then VH may be applied to the wiring WL. Next, the potential of the wiring WL is set to be lower than the threshold voltage of the transistors 662 a and 662 b, whereby the data 0 written to the flip flop is held. At the time of reading, by setting the wiring BL and the wiring BLB to VDD in advance and applying VH to the wiring WL, the wiring BLB remains unchanged at VDD, but the wiring BL is discharged through the transistor 662b and the inverter 663b and the ground potential It becomes. Data 0 held can be read out by amplifying the potential difference between the wiring BL and the wiring BLB with a sense amplifier.

  Therefore, the semiconductor device illustrated in FIG. 29 functions as a so-called static random access memory (SRAM). Since the SRAM uses flip-flops to hold data, a refresh operation is unnecessary. Therefore, power consumption at the time of data retention can be suppressed. In addition, since a capacitor is not used in the flip flop, it is suitable for applications requiring high speed operation.

  Further, in the semiconductor device illustrated in FIG. 29, data can be written from the node VN1 to the node NVN1 through the transistor 661a. Similarly, data can be written from node VN2 to node NVN2 through transistor 661b. The written data is held by turning off the transistor 661a or 661b. For example, even when the supply of the power supply potential is stopped, the data of the nodes VN1 and VN2 may be able to be held.

  Unlike the conventional SRAM in which data disappears immediately when the supply of power supply potential is stopped, the semiconductor device shown in FIG. 29 can retain data even after the supply of power supply potential is stopped. Therefore, a semiconductor device with low power consumption can be realized by turning on or off the power supply potential as appropriate. For example, power consumption of the CPU can be reduced by using the semiconductor device shown in FIG. 29 for the memory area of the CPU.

  Note that the period in which data is held in the nodes NVN1 and NVN2 is changed by the off-state current of the transistors 661a and 661b. Therefore, in order to extend the data retention period, transistors with low off-state current may be used for the transistors 661a and 661b. Alternatively, the capacitances of the capacitor 660a and the capacitor 660b may be increased.

  For example, when the transistor 100 and the capacitor 150 described in Embodiment 1 are used as the transistor 661a and the capacitor 660a, data can be held in the node NVN1 for a long time. Similarly, when the transistor 100 and the capacitor 150 are used as the transistor 661 b and the capacitor 660 b, data can be held at the node NVN 2 for a long time. Therefore, the description of the transistor 100 can be referred to for the transistor 661a and the transistor 661b. Further, for the capacitor 660 a and the capacitor 660 b, the description of the capacitor 150 may be referred to.

  In addition, as described in the above embodiment, by using the plug 121 and the plug 122 for the transistor 100, the area occupied by the elements including the transistor 100 and the capacitor 150 can be reduced. The transistor 100 or the capacitor 150 described in the above embodiment can be used for the transistor 661a, the transistor 661b, the capacitor 660a, and the capacitor 660b illustrated in FIG. Therefore, in some cases, the semiconductor device shown in FIG. 29 can be manufactured without largely increasing the occupied area as compared with the conventional SRAM. The description of the transistor 130 may be referred to for the transistor included in the transistor 662 a, the transistor 662 b, the transistor included in the inverter 663 a, and the transistor included in the inverter 663 b.

  As described above, it is understood that the semiconductor device according to one embodiment of the present invention has high performance with respect to the occupied area. In addition, it is understood that the semiconductor device has high productivity.

  This embodiment can be combined with any of the other embodiments shown in this specification as appropriate.

Fifth Embodiment
In this embodiment, an RF tag including the transistor or the memory device described in the above embodiment is described with reference to FIG.

  The RF tag in this embodiment has a memory circuit inside, stores necessary information in the memory circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. From such a feature, the RF tag can be used for an individual identification system or the like for identifying an item by reading individual information such as an item. In addition, extremely high reliability is required to be used for these applications. Here, the RF tag may be, for example, an RFID tag that recognizes identification information called an ID assigned to an article.

  The configuration of the RF tag is described with reference to FIG. FIG. 23 is a block diagram showing a configuration example of the RF tag.

  As shown in FIG. 23, the RF tag 800 has an antenna 804 that receives a wireless signal 803 transmitted from an antenna 802 connected to a communicator 801 (also referred to as an interrogator or a reader / writer). The RF tag 800 further includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that a transistor capable of sufficiently suppressing a reverse current, such as an oxide semiconductor, may be used as the transistor included in the demodulation circuit 807 and having a rectifying function. As a result, it is possible to suppress the decrease in the rectification action caused by the reverse current and prevent the output of the demodulation circuit from being saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be approximated linearly. The data transmission format is broadly divided into three types: electromagnetic coupling that communicates by mutual induction by arranging a pair of coils facing each other, electromagnetic induction that communicates by induction electromagnetic field, and radio wave that communicates using radio waves. It is divided. The RF tag 800 described in this embodiment can be used in any of the methods.

  Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving the wireless signal 803 with the antenna 802 connected to the communication device 801. In addition, the rectifier circuit 805 rectifies an input AC signal generated by receiving a wireless signal by the antenna 804, for example, a half-wave voltage doubler and converts the rectified signal by a capacitive element provided in a subsequent stage. It is a circuit for generating an input potential by smoothing. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling so as not to input power of a certain power or more to the circuit in the subsequent stage when the amplitude of the input AC signal is large and the internally generated voltage is large.

  The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. The constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 809 using the rise of the stable power supply voltage.

  The demodulation circuit 807 demodulates the input AC signal by envelope detection to generate a demodulated signal. The modulation circuit 808 is a circuit for performing modulation in accordance with data output from the antenna 804.

  The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is a circuit that holds input information and includes a row decoder, a column decoder, a memory area, and the like. The ROM 811 is a circuit for storing a unique number (ID) or the like and outputting according to processing.

  Note that each of the circuits described above can be discarded as appropriate.

  Here, the memory circuit described in the above embodiment can be used for the memory circuit 810. The memory circuit of one embodiment of the present invention can hold information even when the power is shut off; thus, the memory circuit can be suitably used for an RF tag. Furthermore, the memory circuit of one embodiment of the present invention does not cause a difference in the maximum communication distance at the time of reading and writing of data because the power (voltage) required for writing data is significantly smaller than that of a conventional nonvolatile memory. It is also possible. Furthermore, it is possible to suppress the occurrence of malfunction or erroneous writing due to power shortage at the time of data writing.

  Further, the memory circuit of one embodiment of the present invention can be used as a nonvolatile memory; therefore, the memory circuit can also be applied to the ROM 811. In that case, it is preferable that the producer separately prepares a command for writing data in the ROM 811 so that the user can not freely rewrite. By shipping the product after the manufacturer writes the unique number before shipping, it becomes possible to assign unique numbers only to non-defective items to be shipped, instead of assigning unique numbers to all the manufactured RF tags, It becomes easy to manage the customer corresponding to the product after shipment without the unique number of the product after shipment becoming discontinuous.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Sixth Embodiment
In this embodiment, at least the transistor described in the embodiment can be used and a CPU including the memory device described in the above embodiment is described.

  FIG. 24 is a block diagram showing an example of a configuration of a CPU using at least a part of the transistor described in the above embodiment.

  The CPU shown in FIG. 24 includes an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198 on a substrate 1190. (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided on separate chips. Of course, the CPU shown in FIG. 24 is merely an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 24 may be one core, and a plurality of the cores may be included and each core may operate in parallel. Also, the number of bits that the CPU can handle with the internal arithmetic circuit and data bus can be, for example, 8, 16, 32, or 64 bits.

  An instruction input to the CPU via the bus interface 1198 is input to the instruction decoder 1193 and decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

  The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instruction. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or the mask state while the program of the CPU is being executed. The register controller 1197 generates an address of the register 1196 and performs reading and writing of the register 1196 according to the state of the CPU.

  In addition, the timing controller 1195 generates a signal that controls the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.

  In the CPU shown in FIG. 24, the memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in the above embodiment can be used.

  In the CPU shown in FIG. 24, the register controller 1197 selects the holding operation in the register 1196 in accordance with the instruction from the ALU 1191. That is, in the memory cell included in the register 1196, it is selected whether data is held by a flip flop or data is held by a capacitor. When holding of data by flip flop is selected, supply of power supply voltage to memory cells in register 1196 is performed. When data retention in the capacitor is selected, data rewriting to the capacitor is performed, and supply of the power supply voltage to the memory cell in the register 1196 can be stopped.

  FIG. 25 is an example of a circuit diagram of a memory element that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized by power interruption, a circuit 1202 in which stored data is not volatilized by power interruption, a switch 1203, a switch 1204, a logic element 1206, a capacitor element 1207, and a selection function. And the circuit 1220. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include another element such as a diode, a resistor, or an inductor as needed. The transistor 1209 is preferably a transistor in which a channel is formed in the oxide semiconductor layer.

  Here, the memory device described in the above embodiment can be used for the circuit 1202. When supply of the power supply voltage to the memory element 1200 is stopped, a ground potential (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 in the circuit 1202. For example, the gate of the transistor 1209 is grounded via a load such as a resistor.

  The switch 1203 is formed using a transistor 1213 of one conductivity type (eg, n channel type), and the switch 1204 is formed using a transistor 1214 of a conductivity type (eg, p channel type) opposite to the one conductivity type. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 is the gate of the transistor 1213 The conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 1213) is selected by the control signal RD input to the signal. The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214 The control signal RD selects the conduction or non-conduction (that is, the on state or the off state of the transistor 1214) between the first terminal and the second terminal.

  One of the source and the drain of the transistor 1209 is electrically connected to one of the pair of electrodes of the capacitor 1208 and the gate of the transistor 1210. Here, the connection portion is assumed to be a node M2. One of the source and the drain of the transistor 1210 is electrically connected to a wiring (eg, a GND line) which can supply a low power supply potential, and the other is a first terminal of the switch 1203 (a source and a drain of the transistor 1213). On the other hand. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (one of the source and the drain of the transistor 1214). The second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), the first terminal of the switch 1204 (one of the source and the drain of the transistor 1214), the input terminal of the logic element 1206, and the capacitor 1207 One of the pair of electrodes is electrically connected. Here, the connection portion is assumed to be a node M1. A fixed potential can be input to the other of the pair of electrodes of the capacitor 1207. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitive element 1207 is electrically connected to a wiring (eg, a GND line) which can supply a low power supply potential. A fixed potential can be input to the other of the pair of electrodes of the capacitor 1208. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) which can supply a low power supply potential.

  Note that the capacitor 1207 and the capacitor 1208 can be omitted by actively using parasitic capacitance or the like of a transistor or a wiring.

  A control signal WE is input to a first gate (first gate electrode) of the transistor 1209. The switch 1203 and the switch 1204 are selected to be conductive or nonconductive between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in the conductive state, the first terminal and the second terminal of the other switch are in the non-conductive state.

  A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 25 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. The signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal whose logic value is inverted by the logic element 1206, and is input to the circuit 1201 through the circuit 1220. .

  Note that FIG. 25 illustrates an example in which the signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inverting the logic value. For example, when there is a node in the circuit 1201 at which a signal obtained by inverting the logic value of a signal input from an input terminal is held, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is provided. A signal to be output can be input to the node.

  Further, in FIG. 25, among the transistors used for the memory element 1200, the transistors other than the transistor 1209 can be transistors in which a channel is formed in a layer other than an oxide semiconductor or in the substrate 1190. For example, it can be a transistor in which a channel is formed in a silicon layer or a silicon substrate. Alternatively, all the transistors used for the memory element 1200 can be transistors in which a channel is formed using an oxide semiconductor layer. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor layer in addition to the transistor 1209, and the remaining transistors have a channel in a layer or a substrate 1190 other than an oxide semiconductor. It can also be a transistor to be formed.

  For example, a flip flop circuit can be used for the circuit 1201 in FIG. For example, an inverter or a clocked inverter can be used as the logic element 1206.

  In the semiconductor device in one embodiment of the present invention, while the power supply voltage is not supplied to the memory element 1200, data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202.

  In addition, a transistor in which a channel is formed in an oxide semiconductor layer has extremely low off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor layer is significantly lower than the off-state current of a transistor whose channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 can be held for a long time even while the power supply voltage is not supplied to the memory element 1200. Thus, the storage element 1200 can retain stored contents (data) even while the supply of the power supply voltage is stopped.

  In addition, since the memory element is characterized in that a precharge operation is performed by providing the switch 1203 and the switch 1204, the time until the circuit 1201 holds the original data again after power supply voltage restart is shortened. be able to.

  In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after supply of the power supply voltage to the memory element 1200 is resumed, the signal held by the capacitor 1208 can be converted to the state (on or off) of the transistor 1210 and read from the circuit 1202 it can. Therefore, even if the potential corresponding to the signal held in the capacitor element 1208 fluctuates to some extent, the original signal can be accurately read.

  By using such a storage element 1200 for a storage device such as a register included in a processor or a cache memory, data loss in the storage device due to the supply stop of the power supply voltage can be prevented. In addition, after the supply of the power supply voltage is resumed, the state before the stop of the power supply can be restored in a short time. Therefore, power can be shut down even in a short time in the entire processor or one or a plurality of logic circuits constituting the processor, power consumption can be suppressed.

  In this embodiment, the memory element 1200 is described as an example using the CPU, but the memory element 1200 may be a DSP (Digital Signal Processor), a custom LSI, an LSI such as a PLD (Programmable Logic Device), an RF (Radio Frequency) tag. Is also applicable.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Seventh Embodiment
In this embodiment, a structural example of a display panel of one embodiment of the present invention will be described.

[Example of configuration]
FIG. 26A is a top view of a display panel of one embodiment of the present invention, and FIG. 26B can be used when a liquid crystal element is applied to a pixel of the display panel of one embodiment of the present invention It is a circuit diagram for demonstrating a pixel circuit. FIG. 26C is a circuit diagram for describing a pixel circuit which can be used in the case of applying an organic EL element to a pixel of a display panel of one embodiment of the present invention.

  The transistors arranged in the pixel portion can be formed according to the above embodiment mode. In addition, since the transistor can be easily an n-channel transistor, part of the driver circuit which can be formed using an n-channel transistor is formed over the same substrate as the transistor in the pixel portion. As described above, by using the transistor described in the above embodiment for the pixel portion and the driver circuit, a highly reliable display device can be provided.

  An example of a block diagram of an active matrix display device is illustrated in FIG. A pixel portion 701, a first scan line driver circuit 702, a second scan line driver circuit 703, and a signal line driver circuit 704 are provided over a substrate 700 of a display device. In the pixel portion 701, a plurality of signal lines are extended from the signal line driver circuit 704, and a plurality of scan lines are extended from the first scan line driver circuit 702 and the second scan line driver circuit 703. It is arranged. Note that pixels each having a display element are provided in a matrix in a region where the scan line and the signal line intersect. The substrate 700 of the display device is connected to a timing control circuit (also referred to as a controller or a control IC) through a connection portion such as a flexible printed circuit (FPC).

  In FIG. 26A, the first scan line driver circuit 702, the second scan line driver circuit 703, and the signal line driver circuit 704 are formed over the same substrate 700 as the pixel portion 701. Therefore, the number of parts such as a drive circuit provided outside is reduced, so that cost can be reduced. Further, in the case where a driver circuit is provided outside the substrate 700, it is necessary to extend the wiring, which increases the number of connections between the wirings. When the driver circuit is provided over the same substrate 700, the number of connections between the wirings can be reduced, which can improve the reliability or the yield.

[Liquid crystal panel]
Further, an example of a circuit configuration of the pixel is illustrated in FIG. Here, a pixel circuit which can be applied to a pixel of a VA liquid crystal display panel is shown.

  This pixel circuit can be applied to a configuration having a plurality of pixel electrode layers in one pixel. Each pixel electrode layer is connected to a different transistor, and each transistor is configured to be driven by different gate signals. Thus, signals applied to individual pixel electrode layers of multi-domain designed pixels can be independently controlled.

  The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are separated so that different gate signals can be given. On the other hand, the source electrode layer or drain electrode layer 714 functioning as a data line is used in common by the transistor 716 and the transistor 717. As the transistor 716 and the transistor 717, the transistor 100 described in the above embodiment can be used as appropriate. Thus, a highly reliable liquid crystal display panel can be provided.

  The shapes of a first pixel electrode layer electrically connected to the transistor 716 and a second pixel electrode layer electrically connected to the transistor 717 are described. The shapes of the first pixel electrode layer and the second pixel electrode layer are separated by slits. The first pixel electrode layer has a V-shaped shape, and the second pixel electrode layer is formed to surround the outer side of the first pixel electrode layer.

  The gate electrode of the transistor 716 is connected to the gate wiring 712, and the gate electrode of the transistor 717 is connected to the gate wiring 713. Different gate signals are given to the gate wiring 712 and the gate wiring 713 to make the operation timings of the transistor 716 and the transistor 717 different, so that the alignment of liquid crystal can be controlled.

  Alternatively, a storage capacitor may be formed of the capacitor wiring 710, a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer.

  The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer in between, and the second liquid crystal element 719 is a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer in between It consists of

  Note that the pixel circuit illustrated in FIG. 26B is not limited to this. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

[Organic EL panel]
Another example of the circuit configuration of the pixel is shown in FIG. Here, a pixel structure of a display panel using an organic EL element is shown.

  In the organic EL element, when a voltage is applied to the light-emitting element, electrons are injected from one of the pair of electrodes and holes from the other into the layer containing the light-emitting organic compound, and a current flows. Then, the electron and the hole recombine, whereby the light emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light emitting element is referred to as a current excitation light emitting element.

  FIG. 26C shows an example of an applicable pixel circuit. Here, an example in which two n-channel transistors are used in one pixel is shown. Note that the metal oxide film of one embodiment of the present invention can be used for a channel formation region of an n-channel transistor. Further, digital time gray scale driving can be applied to the pixel circuit.

  The configuration of the applicable pixel circuit and the operation of the pixel when digital time gray scale driving is applied will be described.

  The pixel 720 includes a switching transistor 721, a driving transistor 722, a light emitting element 724, and a capacitor 723. In the switching transistor 721, the gate electrode layer is connected to the scan line 726, the first electrode (one of the source electrode layer and the drain electrode layer) is connected to the signal line 725, and the second electrode (source electrode layer and drain electrode layer) And the other is connected to the gate electrode layer of the driving transistor 722. The gate electrode layer of the driving transistor 722 is connected to the power supply line 727 via the capacitor 723, the first electrode is connected to the power supply line 727, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. It is connected. The second electrode of the light emitting element 724 corresponds to the common electrode 728. The common electrode 728 is electrically connected to a common potential line formed on the same substrate.

  As the switching transistor 721 and the driving transistor 722, the transistor 100 described in the above embodiment can be used as appropriate. Thereby, a highly reliable organic EL display panel can be provided.

  The potential of the second electrode (common electrode 728) of the light emitting element 724 is set to a low power supply potential. Note that the low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 727, and, for example, GND or 0 V can be set as the low power supply potential. The high power supply potential and the low power supply potential are set to be higher than or equal to the threshold voltage of the light emitting element 724 in the forward direction, and the potential difference is applied to the light emitting element 724 to flow a current to the light emitting element 724 to emit light. Note that the forward voltage of the light-emitting element 724 refers to a voltage at which desired luminance is obtained, and includes at least a forward threshold voltage.

  Note that the capacitor 723 can be omitted by substituting the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 may be a capacitance between the channel formation region and the gate electrode layer.

  Next, signals input to the driving transistor 722 will be described. In the case of a voltage input voltage driving method, video signals in which the driving transistor 722 is fully turned on or off are input to the driving transistor 722. Note that in order to operate the driving transistor 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the gate electrode layer of the driving transistor 722. Further, a voltage equal to or higher than a value obtained by adding the threshold voltage Vth of the drive transistor 722 to the power supply line voltage is applied to the signal line 725.

  When analog gray scale driving is performed, a voltage equal to or higher than the sum of the forward voltage of the light emitting element 724 and the threshold voltage Vth of the driving transistor 722 is applied to the gate electrode layer of the driving transistor 722. Note that a video signal is input such that the driving transistor 722 operates in a saturation region, and current flows to the light emitting element 724. Further, in order to operate the driving transistor 722 in the saturation region, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. When the video signal is analog, current corresponding to the video signal can be supplied to the light-emitting element 724 to perform analog grayscale driving.

  Note that the configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in FIG.

  When the transistor illustrated in the above embodiment is applied to the circuit illustrated in FIG. 26, the source electrode (first electrode) is electrically connected to the low potential side and the drain electrode (second electrode) is electrically connected to the high potential side. It is assumed to be connected. Furthermore, the potential of the first gate electrode is controlled by a control circuit or the like, and the potential exemplified above, such as a potential lower than the potential applied to the source electrode by a wiring not shown, can be input to the second gate electrode. do it.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

Eighth Embodiment
A semiconductor device according to an aspect of the present invention is a display device, a personal computer, and an image reproducing apparatus including a recording medium (typically, a display capable of reproducing a recording medium such as a DVD: Digital Versatile Disc and displaying the image) Devices that have In addition, as an electronic device that can use the semiconductor device according to one embodiment of the present invention, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book reader, a camera such as a video camera or a digital still camera, goggles Type display (head mounted display), navigation system, sound reproduction device (car audio, digital audio player, etc.), copier, facsimile, printer, printer complex machine, automated teller machine (ATM), vending machine etc. Be A specific example of these electronic devices is shown in FIG.

  FIG. 27A illustrates a portable game machine, which includes a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, an operation key 907, a stylus 908, and the like. Note that although the portable game machine shown in FIG. 27A includes two display portions 903 and a display portion 904, the number of display portions included in the portable game machine is not limited to this.

  FIG. 27B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, an operation key 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connecting portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connecting portion 915. is there. The video in the first display portion 913 may be switched according to the angle between the first housing 911 and the second housing 912 in the connection portion 915. Further, a display device to which a function as a position input device is added may be used as at least one of the first display portion 913 and the second display portion 914. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, which is also called a photosensor, in a pixel portion of a display device.

  FIG. 27C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

  FIG. 27D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a freezer door 933, and the like.

  FIG. 27E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, an operation key 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by the connecting portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connecting portion 946. is there. The video in the display portion 943 may be switched according to the angle between the first housing 941 and the second housing 942 in the connection portion 946.

  FIG. 27F shows a motor vehicle, which includes a car body 951, wheels 952, a dashboard 953, lights 954, and the like.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

(Embodiment 9)
In this embodiment mode, a usage example of the RF tag according to one embodiment of the present invention will be described with reference to FIG. Although the application of the RF tag is extensive, for example, banknotes, coins, securities, bearer bonds, certificates (driver's license, certificate of residence, etc., see FIG. 28A), containers for packaging (wrapping paper or the like) Bottles and the like (see FIG. 28C), recording media (DVDs and video tapes and the like, see FIG. 28B), vehicles (bicycles and the like, see FIG. 28D), personal belongings (such as glasses and glasses) Foods, plants, animals, human body, clothing, household goods, medical products including medicines and drugs, or articles such as electronic devices (liquid crystal display devices, EL display devices, television devices, or mobile phones) Alternatively, it can be used by providing it on a tag attached to each article (see FIG. 28E, FIG. 28F) or the like.

  The RF tag 4000 according to one aspect of the present invention is fixed to an article by being attached to or embedded in a surface. For example, in the case of a book, it is embedded in paper, and in the case of a package made of an organic resin, it is embedded in the inside of the organic resin and fixed to each article. Since the RF tag 4000 according to one aspect of the present invention is small, thin, and lightweight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the RF tag 4000 according to one embodiment of the present invention to bills, coins, securities, bearer bonds, certificates, or the like, an authentication function can be provided. If this authentication function is used, Forgery can be prevented. In addition, by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal goods, food, clothing, household goods, electronic devices and the like, the efficiency of a system such as an inspection system can be improved. Can be Further, even with vehicles, by attaching the RF tag according to one embodiment of the present invention, security against theft or the like can be enhanced.

  As described above, by using the RF tag according to one aspect of the present invention for each of the applications described in this embodiment, the operating power including the writing and reading of information can be reduced, so the maximum communication distance can be increased. Is possible. In addition, since information can be held for an extremely long time even when power is shut off, the present invention can be suitably used for applications where the frequency of writing and reading is low.

  This embodiment can be implemented in appropriate combination with at least a part of the other embodiments described in this specification.

624 Electron 628 substance 100 transistor 101 semiconductor layer 101a semiconductor layer 101b semiconductor layer 101c semiconductor layer 102 gate insulating film 103 gate electrode 104a conductive layer 105 conductive layer 105 conductive layer 111 barrier film 111a barrier film 111b barrier film 111c barrier film 111d barrier film 111e Barrier film 111 f Barrier film 111 g Barrier film 112 Insulating film 113 Insulating film 114 Insulating film 115 a Insulating film 115 b Insulating film 115 c Insulating film 115 d Insulating film 115 d Insulating film 116 Insulating film 116 Insulating film 121 Plug 122 Plug 123 Plug 124 Wiring 125 Conductive layer 126 Plug 127 Plug 128 plug 129 a plug 129 b plug 129 c plug 129 d plug 130 transistor 131 semiconductor substrate 132 semiconductor layer 133 a low resistance layer 13 b Low resistance layer 134 gate insulating film 135 gate electrode 136 insulating film 137 insulating film 138 insulating film 139 plug 140 plug 141 plug 142 wiring 143 conductive layer 144 conductive layer 145 plug 146 conductive layer 147 plug 150 capacitive element 151 conductive layer 152 conductive layer 152 b conductive layer 153 a conductive layer 153 b conductive layer 154 a conductive layer 154 b conductive layer 154 c conductive layer 154 d conductive layer 154 e conductive layer 160 transistor 164 plug 165 plug 166 wiring 176 a region 176 b region 171 a low resistance region 171 b low resistance region 181 conductive film 190 transistor 191 Transistor 211a Barrier film 211b Barrier film 211c Barrier film 211d Barrier film 211e Barrier film 211f Barrier film 215a Insulating film 215b Insulating film 215c Insulating film 15 d insulating film 215 e insulating film 215 f insulating film 251 conductive layer 251 a conductive layer 251 b conductive layer 251 c conductive layer 251 d conductive layer 251 e conductive layer 261 insulating film 281 layer 282 layer 283 layer 284 layer 285 layer 286 layer 288 layer 288 layer 290 layer 291 layer 292 layer 293 layer 295 layer 321 layer 322 plug 322 plug 610 electron gun chamber 612 optical system 614 sample chamber 616 optical system 618 camera 620 observation chamber 622 film chamber 632 fluorescent plate 660 a capacitive element 660 b capacitive element 661 a transistor 661 a transistor 662 b Transistor 663a Inverter 663b Inverter 700 Substrate 701 Pixel portion 702 Scanning line drive circuit 703 Scanning line drive circuit 704 Signal line drive circuit 710 Capacitance wiring 712 Gate wiring 713 gate wiring 714 drain electrode layer 716 transistor 717 transistor 718 liquid crystal element 719 liquid crystal element 720 pixel 721 switching transistor 722 driving transistor 723 capacitive element 724 light emitting element 725 signal line 726 scanning line 727 common electrode 800 RF Tag 801 Communication unit 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Memory circuit 811 ROM
901 housing 902 housing 903 display portion 904 display portion 905 microphone 906 speaker 907 operation key 908 stylus 911 housing 912 housing 913 display portion 914 display portion 915 connection portion 916 operation key 921 housing 922 display portion 923 keyboard 924 pointing device 931 Case 932 Cold Storage Room Door 933 Freezer Room Door 941 Case 942 Case 943 Display Unit 944 Operation Key 945 Lens 946 Connection Unit 951 Vehicle Body 952 Wheel 953 Dashboard 954 Light 1189 ROM Interface 1190 Substrate 1191 ALU
1192 ALU controller 1193 instruction decoder 1194 interrupt controller 1195 timing controller 1196 registers 1197 register controller 1198 bus interface 1199 ROM
1200 storage element 1201 circuit 1202 circuit 1203 switch 1204 switch 1206 logic element 1207 capacitance element 1208 transistor 1210 transistor 1213 transistor 1214 transistor 1214 transistor 1220 circuit 2100 transistor 2200 transistor 3001 wiring 3002 wiring 3003 wiring 3004 wiring 3005 wiring 3200 transistor 3400 transistor 3400 capacitance Element 4000 RF tag 5100 pellet 5100 a pellet 5100 b pellet 5101 ion 5102 zinc oxide layer 5103 particle 5105 a pellet 5105 a1 region 5105 a2 pellet 5105 b pellet 5105 c pellet 5105 d pellet 5105 d1 region 5105 e pellet 5120 substrate 513 Target 5161 area

Claims (3)

A capacitive element, a first transistor, and a second transistor,
The capacitive element includes at least a first insulating film, a second insulating film, a third insulating film, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth. And a conductive layer of
The second transistor is located above the first transistor ,
Before SL first insulating film, said second insulating film and said third insulating film is located between the first transistor, the second transistor,
The first transistor is provided on a semiconductor substrate,
The second transistor includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer.
The second semiconductor layer is provided on the first semiconductor layer,
A source electrode and a drain electrode are provided on the second semiconductor layer and cover the side surface of the first semiconductor layer and the side surface of the second semiconductor layer.
The third semiconductor layer is provided on the source electrode and the drain electrode, and has a region in contact with the second semiconductor layer,
The gate insulating film of the second transistor is provided on the third semiconductor layer,
A gate electrode of the second transistor is provided on the gate insulating film,
The first semiconductor layer, the second semiconductor layer, the source electrode or the drain electrode, and the first plug and the second plug penetrating the gate insulating film.
The first plug is electrically connected to the first conductive layer,
Between the first conductive layer and the fourth conductive layer, the first insulating film, the second insulating film, the second conductive layer, the third conductive layer, and the third insulating layer Have a membrane,
The first conductive layer is electrically connected to the fourth conductive layer by a third plug;
The first insulating film is provided between the first conductive layer and the second conductive layer and between the first conductive layer and the third conductive layer.
The third insulating film is provided between the second conductive layer and the fourth conductive layer and between the third conductive layer and the fourth conductive layer.
The third plug is provided in an opening provided in the first insulating film, the second insulating film, and the third insulating film.
The second conductive layer and the third conductive layer are respectively provided in openings provided in the second insulating film,
The second conductive layer and the third conductive layer are electrically connected;
The fourth conductive layer is electrically connected to the gate electrode of the first transistor,
The semiconductor device in which the second plug is electrically connected to a source region or a drain region of the first transistor . In claim 1 ,
The semiconductor device having a function of blocking at least one of hydrogen, water, and oxygen in the first insulating film and the third insulating film . In claim 1 or 2 ,
The first insulating film and the third insulating film are made of silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxide nitride, gallium oxide, gallium oxide, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, hafnium oxide oxynitride A semiconductor device including at least one of them.