JP6536502B2 - Method of manufacturing wafer for particle counter calibration - Google Patents

Description

  The present invention relates to a method of manufacturing a particle counter calibration wafer.

  A wafer coated with PSL (polystyrene latex) is generally used as a wafer for calibrating the particle counter.

  Although it is not PSL as a technique of producing the wafer for calibration of a particle counter, in patent document 1, the technique of forming an artificial particle on a wafer is disclosed. As another method, Patent Document 2 and Patent Document 3 disclose a technique of forming pits artificially from patterning by the same method as that used in the device process.

  On the other hand, Patent Document 4 discloses a method in which particles or pits are not artificially formed, and a vacancy-like defect on the wafer surface is used as a wafer for particle counter calibration.

JP, 2004-264124, A Japanese Patent Application Laid-Open No. 11-014534 Japanese Patent Application Publication No. 11-506272 JP, 2016-039374, A

  However, it is known that a wafer coated with a general PSL as a wafer for calibrating a particle counter is expensive. Moreover, although there is a concern of contamination after multiple uses, it can not be cleaned because the PSL applied to the wafer falls off.

  In addition, the technology for artificially producing particles or pits described in Patent Documents 1 to 3 requires the same equipment as that used in the device process. Furthermore, the cost for producing the calibration wafer is also expensive, and the time required for the production also takes time.

  The method of using the vacancy-like defects on the wafer surface described in Patent Document 4 is not practical because the method of manufacturing the method is not shown.

  The present invention has been made in view of the above problems, and provides a method for producing a particle counter calibration wafer that can produce a wafer for particle counter calibration that can be used for a long time by cleaning inexpensively and in a short time. The purpose is to

  In order to achieve the above object, the present invention is a method of manufacturing a wafer for particle counter calibration, comprising the steps of: preparing a silicon wafer; and annealing the prepared silicon wafer to bulk the silicon wafer. And a step of forming a hole consisting of the COP in the surface of the silicon wafer by mirror-polishing the surface of the silicon wafer on which the COP is grown. There is provided a method of manufacturing a wafer for particle counter calibration characterized in that a wafer for particle counter calibration in which a hole made of the COP is formed on the surface is manufactured.

  With such a method, it is possible to produce a wafer for particle counter calibration in which a hole made of COP is formed on the surface of a silicon wafer by a simple method. Wafers can be produced inexpensively and in a short time. COP is an abbreviation of "Crystal Originated Particle", and the entity is a hollow defect.

  At this time, the silicon wafer to be prepared can be a mirror-polished silicon wafer.

  As described above, in the present invention, a silicon wafer (mirror wafer) which has already been subjected to mirror polishing can be used as a raw material wafer. In this method, since it is only necessary to add the annealing step and the mirror polishing step to the standard mirror wafer manufacturing process, it is possible to produce at low cost and in a short time.

  In addition, while the silicon wafer to be prepared is lapped or ground by cutting an as-sliced wafer cut out from a silicon single crystal ingot and etched, a silicon wafer not subjected to mirror polishing can be obtained.

  Thus, in the present invention, a silicon wafer before mirror polishing can also be used as a raw material wafer. When such a raw material wafer is used, mirror polishing may be performed once before producing the particle counter calibration wafer, so that the particle counter calibration wafer can be produced more efficiently.

  Further, in the method of manufacturing a wafer for particle counter calibration of the present invention, it is preferable that the silicon wafer to be prepared has an oxygen concentration of 13 ppma (JEIDA) or more.

  When such a silicon wafer is used as a silicon wafer to be prepared, COP can be made to appear by heat treatment for a short time.

  Preferably, the silicon wafer to be prepared has a defect area of V area.

  If such a silicon wafer is used as the silicon wafer to be prepared, COP can be easily revealed by heat treatment.

  Moreover, when performing said annealing, it is preferable to anneal on the conditions which make COP of the size of 20-80 nm grow in the bulk of the said silicon wafer.

  By growing a COP of the above-mentioned size, a particle counter calibration wafer in which a hole composed of a foreign substance on the surface of the wafer actually measured by the particle counter or a COP consisting of a size close to the size of a depression on the wafer is formed. It can be made.

  Also, the annealing can be performed in an argon atmosphere.

  An argon (Ar) atmosphere can be suitably used as an atmosphere of the annealing step for eliciting COP.

  In addition, when mirror-polishing the surface of the silicon wafer on which the COP is grown, it is preferable to mirror-polish so that COP of a size of 20 to 80 nm is exposed on the surface of the silicon wafer.

  By performing such mirror polishing, a particle counter calibration wafer having holes formed of foreign matter on the surface of the wafer actually measured by the particle counter and COPs close to the size of the depression on the wafer is formed. Can.

  In addition, when measuring the particle counter calibration wafer between foreign particle counters when measuring foreign particles present on the surface of the silicon wafer to be measured or the depressions appearing on the surface of the silicon wafer to be measured between different particle counters It can be used to calibrate the detection sensitivity of

  The wafer for calibrating particle counters manufactured by the manufacturing method of the present invention can be suitably used for calibration of detection sensitivity between different particle counters as described above.

  According to the method of manufacturing a wafer for particle counter calibration of the present invention, a wafer for particle counter calibration in which a hole made of COP is formed on the surface of a silicon wafer can be manufactured by a simple method. A usable wafer for particle counter calibration can be manufactured inexpensively and in a short time. In addition, the wafer for particle counter calibration manufactured by the manufacturing method of the present invention can be cleaned even when it gets dirty, and it can be used for a long time without concern of falling off of PSL particles such as PSL coated wafer. .

It is a flowchart which shows the preparation methods of the wafer for particle counter calibration of this invention. It is a flowchart which shows an example and the other example of the manufacturing method of the wafer for particle counter calibration of this invention. It is an example of the SEM image of COP which appeared on the wafer surface after a mirror polishing process. It is an example of the image which observed COP which appeared on the wafer surface by AFM. It is an example which measured the hole diameter of COP of FIG. 4 by AFM. It is the annealing recipe of the Ar annealing process performed in the preparation method of an Example. It is a correlation graph of the COP hole diameter of the wafer for particle counters calibration produced with the production method of an example, and the measurement result in two particle counters of calibration object. It is the number of measurements by the particle counter before and after cleaning of the wafer for particle counter calibration in the embodiment and the comparative example.

  Hereinafter, the present invention will be described in detail by way of an embodiment with reference to the drawings, but the present invention is not limited thereto.

  FIG. 1 is a flow chart showing a method of manufacturing a wafer for particle counter calibration of the present invention.

  First, as shown in S11 of FIG. 1, a silicon wafer to be a raw material of a wafer for particle counter calibration is prepared. The silicon wafer prepared here is a silicon wafer on which COP is grown by heat treatment (annealing). In particular, it is preferable that the defect area is a wafer in the V area. Here, the V region is a region in which there are many vacancy-type point defects called Vacancy that are generated due to a shortage of silicon atoms in a silicon single crystal. The point defects aggregate to form COPs, and further, the COPs grow and become apparent by heat treatment. Moreover, in order to make COP manifest by heat treatment for a short time, it is preferable that the oxygen concentration of the silicon wafer to prepare is 13 ppma (JEIDA) or more.

  Next, as shown in S12 of FIG. 1, COP is grown on the bulk part of the silicon wafer by annealing the prepared silicon wafer. This annealing can be performed in an argon atmosphere. An argon atmosphere can be suitably used as an atmosphere for the annealing step for eliciting COP.

  When this annealing is carried out, it is preferable to carry out the annealing under the conditions to grow COP of a size of 20 to 80 nm in the bulk of the silicon wafer. By growing a COP of the above-mentioned size, a particle counter calibration wafer in which a hole composed of a foreign substance on the surface of the wafer actually measured by the particle counter or a COP consisting of a size close to the size of a depression on the wafer is formed. It can be made. Specifically, the maximum temperature is preferably 1200 ° C. in an argon atmosphere, and the holding time at that time is preferably about 1 hour. Further, it is preferable to set the temperature rising rate until reaching 1200 ° C. and the temperature lowering rate when returning to the normal temperature so as not to cause the slip occurring at the wafer outer periphery or the supporting point with the boat.

  However, since the purpose of this annealing step is to grow a Void defect, that is, COP, to a depth where the wafer surface layer is removed by mirror polishing in the next step (S13), the invention is not limited to the above heat treatment conditions. Various atmospheres, heat treatment temperatures, heat treatment times can be applied according to the oxygen concentration of the wafer used, the pulling rate of the silicon single crystal ingot serving as the wafer raw material, the cut-out crystal position, etc. In addition to RTA, it is also possible to combine these or apply multiple stages of resistance heating treatments. What is important in this annealing step is to control the size and density of the COPs to be revealed within the range applicable to the calibration wafer.

  Next, as shown in S13 of FIG. 1, the surface of the silicon wafer on which COP is grown is mirror-polished to form holes made of COP on the surface of the silicon wafer. The mirror polishing step is generally performed by CMP (Chemical Mechanical Polishing) processing. When mirror-polishing the surface of the silicon wafer on which COP is grown, it is preferable to mirror-polish so that COP of a size of 20 to 80 nm is exposed on the surface of the silicon wafer. By performing such mirror polishing, a particle counter calibration wafer having holes formed of foreign matter on the surface of the wafer actually measured by the particle counter and COPs close to the size of the depression on the wafer is formed. Can.

  Polishing removal in this mirror polishing process can be various conditions depending on the temperature and time in the above-mentioned annealing process. For example, as described above, when the maximum temperature of the annealing step is 1200 ° C. and the holding time is about 1 hour, the removal amount in the mirror polishing step is preferably about 0.5 μm, and COP grown in the annealing step is It is possible to expose to the surface layer by polishing removal.

  As described above, it is possible to produce a wafer for particle counter calibration in which a hole made of COP is formed on the surface of a silicon wafer. According to the method of manufacturing a wafer for particle counter calibration of the present invention, a wafer for particle counter calibration in which a hole made of COP is formed on the surface of a silicon wafer can be manufactured by a simple method. A usable wafer for particle counter calibration can be manufactured inexpensively and in a short time. Also, by performing particle size calibration with COP exposed on the wafer surface, even if the wafer for particle counter calibration becomes dirty, cleaning becomes possible, and there is no concern of PSL particles falling off like PSL coated wafers, It can be used for a long time.

  The particle counter calibration wafer manufactured as described above has different particles when measuring foreign particles present on the surface of the silicon wafer to be measured or depressions appearing on the surface of the silicon wafer to be measured between different particle counters. It can be used to calibrate detection sensitivity between counters. The wafer for calibrating particle counters manufactured by the manufacturing method of the present invention can be suitably used for calibration of detection sensitivity between different particle counters as described above.

  Next, with reference to FIG. 2A, a more specific example of the method of manufacturing a wafer for particle counter calibration of the present invention will be described. The flow shown in FIG. 2A is a flow when using a silicon wafer which has already been mirror-finished. That is, this embodiment is a method of utilizing a mirror surface wafer which has been completed once.

  First, as shown in S21 of FIG. 2A, a mirror-polished silicon wafer (mirror wafer) is prepared. The mirror surface wafer to be prepared at this time can be a silicon wafer manufactured through a standard mirror surface wafer manufacturing process. In the case of using such a silicon wafer, it is also possible to use a stocked wafer. The other points are the same as the silicon wafer prepared in S11 of FIG.

  Next, as shown in S22 of FIG. 2A, COP is grown on the bulk portion of the silicon wafer by annealing the mirror-polished silicon wafer. This process is the same as the annealing process of S12 of FIG.

  Next, as shown in S23 of FIG. 2A, the surface of the silicon wafer on which COP is grown is mirror-polished to form a hole made of COP in the surface of the silicon wafer. This process is also similar to the mirror polishing process of S13 of FIG.

  As described above, it is possible to produce a wafer for particle counter calibration in which a hole made of COP is formed on the surface of a silicon wafer. Further, in the present embodiment, since it is only necessary to further add the annealing step and the mirror polishing step to the standard mirror wafer manufacturing process, it is possible to manufacture at low cost and in a short time.

  Next, with reference to FIG. 2B, another specific example of the method of manufacturing a wafer for particle counter calibration of the present invention will be described. The flow shown in FIG. 2 (b) is a flow in which the annealing step is put in front of the mirror polishing step which is the final step in the standard mirror silicon wafer manufacturing process.

  First, as shown in S31 of FIG. 2B, an as-sliced wafer cut out from a silicon single crystal ingot is lapped or ground and etched, while a silicon wafer not subjected to mirror polishing is prepared. Other steps may be performed as needed. More specifically, it is possible to prepare a silicon wafer which has been subjected to etching of slicing, chamfering, lapping or surface grinding (double-head grinding), etching, and mirror polishing which is a standard mirror silicon wafer manufacturing process. In addition, if there is a double side polishing process or a back side polishing process which is not final mirror polishing between the etching process and the mirror surface polishing process, it is also possible to prepare a silicon wafer which has been subjected to the double side polishing process or the back side polishing process. The other points are the same as the silicon wafer prepared in S11 of FIG.

  Next, as shown in S32 of FIG. 2B, COP is grown on the bulk portion of the silicon wafer by annealing the silicon wafer which is not mirror-polished. This process is the same as the annealing process of S12 of FIG.

  Next, as shown in S33 of FIG. 2B, the surface of the silicon wafer on which COP is grown is mirror-polished to form holes made of COP in the surface of the silicon wafer. This process is also similar to the mirror polishing process of S13 of FIG.

  As described above, it is possible to produce a wafer for particle counter calibration in which a hole made of COP is formed on the surface of a silicon wafer. In the present embodiment, a silicon wafer which is not mirror-polished is used as a silicon wafer to be prepared, so mirror-grinding may be performed once before manufacturing a wafer for particle counter calibration. Therefore, the wafer for particle counter calibration can be produced more efficiently.

  FIG. 3 is an SEM of COP (that is, a hole exposed on the wafer surface) appearing on the wafer surface after the mirror polishing process shown in S13 of FIG. 1, S23 of FIG. 2A, and S33 of FIG. It is an example of an image. Although the size of the hole (COP) is omitted here, it can be seen that COPs of various sizes are obtained because all the main images have the same magnification. An important factor as a wafer for calibration of particle counters is a wafer coated with PSL or a calibration wafer manufactured by the manufacturing method of the present invention, the point of use (the surface of the wafer actually measured) There is a PSL size and a hole size (the size of COP appearing on the surface) close to the foreign matter and the depression on the wafer. Therefore, as shown in FIG. 3, it is better that holes of various sizes (COP appearing on the surface) be present. In addition, when holes of different sizes (COP appearing on the surface) are required, the temperature and holding time in the above-mentioned annealing step may be changed, and further, the polishing allowance in the mirror polishing step may be changed. . At this time, if an example is specifically given about a use point, the range of 20 nm-80 nm is preferable.

  FIG. 4 is an example of an image obtained by observing COP appeared on the wafer surface after mirror polishing by AFM (Atomic Force Microscope). FIG. 5 is an example in which the hole diameter of COP is measured by AFM for COP shown in FIG. Here, in FIG. 5, the distance between two upward triangles (Δ) corresponds to the hole diameter of COP. As described above, by observing a plurality of COPs shown in FIG. 3 by AFM and measuring the hole diameter, the measured value becomes a reference value for particle counter calibration.

  In the above, the hole diameter of COP was measured by AFM, but if the measured value is reliable and the hole diameter of the point of use can be measured, for example, a laser microscope, SEM, etc. can also be used. However, it is a condition that a mirror surface wafer can be measured nondestructively.

  EXAMPLES The present invention will be more specifically described below with reference to examples and comparative examples, but the present invention is not limited to these.

(Example)
Two mirror surface wafers obtained from a silicon single crystal ingot 300 mm in diameter grown by the CZ method (Czochralski method) were prepared. Here, the manufacturing flow of the particle counter calibration wafer is shown in FIG. 2A, and is a mirror surface silicon wafer which is in stock (the defect area is the V area and the oxygen concentration is 14 ppma (JEIDA) ) Was used.

  The annealing step was performed in an argon atmosphere, and the annealing recipe shown in FIG. 6 was used. That is, the maximum temperature of the heat treatment is 1200 ° C., and the holding time at the maximum temperature is 1 hour. The next mirror polishing step was performed by CMP processing, one was polished with an aim of 0.5 μm for polishing removal, and the other was polished with an aim of 2 μm for polishing removal. Here, the reason for changing the polishing conditions (polishing removal amount) between two wafers is to obtain various COP sizes as the size of COP exposed on the wafer surface.

  A laser defect inspection review device M5640 manufactured by Lasertec Corporation was used to identify the COP appearing on the wafer surface. In this apparatus, it is possible to roughly determine the position (coordinates) of a defect present on the wafer surface and whether the defect is a foreign substance (convex) or a dent (concave).

  However, when it is desired to specify COP as in the present invention, it is possible to specify COP by using a so-called review SEM which can specify defect coordinates using defect coordinate information measured by M 5640 described above. Become. An example of the image is the SEM image shown in FIG. The review SEM used in this example is RS-5000 manufactured by Hitachi High-Technologies Corporation.

  With regard to defects that could be identified as COP, COP was observed by AFM as shown in FIG. 4, and the hole diameter of COP was measured as shown in FIG. From the two wafers prepared this time, the hole diameter of COP at each 2 points was measured, and the hole diameter of COP obtained from the wafer polished with a polishing allowance of 2 μm was 26 nm and 42 nm, and polishing was performed with a polishing allowance of 0.5 μm. The hole diameters of COP obtained from the obtained wafer were 65 nm and 78 nm. Here, AFM used Park Systems, Inc. XE-WAFER.

  The two silicon wafers were used as particle counter calibration wafers. The results of measuring these two wafers with the particle counter to be calibrated are shown in FIG.

  In the present embodiment, calibration was performed for two particle counters. Here, one of the two units is indicated as a unit A and the other as a unit B. First of all, regarding the unit A, the difference between the COP hole diameter of the wafer for particle counter calibration and each point of the defect size indicated by the unit A is at most about 2 nm, and the slope of the correlation graph almost agrees with 0.99.

  Next, in Unit B, if the particle diameter of the particle counter calibration wafer is smaller than 60 nm, the defect size shown by Unit A is smaller, and if the particle diameter of the particle counter calibration wafer is larger than 60 nm, Unit A It was found that the size of the defect was measured to be larger than that of From the graph of FIG. 7 also, it is found that there is almost no difference from the COP hole diameter near 60 nm, but the COP hole diameter can not be determined correctly as the distance from 60 nm increases. In addition, it was found that the slope of the correlation graph is obviously different from that of the 1.18 car as compared with the A car. Therefore, it was confirmed that the measurement result similar to that of the unit A can be obtained by calibrating the unit B.

  FIG. 8 shows the result of the cleaning test assuming long-term use. The wafer used for the cleaning test is one of the two shown above. The washing conditions are: ammonia water (concentration: 28%), hydrogen peroxide solution (concentration: 30%), washing solution using water: the ratio is 1: 1: 10, the temperature is 70 ° C., and the sample wafer with this washing solution Retention time was 3 minutes. The particle counter used before and after cleaning is SurfScan SP3 manufactured by KLA-Tencor. As shown in FIG. 8, the number of defects in the sample wafer of the example was 204 without change in the number of defects before and after cleaning.

(Comparative example)
PSL particles of 37 nm to 88 nm were coated on the wafer, and then held for 3 minutes at a baking temperature of 200 ° C. to prepare a wafer for particle counter calibration of a comparative example. The wafer for calibrating the particle counter of the comparative example manufactured in this manner was also subjected to the cleaning test simultaneously with the above example. The washing conditions are the same as in the previous example. The number of counts before and after washing was confirmed with the particle counter SurfScan SP3 in the same manner as in the example, and as shown in FIG. Dropout of particles was confirmed.

  From the above results, it was possible to calibrate the particle counter using the wafer for calibrating the particle counter fabricated by the fabrication method of the example. Specifically, in the case of the present embodiment, calibration could be added to the unit B. In addition, I was able to understand the machine difference between the A and B units. Furthermore, in the cleaning test, the particle counter calibration wafer (PSL coated wafer) of the comparative example is confirmed to come off PSL particles, and there is concern about long-term use, while the particle counter calibration wafer of the example has a count number It has been proved that long-term use is possible without change.

  The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and it has substantially the same configuration as the technical idea described in the claims of the present invention, and any one having the same function and effect can be used. It is included in the technical scope of the invention.

Claims (9)

A method of manufacturing a wafer for particle counter calibration, comprising:
Preparing a silicon wafer;
Growing COP on a bulk portion of the prepared silicon wafer by annealing the prepared silicon wafer;
Forming a hole made of the COP on the surface of the silicon wafer by mirror-polishing the surface of the silicon wafer on which the COP has been grown;
What is claimed is: 1. A method of producing a particle counter calibration wafer comprising producing a particle counter calibration wafer having a hole made of the COP formed on the surface of the silicon wafer.   The method for producing a particle counter calibration wafer according to claim 1, wherein the silicon wafer to be prepared is a mirror-polished silicon wafer.   An as-sliced wafer cut out from a silicon single crystal ingot is lapped or ground and etched while being prepared, and the silicon wafer to be prepared is a silicon wafer which has not been mirror-polished. Method of preparing wafer for particle counter calibration.   The method for producing a particle counter calibration wafer according to any one of claims 1 to 3, wherein the silicon wafer to be prepared has an oxygen concentration of 13 ppma (JEIDA) or more.   The method for producing a particle counter calibration wafer according to any one of claims 1 to 4, wherein the silicon wafer to be prepared has a defect area of a V area.   The particle according to any one of claims 1 to 5, wherein when the annealing is performed, the annealing is performed under the condition that a COP of 20 to 80 nm in size is grown in the bulk of the silicon wafer. Method of manufacturing wafer for counter calibration.   The method for producing a particle counter calibration wafer according to any one of claims 1 to 6, wherein the annealing is performed in an argon atmosphere.   When mirror-polishing the surface of a silicon wafer on which COP has been grown, mirror-polishing is performed so that COP of a size of 20 to 80 nm is exposed on the surface of the silicon wafer. The manufacturing method of the wafer for particle counter calibration as described in any one of these.   The particle counter calibration wafer detects foreign particles present on the surface of the silicon wafer to be measured or the depressions appearing on the surface of the silicon wafer to be measured between different particle counters when measuring between the different particle counters. The method for producing a particle counter calibration wafer according to any one of claims 1 to 8, wherein the method is used for calibration of sensitivity.