JP2006108151A - Method of manufacturing silicon epitaxial wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon epitaxial wafer which can correctly inspect local crystal defects, etc. by an easy operation and eventually can keep a loss caused by unnecessary mirror polishing and epitaxial growth process performed on a defective chemical etch wafer lot to the minimum. <P>SOLUTION: Some of wafers are picked up as sample wafers from the chemical etch wafer lot. These sample wafers are first formed with a silicon epitaxial layer for inspection and then are inspected. By forming the silicon epitaxial layer for inspection on the sample wafers, minute crystal defects existing on the surface of the wafers which are in a state of chemical etch wafers are enlarged in size on the basis of a crystal growth mechanism and thereby can be very easily observed, which remarkably increase the inspection accuracy. Consequently, a loss due to inspection failure (a loss due to calling-back of defective products shipped and compensation for these products, and a loss due to rejection of good products) can be remarkably reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a silicon epitaxial wafer.

JP-A-3-295235 JP 2002-350731 A

  A silicon epitaxial wafer obtained by vapor-phase growth of a silicon single crystal thin film on a silicon single crystal substrate (hereinafter also simply referred to as “epi wafer”) is usually manufactured according to the following steps. First, a silicon single crystal ingot manufactured by a CZ (Czochralski) method is sliced using a slicer. The wafer after slicing is chamfered at the edge, then lapped on both sides and further subjected to chemical etching. The wafer after chemical etching is further subjected to mirror polishing by mechanical chemical polishing (hereinafter, the wafer after mirror polishing is also referred to as mirror wafer), and then an epitaxial growth process for vapor-phase growth of a silicon epitaxial layer (in this industry) In many cases, the process is often referred to as an “epi growth process”. In addition, between these processes, there are processes such as cleaning and drying, as well as a process for imparting so-called external gettering such as donor killer heat treatment and sandblasting before mirror polishing of the chemically etched wafer. May be pinched.

  Among the above processes, in the slicing process, chamfering process, and double-sided lapping process, a processed strain layer is formed on the surface of the wafer. Further, through these steps, crystal defects such as dislocations may occur in the bulk region near the wafer surface. Furthermore, in these processes, since the cutting tool or metal lap surface plate made of diamond abrasive grains and the wafer come into contact with each other, the metal atoms present on the surface of the bond material and the metal lap surface plate fixing the diamond, There is a possibility of entering the inside of the wafer through contact with the wafer. Therefore, after double-sided lapping, the wafer is subjected to acid etching or alkali etching to remove a processing strain layer, crystal defects, and metal impurities existing on the wafer surface or in the vicinity of the wafer to produce a chemically etched wafer.

  The chemically etched wafer is sent to the next mirror polishing step, but there may be a step of inspecting the thickness or the like of the chemical etched wafer before the mirror polishing step. At this time, the quality of the chemically etched wafer may be inspected to examine the influence on the subsequent mirror polishing process. Chemical etch wafer inspection methods include visual observation under a condensing lamp or fluorescent lamp, and magnified observation with a microscope, which may cause processing distortion and local metal contamination that may remain on the surface of the chemical etch wafer. Inspect for local crystal defects.

  However, in the chemical etching process, the quality of the wafer, for example, surface roughness and glossiness, undulation of the entire wafer, due to differences in chemical solutions such as alkaline aqueous solution and acid aqueous solution, chemical composition, and etching amount, etc. A difference may appear in the wafer shape. Therefore, it is difficult to inspect a chemically etched wafer based on a certain standard. In addition, chemical etch wafers have a problem that the surface roughness is much larger than that of mirror-polished silicon single crystal wafers, so measurement devices such as particle counters cannot be used and quantitative observation is not possible. . Furthermore, in the case of investigating the distribution of defects on the surface of chemically etched wafers or comparing the distribution of defects between wafers, the inspection method as described above must be very cumbersome, and the operator himself There is also a possibility that an error may occur due to misidentification of.

  The object of the present invention is to accurately inspect simple processing for processing distortion, local metal contamination, and local crystal defects that may exist on the wafer regardless of the quality difference between chemically etched wafers. Therefore, it is an object of the present invention to provide a method for manufacturing a silicon epitaxial wafer capable of minimizing the loss caused by performing unnecessary mirror polishing and epi-growth processes on defective chemical etch wafer lots.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, a method for producing a silicon epitaxial wafer of the present invention is as follows.
A method of manufacturing a silicon epitaxial wafer as a lot consisting of a plurality of wafers,
A slicing step of obtaining a plurality of lot wafers by slicing from a silicon single crystal ingot;
Lapping process for lapping lot wafers;
Cleaning process for cleaning lot wafers after lapping,
Chemical etching process to make a chemical etch lot wafer by applying chemical etching to the lot wafer after the cleaning process,
An inspection epitaxial growth process for extracting an inspection sample wafer from the chemical etch lot wafer and growing an inspection silicon epitaxial layer on the sample wafer;
A sampling inspection process for inspecting a crystal defect appearing on the surface of the silicon epitaxial layer for inspection of the sample wafer by a crystal defect inspection apparatus, and determining whether the chemical etch lot wafer is acceptable or not based on the inspection result;
Mirror polishing process to make a mirror polishing lot wafer by performing mirror polishing only on chemical etch lot wafers that have been determined to pass based on the inspection result of the sample wafer,
A product epitaxial process for growing a product silicon epitaxial layer on a mirror polished lot wafer is performed in this order.

  As a result of repeating the test in order to solve the above problems, the present inventors perform epitaxial growth on the main surface of the chemical etch lot wafer and then inspect the surface with a known crystal defect measuring device such as a particle counter. Thus, the inventors have conceived that crystal defects can be inspected more easily and accurately than when the main surface of the chemical etch lot wafer is directly measured, and the present invention has been completed.

  A chemical etch lot wafer has a problem that it is difficult to detect a surface crystal defect when it is directly inspected by a crystal defect measuring apparatus as in the prior art. In this case, not only simply the inspection takes time, but also the detection accuracy itself is lowered, so that there is a possibility that the economic loss when viewed as the entire manufacturing process of the epitaxial wafer becomes very large. For example, despite the fact that many crystal defects exist, if this is overlooked and used for the subsequent processes to make an epitaxial wafer, the high-cost mirror polishing process and epitaxial growth process were performed over the entire lot wafer. In addition, the lot must be discarded as defective, and the loss when the inspection fails is too great.

  However, according to the method of the present invention, a part of a chemical etch lot wafer is extracted as a sample wafer, and an inspection silicon epitaxial layer is grown thereon, and then inspection is performed. The minute crystal defects that existed on the surface in the state of a chemically etched wafer can be observed very easily because the dimensions are enlarged based on the crystal growth mechanism by growing a silicon epitaxial layer for inspection. Since accuracy is greatly improved, loss due to inspection failure (recovery and compensation problems due to defective product shipment, loss due to rejection of non-defective products) can be greatly reduced. In addition, since epitaxial growth is aimed at expanding crystal defects, it is not necessary to perform mirror polishing before growth, and only the number required for lot inspection (of course, a plurality of pieces) may be extracted and used for inspection. Since the layer grows, even if it is judged as defective, it is possible to eliminate unnecessary processes compared with the case where the entire surface is mirror-polished / epi-grown and then inspected and determined as defective. become.

  Patent Document 1 discloses a method for manufacturing a silicon epitaxial wafer in which mirror polishing is omitted and a silicon epitaxial layer is directly grown on a chemically etched wafer. However, the present invention discloses mirror polishing after the growth of a silicon epitaxial layer. The purpose is to improve the flatness of the silicon epitaxial layer, and in consideration of the function of mirror polishing in the final process, mirror polishing before epi growth is simply omitted to simplify the process. Not too much. Therefore, a silicon epitaxial layer is grown on the entire number of lots for chemically etched wafers. For the purpose of improving the detection accuracy of crystal defects as in the present invention, a portion of the lot is sampled and silicon epitaxial layers for inspection are used. There is no disclosure of the concept used to grow a layer and feed back the inspection results to the remaining chemically etched wafer of the lot to determine whether to continue the subsequent mirror polishing and epi-growth steps.

  As a crystal defect measuring apparatus used in the present invention, a laser microscope using a laser confocal method disclosed in Patent Document 2 can be used in addition to a known particle detecting apparatus.

  Next, in the sampling inspection step, it is desirable that the inspection silicon epitaxial layer is inspected for crystal defects by a crystal defect inspection apparatus after the surface is polished. Polishing the surface of the silicon epitaxial layer for inspection makes it easier to observe defects and the like than directly inspecting and inspecting the chemically etched surface. Even if each chemical etch wafer to be inspected has a different chemical solution, chemical composition, and etching amount, the epitaxial layer grows on the main surface to be observed. Since the surface of the epitaxial layer is polished, these differences can be eliminated, and an inspection that can easily compare wafers can be performed.

  Chemical-etched lot wafers that have been rejected in the sampling inspection process have lots of crystal defects, and if it is determined that they cannot be repaired, etc. can do. As a result, a large number of lot wafers can be rejected at the stage of chemical etching, and a high value-added mirror polishing process and product epi growth process can be avoided.

  On the other hand, although it is difficult to commercialize the product as it is, if it is judged that the formation of crystal defects is relatively minor, the chemical etch lot wafer that has been rejected in the sampling inspection process will be rejected. The process from one of the lapping process to the chemical etching process to the chemical etching process is performed again as a lot correction process under process conditions that have been changed so that crystal defects are reduced compared to a chemical etch lot wafer. You can also After this, the sample wafer is again extracted, and the above-described sampling inspection process is performed again. If it passes, the subsequent mirror polishing process and product epi-growth process are completed, and if the product is completed, the crystal is crystallized before product epi-growth. Since the defect removal can be corrected, it contributes to the reduction of the defect occurrence rate and the lot-out occurrence frequency in the final product.

  Hereinafter, although the manufacturing method of the silicon epitaxial wafer of this invention is demonstrated with reference to drawings, it cannot be overemphasized that this invention is not limited to this. FIG. 1 is a process flow diagram, and FIG. 2 is a schematic diagram showing an outline of a typical process. First, a silicon single crystal wafer as a material for a silicon epitaxial wafer is prepared. This silicon single crystal wafer is manufactured as follows. First, a silicon single crystal ingot pulled up by a CZ method from a silicon melt in which a dopant is added so as to have a predetermined conductivity type and resistivity in advance, is cylindrically ground with the axis of the pulling direction as the axis of rotation, Subsequently, the cylindrical outer peripheral portion along the axial direction is subjected to a cutting process to indicate the orientation to obtain a silicon single crystal block. By slicing the silicon single crystal block, a plurality of lot wafers are obtained (S1; slicing step).

The lot wafer obtained by slicing is chamfered and then double-sided lapped (S3: lapping step). The lapping abrasive grains are, for example, mixed abrasive grains of alumina and zirconia, and the counts of the abrasive grains are in the range of # 600 to # 4000. After this lapping, cleaning is performed using a cleaning liquid containing sodium hydroxide as a main component (S4: cleaning step), and a chemical etching lot wafer is obtained by performing the chemical etching step of S5. Chemical etching includes acid etching using a mixed acid aqueous solution of hydrofluoric acid, nitric acid, and acetic acid, alkaline etching using a caustic soda (NaOH) aqueous solution or a tetramethylammonium hydroxide (TMAH: (CH ₃ ) ₄ NOH) aqueous solution, and It can be implemented by a combination of both. The etching time is adjusted so that the etching allowance for the both surfaces is in the range of, for example, 5 to 50 μm (more desirably 20 to 50 μm).

The chemical etch lot wafer is temporarily inspected here for inspection. For inspection, a sample wafer is extracted from a plurality of chemical etch lot wafers, and an epitaxial layer for inspection is grown without applying mirror polishing to the sample wafer. Specifically, as shown in FIG. 3, a sample wafer 14 is placed in a reaction vessel 11 and heated to 1000 ° C. or higher with a heating device (not shown), and at the same time, a silicon source such as trichlorosilane (TCS: SiHCl ₃ ). The main surface of the sample wafer is introduced into the reaction vessel 11 while being diluted with a gas, a dopant gas such as diborane (B ₂ H ₆ ) or phosphine (PH ₃ ), and a carrier gas (for example, hydrogen (H ₂ ) gas). A silicon epitaxial layer for inspection is grown. The thickness of the silicon epitaxial layer for inspection is larger than the polishing allowance for inspection described later, and can be expanded to such an extent that minor crystal defects formed on the surface of the chemically etched wafer can be easily observed, and In order not to become unnecessarily too thick, for example, it is preferable to adjust in a range of 2 μm to 20 μm. The epitaxial growth apparatus used may be a vertical type as shown in FIG. 3, or may be a cylinder type or a single wafer type.

The inspection silicon epitaxial layer may be subjected to crystal defect measurement as it is, but in this embodiment, the surface of the inspection silicon epitaxial layer is mirror-polished with a mirror polishing apparatus in order to make the crystal defect easier to observe ( S21: Polishing step) Mirror polishing is a so-called chemical machine in which a rotary table is rotated while supplying a polishing liquid containing abrasive particles such as colloidal silica mainly composed of SiO ₂ and an alkaline liquid to a polishing cloth. By mechanical polishing. In this case, known three- to four-step mirror polishing may be performed, or only the secondary polishing and the final polishing may be performed without performing the primary polishing. The polishing amount is suitably 1 μm or more and 15 μm or less, but in order to make the defect enlargement effect remarkable, the residual thickness of the inspection silicon epitaxial layer after polishing is preferably 1 μm or more and 19 μm or less.

  The inspected silicon epitaxial layer after polishing is inspected and determined for crystal defects using a known particle detector (S22). The particle detector scans the surface of the wafer with laser light and measures the light scattering intensity from the particles, etc., so that the position and size of foreign matter and COP can be recognized. Device. By using such a light scattering method, only defects near the surface of the semiconductor wafer can be accurately measured. Specifically, the position and size of particles on the wafer surface can be measured by scanning the wafer surface with a laser beam and measuring the light scattering intensity from irregularities such as particles. Since the crystal defect also has unevenness, the scattered light intensity is detected as a particle higher than the surrounding portion, and coordinate data indicating the particle position is acquired as crystal defect detection point data. In addition to the particle detector, a laser microscope using a laser confocal method disclosed in Patent Document 2 can be used.

  In crystal defect inspection of a silicon epitaxial layer for inspection, for example, when a number (or density) of crystal defects exceeding the first number threshold is detected, or when a crystal defect exceeding the first dimension threshold is detected Then, it is determined to be defective. Then, when a plurality of sample wafers are extracted from one lot and the number of sample wafers determined to be defective exceeds the allowable number, the entire lot is determined to be defective (S6, S7). On the other hand, if the sample wafer judged as defective does not exist or is less than the allowable number, it is judged as acceptable and mirror polishing (primary polishing + (Secondary polishing) is performed (S8), and an epitaxial growth process for products is further performed (S9). All lots of product silicon epitaxial wafers obtained by the implementation of the product epi-growth process are inspected and then shipped.

  On the other hand, when a defect is determined, the number of sample wafers determined to be defective exceeds a limit value, or the position of the sample wafer in the ingot (for example, not only near a specific position but also over the entire length of the ingot In addition, if the formation density and size of crystal defects in the sample wafer exceed the second threshold set higher than the pass / fail judgment threshold, the correction cannot be made. And lot-out is determined (S12).

  On the other hand, when it is determined that it can be corrected (for example, when it is determined that a crystal defect mainly caused by improper processing conditions is the main cause), the crystal defect is higher than the chemical etch lot wafer that is determined to be rejected. In the process conditions changed so as to decrease, the process may be re-executed only from the lapping process to the chemical etching process (S3 to S5) to the chemical etching process (S5: chemical etching process only). It is also possible to re-execute the process leading to (a) as a lot correction process. Thereafter, the sample wafer is extracted again, and the above-described sampling inspection process is performed again (S20 to S22). If it passes, the subsequent mirror polishing process and product epi-growth process are performed.

  The lot correction process may include a lapping process using lapping abrasive grains (for example, # 600 to # 4000 in the count) smaller than that at the time of manufacturing the chemically-etched lot wafer determined to be rejected (S14). By reducing the average grain size of the lapping abrasive grains, it is possible to reduce the introduction of crystal defects accompanying the biting of the lapping abrasive grains. In addition, the cleaning and chemical etching process performed after the lapping process may be performed under the same conditions as the first process, or may be performed by changing the conditions so as to suppress the occurrence of defects as described below. . The lot correction process can also be implemented as including a cleaning process that is extended in time from the time of manufacture of the chemically-etched lot wafer determined to be rejected (S15). By extending the cleaning time, it is possible to reduce the frequency of occurrence of crystal defects due to residual foreign matter.

  Further, the lot correction step includes a chemical etching step in which the etching allowance is increased (for example, 5 to 50 μm in total on both sides, more preferably 20 to 50 μm) compared to the manufacturing time of the chemically etched lot wafer determined to be rejected. (S16). As a result, the processing damage layer can be etched deeper, and residual crystal defects can be suppressed. The lot correction process may be performed only by this chemical etching process, or may be started from a lapping process preceding this.

  EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these. 100 lap wafers were manufactured by slicing, chamfering, and lapping on a silicon single crystal ingot manufactured by the Czochralski method having a p-type conductivity, a diameter of 200 mmφ, and a crystal orientation <100>. Next, these wafers were immersed in an aqueous NaOH solution having a liquid temperature of 85 ° C. and a concentration of 55% by weight for 450 seconds to perform an alkali etching treatment. The etching amount by alkali etching at this time was 20 μm in total on the main surface and the main back surface. The wafer subjected to the above treatment is dipped in a mixed acid obtained by mixing 50% by volume of hydrofluoric acid, 70% by volume of nitric acid, and 99% by volume of acetic acid in a ratio of 1: 2: 1 for 10 seconds to perform an acid etching process. A chemically etched wafer was prepared. The etching amount by acid etching at this time was 10 μm in total for the main surface and the main back surface, and the total etching amount of alkali etching and acid etching was 30 μm.

  Three of the above chemically-etched wafers are put into an epitaxial growth apparatus as shown in FIG. 3 and heated to 1130 ° C. Then, trichlorosilane as a silicon source gas and diborane as a dopant gas together with hydrogen gas as a carrier gas. Epitaxial growth was carried out by introducing into a reaction vessel, and a 20 μm inspection silicon epitaxial layer was formed on the main surface of the chemically etched wafer.

  Further, the surface of the silicon epitaxial layer for inspection is mirror-polished so that the total polishing amount is about 4 μm with a secondary polishing apparatus in which SUBA400 is bonded to the polishing surface plate and a final polishing apparatus in which Seagull 7355 is bonded to the polishing surface plate. Polished. When the mirror-polished polishing silicon epitaxial layer surface was measured with a particle counter (particle counter SP-1 manufactured by KLA-Tencor), 11 to 20 LPDs were counted. Two of the seven chemically etched wafers epitaxially grown on silicon were extracted, and the main surface of the wafer was observed with a laser confocal microscope MAGICS manufactured by Lasertec Corporation. As a result, 214 defects were found in one wafer. Was counted. Of these defects, 100 were observed in descending order with another high-sensitivity laser microscope. The breakdown was 3 stacking faults (FIG. 4A), 12 linear defects (FIG. 4B), and micro-LPD (Light Point Defect). : FIG. 4C) was 85 pieces. In the other wafer, 118 defects were counted by observation with MAGICS. When 100 of these defects were observed in the descending order with a high-sensitivity laser microscope, the breakdown was 4 stacking faults, 18 linear defects, and 78 fine LPDs.

  Although the surface of the chemically etched wafer was directly measured with a particle counter, MGICS, and high sensitivity laser microscope without forming a silicon epitaxial layer for inspection, it was impossible to detect defects.

The process flowchart which shows an example of the manufacturing method of the silicon epitaxial wafer of this invention. The process schematic diagram which shows an example of the manufacturing method of the silicon epitaxial wafer of this invention. It is a composition schematic diagram showing an example of an epitaxial growth device. The image which shows the example of a measurement of the stacking fault by a particle counter. The image which shows the example of a measurement of the linear defect by a particle counter. The image which shows the measurement example of minute LPD by a particle counter.

Claims (7)

A method of manufacturing a silicon epitaxial wafer as a lot consisting of a plurality of wafers,
A slicing step of obtaining a plurality of lot wafers by slicing from a silicon single crystal ingot;
A lapping process for lapping the lot wafer;
A cleaning process for cleaning the lot wafer after the lapping process,
Chemical etching process to make a chemical etch lot wafer by applying chemical etching to the lot wafer after the cleaning process,
An inspection epitaxial growth step of extracting a sample wafer for inspection from the chemical etch lot wafer and growing a silicon epitaxial layer for inspection on the sample wafer;
Inspecting the crystal defects appearing on the surface of the silicon epitaxial layer for inspection of the sample wafer by a crystal defect inspection apparatus, and a sampling inspection step for determining pass / fail of the chemical etch lot wafer based on the inspection result;
Mirror polishing process to make a mirror polishing lot wafer by performing mirror polishing only on the chemical etch lot wafer that has been determined to pass based on the result of the inspection of the sample wafer,
A product epi process for growing a product silicon epitaxial layer on the mirror polished lot wafer;
Are performed in this order. A method for producing a silicon epitaxial wafer, wherein: 2. The method of manufacturing a silicon epitaxial wafer according to claim 1, wherein in the sampling inspection step, the inspection silicon epitaxial layer is subjected to inspection of crystal defects by the crystal defect inspection apparatus after polishing the surface thereof. 3. The method for producing a silicon epitaxial wafer according to claim 1, wherein the chemical-etched lot wafer determined to be rejected in the sampling inspection process is made a lot-out in a form in which a productizing process subsequent to the mirror polishing process is omitted. . From the lapping step to the chemical etch lot wafer that has been determined to be rejected in the sampling inspection process, the process conditions have been changed so that crystal defects are reduced compared to the chemical etch lot wafer that has been determined to be rejected. The method for manufacturing a silicon epitaxial wafer according to any one of claims 1 to 3, wherein a process from any process up to the chemical etching process to the chemical etching process is performed again as a lot correction process. The said lot correction process is a manufacturing method of the silicon epitaxial wafer of Claim 4 including the lapping process using the lapping abrasive grain smaller than the time of manufacture of the said chemical etch lot wafer determined to be unacceptable. 6. The method for manufacturing a silicon epitaxial wafer according to claim 4, wherein the lot correction step includes a cleaning step that is extended in time from the time of manufacturing the chemically-etched lot wafer determined to be rejected. 7. The silicon epitaxial wafer according to claim 4, wherein the lot correction step includes a chemical etching step in which an etching allowance is increased as compared with a manufacturing time of the chemical etch lot wafer determined to be rejected. Manufacturing method.

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