JP6505769B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a field effect transistor.

A transistor used in many flat panel displays represented by a liquid crystal display device and a light emitting display device is formed of a silicon semiconductor such as amorphous silicon, single crystal silicon or polycrystalline silicon formed on a glass substrate. . In addition, transistors using the silicon semiconductor are also used in integrated circuits (ICs) and the like.

In recent years, in place of silicon semiconductors, a technique using a metal oxide exhibiting semiconductor characteristics for a transistor has attracted attention. Note that in this specification, a metal oxide exhibiting semiconductor characteristics is referred to as an oxide semiconductor.

For example, a technology is disclosed in which a transistor including zinc oxide or an In—Ga—Zn-based oxide is manufactured as an oxide semiconductor and the transistor is used as a switching element of a pixel of a display device (Patent Document 1) And Patent Document 2).

Unexamined-Japanese-Patent No. 2007-123861 JP 2007-96055 A

In the transistor including an oxide semiconductor, fluctuation of the threshold voltage of the transistor and the trap state (also referred to as interface state) in the interface between the oxide semiconductor film and the gate insulating film or in the gate insulating film This causes an increase in the subthreshold coefficient (S value) indicating the gate voltage required for the drain current to change by an order of magnitude when the transistor is turned on. As a result, there is a problem that the electrical characteristics vary among the transistors.

In addition, when trap states are included in the interface between the oxide semiconductor film and the gate insulating film or in the gate insulating film, electrical characteristics of the transistor can be reduced typically by a change over time or a light-gate BT (Bias-Temperature) stress test. There is a problem that the threshold voltage may fluctuate.

Therefore, an object of one embodiment of the present invention is to improve electrical characteristics in a semiconductor device using an oxide semiconductor. Another object is to manufacture a highly reliable semiconductor device with little change in electrical characteristics due to change over time or an optical gate BT stress test.

One embodiment of the present invention is a transistor including a gate electrode, an oxide semiconductor film which overlaps with part of the gate electrode with a gate insulating film interposed therebetween, and a pair of electrodes in contact with the oxide semiconductor film; It is characterized in that one or more of the insulating films in contact are formed of an insulating film which has a high film density and which has few defects.

One embodiment of the present invention is a transistor including a gate electrode, an oxide semiconductor film overlapping with part of the gate electrode with a gate insulating film interposed therebetween, and a pair of electrodes in contact with the oxide semiconductor film, film density is below 2.26 g / cm ³ or more 2.63 g / cm ^3, in the signal measured by the electron spin resonance method, g values are the spin density of 2 × ¹⁰ 15 of the signal appearing at 2.001 spins / It is characterized in that it is formed of an insulating film which is cm ³ or less.

One embodiment of the present invention includes a gate electrode, an oxide semiconductor film overlapping with a part of the gate electrode with the gate insulating film interposed therebetween, a pair of electrodes in contact with the oxide semiconductor film, and a gate insulating film of the oxide semiconductor film an insulating film in contact in the plane opposite to the surface in contact, in a transistor having a gate insulating film and the insulating film, the film density is at 2.26 g / cm ³ or more 2.63 g / cm ³ or less, by electron spin resonance A signal to be measured is formed using an insulating film in which a spin density of a signal whose g value appears at 2.001 is 2 × 10 ¹⁵ spins / cm ³ or less.

Note that the gate insulating film and the insulating film in contact with the oxide semiconductor film on the surface opposite to the gate insulating film are silicon oxide or silicon oxynitride.

In a transistor including an oxide semiconductor film, the use of an insulating film with high film density and few defects as an insulating film in contact with the oxide semiconductor film reduces variation in threshold voltage of the transistor and variation in electrical characteristics. It is possible to manufacture a transistor having few and excellent electrical characteristics. In addition, a highly reliable transistor with little change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. FIG. 7 is a cross-sectional view illustrating one embodiment of a method for manufacturing a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 7 is a cross-sectional view illustrating one embodiment of a method for manufacturing a transistor. 7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. FIG. 7 is a cross-sectional view illustrating one embodiment of a method for manufacturing a transistor. 7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. 7A and 7B are a top view and a cross-sectional view illustrating one embodiment of a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a transistor. FIG. 5 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 5 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 1 is a block diagram illustrating an embodiment of a semiconductor device. FIG. 1 is a block diagram illustrating an embodiment of a semiconductor device. FIG. 1 is a block diagram illustrating an embodiment of a semiconductor device. It is a figure explaining the spin density of a sample. It is a figure explaining the film density of a sample. It is a figure explaining the fluctuation | variation of the threshold voltage of a transistor.

Hereinafter, embodiments and examples of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it can be easily understood by those skilled in the art that various changes can be made in the form and details without departing from the spirit of the present invention and the scope thereof. Therefore,
The present invention should not be construed as being limited to the description of the embodiments and examples given below. In the embodiments and examples described below, the same reference numerals or the same hatch patterns are used in common in different drawings for the same portions or portions having similar functions, and the repetitive description thereof is omitted. Do.

It should be noted that in the figures described herein, the size of each component, the thickness of the film, or the area may be exaggerated for clarity. Therefore, it is not necessarily limited to the scale.

Further, the terms first, second, third and the like used in the present specification are given to avoid confusion of components, and are not limited numerically. Therefore, for example, "first"
The description can be appropriately replaced with the second "or" or the like.

The functions of "source" and "drain" may be switched when the direction of current changes in circuit operation. Therefore, in the present specification, the terms "source" and "drain" can be used interchangeably.

In this specification, in the case where the etching step is performed after the photolithography step,
The mask formed in the photolithography step is to be removed after the etching step.

Embodiment 1
In this embodiment mode, a semiconductor device which is one embodiment of the present invention and a manufacturing method of the semiconductor device are described with reference to drawings.

1A to 1C illustrate a top view and a cross-sectional view of the transistor 10 included in the semiconductor device. 1A is a top view of the transistor 10, FIG. 1B is a cross-sectional view taken along dashed-dotted line A-B in FIG. 1A, and FIG. 1C is a cross-sectional view of FIG. ) Is a cross-sectional view taken along the alternate long and short dash line C-D. Note that in FIG. 1A, the substrate 11, the base insulating film 13, part of components of the transistor 10 (eg, the gate insulating film 17), the insulating film 23, and the like are omitted for clarity.

The transistor 10 illustrated in FIGS. 1B and 1C includes a gate electrode 15 formed over the base insulating film 13, a gate insulating film 17 formed over the base insulating film 13 and the gate electrode 15, and The oxide semiconductor film 19 overlapping with the gate electrode 15 and the pair of electrodes 21 in contact with the oxide semiconductor film 19 are provided with the gate insulating film 17 interposed therebetween. In addition, an insulating film 23 which covers the gate insulating film 17, the oxide semiconductor film 19, and the pair of electrodes 21 is provided.

In the transistor 10 described in this embodiment, the gate insulating film 17 is formed of an insulating film with high film density and few defects. Typically, the film density of the gate insulating film 17 is 2.26 g
/ Cm ³ or more, theoretical film density 2.63 g / cm ³ or less, preferably 2.30 g / cm
The film density is ³ or more and 2.63 g / cm ³ or less, and the film density of the gate insulating film 17 is high. In addition, in the signal measured by electron spin resonance (ESR), the spin density of the signal appearing at E′-center (g value is 2.001) indicating a tongue ring bond of silicon is 2 × 10 ^1
5 spins / cm ³ or less, more preferably the lower detection limit (1 × 10 ¹⁵ spins / cm
³ ) or less, and dangling bonds of silicon contained in the gate insulating film 17 are extremely small. Therefore, the threshold voltage of the transistor 10 including the gate insulating film 17 does not fluctuate significantly, and the transistor 10 has excellent electrical characteristics.

As an insulating film to be the gate insulating film 17, for example, silicon oxide, silicon oxynitride or the like having a thickness of 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 50 nm to 250 nm can be used.

Details of other configurations of the transistor 10 will be described below.

The material of the substrate 11 and the like are not particularly limited, but at least the heat resistance needs to be sufficient to withstand the subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 11. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI
It is also possible to apply a substrate or the like, and those in which semiconductor elements are provided on these substrates,
It may be used as the substrate 11.

Alternatively, a flexible substrate may be used as the substrate 11, and the base insulating film 13 and the transistor 10 may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 11 and the base insulating film 13. The peeling layer is formed on the substrate 11 after the semiconductor device is partially or completely completed.
It can be used to separate more and transfer to another substrate. At this time, the transistor 10 can be transferred to a substrate having low heat resistance or a flexible substrate.

The base insulating film 13 includes silicon oxide, silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, and the like. As the base insulating film 13, silicon nitride, gallium oxide,
By using hafnium oxide, yttrium oxide, aluminum oxide or the like, diffusion of an impurity such as an alkali metal, water, hydrogen or the like from the substrate 11 to the oxide semiconductor film 19 can be suppressed.

The gate electrode 15 is formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described metal element, or an alloy combining the above-described metal elements, or the like. can do. In addition, a metal element selected from any one or more of manganese and zirconium may be used. The gate electrode 15 may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which an aluminum film is stacked on a titanium film and a titanium film, and a titanium film is formed thereon is there. Alternatively, a film of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium, or an alloy film or a combination of two or more elements may be used for aluminum.

The gate electrode 15 may be made of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, the light-transmitting conductive material can have a stacked-layer structure of the above-described metal element.

In addition, an In—Ga—Zn-based oxynitride semiconductor film, an In—Sn-based oxynitride semiconductor film, an In—Ga-based oxynitride semiconductor film, and an In—Zn between the gate electrode 15 and the gate insulating film 17. -Based oxynitride semiconductor film, Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film (InN
, ZnN etc.) is preferably provided. These films are 5 eV or more, preferably 5.5 e
Since it has a work function of V or more and is a value larger than the electron affinity of an oxide semiconductor, the threshold voltage of a transistor including an oxide semiconductor can be positively shifted, which is a so-called normally-off characteristic. A switching element can be realized. For example, in the case of using an In—Ga—Zn-based oxynitride semiconductor film, a nitrogen concentration higher than at least the oxide semiconductor film 19, specifically, 7%.
An In-Ga-Zn-based oxynitride semiconductor film of atomic percent or more is used.

The oxide semiconductor film 19 preferably contains at least indium (In) or zinc (Zn). Alternatively, it is preferable to contain both In and Zn. In addition, in order to reduce variation in electrical characteristics of a transistor including the oxide semiconductor, it is preferable to include one or more stabilizers in addition to them.

As the stabilizer, there are gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), zirconium (Zr), and the like. Other stabilizers include lanthanoids, lanthanum (La), cerium (Ce), praseodymium (P
r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (
Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu) and the like.

For example, as the oxide semiconductor, indium oxide which is a one-way metal oxide, tin oxide, zinc oxide, In-Zn-based metal oxide which is a two-way metal oxide, Sn-Zn-based metal oxide, Al
Zn-based metal oxide, Zn-Mg-based metal oxide, Sn-Mg-based metal oxide, In-Mg-based metal oxide, In-Ga-based metal oxide, In-W-based metal oxide, ternary system In-Ga-Zn-based metal oxide (also referred to as IGZO) which is a metal oxide, In-Al-Zn-based metal oxide, In-Sn-Zn-based metal oxide, Sn-Ga-Zn-based metal oxide , Al-Ga-Zn
-Based metal oxide, Sn-Al-Zn-based metal oxide, In-Hf-Zn-based metal oxide, In-
La-Zn based metal oxide, In-Ce-Zn based metal oxide, In-Pr-Zn based metal oxide, In-Nd-Zn based metal oxide, In-Sm-Zn based metal oxide, In- Eu-Zn
-Based metal oxide, In-Gd-Zn-based metal oxide, In-Tb-Zn-based metal oxide, In-
Dy-Zn based metal oxide, In-Ho-Zn based metal oxide, In-Er-Zn based metal oxide, In-Tm-Zn based metal oxide, In-Yb-Zn based metal oxide, In- Lu-Zn
-Based metal oxides, quaternary metal oxides In-Sn-Ga-Zn-based metal oxides, In-H
f-Ga-Zn based metal oxide, In-Al-Ga-Zn based metal oxide, In-Sn-Al
A -Zn-based metal oxide, an In-Sn-Hf-Zn-based metal oxide, or an In-Hf-Al-Zn-based metal oxide can be used.

Here, for example, an In—Ga—Zn-based metal oxide means an oxide having In, Ga, and Zn as main components, and there is no limitation on the ratio of In, Ga, and Zn. Also, In
And may contain metal elements other than Ga and Zn.

In addition, as an oxide semiconductor, InMO ₃ (ZnO) _m (m> 0, and m is not an integer)
The material represented by may be used. M represents one or more metal elements selected from Ga, Fe, Mn, and Co. In addition, as an oxide semiconductor, In ₂ SnO ₅
A material represented by (ZnO) _n (n> 0, and n is an integer) may be used.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Z
n = 2: 2: 1 (= 2/5: 2/5: 1/5), or In: Ga: Zn = 3: 1: 2
An In—Ga—Zn-based metal oxide having an atomic ratio of (= 1/2: 1/6: 1/3) or an oxide near the composition thereof can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/1
3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1/2) or In: Sn: Zn = 2: 1: 5 (= In- of atomic ratio of 1/4: 1/8: 5/8)
It is preferable to use an Sn—Zn-based metal oxide or an oxide near the composition thereof. Note that the atomic ratio of the metal oxide includes a variation of plus or minus 20% of the above atomic ratio as an error.

However, the composition is not limited to these, and one having an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.). Further, in order to obtain the required semiconductor characteristics and electrical characteristics, it is preferable to set the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density and the like to be appropriate.

For example, high mobility can be obtained relatively easily in an In-Sn-Zn-based metal oxide. However, even in the In—Ga—Zn-based metal oxide, the mobility can be increased by lowering the defect density in the bulk.

The metal oxide that can be formed in the oxide semiconductor film 19 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. As described above, with the use of the oxide semiconductor with a wide energy gap, the off-state current of the transistor can be reduced.

The oxide semiconductor film 19 may have an amorphous structure, a single crystal structure, or a polycrystalline structure.

The oxide semiconductor film 19 may have, for example, a non-single crystal. Non-single crystals are, for example, C
AAC (C Axis Aligned Crystal), polycrystal, microcrystalline, having one or more of amorphous parts. The amorphous part has a higher density of defect states than microcrystalline or CAAC. In addition, microcrystals have a higher density of defect states than CAAC. Note that an oxide semiconductor containing a CAAC is
CAAC-OS (C Axis Aligned Crystal Oxide Sem
It is called an iconductor. The oxide semiconductor film 19 may have, for example, a CAAC-OS. The CAAC-OS is, for example, c-axis oriented, and the a-axis or / and the b-axis are not aligned with the macro.

The oxide semiconductor film 19 may have, for example, microcrystalline. Note that an oxide semiconductor having microcrystalline is referred to as a microcrystalline oxide semiconductor. The microcrystalline oxide semiconductor film is, for example, 1 nm to 10 n
Microcrystals (also referred to as nanocrystals) with a size of less than m are included in the film.

The oxide semiconductor film 19 may have an amorphous portion, for example. Note that an oxide semiconductor having an amorphous portion is referred to as an amorphous oxide semiconductor. The amorphous oxide semiconductor film has, for example, disordered atomic arrangement and no crystalline component. Alternatively, the amorphous oxide semiconductor film is, for example, completely amorphous and does not have a crystal part.

Note that the oxide semiconductor film 19 may be a mixed film of a CAAC-OS, a microcrystalline oxide semiconductor, or an amorphous oxide semiconductor. The mixed film includes, for example, a region of an amorphous oxide semiconductor, a region of a microcrystalline oxide semiconductor, and a region of a CAAC-OS. The mixed film may have, for example, a stacked structure of a region of an amorphous oxide semiconductor, a region of a microcrystalline oxide semiconductor, and a region of a CAAC-OS.

Note that the oxide semiconductor film 19 may have, for example, a single crystal.

The oxide semiconductor film 19 preferably includes a plurality of crystal parts, and c axes of the crystal parts are preferably aligned in a direction parallel to a normal vector of the formation surface or a normal vector of the surface. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. A CAAC-OS film is an example of such an oxide semiconductor film.

Here, the details of the CAAC-OS film are described. In most cases, the crystal part included in the CAAC-OS film fits in a cube whose one side is less than 100 nm. Also, a transmission electron microscope (TEM: Transmission Electron Microscope)
In the observation image according to the above, the boundary between the crystal part and the crystal part contained in the CAAC-OS film is not clear. In addition, a clear grain boundary (also referred to as a grain boundary) can not be confirmed in the CAAC-OS film by TEM. Therefore, in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is suppressed.

For example, the crystal part included in the CAAC-OS film is aligned such that the c-axis is parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface, and the direction perpendicular to the ab plane The metal atoms are arranged in a triangular shape or a hexagonal shape as viewed from the direction perpendicular to the c-axis, and the metal atoms are arranged in layers or the metal atoms and the oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In the present specification, the term “perpendicular” also includes a range of 80 ° to 100 °, preferably 85 ° to 95 °. Moreover, when it describes only as parallel, it shall also contain the range of -10 degrees or more and 10 degrees or less, preferably -5 degrees or more and 5 degrees or less.

In the CAAC-OS film, distribution of crystal parts is not necessarily uniform. For example, CAA
In the case of crystal growth from the surface side of the oxide semiconductor film in the formation process of the C-OS film, the proportion of the crystal part in the vicinity of the surface may be higher than that in the vicinity of the formation surface. Also, CA
By adding the impurity to the AC-OS film, the crystallinity of the crystal part in the impurity added region may be lowered.

The c-axis of the crystal part included in the CAAC-OS film is aligned parallel to the normal vector of the formation surface of the CAAC-OS film or the normal vector of the surface; therefore, the shape of the CAAC-OS film ( Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface), they may be directed in different directions. In addition, the crystal part is formed when a film is formed or when a crystallization process such as a heat treatment is performed after the film formation. Therefore, the c-axis of the crystal part is aligned in a direction parallel to the normal vector of the formation surface or the normal vector of the surface when the CAAC-OS film is formed.

The transistor including the CAAC-OS film has less variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Thus, the transistor is highly reliable.

The oxide semiconductor film 19 may have a structure in which a plurality of oxide semiconductor films are stacked. For example, the oxide semiconductor film 19 is a stack of a first oxide semiconductor film and a second oxide semiconductor film.
Metal oxides of different compositions may be used for the first oxide semiconductor film and the second oxide semiconductor film. For example, a binary metal oxide which is different from the first oxide semiconductor film is used for the second oxide semiconductor film, using one of a binary metal oxide to a quaternary metal oxide for the first oxide semiconductor film. Alternatively, quaternary or quaternary metal oxides may be used.

The constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be the same, and the compositions of the two may be different. For example, the atomic ratio of the first oxide semiconductor film can be expressed as In: Ga: Zn = 1
Alternatively, the atomic ratio of the second oxide semiconductor film may be In: 1: 3: 1: 2. Further, the atomic ratio of the first oxide semiconductor film is set to In: Ga: Zn = 1: 3: 2,
The atomic ratio of the second oxide semiconductor film may be In: Ga: Zn = 2: 1: 3. Note that
The atomic ratio of each oxide semiconductor film includes a variation of plus or minus 20% of the atomic ratio described above as an error.

At this time, in the first oxide semiconductor film and the second oxide semiconductor film, the content ratio of In and Ga in the oxide semiconductor film closer to the gate electrode (channel side) may be In> Ga. Further, the In and Ga contents of the oxide semiconductor film on the side (back channel side) far from the gate electrode are In ≦≦.
It is good to be Ga.

In oxide semiconductors, the s orbital of heavy metal mainly contributes to carrier conduction, and by increasing the In content, more s orbitals overlap, so that an oxide with a composition of In> Ga is In ≦ Ga. It has a high mobility compared to the oxide that has the composition of In addition, since Ga has a large formation energy of oxygen vacancy compared to In and is less likely to cause oxygen vacancy, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

An oxide semiconductor with a composition of In> Ga is applied to the channel side, and In ≦≦ on the back channel side.
By using an oxide semiconductor which has a composition of Ga, the field-effect mobility and reliability of the transistor can be further improved.

Alternatively, oxide semiconductors with different crystallinity may be applied to the first oxide semiconductor film and the second oxide semiconductor film. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS may be combined as appropriate. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor film and the second oxide semiconductor film, internal stress or stress from the outside of the oxide semiconductor film 19 is alleviated. Variations in transistor characteristics are reduced, and transistor reliability can be further enhanced.

The thickness of the oxide semiconductor film 19 is 1 nm to 100 nm, preferably 1 nm to 5 nm.
0 nm or less, more preferably 1 nm to 30 nm, further preferably 3 nm to 20 n
It is preferable to set it as m or less.

In the oxide semiconductor film 19, the concentration of alkali metal or alkaline earth metal is 1 × 10
It is desirable that it is ¹⁸ atoms / cm ³ or less, more preferably 2 × 10 ¹⁶ atoms / cm ³ or less. When an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, a carrier may be generated, which causes an increase in off-state current of the transistor.

The oxide semiconductor film 19 may contain nitrogen of 5 × 10 ¹⁸ atoms / cm ³ or less.

The pair of electrodes 21 has a single-layer structure or a single metal composed of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten as a conductive material, or an alloy containing this as a main component Used as a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a tungsten film, a copper film on a copper-magnesium-aluminum alloy film A two-layer structure to be stacked, a three-layer structure in which an aluminum film or a copper film is stacked on the titanium film or titanium nitride film and the titanium film or titanium nitride film and further a titanium film or a titanium nitride film is formed thereon A molybdenum film or a molybdenum nitride film,
There is a three-layer structure or the like in which an aluminum film or a copper film is stacked on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide or zinc oxide may be used.

The insulating film 23 has a thickness of 30 nm to 500 nm, preferably 100 nm to 400 n.
A silicon oxide, a silicon oxynitride, a silicon nitride oxide, a silicon nitride, an aluminum oxide, an aluminum oxynitride, an aluminum nitride oxide, an aluminum nitride, or the like which is less than or equal to m may be used.

As the insulating film 23, an insulating film having a high film density and few defects, as in the case of the gate insulating film 17, typically, a film density of 2.26 g / cm ³ or more and a theoretical film density 2. 63g /
cm ^3, preferably not more than 2.30 g / cm ³ or more 2.63 g / cm ^3, in the signal measured by the electron spin resonance method, signals spin density of 2 × 10 of the g value appears to 2.001 ¹⁵ spins / cm ³ or less, more preferably the lower detection limit (1 × 10 ¹⁵ s
By using the insulating film which is smaller than or equal to pins / cm ³ , variation in threshold voltage of the transistor can be suppressed.

Note that in the case where the oxide semiconductor film 19 is formed of a metal oxide containing indium, the insulating film 23
And 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less of indium. This is because indium contained in the oxide semiconductor film 19 diffuses into the insulating film 23 when the insulating film 23 is formed. Note that, as the film formation temperature of the insulating film 23 becomes higher, for example, 350 ° C. or more, the content of indium contained in the insulating film 23 increases.

Next, a method for manufacturing a transistor included in the semiconductor device illustrated in FIG. 1 is described with reference to FIGS.

As shown in FIG. 2A, the base insulating film 13 and the gate electrode 15 are formed on the substrate 11, and the gate insulating film 17 is formed on the gate electrode 15. Next, the oxide semiconductor film 18 is formed over the gate insulating film 17.

The base insulating film 13 is formed by sputtering, CVD or the like. Here, thickness 10
A 0 nm silicon oxynitride film is formed by a CVD method.

The formation method of the gate electrode 15 is shown below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like, and a mask is formed over the conductive film by a photolithography step. Next, part of the conductive film is etched using the mask to form the gate electrode 15.
After this, the mask is removed.

The gate electrode 15 may be formed by an electrolytic plating method, a printing method, an inkjet method or the like instead of the above forming method.

Here, a tungsten film with a thickness of 100 nm is formed by a sputtering method. next,
A mask is formed by a photolithography step, and the tungsten film is dry etched using the mask to form the gate electrode 15.

The gate insulating film 17 holds the substrate placed in the evacuated processing chamber of the plasma CVD apparatus at 300 ° C. to 400 ° C., more preferably 320 ° C. to 380 ° C., and introduces the source gas into the processing chamber. The pressure in the processing chamber is set to 30 Pa to 250 Pa, more preferably 40 Pa to 200 Pa, and the electrode provided in the processing chamber is 0.17 W / c.
m ² or more 0.5 W / cm ² or less, more preferably 0.26 W / cm ² or more 0.35 W /
A silicon oxide film or a silicon oxynitride film is formed under the condition of supplying high frequency power of cm ² or less.

As a source gas of the gate insulating film 17, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, fluorosilane and the like. Oxidizing gases include oxygen, ozone, nitrous oxide,
There are nitrogen dioxide, dry air, etc.

Under the film forming conditions of the gate insulating film 17, by setting the power density of the high frequency power to the high power density as described above, the decomposition efficiency of the source gas in the plasma is enhanced, the oxygen radicals are increased, and the deposition including silicon is performed. Gas oxidation proceeds. Further, by setting the substrate temperature to the above temperature, the bonding strength between silicon and oxygen becomes strong. As a result, an insulating film with high film density and few dangling bonds of silicon, that is, a silicon oxide film or a silicon oxynitride film with high film density and few defects can be formed as a gate insulating film.

Here, a gate insulating film 17 is formed by forming a silicon oxynitride film having a thickness of 250 nm by a CVD method.

The oxide semiconductor film 18 is formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, or the like.

In the case of forming the oxide semiconductor film 18 by a sputtering method, an RF power supply, an AC power supply, a DC power supply, or the like can be used as appropriate as a power supply for generating plasma.

As a sputtering gas, a rare gas (typically, argon) atmosphere, an oxygen atmosphere, and a mixed gas atmosphere of a rare gas and oxygen are appropriately used. In the case of a mixed gas of a rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to the rare gas.

The target may be selected as appropriate in accordance with the composition of the oxide semiconductor film 18 to be formed.

When the oxide semiconductor film 18 is formed, for example, in the case of using a sputtering method, the substrate temperature is set to 150 ° C. to 750 ° C., preferably 150 ° C. to 450 ° C., and more preferably 200 ° C. to 350 ° C. By forming the oxide semiconductor film 18, the CAA
A C-OS film can be formed.

Note that the CAAC-OS film is formed, for example, by a sputtering method using a polycrystalline oxide semiconductor sputtering target. When ions collide with the sputtering target, the crystal region included in the sputtering target is cleaved from the a-b plane, and separated as flat-plate-like or pellet-like sputtering particles having a plane parallel to the a-b plane. is there. In this case, the CAAC-OS film can be formed by the flat sputtering particles reaching the substrate while maintaining the crystalline state.

Further, in order to form a CAAC-OS film, the following conditions are preferably applied.

By suppressing the mixing of impurities at the time of film formation, it is possible to suppress that the crystal state is broken by the impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) in the deposition chamber may be reduced. Further, the concentration of impurities in the deposition gas may be reduced. Specifically, a deposition gas whose dew point is lower than or equal to -80.degree. C., preferably lower than or equal to -100.degree. C. is used.

In addition, by raising the substrate heating temperature at the time of film formation, migration of sputtering particles occurs after reaching the substrate. Specifically, the film is formed at a substrate heating temperature of 100 ° C. or more and less than the substrate strain point, preferably 200 ° C. or more and 500 ° C. or less. By raising the substrate heating temperature during film formation,
When the flat sputtering particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtering particles adheres to the substrate.

Further, it is preferable to reduce plasma damage at the time of film formation by increasing the proportion of oxygen in the film formation gas and optimizing the power. The proportion of oxygen in the deposition gas is 30% by volume or more, preferably 100% by volume.

An In—Ga—Zn-based metal oxide target is described below as an example of a sputtering target.

In-G which is polycrystalline by mixing InO _X powder, GaO _Y powder, and ZnO _Z powder at a predetermined molar ratio, heat-treating at a temperature of 1000 ° C. to 1500 ° C. after pressure treatment
An a-Zn-based metal oxide target is used. Note that X, Y and Z are arbitrary positive numbers. Here, the predetermined molar ratio is, for example, InO _X powder, GaO _Y powder, and ZnO _Z powder: 2: 2: 1, 8: 4: 3, 3: 1: 1, 1: 1: 1, 4 It is 2: 3 or 3: 1: 2. The type of powder and the molar ratio to be mixed may be changed as appropriate depending on the sputtering target to be produced.

Next, as illustrated in FIG. 2B, the oxide semiconductor film 19 which is separated into elements is formed on the gate insulating film 17 so as to overlap with part of the gate electrode 15. After a mask is formed over the oxide semiconductor film 18 by a photolithography step, the oxide semiconductor film 1 is formed using the mask.
By etching part of the element 8, the element-separated oxide semiconductor film 19 can be formed.

In addition, by using a printing method as the oxide semiconductor film 19, the oxide semiconductor film 19 which is subjected to element isolation can be formed directly.

Here, after the oxide semiconductor film 18 with a thickness of 35 nm is formed by sputtering,
A mask is formed over the oxide semiconductor film 18, and a part of the oxide semiconductor film 18 is selectively etched to form the oxide semiconductor film 19. After this, the mask is removed.

Next, as shown in FIG. 2C, a pair of electrodes 21 is formed.

The method of forming the pair of electrodes 21 is shown below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like. Next, a mask is formed over the conductive film by a photolithography step. Next, the conductive film is etched using the mask to form a pair of electrodes 21.
After this, the mask is removed.

Here, a 50-nm-thick tungsten film, a 400-nm-thick aluminum film, and a 100-nm-thick titanium film are sequentially stacked by a sputtering method by a sputtering method.
Next, a mask is formed over the titanium film by a photolithography step, and the tungsten film, the aluminum film, and the titanium film are dry etched using the mask to form a pair of electrodes 2.
Form one.

Note that after the pair of electrodes 21 is formed, a cleaning process is preferably performed to remove etching residues. By performing this cleaning process, a short circuit of the pair of electrodes 21 can be suppressed. The cleaning process is carried out using TMAH (Tetramethylammonium Hydro
It can be carried out using an alkaline solution such as a solution, an acidic solution such as dilute hydrofluoric acid, oxalic acid or phosphoric acid, or water.

Next, as shown in FIG. 2D, the insulating film 23 is formed.

The insulating film 23 is formed by a CVD method or a sputtering method.

Note that under the same conditions as the gate insulating film 17, an insulating film with high film density and few defects may be formed as the insulating film 23.

Alternatively, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is maintained at 180 ° C. or more and 250 ° C. or less, more preferably 180 ° C. or more and 230 ° C. or less, and source gas is introduced into the processing chamber Pressure in the range from 100 Pa to 250 Pa, more preferably 1
And 00Pa or 200Pa or less, the process in the electrode provided in the indoor 0.17 W / cm ² or more 0.5 W / cm ² or less, more preferably supply the following high-frequency power 0.25 W / cm ² or more 0.35 W / cm ² Depending on the conditions, a silicon oxide film or a silicon oxynitride film may be formed as the insulating film 23.

As a source gas of the insulating film 23, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, fluorosilane and the like. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

By supplying the high frequency power of the above power density in the processing chamber under the above pressure as the film forming condition of the insulating film 23, the decomposition efficiency of the source gas is enhanced in the plasma, oxygen radicals are increased, and the deposition gas contains silicon. As a result, the oxygen content in the insulating film 23 becomes larger than the stoichiometric ratio. On the other hand, in the case of a film formed at the above temperature, the bonding force between silicon and oxygen is weak, so that part of oxygen in the film is released by heat treatment in a later step. As a result, an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition can be formed. That is, an oxide insulating film from which part of oxygen is released by heating can be formed.

By providing an oxide insulating film which contains oxygen at a proportion higher than that in the stoichiometric composition as the insulating film 23, oxygen is diffused into the oxide semiconductor film 19 by heat treatment, and the oxygen contained in the oxide semiconductor film 19 is obtained. It is possible to compensate for the defect.

Next, heat treatment is performed. The temperature of the heat treatment is typically 150 ° C. or more and less than the substrate strain point, preferably 250 ° C. or more and 450 ° C. or less, and more preferably 300 ° C. or more and 450 ° C. or less.

As the heat treatment, an electric furnace, a rapid thermal annealing (RTA) apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature higher than the strain point of the substrate for only a short time. Therefore, oxygen diffusion time from the insulating film 23 to the oxide semiconductor film 19 can be shortened.

Heat treatment is carried out using nitrogen, oxygen, ultra-dry air (water content is 20 ppm or less, preferably 1 pp
The heating may be performed under an atmosphere of m or less, preferably 10 ppb or less) or a rare gas (argon, helium or the like).

Here, heat treatment is performed at 350 ° C. for one hour in a nitrogen and oxygen atmosphere.

Through the above steps, a transistor with excellent characteristics and less variation in threshold voltage can be manufactured. In addition, a highly reliable transistor with little change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

Next, a transistor having a structure different from that in FIG. 1 is described with reference to FIGS. 3 and 4. Here, a mode in which an insulating film provided over the gate insulating film and the oxide semiconductor film has a stacked structure in comparison with the transistor 10 illustrated in FIG. 1 is described with reference to FIGS.

The transistor 30 illustrated in FIG. 3 includes a base insulating film 13 provided on the substrate 11 and a gate electrode 15 formed on the base insulating film 13. In addition, base insulating film 13 and gate electrode 1
A gate insulating film 33 composed of the insulating film 31 and the insulating film 32 is formed on the fifth, and the oxide semiconductor film 20 overlapping the gate electrode 15 with the gate insulating film 33 interposed therebetween, and the oxide semiconductor film 20
And a pair of electrodes 21 in contact with the Further, over the gate insulating film 33, the oxide semiconductor film 20, and the pair of electrodes 21, a protective film 37 including the insulating film 34 and the insulating film 36 is formed.

Further, the gate insulating film 33 has a stacked structure of the insulating film 31 and the insulating film 32. As the insulating film 31, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, a Ga—Zn-based metal oxide, or the like may be used. Alternatively, as the insulating film 31, an oxide insulating film from which oxygen is released by heating may be used. By using a film from which oxygen is released by heating for the insulating film 31, the interface state at the interface between the insulating film 32 and the oxide semiconductor film 20 can be reduced, and a transistor with less variation in electrical characteristics can be obtained. be able to. Further, by providing an insulating film having a blocking effect of oxygen, hydrogen, water, or the like as the insulating film 31, diffusion of oxygen from the oxide semiconductor film 20 to the outside and hydrogen from the outside to the oxide semiconductor film 20 Can prevent the entry of water etc. As an insulating film having a blocking effect of oxygen, hydrogen, water and the like, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, hafnium oxide nitride and the like can be given.

Further, as the insulating film 31, hafnium silicate (HfSiO _x ), hafnium silicate to which nitrogen is added (HfSi _x O _y N _z ), hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z ), hafnium oxide, The gate leakage of the transistor can be reduced by using a high-k material such as yttrium oxide.

Note that as the insulating film 31, an insulating film is formed with a thickness of 5 nm or more and 400 nm or less, using the materials listed above as appropriate. As the insulating film 32, a silicon oxide film or a silicon oxynitride film with a thickness of 5 nm to 400 nm is formed. Note that the thicknesses of the insulating film 31 and the insulating film 32 may be appropriately selected so that the total thickness of the two insulating films falls within the range of the gate insulating film 17 of the transistor 10 shown in FIG.

In addition, the oxide semiconductor film 20 is exposed to plasma generated in an oxidizing atmosphere. As an oxidizing atmosphere, there is an atmosphere of oxygen, ozone, dinitrogen monoxide or the like. Furthermore, in the plasma processing, a bias is applied to the upper electrode using a parallel plate type plasma CVD apparatus to
It is preferable to expose the oxide semiconductor film to plasma generated in a state where a bias is not applied to the lower electrode on which 1 is mounted. As a result, damage is small and oxygen is an oxide semiconductor film 2
Since oxygen is supplied to 0, the amount of oxygen vacancies contained in the oxide semiconductor film 20 can be reduced.

In the transistor 30, the insulating film 32 and the insulating film 34 are formed to be in contact with the oxide semiconductor film 20. Similarly to the gate insulating film 17 shown in FIG. 1, the insulating film 32 and the insulating film 34 are formed of an insulating film having a high film density and few defects. Typically, the film density is 2.26 g / cm ³ or more and the theoretical film density is 2.63 g / cm ³ or less, preferably 2.3.
0 g / cm ³ or more 2.63 g / cm ³ or less, the signal measured by the electron spin resonance method, g values are the spin density of 2 × ¹⁰ 15 of the signal appearing at 2.001 spins /
It is formed of an insulating film having a cm ³ or less, more preferably a detection lower limit (1 × 10 ¹⁵ spins / cm ³ ) or less. For this reason, the threshold voltage of the transistor 30 including the gate insulating film 33 including the insulating film 32 is less varied, and the transistor 30 has excellent electrical characteristics. Further, by having the insulating film 32 formed of an insulating film having a high film density, the substrate 1 can be obtained.
1, impurities from the base insulating film 13, the gate electrode 15, and the insulating film 31 are the oxide semiconductor film 2
It can suppress mixing in 0. In addition, the insulating film 34 enables the insulating film 34 to be formed.
In the heat treatment step after formation of oxygen, the amount of oxygen released from the oxide semiconductor film 20 can be reduced, and the amount of oxygen vacancies in the oxide semiconductor film 20 can be reduced.

Note that in the case where the oxide semiconductor film 20 is formed of a metal oxide containing indium, the insulating film 34
And 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less of indium. This is because indium contained in the oxide semiconductor film 20 diffuses into the insulating film 34 when the insulating film 34 is formed. Note that as the film formation temperature of the insulating film 34 becomes higher, for example, 350 ° C. or more, the content of indium contained in the insulating film 34 increases.

As the insulating film 32 and the insulating film 34, a silicon oxide film, a silicon oxynitride film, or the like can be used.

The insulating film 36 has a thickness of 30 nm to 500 nm, preferably 100 nm to 40 nm.
A silicon oxide, a silicon oxynitride, a silicon nitride oxide, a silicon nitride, an aluminum oxide, an aluminum oxynitride, an aluminum nitride oxide, an aluminum nitride, or the like with a thickness of 0 nm or less may be used. Note that as the insulating film 36, an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition may be provided.

The transistor 30 is exposed to plasma generated in an oxidizing atmosphere and includes an oxide semiconductor film with few oxygen vacancies. Further, in the oxide semiconductor film, the exposed portion is covered with the insulating film 32 and the insulating film 34 which have high density and few defects. Therefore, the transistor has excellent electrical characteristics with less variation in threshold voltage of the transistor and less variation in electrical characteristics. In addition, the transistor has excellent electrical characteristics with little change in electrical characteristics due to time-lapse changes and light gate BT stress tests.

Next, a method for manufacturing the transistor illustrated in FIG. 3 is described with reference to FIGS.

As shown in FIG. 4A, the base insulating film 13 and the gate electrode 15 are formed on the substrate 11 in the same manner as the step shown in FIG. Next, the insulating film 31 and the insulating film 32 which function as the gate insulating film 33 are formed.

The insulating film 31 is formed by using a CVD method or a sputtering method. By using the same conditions as the gate insulating film 17 of the transistor 10 as the insulating film 32, a silicon oxide film or a silicon oxynitride film with high film density and few defects is formed.

Here, a silicon nitride film with a thickness of 50 nm is formed as the insulating film 31 by the CVD method. In addition, a silicon oxynitride film with a thickness of 200 nm is formed as the insulating film 32 under the same conditions as the gate insulating film 17 of the transistor 10. Under the conditions, the film density is high,
In addition, a silicon oxynitride film with few defects can be formed.

Here, by increasing the thickness of the gate insulating film 33, more preferably, the resistivity is 5 × 1.
By stacking a silicon nitride film and a silicon oxynitride film at 0 ¹³ Ω · cm or more and 1 × 10 ¹⁵ Ω · cm or less, a gate electrode 15 of a transistor to be formed later, an oxide semiconductor film 20, or a pair of transistors It is possible to suppress electrostatic breakdown occurring between the electrode 21 and the electrode 21.

Next, as illustrated in FIG. 4B, the oxide semiconductor film 19 is formed over the gate insulating film 33 in the same manner as the process illustrated in FIG.

Next, as shown in FIG. 4C, a pair of electrodes 21 is formed. Next, the oxide semiconductor film 19
Is exposed to plasma generated in an oxidizing atmosphere, oxygen 22 is supplied to the oxide semiconductor film 19, and an oxide semiconductor film 20 shown in FIG. 4D is formed. As an oxidizing atmosphere, there is an atmosphere of oxygen, ozone, dinitrogen monoxide or the like. Furthermore, in plasma treatment, it is preferable to expose the oxide semiconductor film 19 to plasma generated without applying a bias to the lower electrode on which the substrate 11 is mounted. As a result, oxygen can be supplied without damaging the oxide semiconductor film 19.

In this case, dinitrogen monoxide is introduced into the processing chamber of the plasma CVD apparatus, and 150 W of high frequency power is supplied to the upper electrode provided in the processing chamber using a 27.12 MHz high frequency power source to oxidize the generated oxygen plasma. The semiconductor semiconductor film 19 is exposed.

Next, the insulating film 34 is formed over the oxide semiconductor film 20 and the pair of electrodes 21. Here, a silicon oxynitride film with a thickness of 10 nm is formed under the same conditions as the gate insulating film 17 of the transistor 10. Under the conditions, a silicon oxynitride film with high film density and few defects can be formed.

Next, oxygen 35 may be added to the insulating film 34. Methods of adding oxygen 35 to the insulating film 34 include an ion implantation method, an ion doping method, plasma treatment, and the like. As a result, the insulating film 34 can be an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition.

Next, as shown in FIG. 4E, the insulating film 36 is formed on the insulating film 34. As the insulating film 36, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is heated to 180 ° C. or higher.
The pressure in the processing chamber is maintained at 0 ° C. or less, more preferably 180 ° C. or more and 230 ° C. or less, and the pressure in the processing chamber is 100 Pa or more and 250 Pa or less, more preferably 100.
And Pa to 200Pa or less, the electrode provided in the processing chamber 0.17 W / cm ² or more 0.
5W / cm ² or less, more preferably under the conditions for supplying high-frequency power of 0.25 W / cm ² or more 0.35 W / cm ² or less, a silicon oxide film or a silicon oxynitride film.

Next, heat treatment is performed in the same manner as the step shown in FIG.

Through the above steps, a transistor in which the negative shift of the threshold voltage is suppressed can be manufactured. In addition, a transistor with excellent electrical characteristics, which has less variation in threshold voltage of the transistor and less variation in electrical characteristics, can be manufactured. In addition, a highly reliable transistor with little change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Second Embodiment
In this embodiment, a transistor having a structure different from that in Embodiment 1 will be described with reference to FIG. The transistor 100 described in this embodiment is different from the transistor described in Embodiment 1 in that it is a top-gate transistor.

5A to 5C illustrate a top view and a cross-sectional view of the transistor 100. FIG. Figure 5 (A
5A is a top view of the transistor 100, FIG. 5B is a cross-sectional view taken along dashed-dotted line A-B in FIG. 5A, and FIG. 5C is a dashed-dotted line in FIG. It is a sectional view between C-D. Note that
In FIG. 5A, the substrate 101, the base insulating film 103, part of components of the transistor 100 (eg, the gate insulating film 109), the insulating film 113, and the like are omitted for clarity.

The transistor 100 illustrated in FIG. 5 includes an oxide semiconductor film 10 formed over the base insulating film 103.
5, a pair of electrodes 107 in contact with the oxide semiconductor film 105, a base insulating film 103, the oxide semiconductor film 105, a gate insulating film 109 in contact with the pair of electrodes 107, and a gate insulating film 10.
And a gate electrode 111 which overlaps with the oxide semiconductor film 105 with the reference numeral 9. In addition, an insulating film 113 which covers the gate insulating film 109 and the gate electrode 111 is provided. Also, gate insulating film 10
In the opening portion 110 of the insulating film 113 and the wiring 9, the wiring 115 may be in contact with the pair of electrodes 107.

In the transistor 100 described in this embodiment, the pair of electrodes 107 and the gate electrode 111 overlap with each other with the gate insulating film 109 interposed therebetween. Thus, in the oxide semiconductor film 105, a region facing the gate electrode 111 with the gate insulating film 109 functions as a channel region, and regions in contact with the pair of electrodes 107 function as a source region and a drain region. That is,
The channel region is in contact with the source region and the drain region. Since there is no region serving as a resistance between the channel region and the source and drain regions, a transistor with high on-state current and field-effect mobility can be obtained.

In the transistor 100 described in this embodiment, the gate insulating film 109 is formed using an insulating film with high film density and few defects. Typically, the film density of the gate insulating film 109 is 2.
26 g / cm ³ or more, theoretical film density 2.63 g / cm ³ or less, preferably 2.30 g
The film density of the gate insulating film 17 is high because it is not less than ³ cm ^{3 and not} more than 2.63 g / cm ³ . In addition, in the signal measured by the electron spin resonance method (ESR), the spin density of the signal appearing at E′-center (g value is 2.001) indicating a tongue ring bond of silicon is 2 × 10 ¹⁵ spins / cm ³ Or less, more preferably the lower detection limit (1 × 10 ¹⁵ spi
Since it is equal to or less than ns / cm ³ , dangling bonds of silicon contained in the gate insulating film 109 are extremely small. Therefore, the transistor 100 including the gate insulating film 109
The transistor 100 has excellent electrical characteristics.

Examples of the gate insulating film 109 include silicon oxide and silicon oxynitride.

Note that in the case where the oxide semiconductor film 105 is formed using a metal oxide containing indium, the gate insulating film 109 contains indium at 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less. This is because the oxide semiconductor film 10 is formed when the gate insulating film 109 is formed.
This is because indium contained in 5 diffuses into the gate insulating film 109. As the film formation temperature of the gate insulating film 109 becomes higher, for example, 350 ° C. or higher, the gate insulating film 1 is formed.
The content of indium contained in 09 increases.

Hereinafter, details of another structure of the transistor 100 are described.

As the substrate 101, any of the substrates listed in the substrate 11 described in Embodiment 1 can be used as appropriate.

The base insulating film 103 is preferably formed using an oxide insulating film from which part of oxygen is released by heating. As an oxide insulating film from which part of oxygen is released by heating, it is preferable to use an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition. The oxide insulating film from which part of oxygen is released by heating can diffuse oxygen into the oxide semiconductor film by heat treatment. Typical examples of the base insulating film 103 include silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, and the like.

The base insulating film 103 has a thickness of 50 nm or more, preferably 200 nm to 3000 nm, and preferably 300 nm to 1000 nm. By thickening the base insulating film 103, the amount of oxygen released from the base insulating film 103 can be increased, and interface states at the interface with the base insulating film 103 and an oxide semiconductor film to be formed later are reduced. It is possible.

Here, “part of oxygen is released by heating” means TDS (Thermal Deso
rption Spectroscopy: Temperature-programmed desorption gas spectroscopy) analysis shows that the amount of desorbed oxygen in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0
X 10 ²⁰ atoms / cm ³ or more.

In the above structure, the insulating film from which part of oxygen is released by heating may be silicon oxide with excess oxygen (SiO _x (X> 2)). Oxygen-rich silicon oxide (SiO _X (X>
2) is one containing an oxygen atom per unit volume which is more than twice the number of silicon atoms. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

Here, a method of measuring the amount of desorption of oxygen in terms of oxygen atoms in TDS analysis will be described below.

The amount of gas desorption when TDS analysis is proportional to the integral value of the spectrum. Therefore, the desorption amount of gas can be calculated by the integral value of the spectrum of the insulating film and the ratio to the reference value of the standard sample. The reference value of the standard sample is the ratio of the density of atoms to the integral value of the spectrum of a sample containing a predetermined atom.

For example, from the results of TDS analysis of a silicon wafer containing hydrogen of a predetermined density, which is a standard sample, and the TDS analysis result of an insulating film, the desorption amount (N _O2 ) of oxygen molecules in the insulating film can be obtained by Equation 1. it can. Here, it is assumed that all of the spectra detected with a mass number of 32 obtained by TDS analysis are derived from molecular oxygen. There is CH ₃ OH as mass number 32 but it is not considered here as being unlikely to be present. Further, oxygen molecules containing an oxygen atom having a mass number of 17 and an oxygen atom having a mass number of 18, which are isotopes of oxygen atoms, are not considered because the abundance ratio in the natural world is extremely small.

N _O2 = N _H2 / S _H2 × S _O2 × α (Equation 1)

N _H2 is a value obtained by converting the density of hydrogen molecules desorbed from the standard sample. S _H2 is an integral value of a spectrum when TDS analysis of a standard sample is performed. Here, the reference value of the standard sample is N
_{It is set to H2} / S _H2 . _SO2 is an integral value of the spectrum when TDS analysis of the insulating film is performed. α is a coefficient that affects the spectral intensity in TDS analysis. For details of Formula 1, refer to Japanese Patent Application Laid-Open No. 6-275697. Note that the amount of oxygen released from the insulating film is
It measures using the silicon wafer which contains a hydrogen atom of 1 * 10 < ¹⁶ > atoms / cm < ² > as a standard sample using the temperature rising desorption analyzer EMD-WA1000S / W made from electronic science corporation | Co., Ltd. | KK.

In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. In addition, since the above-mentioned (alpha) contains the ionization rate of an oxygen molecule, it can estimate also about the detachment amount of an oxygen atom by evaluating the desorption amount of an oxygen molecule.

Here, _NO2 is the amount of desorption of molecular oxygen. In the insulating film, the amount of desorption of oxygen when converted to oxygen atoms is twice the amount of desorption of molecular oxygen.

Oxygen is supplied from the base insulating film 103 to the oxide semiconductor film 105, whereby the base insulating film 10 is formed.
The interface states of the oxide semiconductor film 105 and the oxide semiconductor film 105 can be reduced. As a result, charge which may be generated due to the operation of the transistor and the like can be prevented from being captured at the interface between the above base insulating film 103 and the oxide semiconductor film 105, and the transistor has less variation in electrical characteristics. You can get

That is, when oxygen vacancies are generated in the oxide semiconductor film 105, charges are captured at the interface between the base insulating film 103 and the oxide semiconductor film 105, and the charges affect the electrical characteristics of the transistor. 103 by providing an insulating film from which oxygen is released by heating;
The interface state of the oxide semiconductor film 105 and the base insulating film 103 is reduced, and the oxide semiconductor film 105 is formed.
And the influence of charge trapping at the interface of the base insulating film 103 can be reduced.

Note that as the base insulating film 103, an insulating film with a high film density and few defects, which is similar to the gate insulating film 109, typically, a film density of 2.26 g / cm ³ or more and a theoretical film density 2 .
63 g / cm ³ or less, preferably not more than 2.30 g / cm ³ or more 2.63 g / cm ^3, in the signal measured by the electron spin resonance method, the spin density of the signal g value appears to 2.001 2 Alternatively, an insulating film which is 10 ¹⁵ spins / cm ³ or less may be used. Alternatively, the base insulating film 103 has a stacked-layer structure, and on the oxide semiconductor film 105 side, an insulating film with a high film density and few defects similar to the gate insulating film 109, typically, a film density of 2.26 g. / C
In the signal which is m ^{3 to} 2.63 g / cm ³ and is measured by the electron spin resonance method, the spin density of the signal having a g value of 2.001 is 2 × 10 ¹⁵ spins / cm ³ or less, more preferably By using the insulating film which is lower than or equal to the detection lower limit (1 × 10 ¹⁵ spins / cm ³ ), fluctuation of the threshold voltage of the transistor can be suppressed.

The oxide semiconductor film 105 can be formed in the same manner as the oxide semiconductor film 19 described in Embodiment 1.

The pair of electrodes 107 can be formed in the same manner as the pair of electrodes 21 described in Embodiment 1. Note that the length of the pair of electrodes 107 in the channel width direction is the oxide semiconductor film 10.
In addition, the end portion which is longer than 5 and further intersects the channel length direction is covered, and the contact area of the pair of electrodes 107 and the oxide semiconductor film 105 is increased. The contact resistance can be reduced, and the on current of the transistor can be increased.

The gate electrode 111 can be formed in the same manner as the gate electrode 15 described in Embodiment 1. The insulating film 113 can be formed in the same manner as the insulating film 23 described in Embodiment 1.

For the wiring 115, any of the materials listed in the pair of electrodes 107 can be used as appropriate.

Next, a method for manufacturing the transistor illustrated in FIG. 5 is described with reference to FIGS.

As shown in FIG. 6A, the base insulating film 103 is formed over the substrate 101. Next, the oxide semiconductor film 105 is formed over the base insulating film 103.

The base insulating film 103 is formed by a sputtering method, a CVD method, or the like.

In the case where an oxide insulating film from which part of oxygen is released by heating is formed as the base insulating film 103 by a sputtering method, the amount of oxygen in a deposition gas is preferably high, and oxygen or a mixture of oxygen and a rare gas is preferably used. Gas or the like can be used. Typically, the oxygen concentration in the deposition gas is 6
It is preferable to make it% or more and 100% or less.

In the case where an oxide insulating film is formed as the base insulating film 103 by a CVD method, hydrogen or water derived from a source gas may be mixed into the oxide insulating film. Therefore, after the oxide insulating film is formed by a CVD method, heat treatment is preferably performed as dehydrogenation or dehydration.

Further, by introducing oxygen into the oxide insulating film formed by a CVD method, the amount of oxygen released by heating can be increased. Methods of introducing oxygen into the oxide insulating film include an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, and the like.

Here, the oxide semiconductor film 105 can be formed by a method similar to that of the oxide semiconductor film 19 described in Embodiment 1 as appropriate.

In order to increase the orientation of the crystal part in the CAAC-OS film, planarity of the surface of the base insulating film 103 which is a base insulating film of an oxide semiconductor film is preferably increased. Typically, the average surface roughness (Ra) of the base insulating film 103 is 1 nm or less, 0.3 nm or less, or 0.
It is preferable to set it as 1 nm or less. In this specification and the like, the average surface roughness (Ra) is a three-dimensional extension of the arithmetic average roughness defined in JIS B 0601: 2001 (ISO 4287: 1997) so that it can be applied to a curved surface. Yes, expressed as a value obtained by averaging the absolute value of the deviation from the reference surface to the designated surface. In addition, as planarization treatment, chemical mechanical polishing (CMP) treatment, dry etching treatment, an inert gas such as argon gas is introduced into a vacuum chamber, and an electric field having a surface to be treated as a cathode is used. In addition, one or more of plasma treatment (so-called reverse sputtering) or the like can be applied to flatten fine irregularities on the surface.

Next, heat treatment is preferably performed. By the heat treatment, part of oxygen contained in the base insulating film 103 can be diffused in the vicinity of the interface between the base insulating film 103 and the oxide semiconductor film 105. As a result, interface states in the vicinity of the interface between the base insulating film 103 and the oxide semiconductor film 105 can be reduced.

The temperature of the heat treatment is typically 150 ° C. or more and less than the substrate strain point, preferably 250 ° C. or more and 450 ° C. or less, and more preferably 300 ° C. or more and 450 ° C. or less.

The heat treatment is performed in a rare gas such as helium, neon, argon, xenon, krypton, or an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Preferably, the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, and the like. Treatment time is 3 minutes to 24 hours.

Note that an oxide semiconductor film to be an oxide semiconductor film 105 later is formed over the base insulating film 103,
After the heat treatment, part of the oxide semiconductor film is etched to form the oxide semiconductor film 1.
May form 05. Through the step, oxygen which is included in the base insulating film 103 can be diffused in the vicinity of the interface between the base insulating film 103 and the oxide semiconductor film 105.

Next, as shown in FIG. 6B, a pair of electrodes 107 is formed. The pair of electrodes 107 can be formed using a method similar to that of the pair of electrodes 21 described in Embodiment 1 as appropriate. Alternatively, the pair of electrodes 107 can be formed by a printing method or an inkjet method.

Next, as shown in FIG. 6C, after the gate insulating film 109 is formed, the gate insulating film 109 is formed.
A gate electrode 111 is formed thereon.

The gate insulating film 109 can be formed using a method similar to that of the gate insulating film 17 described in Embodiment 1 to form a silicon oxide film or a silicon oxynitride film with high film density and few defects.

In addition, oxygen is easily moved along the formation surface or the surface of the CAAC-OS film. Thus, desorption of oxygen is likely to occur from the side surface of the element-separated oxide semiconductor film 105, and oxygen vacancies are easily formed. However, an oxide insulating film from which part of oxygen is released by heating is formed over the oxide semiconductor film 105, and a metal oxide film is provided as the gate insulating film 109 over the oxide insulating film; It is possible to suppress oxygen desorption from As a result, suppression of the increase in conductivity of the side surface of the oxide semiconductor film 105 can be suppressed.

For the gate electrode 111, the method for forming the gate electrode 15 described in Embodiment 1 can be used as appropriate.

Next, as shown in FIG. 6D, the insulating film 1 is formed on the gate insulating film 109 and the gate electrode 111.
After formation of the wiring 13, a wiring 115 connected to the pair of electrodes 107 is formed.

The insulating film 113 can be formed in the same manner as the insulating film 23 described in Embodiment 1.

Next, heat treatment is performed as in the first embodiment. The temperature of the heat treatment is typically 15
0 ° C. or more and less than the substrate strain point, preferably 250 ° C. or more and 450 ° C. or less, more preferably 300
° C to 450 ° C.

The wiring 115 is formed by forming a conductive film by a sputtering method, a CVD method, an evaporation method, or the like, and then forming a mask over the conductive film and etching the conductive film. The mask formed on the conductive film is
A printing method, an inkjet method, or a photolithography method can be used as appropriate. After this, the mask is removed. Alternatively, the wiring 115 may be formed by a dual damascene method.

Through the above steps, a transistor having excellent electrical characteristics and less variation in threshold voltage of the transistor and less variation in electrical characteristics can be manufactured. In addition, a highly reliable transistor with little change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Third Embodiment
In this embodiment, a transistor having a different structure from those in Embodiments 1 and 2 will be described with reference to FIGS. The transistor 120 described in this embodiment is different from the transistor 100 described in Embodiment 2 in that a pair of electrodes does not overlap with a gate electrode. Another difference is that a dopant is added to the oxide semiconductor film.

7A and 7B illustrate a top view and a cross-sectional view of the transistor 120. FIG. Figure 7 (A
7B is a top view of the transistor 120, and FIG. 7B is a cross-sectional view taken along dashed-dotted line A-B in FIG. 7A. Note that in FIG. 7A, the substrate 101 and the base insulating film 103 are provided for the sake of clarity.
, Part of the components of the transistor 120 (eg, the gate insulating film 109), the insulating film 113
Etc are omitted.

The transistor 120 illustrated in FIG. 7B includes an oxide semiconductor film 121 formed over the base insulating film 103, a pair of electrodes 107 in contact with the oxide semiconductor film 121, the base insulating film 103, and the oxide semiconductor film 121. And a gate insulating film 109 in contact with the pair of electrodes 107, and a gate electrode 129 overlapping with the oxide semiconductor film 121 with the gate insulating film 109 interposed therebetween. In addition, an insulating film 113 which covers the gate insulating film 109 and the gate electrode 129 is provided. Further, in the opening 110 (see FIG. 7A) of the gate insulating film 109 and the insulating film 113, the pair of electrodes 1 is formed.
A wiring 115 may be in contact with the wiring 07.

In the transistor 120 described in this embodiment, the first region 123 overlaps with the gate electrode 129 with the gate insulating film 109 in the oxide semiconductor film 121, and a pair of second regions 125 to which a dopant is added. And a pair of third regions 127 in contact with the pair of electrodes 107. Note that no dopant is added to the first region 123 and the third region 127. A pair of second regions 125 is provided to sandwich the first region 123. In addition, a pair of third regions 127 is provided so as to sandwich the first region 123 and the second region 125 therebetween.

The first region 123 functions as a channel region in the transistor 120. In a region in contact with the pair of electrodes 107 in the third region 127, part of oxygen is diffused to the pair of electrodes 107 by the pair of electrodes 107, oxygen deficiency is caused, and n-type is realized. Therefore, part of the third region 127 functions as a source region and a drain region. The second region is doped with a dopant and has high conductivity, so that it can function as a low resistance region and reduce the resistance between the channel region and the source and drain regions. Therefore, the transistor 120
Current and field effect mobility can be increased.

The dopant added to the second region 125 includes at least one or more of boron, nitrogen, phosphorus, and arsenic. Alternatively, there is at least one or more of helium, neon, argon, krypton, and xenon. Note that one or more of boron, nitrogen, phosphorus, and arsenic and one or more of helium, neon, argon, krypton, and xenon may be appropriately combined and contained as a dopant.

Further, the concentration of the dopant contained in the pair of second regions 125 is 5 × 10 ¹⁸ atoms.
/ Cm ³ or more and 1 × 10 ²² atoms / cm ³ or less, preferably 5 × 10 ¹⁸ atoms
/ Cm ³ or more and 5 × 10 ¹⁹ atoms / cm ^{3 or} less.

Since the second region 125 contains a dopant, carrier density or defects can be increased. Therefore, the conductivity can be enhanced as compared to the first region 123 and the third region 127 which do not contain a dopant. Note that if the dopant concentration is increased too much, the dopant will inhibit the movement of carriers, and the conductivity of the second region 125 will be reduced.

The second region 125 has a conductivity of 0.1 S / cm or more and 1000 S / cm or less, preferably 1
It is preferable to set it as 0 S / cm or more and 1000 S / cm or less.

Next, a method for manufacturing the transistor 120 described in this embodiment will be described with reference to FIGS.

As in Embodiment 2, through the steps of FIGS. 6A to 6B, the base insulating film 103 is formed over the substrate 101, and the oxide semiconductor film 121 is formed over the base insulating film 103. The pair of electrodes 107 is formed over the oxide semiconductor film 121. Next, the gate insulating film 109 is formed over the oxide semiconductor film 121 and the pair of electrodes 107, and the gate electrode 129 is formed to overlap with part of the oxide semiconductor film 121 with the gate insulating film 109 interposed therebetween. .

Here, an example of a method for forming a gate electrode which is miniaturized to a width equal to or less than the resolution limit of the exposure apparatus will be described. It is preferable that a slimming process be performed on a mask used for forming the gate electrode 129 to make a mask having a finer structure. As the slimming process, for example, an ashing process using an oxygen radical or the like can be applied. However, the slimming process may be a method other than the ashing process as long as the mask can be processed into a finer structure by a photolithography method or the like. In addition, since the mask formed by the slimming process determines the channel length of the transistor,
It is preferable to apply a process with good controllability. As a result of the slimming process, the mask formed by photolithography or the like is equal to or less than the resolution limit of the exposure apparatus, preferably 1/2.
It is possible to reduce the width to a width of 1/3 or less, more preferably. For example, the width of the formed mask is 20 nm or more and 2000 nm or less, preferably 50 nm or more and 350 n
m or less can be achieved. In addition, the gate electrode 1 miniaturized to a width equal to or less than the resolution limit of the exposure apparatus by etching the conductive film while retracting the slimmed mask.
29 can be formed.

Next, a dopant is added to the oxide semiconductor film 121 using the pair of electrodes 107 and the gate electrode 129 as a mask. As a method for adding a dopant to the oxide semiconductor film 121, an ion doping method or an ion implantation method can be used.

In addition, although the addition of the dopant to the oxide semiconductor film 121 shows a state in which the gate insulating film 109 is formed to cover the oxide semiconductor film 121, a state in which the oxide semiconductor film 121 is exposed The dopant may be added by

Furthermore, addition of the above-mentioned dopant can also be performed by methods other than implantation by ion doping method or ion implantation method. For example, the dopant can be added by generating plasma in a gas atmosphere containing an element to be added and performing plasma treatment on the oxide semiconductor film 121. As an apparatus for generating the plasma, a dry etching apparatus, a plasma CVD apparatus, or the like can be used.

Note that the addition processing of the dopant may be performed while heating the substrate 101.

Here, phosphorus is added to the oxide semiconductor film 121 by an ion implantation method.

After this, heat treatment is performed. The temperature of the heat treatment is typically 150 ° C. or more and 450 ° C. or less, preferably 250 ° C. or more and 325 ° C. or less. Alternatively, heating may be performed while gradually raising the temperature from 250 ° C to 325 ° C.

The heat treatment can increase the conductivity of the second region 125. Note that in the heat treatment, the first region 123, the second region 125, and the third region 127 have a polycrystalline structure, an amorphous structure, or a CAAC-OS.

Thereafter, as in the second embodiment, the insulating film 113 is formed and heat treatment is performed.
15 can be formed to form the transistor 120 shown in FIG.

Through the above steps, a transistor having excellent electrical characteristics and less variation in threshold voltage of the transistor and less variation in electrical characteristics can be manufactured. In addition, a highly reliable transistor with little change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Embodiment 4
In this embodiment, a transistor having a different structure from those in Embodiments 1 to 3 will be described with reference to FIGS. The transistor 130 described in this embodiment has a different structure from the oxide semiconductor film in the transistor described in the other embodiments, and an electric field relaxation region is provided between the channel region and the source and drain regions. Have.

8A and 8B illustrate a top view and a cross-sectional view of the transistor 130. FIG. Figure 8 (A
8B is a top view of the transistor 130, and FIG. 8B is a cross-sectional view taken along dashed-dotted line A-B in FIG. 8A. Note that in FIG. 8A, the substrate 101 and the base insulating film 103 are provided for the sake of clarity.
, Part of the components of the transistor 130 (eg, the gate insulating film 109), the insulating film 113
Etc are omitted.

The transistor 130 illustrated in FIG. 8B includes an oxide semiconductor film 131 formed over the base insulating film 103, a pair of electrodes 139 in contact with the oxide semiconductor film 131, the base insulating film 103, and the oxide semiconductor film 131. And a gate insulating film 109 in contact with the pair of electrodes 139, and a gate electrode 129 overlapping with the oxide semiconductor film 131 with the gate insulating film 109 interposed therebetween. In addition, an insulating film 113 which covers the gate insulating film 109 and the gate electrode 129 is provided. In addition, in the opening 110 of the gate insulating film 109 and the insulating film 113, the wiring 11 in contact with the pair of electrodes 139
And 5 may be provided.

In the transistor 130 described in this embodiment, in the oxide semiconductor film 131, a first region 133 overlapping with the gate electrode with the gate insulating film 109 interposed therebetween, a pair of second regions 135 to which a dopant is added, and a pair And a pair of third regions 137 in contact with the electrode 139 and doped with a dopant. Note that the dopant is not added to the first region 133. A pair of second regions 135 is provided to sandwich the first region 133. In addition, a pair of third regions 137 is provided so as to sandwich the first region 133 and the second region 135 therebetween.

As a dopant to be added to the second region 135 and the third region 137, Embodiment 3 can be used.
A dopant similar to that of the second region 125 shown in FIG.

Further, the concentration and the conductivity of the dopant included in the second region 135 and the third region 137 can be the same as the concentration of the dopant in the second region 125 described in Embodiment 3.
In the present embodiment, the third region 137 has a higher concentration and conductivity of the dopant than the second region 135.

The first region 133 functions as a channel region in the transistor 130. The second region 135 functions as an electric field relaxation region. In the third region 137, the pair of electrodes 13
Depending on the material of the pair of electrodes 139, part of oxygen diffuses to the pair of electrodes 139 in a region in contact with the electrode 9 and oxygen deficiency occurs, which results in n-type conversion. In addition, since a dopant is added to the third region 137 and conductivity is high, the contact resistance of the third region 137 and the pair of electrodes 139 can be further reduced. Thus, the on-state current and the field-effect mobility of the transistor 130 can be increased.

Note that in order to add a dopant to the third region 137, the pair of electrodes 139 preferably has a thin film thickness, typically 10 nm to 100 nm, and preferably 20 n.
m or more and 50 nm or less.

Next, a method for manufacturing the transistor 130 described in this embodiment will be described with reference to FIGS.

As in Embodiment 2, through the steps of FIGS. 6A and 6B, the base insulating film 103 is formed over the substrate 101, and the oxide semiconductor film 131 is formed over the base insulating film 103. A pair of electrodes 139 (see FIG. 8B) is formed over the oxide semiconductor film 131. Next, the gate insulating film 109 is formed over the oxide semiconductor film 131 and the pair of electrodes 139, and the gate electrode 129 is formed to overlap with part of the oxide semiconductor film 131 with the gate insulating film 109 interposed therebetween. .

Next, a dopant is added to the oxide semiconductor film 131 using the gate electrode 129 as a mask. As a method for adding a dopant, the method described in Embodiment 3 can be used as appropriate. Note that
In this embodiment mode, a dopant is added to the third region 137 as well as the second region 135. Furthermore, the concentration of the dopant is higher in the third region 137 than in the second region 135. Therefore, the conditions of the addition method are appropriately used so that the peak of the profile of the dopant concentration becomes the third region 137. At this time, the third region 137 overlaps with the pair of electrodes 139, but
The second region 135 does not overlap with the pair of electrodes 139. Therefore, in the second region 135, the peak of the profile of the dopant concentration serves as the base insulating film 103.
The concentration of dopant at 35 is lower than in the third region 137.

After this, heat treatment is performed. The temperature of the heat treatment is typically 150 ° C. or more and 450 ° C. or less, preferably 250 ° C. or more and 325 ° C. or less. Alternatively, heating may be performed while gradually raising the temperature from 250 ° C to 325 ° C.

By the heat treatment, the conductivity of the second region 135 and the third region 137 can be increased. Note that in the heat treatment, the first region 133, the second region 135, and the third region 137 have a polycrystalline structure, an amorphous structure, or a CAAC-OS.

Thereafter, as in the second embodiment, the insulating film 113 is formed and heat treatment is performed.
15 can be formed to form the transistor 130 shown in FIG.

In the oxide semiconductor film 131, the transistor 130 described in this embodiment is a first region 133 which serves as a channel region and a third region 1 which functions as a source region and a drain region.
Between 37 is a second region 135 which functions as a field relaxation region. Therefore, deterioration of the transistor can be suppressed as compared to the transistor 100 described in Embodiment 2. In addition, since the third region 137 in contact with the pair of electrodes 139 contains a dopant, the contact resistance between the pair of electrodes 139 and the third region 137 can be further reduced, and a transistor with an increased on-state current can be obtained. It can be made. In addition, a transistor with excellent electrical characteristics, which has less variation in threshold voltage of the transistor and less variation in electrical characteristics, can be manufactured. In addition, a highly reliable transistor with little change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Fifth Embodiment
In this embodiment, a transistor having a structure different from that in Embodiments 1 to 4 is described with reference to FIG.

The transistor 210 illustrated in FIG. 9A includes the base insulating film 103 provided over the substrate 101, the oxide semiconductor film 211 formed over the base insulating film 103, the base insulating film 103, and the oxide semiconductor film 211. The gate insulating film 109 is in contact with a gate electrode 129 which overlaps with the oxide semiconductor film 211 with the gate insulating film 109 interposed therebetween. Further, the insulating film 217 which covers the gate insulating film 109 and the gate electrode 129 and a wiring 219 which is in contact with the oxide semiconductor film 211 in the opening portion of the gate insulating film 109 and the insulating film 217 is provided.

In the transistor 210 described in this embodiment, the oxide semiconductor film 211 includes a gate electrode 129.
And a gate insulating film 109 and a first region 213 overlapping with each other, and a pair of second regions 215 to which a dopant is added. Note that the dopant is not added to the first region 213. In addition, a pair of second regions 215 is provided so as to sandwich the first region 213.

The first region 213 functions as a channel region in the transistor 210. The second region 215 functions as a source region and a drain region.

As a dopant to be added to the second region 215, the second region 12 described in Embodiment 3 can be used.
A dopant similar to 5 can be used as appropriate.

Further, the concentration and conductivity of the dopant included in the second region 215 can be the same as the concentration of the dopant in the second region 125 described in Embodiment 3.

The transistor 220 illustrated in FIG. 9B includes a base insulating film 103 provided over the substrate 101, an oxide semiconductor film 211 provided over the base insulating film 103, and a source electrode and a drain in contact with the oxide semiconductor film 211. A pair of electrodes 225 functioning as electrodes, a gate insulating film 223 in contact with at least part of the oxide semiconductor film 211, and a gate electrode 129 over the gate insulating film 223 and overlapping with the oxide semiconductor film 211 Have.

In addition, sidewall insulating films 221 in contact with the side surfaces of the gate electrode 129 are provided. The base insulating film 103, the gate electrode 129, the sidewall insulating film 221, and the pair of electrodes 22 are also provided.
An insulating film 217 is provided over the device 5. In the opening of the insulating film 217, the pair of electrodes 225 is formed.
And a wire 219 in contact with the device.

In the transistor illustrated in FIG. 9B, the oxide semiconductor film 211 includes a first region 213 overlapping with the gate electrode 129 with the gate insulating film 223 interposed therebetween, and a pair of second regions 215 to which a dopant is added. Have. Note that the dopant is not added to the first region 213. A pair of second regions 215 is provided to sandwich the first region 213.

End portions of the pair of electrodes 225 of the transistor are located over the sidewall insulating film 221, and in the oxide semiconductor film 211, the pair of electrodes 225 includes all exposed portions of the pair of second regions 215 including a dopant. Covering. Therefore, the source electrode in the channel length direction
The distance between the drain electrodes (more precisely, the oxide semiconductor film 211 in contact with the pair of electrodes 225
The distance between the two) can be controlled by the width of the sidewall insulating film 221. That is, in a fine device in which it is difficult to form a pattern using a mask, the oxide semiconductor film 21
The end portions on the channel side of the pair of electrodes 225 in contact with 1 can be formed without using a mask. In addition, since no mask is used, processing variations in a plurality of transistors can be reduced.

Gate insulating films 109 and 22 provided in the transistors 210 and 220 described in this embodiment.
3 is an insulating film having a high film density and few defects. As a result, a transistor with excellent electrical characteristics can be manufactured, which has less variation in threshold voltage of the transistor and less variation in electrical characteristics. In addition, a highly reliable transistor with little change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Sixth Embodiment
In this embodiment, a transistor having a different structure from those in Embodiments 1 to 5 will be described with reference to FIGS. The transistor described in this embodiment is characterized by having a plurality of gate electrodes facing each other through an oxide semiconductor film. Although this embodiment mode will be described using the transistor described in Embodiment Mode 2, this embodiment mode can be combined with other embodiment modes as appropriate.

The transistor 230 illustrated in FIG. 10 includes a gate electrode 231 provided over the substrate 101 and an insulating film 233 which covers the gate electrode 231. In addition, an oxide semiconductor film 105 formed over the insulating film 233, a pair of electrodes 107 in contact with the oxide semiconductor film 105, an insulating film 233, and
The oxide semiconductor film 105 and the gate insulating film 109 in contact with the pair of electrodes 107 and the gate electrode 111 overlapping with the oxide semiconductor film 105 with the gate insulating film 109 interposed therebetween are included. Also,
An insulating film 113 covering the gate insulating film 109 and the gate electrode 111 is provided. In addition, the opening portion of the gate insulating film 109 and the insulating film 113 may have a wiring 115 in contact with the pair of electrodes 107.

The gate electrode 231 can be formed in the same manner as the gate electrode 15 described in Embodiment 1. Note that in order to enhance the coverage of the insulating film 233 to be formed later, the gate electrode 231 preferably has a tapered side surface, and the angle between the substrate 101 and the side surface of the gate electrode 231 is 20 degrees to 70 degrees. Hereinafter, preferably, it is 30 degrees or more and 60 degrees or less.

The insulating film 233 can be formed in the same manner as the base insulating film 103 described in Embodiment 2.
Note that in order to form the oxide semiconductor film 105 over the insulating film 233 later, the surface of the insulating film 233 is preferably flat. Therefore, the insulating film to be the insulating film 233 later is used as the substrate 101.
After the insulating film is formed over the gate electrode 231, the insulating film is planarized to form the insulating film 233 with few surface irregularities.

The transistor 230 described in this embodiment includes the gate electrode 231 and the gate electrode 111 which are opposed to each other with the oxide semiconductor film 105 interposed therebetween. The threshold voltage of the transistor 230 is controlled by applying different potentials to the gate electrode 231 and the gate electrode 111, preferably,
The threshold voltage can be positively shifted.

The gate insulating film 109 provided in the transistor 230 described in this embodiment is a high-density insulating film with few defects. As a result, a transistor with excellent electrical characteristics can be manufactured, which has less variation in threshold voltage of the transistor and less variation in electrical characteristics. In addition, a highly reliable transistor with little change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

Seventh Embodiment
In this embodiment, a method for manufacturing the transistor described in any of Embodiments 1 to 6 in which the concentration of hydrogen contained in the oxide semiconductor film is reduced is described. Here, although the description will be made typically using Embodiment 1 and Embodiment 2, they can be combined with other embodiments as appropriate. Note that one or more of the steps described in this embodiment may be combined with the manufacturing steps of the transistor described in Embodiments 1 and 2, and it is not necessary to combine them all.

In the oxide semiconductor film 19 described in Embodiment 1 and the oxide semiconductor film 105 described in Embodiment 2, the hydrogen concentration is less than 5 × 10 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ at.
It is preferable that oms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, and still more preferably 1 × 10 ¹⁶ atoms / cm ³ or less.

Hydrogen contained in the oxide semiconductor films 19 and 105 reacts with oxygen bonded to metal atoms to form water, and defects are formed in a lattice from which oxygen is released (or a portion from which oxygen is released). I will. Further, hydrogen bonds with oxygen to generate electrons as carriers. For these reasons, the concentration of hydrogen in the oxide semiconductor film can be reduced by extremely reducing the impurity containing hydrogen in the step of forming the oxide semiconductor film. Therefore, negative shift of the threshold voltage can be reduced by removing hydrogen as much as possible and using a highly purified oxide semiconductor film as a channel region, and between the source electrode and the drain electrode of the transistor. Leakage current that occurs is typically a few yA / off current per channel width.
The electric characteristics can be reduced to μm to several zA / μm, and the electric characteristics of the transistor can be improved.

As a first method of reducing the hydrogen concentration in the oxide semiconductor film 19, the substrate 11, the base insulating film 13, the gate electrode 15, and the gate insulating film are formed by heat treatment or plasma treatment before the oxide semiconductor film 19 is formed. There is a method of desorbing hydrogen or water contained in each of the membranes 17. As a result, diffusion of hydrogen or water attached to or contained in the substrate 11 to the gate insulating film 17 into the oxide semiconductor film 19 can be prevented in heat treatment to be performed later. The heat treatment is performed in an inert atmosphere, a reduced pressure atmosphere, or a dry air atmosphere at a temperature of 100 ° C. or more and less than the strain point of the substrate. In addition, plasma treatment uses a rare gas, oxygen, nitrogen, or nitrogen oxide (such as nitrous oxide, nitrogen monoxide, or nitrogen dioxide). Note that in Embodiment Modes 2 to 6, heat treatment or plasma treatment is performed before the oxide semiconductor film 105 is formed.
Hydrogen or water contained in each of the substrate 101 and the base insulating film 103 is released.

As a second method of reducing the hydrogen concentration in the oxide semiconductor films 19 and 105, the dummy substrate is carried into the sputtering apparatus before the oxide semiconductor film is formed by the sputtering apparatus, and the oxide semiconductor is deposited on the dummy substrate. Hydrogen deposited on the target surface or anti-adhesion plate
There is a way to remove water etc. As a result, mixing of hydrogen, water, and the like into the oxide semiconductor film can be reduced.

As a third method of reducing the hydrogen concentration in the oxide semiconductor films 19 and 105, the substrate temperature is set to 150 ° C. or higher, for example, in the case of using a sputtering method in forming the oxide semiconductor film.
0 ° C. or less, preferably 150 ° C. or more and 450 ° C. or less, more preferably 200 ° C. or more and 350 or more
There is a method in which an oxide semiconductor film is formed at a temperature lower than or equal to ° C. By this method, the mixing of hydrogen, water, and the like into the oxide semiconductor film can be reduced.

Here, the sputtering apparatus capable of reducing the concentration of hydrogen contained in the oxide semiconductor films 19 and 105 will be described in detail below.

In the treatment chamber for forming the oxide semiconductor film, the leak rate is preferably 1 × 10 ⁻¹⁰ Pa · m ³ / sec or less, whereby hydrogen or water in the film is deposited by sputtering. And the like can be reduced.

In order to evacuate the processing chamber of the sputtering apparatus, a roughing pump such as a dry pump and a high vacuum pump such as a sputter ion pump, a turbo molecular pump, or a cryopump may be appropriately combined. While turbo molecular pumps excel at evacuating large sized molecules, they have low evacuating ability of hydrogen and water. Furthermore, it is effective to combine a sputter ion pump having a high hydrogen discharge capacity or a cryopump having a high water discharge capacity.

Although the adsorbate present inside the processing chamber does not affect the pressure in the processing chamber because it is adsorbed on the inner wall, it causes gas release when the processing chamber is exhausted. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to desorb the adsorbate present in the processing chamber as much as possible and exhaust the exhaust beforehand by using a pump having a high exhaust capacity. Note that the processing chamber may be baked to promote desorption of the adsorbate. By the baking, the desorption rate of the adsorbate can be increased about 10 times. Baking may be performed at 100 ° C. or more and 450 ° C. or less. At this time, if the adsorbate is removed while introducing an inert gas, it is possible to further increase the desorption rate of water or the like which is difficult to be detached only by exhausting.

As described above, in the film formation step of the oxide semiconductor film, mixing of impurities such as hydrogen or water contained in the oxide semiconductor film is suppressed by minimizing the mixing of impurities in the pressure of the treatment chamber, the leak rate of the treatment chamber, and the like. It can be reduced.

As a fourth method for reducing the hydrogen concentration in the oxide semiconductor films 19 and 105, there is a method using a high purity gas from which an impurity containing hydrogen is removed as a source gas. As a result, mixing of hydrogen, water, and the like into the oxide semiconductor film can be reduced.

As a fifth method for reducing the hydrogen concentration in the oxide semiconductor films 19 and 105, there is a method in which heat treatment is performed after the oxide semiconductor film is formed. By the heat treatment, the oxide semiconductor film can be dehydrogenated or dehydrated.

The temperature of the heat treatment is typically 150 ° C. or more and less than the substrate strain point, preferably 250 ° C. or more and 450 ° C. or less, and more preferably 300 ° C. or more and 450 ° C. or less.

The heat treatment is performed in a rare gas such as helium, neon, argon, xenon, krypton, or an inert gas atmosphere containing nitrogen. Alternatively, after heating in an inert gas atmosphere, heating may be performed in an oxygen atmosphere. Preferably, the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, and the like. Treatment time is 3 minutes to 24 hours.

Note that, as shown in FIGS. 2B and 6A, the oxide semiconductor films 19 and 10 are separated.
After forming 5, the heat treatment for the above dehydrogenation or dehydration may be performed. By passing through such a step, the gate insulating film 1 is heated in the heat treatment for dehydrogenation or dehydration.
Or hydrogen or water contained in the base insulating film 103 can be released efficiently.

Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times, and may be combined with another heat treatment.

By combining one or more of the first to fifth methods for reducing the concentration of hydrogen in the oxide semiconductor film with the method for manufacturing a transistor described in Embodiments 1 to 6, hydrogen, water, and the like can be obtained. As much as possible, the transistor including the highly purified oxide semiconductor film in the channel region can be manufactured. As a result, the negative shift of the threshold voltage can be reduced, and the leakage current generated between the source electrode and the drain electrode of the transistor can be typically represented by several off current per channel width It can be reduced to several zA / μm, and the electrical characteristics of the transistor can be improved. From the above, according to the present embodiment, the negative shift of the threshold is reduced, and the leakage current is low.
A transistor having excellent electrical characteristics can be manufactured.

Eighth Embodiment
In this embodiment mode, a semiconductor device includes a transistor including a first semiconductor material in a lower portion and a transistor including a second semiconductor material in an upper portion, and the transistor includes the first semiconductor material. A structure using a semiconductor substrate will be described with reference to FIG.

FIG. 11 is an example illustrating a cross-sectional configuration of a semiconductor device including a transistor including a first semiconductor material in the lower portion and a transistor including a second semiconductor material in the upper portion. Where the first
The second semiconductor material and the second semiconductor material use different materials. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor, and the second semiconductor material can be an oxide semiconductor. As a material other than the oxide semiconductor, for example, silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor or a polycrystalline semiconductor is preferably used. A transistor using a single crystal semiconductor can operate at high speed. On the other hand, a transistor including an oxide semiconductor can be used in a circuit in which off-state current per channel width is sufficiently low such as several yA / μm to several zA / μm. From these things, for example, a logic circuit with low power consumption can also be configured using the semiconductor device shown in FIG. Note that an organic semiconductor material or the like may be used as the first semiconductor material.

The transistor 704a, the transistor 704b, and the transistor 704c are each n.
Channel type transistor (NMOSFET) or p channel type transistor (PMOS
Any of FET) can be used. Here, p-channel transistors are illustrated as the transistor 704 a and the transistor 704 b, and n
A channel type transistor is shown. In the example illustrated in FIG. 11, the transistor 704 a and the transistor 704 b are STI (Shallow Trench Isolation).
n) isolated from other elements by 702; On the other hand, the transistor 704 c is
The transistor 702 is isolated from the transistors 704 a and 704 b by the TI 702. STI7
The use of O.02 makes it possible to suppress bird's beaks of the element isolation portion generated by the element isolation method using LOCOS, and to make the element isolation portion smaller. On the other hand, in the semiconductor device in which miniaturization of the structure of the transistor is not required, the formation of the STI 702 is not necessarily required, and an element separation unit such as LOCOS can be used.

The transistor 704a, the transistor 704b, and the transistor 704c in FIG.
A channel region provided in the substrate 701, an impurity region 705 (also referred to as a source region and a drain region) provided so as to sandwich the channel region, and a gate insulating film 706 provided over the channel region. Gate electrodes 707 and 708 are provided over the gate insulating film 706 so as to overlap with the channel region. The gate electrode can have a structure in which a gate electrode 707 made of a first material for enhancing processing accuracy and a gate electrode 708 made of a second material for reducing resistance are stacked. Not only the structure but also materials, the number of layers, the shape, etc. can be adjusted appropriately according to the required specifications. Note that although there may be a case where the source electrode and the drain electrode are not explicitly shown in the drawing, the transistor may be referred to for convenience including such a state.

Further, a contact plug 714 a is connected to the impurity region 705 provided in the substrate 701. Here, the contact plug 714a also functions as a source electrode or a drain electrode of the transistor 704a or the like. Also, between the impurity region 705 and the channel region,
An impurity region different from the impurity region 705 is provided. The impurity region functions as an LDD region or an extension region to control the electric field distribution in the vicinity of the channel region depending on the concentration of the introduced impurity. A sidewall insulating film 710 is provided on side walls of the gate electrodes 707 and 708 with an insulating film 709 interposed therebetween. By using the insulating film 709 and the sidewall insulating film 710, an LDD region or an extension region can be formed.

The transistor 704 a, the transistor 704 b, and the transistor 704 c are covered with the insulating film 711. The insulating film 711 can have a function as a protective film and can prevent impurities from entering the channel region from the outside. Insulating film 7
By using 11 as a material such as silicon nitride by the CVD method, when single crystal silicon is used for the channel region, hydrogenation of the single crystal silicon can be performed by heat treatment. Further, by using an insulating film having tensile stress or compressive stress as the insulating film 711, distortion can be given to the semiconductor material forming the channel region. In the case of an n-channel transistor, tensile stress is applied to the silicon material serving as the channel region, and in the case of the p-channel transistor, compressive stress is applied to the silicon material serving as the channel region, whereby the mobility of each transistor is obtained. It can be improved.

Here, the transistor 750 in FIG.
It has the same structure as 0. Further, the base insulating film of the transistor 750 is a barrier film 724,
It has a three-layer structure of an insulating film 725a and an insulating film 725b, and includes a gate electrode 751 which faces the oxide semiconductor film of the transistor 750 with a base insulating film interposed therebetween. The insulating film 725 a is preferably formed using an insulating film having a blocking effect of hydrogen, water, and oxygen, and is typically formed using an aluminum oxide film. The insulating film 725 b is the base insulating film 1 described in Embodiment 2.
03 can be used appropriately.

Note that although the transistor 100 described in Embodiment 2 is described here as the transistor 750, any of the transistors described in Embodiments 1 to 7 can be used as appropriate.

A transistor 750 using a second semiconductor material is electrically connected to a transistor using a first semiconductor material such as the transistor 704 a in the lower layer depending on a necessary circuit configuration. Figure 11.
11A shows, as an example, a structure in which the source electrode or the drain electrode of the transistor 750 is electrically connected to the source electrode or the drain electrode of the transistor 704a.

One of a source electrode and a drain electrode of a transistor 750 using a second semiconductor material is a gate insulating film 726, an insulating film 727, an insulating film 728, and an insulating film 72 of the transistor 750.
It is connected to a wiring 734 a formed higher than the transistor 750 through the contact plug 730 b penetrating through 9. The structures and materials described in Embodiment Modes 1 to 7 can be used as appropriate for the gate insulating film 726 and the insulating film 727.

The wiring 734 a is embedded in the insulating film 731. The wiring 734a is preferably made of a low-resistance conductive material such as copper or aluminum. By using a low resistance conductive material, RC delay of a signal propagating through the wiring 734a can be reduced. Wiring 734a
In the case of using copper, the barrier film 733 is formed to prevent the diffusion of copper into the channel region. As the barrier film, for example, a film of tantalum nitride, a laminate of tantalum nitride and tantalum, titanium nitride, a laminate of titanium nitride and titanium, etc. can be used, but the diffusion preventing function of the wiring material, the wiring material, the base film, etc. It is not limited to the film made of these materials to the extent that the adhesion with them is secured. The barrier film 733 may be formed as a layer separate from the wiring 734a, and a material serving as a barrier film is contained in the wiring material and deposited on the inner wall of the opening provided in the insulating film 731 by heat treatment. It is good.

As the insulating film 731, silicon oxide, silicon oxynitride, silicon nitride oxide, BPSG (B
oron Phosphorus Silicate Glass, PSG (Phos
phorus Silicate Glass, silicon oxide doped with carbon (SiO 2)
C) Silicon oxide (SiOF) to which fluorine is added, TEOS (Tetraethyl orthosilicate) which is silicon oxide starting from Si (OC ₂ H ₅ ) ₄ ,
HSQ (Hydrogen Silsesquioxane), MSQ (Methyl)
Silsesquioxane), OSG (Organo Silicate Glas)
s), insulators such as organic polymer materials can be used. In particular, when the miniaturization of the semiconductor device is promoted, the parasitic capacitance between the interconnections becomes remarkable and the signal delay increases, so that the dielectric constant of silicon oxide (k = 4.0 to 4.5) is high, k is 3 It is preferable to use a material of .0 or less. In addition, since the CMP process is performed after the wiring is embedded in the insulating film, the insulating film is required to have mechanical strength. As long as this mechanical strength can be secured, they can be made porous (porous) to lower the dielectric constant. The insulating film 731 is formed by a sputtering method, a CVD method, a coating method including a spin coating method (also referred to as spin on glass (SOG)), or the like.

An insulating film 732 may be provided over the insulating film 731. The insulating film 732 functions as an etching stopper at the time of performing planarization processing by CMP or the like after the wiring material is embedded in the insulating film 731.

A barrier film 735 is provided over the wiring 734 a, and a protective film 74 is formed over the barrier film 735.
0 is provided. The barrier film 735 is a film intended to prevent the diffusion of a wiring material such as copper. The barrier film 735 is not limited to only the upper surface of the wiring 734 a, and the insulating films 731 and 73.
You may form on two. The barrier film 735 can be formed of an insulating material such as silicon nitride, SiC, or SiBON.

The wiring 734 a is connected to the wiring 723 provided below the barrier film 724 through the contact plug 730 a. Unlike the contact plug 730b, the contact plug 730a penetrates the barrier film 724, the insulating film 725a, the insulating film 725b, the gate insulating film 726, the insulating film 727, the insulating film 728, and the insulating film 729 to be electrically connected to the wiring 723. doing.
Therefore, the contact plug 730a is taller than the contact plug 730b. When the diameters of the contact plug 730a and the contact plug 730b are equal, the aspect ratio of the contact plug 730a is larger, but the diameters of the contact plug 730a and the contact plug 730b can be different. Although the contact plug 730 a is described as a series formed of one material, for example, the barrier film 724
, A contact plug penetrating the insulating film 725a and the insulating film 725b, and a gate insulating film 7
A contact plug penetrating through the insulating film 727, the insulating film 728 and the insulating film 729 may be separately formed separately.

The wiring 723 is covered with the barrier films 722 and 724 in the same manner as the wirings 734 a and 734 b, and is embedded in the insulating film 720. As shown in FIG. 11, the wiring 723 is composed of an upper wiring portion and a lower via hole portion. The lower via hole portion is connected to the lower wiring 718. The wiring 723 having this structure can be formed by a so-called dual damascene method or the like. Further, the connection between the upper and lower layers may be connected using a contact plug instead of the dual damascene method. Over the insulating film 720, an insulating film 721 may be provided which functions as an etching stopper at the time of performing planarization treatment by CMP or the like.

The wiring 718 to which the wiring 723 is electrically connected can also be formed with the same structure as the wiring layer in the upper layer of the transistor 750 described above. The transistor 704 a using a first semiconductor material such as silicon for the channel region includes the insulating film 711, the insulating film 712, and the insulating film 7.
It is connected to the wiring 718 through the contact plug 714a passing through 13. The gate electrode of the transistor 704 c using a first semiconductor material such as silicon for the channel region is connected to the wiring 718 through the insulating film 711, the insulating film 712, and the contact plug 714 b penetrating the insulating film 713. The wire 718 is a barrier film 7 in the same manner as the wires 734 a and 734 b described above.
17 and 719, and embedded in the insulating film 715. Insulating film 7
An insulating film 716 which functions as an etching stopper at the time of performing a planarization process by CMP or the like may be provided on the surface 15.

As described above, the transistor 7 using the first semiconductor material provided below the semiconductor device
The transistor 04 a is electrically connected to the transistor 750 using the second semiconductor material provided in the upper portion through the plurality of contact plugs and the plurality of wirings. By configuring the semiconductor device as described above, the transistor using the first semiconductor material having high-speed operation performance is combined with the transistor using the second semiconductor material having extremely low off-state current to achieve low power consumption. A semiconductor device having a high-speed logic circuit which can be integrated, for example, a memory device, a central processing unit (CPU), or the like can be manufactured.

Such a semiconductor device is not limited to the above-described configuration, and within the scope of the present invention,
It can be changed arbitrarily. For example, although the wiring layer between the transistor using the first semiconductor material and the transistor using the second semiconductor material is described as two layers in the description, it may be one layer or three or more layers. Alternatively, both transistors can be directly connected only by the contact plug without using a wire. In this case, for example, through silicon via (TSV) technology can also be used. In addition, although the case where the wiring is formed by embedding a material such as copper in the insulating film has been described, for example, a three-layer structure of a barrier film, a wiring material layer, and a barrier film is processed into a wiring pattern by photolithography. May be used.

In particular, in the case where the copper wiring is formed in a hierarchy between the transistors 704 a and 704 b using the first semiconductor material and the transistor 750 using the second semiconductor material, the transistor 750 using the second semiconductor material is used. It is necessary to fully consider the effect of heat treatment added in the manufacturing process of In other words, it is necessary to be careful that the temperature of the heat treatment added in the manufacturing process of the transistor 750 using the second semiconductor material conforms to the property of the wiring material. For example, when heat treatment is performed on a component of the transistor 750 at high temperature, thermal stress is generated in the copper wiring, which causes disadvantages such as stress migration.

Here, one mode of a logic circuit included in the semiconductor device illustrated in FIG. 11 is described with reference to FIG. Here, a NOR circuit and a NAND circuit are described as one embodiment of the logic circuit.

FIG. 12A is a circuit diagram of a NOR circuit, and FIG. 12B is a circuit diagram of a NAND circuit.

In the NOR circuit shown in FIG. 12A, the transistor 761 and the transistor 762 are p-channel transistors. The transistor 763 and the transistor 764 are n-channel transistors, to which any of the transistors described in any of the above embodiments can be applied.

In the NAND circuit illustrated in FIG. 12B, the transistor 771 and the transistor 77 can be used.
4 is a p-channel transistor. The transistor 772 and the transistor 773 have n
It is a channel transistor and the transistor described in any of the above embodiments can be applied. Note that the OS described in FIGS. 12A and 12B indicates that the transistor described in any of the above embodiments can be applied to the transistor 763, the transistor 764, the transistor 772, and the transistor 773.

Note that in the NOR circuit and the NAND circuit illustrated in FIGS. 12A and 12B, the transistor 763, the transistor 764, the transistor 772, and the transistor 773 are not
The transistor 750 including a plurality of gate electrodes through an oxide semiconductor film as illustrated in FIG. 11 can also be applied. With such a structure, by applying different potentials to the plurality of gate electrodes, the threshold voltage of the transistor can be controlled, and preferably, the threshold voltage can be positively shifted. Alternatively, by applying the same potential to the plurality of gate electrodes, the on-state current of the transistor can be increased.

Here, the cross-sectional structure of the NAND circuit illustrated in FIG. 12A will be described with reference to FIG. Figure 1
A transistor 761 and a transistor 762 which are shown in FIG. 2A correspond to the transistor 704 a and the transistor 704 b which are shown in FIG. Further, the transistor 763 illustrated in FIG. 12A corresponds to the transistor 750 illustrated in FIG. Note that the connection portion of the gate electrodes of the transistor 762 and the transistor 763 illustrated in FIG.
Is omitted.

When an insulating film with high film density and few defects is used as a gate insulating film provided in the transistor 750, the transistor 763, the transistor 764, the transistor 772, and the transistor 773 described in this embodiment, the threshold voltage of the transistor Thus, a transistor with excellent electrical characteristics can be manufactured, with less variation in electrical characteristics and less variation in electrical characteristics. In addition, a highly reliable semiconductor device with less change in electrical characteristics due to change with time or light gate BT stress test can be manufactured.

Note that the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments and examples.

(Embodiment 9)
Examples of the semiconductor device described in the above embodiment include a central processing unit, a microprocessor, a microcomputer, a memory device, an image sensor, an electro-optical device, a light-emitting display device, and the like. In addition, the semiconductor device can be applied to various electronic devices. As an electronic device, for example, a display device, a lighting device, a personal computer, a word processor,
Image playback device, portable CD player, radio, tape recorder, headphone stereo, stereo, clock, cordless handset, transceiver, portable radio, mobile phone, smartphone, electronic book, car phone, portable game machine, calculator, portable Information terminal, electronic notebook, electronic translator, voice input device, video camera, digital still camera, electric shaver, high frequency heating device, electric rice cooker, electric washing machine, electric vacuum cleaner, water heater, fan, hair dryer, air dryer Conditioner, Humidifier, Dehumidifier, Air Conditioner, Dishwasher, Dishware Dryer, Clothes Dryer, Duvet Dryer, Electric Refrigerator, Electric Freezer, Electric Refrigerator, Electric Freezer, DNA Storage Freezer, Flashlight,
Tools, smoke detectors, medical devices, guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, electric vehicles, hybrid vehicles, plug-in hybrid vehicles, tracked vehicles, motorized bicycles, motorcycles , Electric wheelchairs, golf carts, ships, submarines, helicopters, aircraft, rockets, satellites, space probes, planet probes, spacecrafts, etc. In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to a mobile device such as a mobile phone, a smartphone, or an e-book reader will be described with reference to FIGS.

In portable devices such as mobile phones, smart phones, and electronic books, SRAMs or DRAMs are used for temporary storage of image data. The reason why the SRAM or DRAM is used is that the response is slow in the flash memory and unsuitable for the image processing.
On the other hand, when SRAM or DRAM is used for temporary storage of image data, there are the following features.

In a typical SRAM, as shown in FIG.
It is composed of six transistors of 806 and is driven by an X decoder 807 and a Y decoder 808. Transistor 803, Transistor 805, Transistor 8
The transistor 04 and the transistor 806 constitute an inverter to enable high speed driving. But 1
Since one memory cell is composed of six transistors, there is a disadvantage that the cell area is large. The memory cell area of SRAM is usually 10 when the minimum size of design rule is F.
It is a 0~150F ^2. Therefore, the unit price per bit of SRAM is the highest among various memories.

On the other hand, in the DRAM, the memory cell is the transistor 811 as shown in FIG.
A storage capacitor 812 is constituted and driven by an X decoder 813 and a Y decoder 814. One cell consists of one transistor and one capacitor, and the area is small.
The memory cell area of DRAM is usually 10 F ² or less. However, DRAM always needs to be refreshed, and consumes power even when rewriting is not performed.

However, by using the transistor with low off-state current described in the above embodiment for the transistor 811, the charge of the storage capacitor 812 can be held for a long time, and frequent refresh is not necessary. Therefore, power consumption can be reduced.

FIG. 14 shows a block diagram of the portable device. The portable device illustrated in FIG. 14 includes an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, and a touch. Sensor 919,
An audio circuit 917, a keyboard 918 and the like are included. The display 913 includes a display unit 914, a source driver 915, and a gate driver 916. The application processor 906 is a central processing unit (CPU 907), a DSP 908,
It has an interface (IF) 909. In general, the memory circuit 912 is formed of an SRAM or a DRAM, and by adopting the semiconductor device described in the above embodiment for this portion, high-speed writing and reading of information and long-term storage can be realized. Power consumption can be sufficiently reduced. In addition, the main storage device for storing data and instructions included in the CPU 907, and a buffer storage device such as a register and cache which can write and read data at high speed, the semiconductor device described in the above embodiments. By adopting this feature, the power consumption of the CPU can be sufficiently reduced.

FIG. 15 shows an example in which the semiconductor device described in the above embodiment is used for the memory circuit 950 of the display. The memory circuit 950 illustrated in FIG. 15 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. The memory circuit also includes image data (input image data) input from the signal line, the memory 952,
A display controller 956 for reading out and controlling data stored in the memory 953 (stored image data) and a display 957 for displaying by a signal from the display controller 956 are connected.

First, certain image data is formed by an application processor (not shown) (input image data A). Input image data A is stored in memory 952 via switch 954. The image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and displayed.

When there is no change in the input image data A, the stored image data A is read from the memory 952 from the display controller 956 via the switch 955 in a cycle of about 30 to 60 Hz.

Next, for example, when the user performs an operation to rewrite the screen (ie, input image data A
(If there is a change), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. Also during this time, stored image data A is read from the memory 952 via the switch 955 periodically. When new image data (stored image data B) is stored in the memory 953,
The stored image data B is read from the next frame of the display 957 and the switch 95
The stored image data B is sent to the display 957 via the display controller 956 and the display controller 956 to perform display. This read is further continued until new image data is stored in the memory 952.

As described above, the memory 952 and the memory 953 alternately perform writing of image data and reading of image data to perform display on the display 957. Memory 9
The memory 52 and the memory 953 are not limited to separate memories, and one memory may be divided and used. By employing the semiconductor device described in the above embodiment for the memory 952 and the memory 953, writing and reading of information can be performed at high speed, storage can be held for a long time, and power consumption can be sufficiently reduced. it can.

FIG. 16 shows a block diagram of the electronic book. FIG. 16 shows a battery 1001 and a power supply circuit 1002.
, A microprocessor 1003, a flash memory 1004, an audio circuit 1005, a keyboard 1006, a memory circuit 1007, a touch panel 1008, a display 1009, and a display controller 1010.

Here, the semiconductor device described in the above embodiment can be used for the memory circuit 1007 in FIG. The memory circuit 1007 has a function of temporarily retaining the contents of a book. An example of the function is when the user uses the highlight function. When the user is reading an e-book, he may want to mark a specific place. This marking function is called highlight function, and it is to show the difference from the surroundings by changing the color of the display, drawing an underline, thickening the character, changing the font of the character, etc. It is a function to store and hold information of the part specified by the user. If this information is to be stored for a long time, it may be copied to the flash memory 1004. Even in such a case, by employing the semiconductor device described in the above embodiment, high-speed writing and reading of information, long-term storage retention can be achieved, and power consumption can be sufficiently reduced. Can.

As described above, the semiconductor device according to any of the above embodiments is mounted on the mobile device described in this embodiment. Therefore, a portable device can be realized which can write and read information at high speed, can hold data for a long time, and can reduce power consumption.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

In this embodiment, defects generated when forming a silicon oxynitride film by a CVD method and the film density of the silicon oxynitride film will be described.

First, defects generated when a silicon oxynitride film is formed will be described. Specifically, description will be made using ESR measurement results of a sample in which a silicon oxynitride film is formed over a quartz substrate.

First, the prepared sample will be described. The manufactured sample is a sample having a structure in which a silicon oxynitride film having a thickness of 200 nm is formed on a quartz substrate.

A quartz substrate is placed in the processing chamber of a plasma CVD apparatus, silane with a flow rate of 100 sccm and dinitrogen monoxide at a flow rate of 3000 sccm are supplied as source gases into the processing chamber, the pressure in the processing chamber is controlled to 40 Pa, and a 27.12 MHz high frequency Power was supplied from a power supply to form a silicon oxynitride film. The substrate temperature was 350.degree. In addition, the plasma CVD apparatus has 600
It is a parallel plate type plasma CVD apparatus of 0 cm ² . Power supply (power density) is 3
00 W (0.05 W / cm ² ), 1000 W (0.17 W / cm ² ), 1500 W (0.
Three conditions of 26 W / cm ² ) are used, and these are set as comparative sample 1, sample 1 and sample 2, respectively.

Then, ESR measurement was performed on Sample 1 and Sample 2 and Comparative Sample 1. The ESR measurement was performed under the following conditions. The measurement temperature is room temperature (25 ° C.), the high frequency power (microwave power) of 9.2 GHz is 20 mW, and the direction of the magnetic field is Sample 1, Sample 2 and Comparative Sample 1 prepared.
The lower limit of detection of the spin density of the signal appearing at g = 2.001, which is derived from the dangling bond of silicon contained in the silicon oxynitride film, is parallel to the surface of the silicon oxynitride film of
It was × ¹⁰ 15 spins / cm ^2.

The results of ESR measurement are shown in FIG. FIG. 17A shows the first derivative curves of the silicon oxynitride film in Sample 1 and Sample 2 and Comparative Sample 1. From FIG. 17A, the g value is 2.0
At 01, it can be seen that the signal intensity of sample 1 and sample 2 is smaller than that of comparative sample 1.

FIG. 17B is a graph showing the relationship between the power supplied when forming a silicon oxynitride film and the spin density of the signal appearing at g = 2.001 of the silicon oxynitride film. It can be said that the smaller the spin density, the smaller the number of defects that are dangling bonds of silicon contained in the silicon oxynitride film. When the power supplied was 1000 W, the spin density of the signal appearing at g = 2.001 in sample 1 was 1.3 × 10 ¹⁵ spins / cm ³ . In addition, when the power supplied was 1500 W, the spin density of the signal appearing at g = 2.001 in sample 2 was below the lower limit of detection. The spin density of the signal appearing at g = 2.001 in comparative sample 1 is 1.
It was 7 × 10 ¹⁶ spins / cm ³ .

From FIG. 17, it can be confirmed that the spin density tends to decrease as the power supplied when forming the silicon oxynitride film is increased.

Next, the film density of the silicon oxynitride film will be described. Specifically, XRR (X-ray reflectance method) measurement results of the sample 1 and the sample 2 and the comparative sample 1 will be described.

The measurement results of the film density of the sample 1 and the sample 2 and the comparative sample 1 are shown in FIG. FIG. 18 is a view showing the relationship between the power supplied when forming a silicon oxynitride film and the film density of the silicon oxynitride film.

When the power supplied was 1000 W, the film density in sample 1 was 2.33 g / cm ³ . When the power supplied was 1500 W, the film density in sample 2 was 2.31 g / cm ³ . On the other hand, when the power supplied is 300 W, the film density in comparative sample 1 is 2.29 g / c
It was m ^3.

From FIG. 18, it can be confirmed that the film density tends to increase when the power supplied when forming the silicon oxynitride film is 1000 W or more.

Here, the hydrogen concentration and the nitrogen concentration of the silicon oxynitride film of Sample 1 are shown in Table 1.

From the above, it can be seen that the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is
Maintain the temperature at 0 ° C. to 400 ° C., more preferably 320 ° C. to 380 ° C., introduce the source gas into the processing chamber, and set the pressure in the processing chamber to 30 Pa to 250 Pa, more preferably 40 Pa to 200 Pa, 0.17 W / cm ² for the electrodes provided on
Above 0.5 W / cm ² or less, more preferably 0.26 W / cm ² or more 0.35 W / cm
^The film density is high by forming a silicon oxide film or a silicon oxynitride film under conditions of supplying high-frequency power of ² or less, and typically, the film density is 2.26 g / cm ³ or more and 2.63.
g / cm ³ or less, with few defects that are dangling bonds of silicon, typically in a signal measured by ESR, the spin density of the signal appearing at a g value of 2.001 is 2 × 10 ¹⁵ spins / It can be seen that a silicon oxynitride film which is cm ³ or less can be formed. In addition, in the transistor including an oxide semiconductor film, the silicon oxynitride film is provided as an insulating film in contact with the oxide semiconductor film, whereby the transistor having excellent electrical characteristics can be manufactured.

This example describes the results of the optical gate BT test of the semiconductor device which is one embodiment of the present invention. Specifically, the variation of the threshold voltage of the transistor which is one embodiment of the present invention will be described.

First, a manufacturing process of a transistor is described. This embodiment will be described with reference to FIG.

First, heat treatment was performed on the substrate 11 using a glass substrate as the substrate 11. The heat treatment was performed at a temperature of 480 ° C. in an atmosphere containing nitrogen for one hour. Next, the base insulating film 13 was formed on the substrate 11.

A 100 nm-thick silicon nitride film and a 150 nm-thick silicon oxynitride film were stacked as the base insulating film 13.

Next, the gate electrode 15 was formed on the base insulating film 13.

A tungsten film with a thickness of 100 nm was formed by a sputtering method, a mask was formed on the tungsten film by a photolithography step, and part of the tungsten film was etched using the mask to form a gate electrode 15.

Next, a gate insulating film 17 in which a 50 nm-thick silicon nitride film and a 200 nm-thick silicon oxide film are stacked is formed on the gate electrode 15.

The silicon nitride film was formed by supplying 50 sccm of silane and 5000 sccm of nitrogen to the processing chamber of the plasma CVD apparatus, controlling the pressure in the processing chamber to 60 Pa, and supplying 1500 W of power using a 27.12 MHz high frequency power supply. Silicon oxynitride film, silane 100sc
It was formed by supplying cm, 3000 sccm of dinitrogen monoxide to the processing chamber of the plasma CVD apparatus, controlling the pressure in the processing chamber to 40 Pa, and supplying power of 1500 W using a 27.12 MHz high frequency power supply. In addition, the silicon nitride film and the silicon oxynitride film have a substrate temperature of 3
It was formed as 50 ° C. Note that as the film formation condition of the silicon oxynitride film, the film formation condition of the gate insulating film 17 of the transistor 10 described in Embodiment 1 was used.

Next, an oxide semiconductor film 18 overlapping with the gate electrode 15 was formed with the gate insulating film 17 interposed therebetween.

As the oxide semiconductor film 18, a 35 nm-thick IGZO film which is a CAAC-OS film was formed by a sputtering method. The IGZO film has a sputtering target of In: Ga: Zn
A target of 1: 1: 1 (atomic number ratio), 50 sccm Ar and 50 sccm oxygen are supplied as a sputtering gas into the processing chamber of the sputtering apparatus, the pressure in the processing chamber is controlled to 0.6 Pa, and 5 kW DC It was formed by supplying power. The substrate temperature at the time of forming the IGZO film was 170 ° C.

The structure obtained through the steps up to here can be referred to FIG.

Next, a mask was formed over the IGZO film by a photolithography step, and part of the IGZO film was etched using the mask. After that, the etched IGZO film was subjected to heat treatment to form an oxide semiconductor film 19.

Next, heat treatment was performed. Here, the first heat treatment performed in a nitrogen atmosphere and the second heat treatment performed in an oxygen atmosphere after the first heat treatment were performed. The temperatures of the first heat treatment and the second heat treatment were both 450 ° C., and the treatment time was 1 hour.

The structure obtained through the steps up to here can be referred to FIG.

Next, a pair of electrodes 21 in contact with the oxide semiconductor film 19 was formed.

A conductive film is formed over the gate insulating film 17 and the oxide semiconductor film 19, a mask is formed over the conductive film by a photolithography step, and a part of the conductive film is etched using the mask.
A pair of electrodes 21 was formed. The conductive film has a thickness of 40 nm on a 100 nm thick titanium film.
A 0 nm aluminum film was formed, and a 100 nm thick titanium film was formed on the aluminum film.

The structure obtained in the steps up to here can be referred to FIG.

Next, heat treatment was performed. The heat treatment is performed at a temperature of 300 ° C. in an atmosphere containing nitrogen.
I went for hours.

Next, the insulating film 23 was formed over the gate insulating film 17, the oxide semiconductor film 19, and the pair of electrodes 21.

The structure obtained through the steps up to here can be referred to FIG.

After the insulating film 23 was formed, heat treatment was performed on the structure obtained in the steps up to here. The heat treatment was performed using a first heat treatment performed in a nitrogen atmosphere and a second heat treatment performed in an oxygen atmosphere after the first heat treatment. The temperature of the first heat treatment and the temperature of the second heat treatment are both 300 ° C.,
The processing time was 1 hour for both.

Next, an acrylic layer having a thickness of 1.5 μm was formed on the insulating film 23. Next, part of the acrylic layer was etched to expose the pair of electrodes, and then a pixel electrode connected to the pair of electrodes was formed. Here, ITO with a thickness of 100 nm was formed as a pixel electrode by a sputtering method.

Through the above steps, a transistor which is an embodiment of the present invention is manufactured. Note that a transistor manufactured by the above steps is referred to as a sample X.

Here, a manufacturing process of a transistor to be a comparative example is described. A transistor serving as a comparative example (hereinafter, referred to as sample Y) is a transistor in which the gate insulating film 17 of the sample X is formed as follows, and all other steps are the same. The gate insulating film 17 of the sample Y is
Similar to the sample X, a stacked structure of a silicon nitride film and a silicon oxynitride film was formed, and a silicon oxynitride film was formed under the following conditions. The film formation conditions of the silicon nitride film are the same as those of the sample X.

The silicon oxynitride film of the sample Y supplies 100 sccm of silane and 3000 sccm of nitrogen to the processing chamber of the plasma CVD apparatus and controls the pressure in the processing chamber to 40 Pa, 27.12 MHz
Power supply of 300 W using the high frequency power source of. The silicon nitride film and the silicon oxynitride film were formed at a substrate temperature of 350.degree. Note that as a film formation condition of the silicon oxynitride film, a film formation condition different from that of the gate insulating film 17 of the transistor 10 described in Embodiment 1 was used.

Next, optical gate BT tests of sample X and sample Y were performed. Here, as a light gate BT test, a white LED emitting white light of 3000 lx is used with a substrate temperature of 80 ° C., an electric field strength of 1.2 MV / cm applied to the gate insulating film, and an application time of 2000 seconds. An optical negative gate BT test was conducted by applying a negative voltage to the

The light negative gate BT test method and the method of measuring the Vg-Id characteristics of the transistor will be described. In order to measure the initial characteristics of the transistor targeted for the light negative gate BT test,
The substrate temperature is 25 ° C., the voltage between the source electrode and the drain electrode (hereinafter referred to as drain voltage) is 1 V and 10 V, and the voltage between the source electrode and the gate electrode (hereinafter referred to as gate voltage).
The Vg-Id characteristics of the current (hereinafter referred to as drain current) generated between the source electrode and the drain electrode when changing V.) from -30 V to +30 V was measured.

Next, after the substrate temperature was raised to 80 ° C., the potential of the source electrode and the drain electrode of the transistor was set to 0 V. Subsequently, the electric field strength applied to the gate insulating film is 1.2 MV / cm.
A voltage was applied to the gate electrode so that Here, since the thickness of the gate insulating film of the transistor is 250 nm, -30 V is applied to the gate electrode and held for 2000 seconds.

Next, with the voltage applied to the gate electrode, the source electrode and the drain electrode, the substrate temperature is 2
It was lowered to 5 ° C. After the substrate temperature reached 25 ° C., the application of voltage to the gate electrode, the source electrode and the drain electrode was terminated.

Next, Vg-Id characteristics were measured under the same conditions as the measurement of the initial characteristics, and Vg-Id characteristics after the light negative gate BT test were obtained.

Difference between threshold voltage of initial characteristics and threshold voltage after light negative gate BT test (ΔVth)
Is shown in FIG. The vertical axis represents ΔVth. As compared with the sample X, it can be seen that the sample Y has a large amount of fluctuation of the threshold voltage. From this, it can be seen that, by using a gate insulating film having a high film density and a small amount of dangling bonds of silicon as the gate insulating film of the transistor, the variation of the threshold voltage in the light negative gate BT test is small. .

Claims (3)

Insulation film,
An oxide semiconductor film on the insulating film;
A pair of electrodes having a region in contact with the oxide semiconductor film,
A gate insulating film on the oxide semiconductor film;
A nitride semiconductor film on the gate insulating film and a gate electrode on the nitride semiconductor film;
An insulating film in contact with the upper surface of the gate insulating film and the side surface of the gate electrode;
And a pair of electrodes in contact with the side surface of the insulating film, the side surface of the gate insulating film, and the top surface of the oxide semiconductor film,
The gate insulating film has a spin density of 2 × 10 ¹⁵ spins / cm ³ or less, in a signal measured by electron spin resonance, in which the g value is 2.001 ,
The oxide semiconductor film is a semi-conductor device that have a region overlapping with the gate electrode. In claim 1,
The insulating layer, Ru silicon oxide or silicon nitride der semiconductors devices. In claim 1 or claim 2,
The gate insulating film, Ru silicon oxide or silicon nitride der semiconductors devices.

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