JP6367083B2 - Test circuit and test method - Google Patents

Description

  The present invention relates to a test circuit and a test method for testing a memory mounted on a semiconductor device.

  When a semiconductor device mounted on a printed circuit board does not operate as specified and a failure of the semiconductor device is suspected, but the failure location cannot be directly visually recognized from the outside, in order to identify the failure location, the following (1 ) And (2).

(1) When debugging with a semiconductor device mounted on a printed circuit board In this case, the semiconductor device is normally operated, and the problem location is identified from the symptom of the problem suspected of being affected by the failure. .

(2) When debugging by peeling the semiconductor device from the printed circuit board In this case, the semiconductor device is peeled from the printed circuit board and a product test of the semiconductor device is performed using a test circuit built in the semiconductor device. This product test has been performed once before mounting on the printed circuit board, and at that time, all test items have been passed.

  Here, when a test item that does not pass occurs, it is assumed that the part related to the test item is broken, and the cause of failure is identified by investigating the cause in more detail, but there are problems as described below. is there.

(1) When debugging with the semiconductor device mounted on the printed circuit board In this state, the product test of the semiconductor device alone cannot be performed. As estimated, it is difficult to specify what is broken in the semiconductor device by this alone.
In addition, even if a test circuit that facilitates debugging is built in the semiconductor device in advance and the test circuit is controlled from an external pin, the number of external pins that can be used for debugging is limited when the semiconductor device is mounted on a printed circuit board. Many external pins cannot be secured.

(2) When debugging by peeling the semiconductor device from the printed circuit board When the semiconductor device is peeled from the printed circuit board, there is a risk that the joint component may be broken, such as breaking an external pin connecting the semiconductor device and the printed circuit board. If the joint part is broken, it becomes impossible to perform a product test in which a test pattern is input from an external pin, and it becomes difficult to specify a failure location.

  Here, as prior art documents related to the present invention, Patent Document 1 relating to a register device, Patent Document 2 relating to a FIFO register circuit used for data communication, and a shift register circuit configured with a flip-flop circuit for generating addresses. There are Patent Document 3 regarding a large-scale FIFO circuit to be performed, Patent Document 4 regarding an interface circuit for performing data transfer processing, Patent Document 5 regarding a semiconductor device having a multistage buffer composed of a plurality of flip-flops, and the like.

Japanese Patent Laid-Open No. 4-291164 JP-A-11-120757 JP 11-328947 A JP 2006-323976 A JP 2007-149201 A

  An object of the present invention is to solve the above-mentioned problems of the prior art, and to test by controlling a memory inside a semiconductor device from a small number of external pins while the semiconductor device is still mounted on a printed circuit board. It is to provide a circuit and a test method.

In order to achieve the above object, the present invention is a test circuit for testing a memory mounted on a semiconductor device,
When the output enable signal becomes inactive, the input mode is entered. The serial data input signal and serial clock input signal are input from the first and second input / output pins, respectively, and output when the output enable signal becomes active. An input / output unit configured to output a serial data output signal and a serial clock output signal to the first and second input / output pins, respectively,
Synchronously with the serial clock input signal, the serial data input signal of a certain number of bits sequentially input is converted into a parallel data input signal and set as a test setting data signal;
A test clock generator for generating a test clock signal having a constant frequency;
A memory data output unit for converting a parallel memory data output signal read in synchronization with the test clock signal from a memory address of a memory to be tested designated by the test setting data signal into a serial memory data output signal;
In synchronization with the test clock signal, the serial memory data output signal is sequentially output as the serial data output signal, and the test clock signal is sequentially output as the serial clock output signal. Provided is a test circuit comprising: an input / output control unit that outputs the output enable signal that becomes active when the test setting data signal is set in an active state in synchronization with the test clock signal To do.

Furthermore, a count value is initialized when the clear signal is in an active state, and when the clear signal is in an inactive state, the first counter that counts in synchronization with the test clock signal and outputs the count value;
When the debug mode signal represents the normal operation mode, and when the debug mode signal represents the test mode and the count value becomes a constant value, the debug mode signal represents the test mode. And a clear signal generation circuit that generates the clear signal that is inactive when the count value is not the constant value.

  The memory test setting unit is initialized when the clear signal is in an active state, and when the clear signal is in an inactive state, the memory test setting unit is sequentially input in a fixed number of bits in synchronization with the serial clock input signal. Serial data input signal is sequentially shifted to be converted into the parallel data input signal and held, and as the test setting data signal, a test address signal for designating a memory address of the memory to be tested, and an inactive state reset A shift register for setting a signal is preferably provided.

The test clock generator is
A ring oscillator that generates an oscillation clock of a constant frequency when the debug mode signal represents the test mode;
It is preferable to include a second counter that is initialized when the reset signal is in an active state and counts in synchronization with the oscillation clock to generate the test clock signal when the reset signal is in an inactive state.

  Preferably, the memory output control unit further includes a decoder that outputs a memory data bit selection signal having a fixed number of bits that sequentially activates only one bit corresponding to the count value.

The memory data output unit inputs an internal signal in the normal operation mode to the memory to be tested when the debug mode signal represents the normal operation mode, and the debug mode signal indicates the test mode. An input switching circuit for inputting a test signal including the test address signal and the test clock signal to the test target memory so that the parallel memory data output signal is read from the test target memory.
It is preferable that an output switching circuit that sequentially outputs the bits of the parallel memory data output signal corresponding to the bits of the memory data bit selection signal in the active state as the serial memory data output signal is provided.

The input / output control unit
The reset signal is initialized when it is in an active state, and when the reset signal is in an inactive state, the serial memory data output signal is held in synchronization with the test clock signal and is output as the serial data output signal. A holding circuit;
When the reset signal becomes active, it is initialized and becomes inactive, and when the reset signal becomes inactive, the serial clock output control signal that becomes active in synchronization with the test clock signal is held, and the serial signal A second holding circuit that outputs the test clock signal as the serial clock output signal when a clock output control signal is in an active state;
When the reset signal becomes active, it is initialized and becomes inactive. When the reset signal becomes inactive, the output enable signal that becomes active in synchronization with the test clock signal is held and output. 3 holding circuit.

The test circuit includes a plurality of the memory data output units,
The shift register of the memory test setting unit is for setting a memory specifying signal for specifying the test target memory from the plurality of memories as the test setting data signal,
The input / output control unit further includes a serial memory output from the test target memory designated by the memory designation signal from among the serial memory data output signals outputted from each of the plurality of memory data output units. It has a multiplexer that outputs the data output signal,
The first holding circuit of the input / output controller holds the serial memory data output signal output from the multiplexer in synchronization with the test clock signal when the reset signal becomes inactive, and the serial data output signal It is preferable that the output is as follows.

  The first and second input / output pins are preferably assigned to input / output pins that do not affect the operation of the semiconductor device in the normal operation mode.

Further, the present invention is a test method for testing a memory mounted on a semiconductor device,
The input / output control unit sets the output enable signal to an inactive state and sets the input / output unit to the input mode;
The input / output unit inputs a serial data input signal and a serial clock input signal from the first and second input / output pins, respectively;
A memory test setting unit, in synchronization with the serial clock input signal, sequentially converting the serial data input signal having a fixed number of bits into a parallel data input signal, and setting as a test setting data signal;
A step of generating a test clock signal having a constant frequency by a test clock generator;
When the input / output control unit is set to the test setting data signal, in synchronization with the test clock signal, the output enable signal is activated to place the input / output unit in an output mode;
The memory data output unit converts the parallel memory data output signal read in synchronization with the test clock signal from the memory address of the test target memory designated by the test setting data signal into a serial memory data output signal When,
An input / output controller that sequentially outputs the serial memory data output signal as a serial data output signal in synchronization with the test clock signal, and sequentially outputs the test clock signal as a serial clock output signal;
The input / output unit includes a step of outputting the serial data output signal and the serial clock output signal to the first and second input / output pins, respectively.

  In the present invention, by securing two external pins, memory data read from the memory mounted on the semiconductor device can be sequentially output from the external pins while the semiconductor device is still mounted on the printed circuit board. Can do. Therefore, according to the present invention, whether or not the memory data is stacked at L (low level) or H (high level) while avoiding the risk of destruction of the joint portion that occurs when the semiconductor device is peeled from the printed circuit board. The state of can be observed externally.

It is a block diagram of one embodiment showing composition of a test circuit of the present invention. FIG. 2 is a circuit diagram illustrating an example of a configuration of an input / output unit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a memory test setting unit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a test clock generation unit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a memory output control unit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a memory data output unit illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of an input / output control unit illustrated in FIG. 1. 2 is a flowchart illustrating an example of a schematic operation of the test circuit illustrated in FIG. 1. 5 is an example timing chart illustrating an operation of a test circuit when a debug mode signal changes from a state representing a normal operation mode to a state representing a test mode. It is a conceptual diagram of an example showing a test setting data signal set in the shift register of the memory test setting unit. It is a conceptual diagram of an example showing a mode that a test setting data signal is set to a shift register. It is an example timing chart showing operation | movement in case a test setting data signal is set to a shift register. It is a timing chart of an example showing operation when a test clock signal is generated. 6 is an example timing chart illustrating an operation when a memory data bit selection signal is generated. 6 is a timing chart illustrating an example of an operation when a parallel memory data output signal is read from a memory. 6 is a timing chart illustrating an example of an operation when a parallel memory data output signal is converted into a serial memory data output signal. 4 is an example timing chart showing an operation when a serial memory data output signal designated by a memory designation signal is output from a plurality of serial memory data output signals. It is a timing chart of an example showing operation | movement in case an output enable signal will be in an active state. 6 is a timing chart illustrating an example of an operation when a serial data output signal and a serial clock output signal are output. 6 is a timing chart illustrating an example of an operation when the test circuit is in an initial state and is in a standby state waiting for the next test setting data signal to be set.

  Hereinafter, a test circuit and a test method of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a block diagram of an embodiment showing a configuration of a test circuit of the present invention. The test circuit 10 shown in the figure is mounted on a semiconductor device mounted on a printed circuit board, and tests the memory mounted on the semiconductor device while the semiconductor device is mounted on the printed circuit board. An input / output unit 12, a memory test setting unit 14, a test clock generation unit 16, a memory output control unit 18, (p + 1) memory data output units 20 [p: 0], and an input / output control unit 22 It is constituted by.

  When DEBUG_MODE is H, the input / output unit 12 enters the input mode when the output enable signal ENL becomes inactive, and input / output pins (first and second input / output pins) for the serial data SDA and the serial clock SCL. The serial data input signal SDI and the serial clock input signal CLK are input, and when the output enable signal ENL becomes active, the output mode is entered. The serial data output signal SDO and the serial clock output signal SCLKO are converted into the serial data SDA, respectively. And output to the input / output pins of the serial clock SCL.

  As shown in FIG. 2, the input / output unit 12 includes a first input / output circuit 24A corresponding to the input / output pin of the serial data SDA and a second input / output circuit 24B corresponding to the input / output pin of the serial clock SCL. ing.

The first input / output circuit 24A includes an input / output buffer including an input buffer 26A and an output buffer 28A, and two multiplexers 32A and 34A.
The output signals of the multiplexers 32A and 34A are input to the input terminal and the inverted output enable terminal of the output buffer 28A, respectively. The output signal of the output buffer 28A is input to the input / output pin of the serial data SDA.
Serial data SDA is input from the input / output pin of the serial data SDA to the input buffer 26A, and a serial data input signal SDI corresponding to the serial data SDA is output from the input buffer 26A.

Similarly, the second input / output circuit 24B includes an input / output buffer including an input buffer 26B and an output buffer 28B, and two multiplexers 32B and 34B.
The output signals of the multiplexers 32B and 34B are input to the input terminal and the inverted output enable terminal of the output buffer 28B, respectively. The output signal of the output buffer 28B is input to the input / output pin of the serial clock SCL.
A serial clock SCL is input to the input buffer 26B from an input / output pin of the serial clock SCL, and a serial clock input signal CLK corresponding to the serial clock SCL is output from the input buffer 26B.

  The internal signals (not shown) in the corresponding normal operation mode are input to the input terminals 0 of the multiplexers 32A and 34A and the multiplexers 32B and 34B, respectively, and debugging for switching between the normal operation mode and the test mode is performed on the selected input terminal. A mode signal DEBUG_MODE is input. The serial data output signal SDO is input to the input terminal 1 of the multiplexer 32A, the serial clock output signal SCLKO is input to the input terminal 1 of the multiplexer 32B, and the output enable signal ENL is input to the input terminal 1 of the multiplexers 34A and 34B. Each is input from the control unit 22.

  The serial data input signal SDI and the serial clock input signal CLK are signals used for setting the test setting data signal. For example, the external operation that does not affect the operation (normal operation) of the semiconductor device in the normal operation mode. Can be assigned to a pin. The external pins that do not affect the operation of the semiconductor device in the normal operation mode include, for example, extra external pins that are not used during normal operation and external pins that do not operate during normal operation (the level does not change) ( For example, immediately after the semiconductor device starts its operation, it is used only for inputting an initial value and is not used after the initial value is input.

  In FIG. 2, input / output pins are used. However, if there is a margin in the number of external pins that do not affect the operation of the semiconductor device in the normal operation mode, input pins (external pins) and output pins ( External pins) can be used in combination.

  The debug mode signal DEBUG_MODE is an internal signal of the semiconductor device, and is used when testing a circuit other than the memory. For example, the debug mode signal DEBUG_MODE is set by an external pin used during normal operation. The

Subsequently, in synchronization with the serial clock input signal CLK, the memory test setting unit 14 converts the serial data input signal SDI having a certain number of bits sequentially input into a parallel data input signal and sets it as a test setting data signal. It is.
As shown in FIG. 3, the memory test setting unit 14 includes an OR circuit 36 and a shift register 38.

  The OR circuit 36 receives the serial clock input signal CLK from the input / output unit 12 and the reset signal RSTN from the flip-flop (FF) 44 at the final stage of the shift register 38.

  The shift register 38 is initialized when the clear signal CLR input from the memory output control unit 18 becomes active, and is sequentially input in synchronization with the serial clock input signal CLK when the clear signal CLR becomes inactive. A serial data input signal SDI having a certain number of bits is sequentially shifted to be converted into a parallel data input signal and held, and a test address signal ADR1 [i: 0] for designating a memory address of a test target memory as a test setting data signal A memory designation signal ADR2 [j: 0] for designating a memory to be tested from a plurality of memories and a reset signal RSTN in an inactive state are set.

  The shift register 38 holds (i + 1) stages of FFs 40 [i: 0] holding the test address signal ADR1 [i: 0] and (j + 1) stages of FFs 42 [j] holding the memory designation signal ADR2 [j: 0]. : 0] and the last stage FF 44 holding the reset signal RSTN are connected in series.

  The output signal CLKM of the OR circuit 36 is input to the clock input terminals of the FF 40 [i: 0], FF 42 [j: 0], and FF 44, and the clear signal CLR from the memory output control unit 18 is input to the inverted reset input terminal R. Have been entered.

  The serial data input signal SDI is input from the input / output unit 12 to the data input terminal D of the FF 40 [0] of the FF 40 [i: 0]. The test address signal ADR1 [i-1: 0] is input to the data input terminal D of the FF 40 [i: 1] from the data output terminal Q of the preceding FF 40 [i-1: 0]. Test address signals ADR1 [i: 0] are output from the data output terminals Q of the FFs 40 [i: 0], respectively.

  Among the FFs 42 [j: 0], the test address signal ADR1 [i] is input to the data input terminal D of the FF 42 [0] from the data output terminal Q of the preceding FF 40 [i]. The memory designation signal ADR2 [j-1: 0] is input from the data output terminal Q of the preceding FF42 [j-1: 0] to the data input terminal D of the FF42 [j: 1]. From the data output terminals Q of the FFs 42 [j: 0], memory designation signals ADR2 [j: 0] are output, respectively.

  The memory designation signal ADR2 [j] is input from the data output terminal Q of the previous stage FF42 [j] to the data input terminal D of the last stage FF44. A reset signal RSTN is output from the data output terminal Q of the FF 44.

Subsequently, the test clock generator 16 generates a test clock signal CLKOUT having a constant frequency.
As shown in FIG. 4, the test clock generator 16 includes a ring oscillator (Ring-OSC) 46 and a counter 48 (second counter).

The ring oscillator 46 generates an oscillation clock having a constant frequency when the debug mode signal DEBUG_MODE indicates the test mode.
A debug mode signal DEBUG_MODE is input to the enable input terminal EN of the ring oscillator 46, and an oscillation clock is output from the oscillation clock output terminal CLK.

The counter 48 is initialized when the reset signal RSTN enters an active state, and generates a test clock signal CLKOUT by counting in synchronization with the oscillation clock when the reset signal RSTN enters an inactive state and is connected in series. The (k + 1) FFs 50 [k: 0] are provided.
A reset signal RSTN is input from the memory test setting unit 14 to the inverting reset terminal of the FF 50 [k: 0]. An oscillation clock is input from the ring oscillator 46 to the clock input terminal of the FF 50 [0]. From the inverted data output terminal QB of FF50 [k-1: 0], the internal clock signal CLK [k-1: 0] is output, respectively, and the clock of its own data input terminal D and FF50 [k: 1]. Input to the input terminal. The internal clock signal CLK [k] is output from the inverted data output terminal QB of the FF 50 [k] and input to its own data input terminal D, and the test clock signal CLKOUT is output from the data output terminal Q. Has been.

Subsequently, the memory output control unit 18 generates a memory data bit selection signal SEL [m: 0] in synchronization with the test clock signal CLKOUT, and further generates a clear signal CLR.
As shown in FIG. 5, the memory output control unit 18 includes a counter 52 (first counter), a clear signal generation circuit 54, and a decoder 56.

  When the clear signal CLR becomes active, the counter 52 initializes the count value CNT [n: 0], and when the clear signal CLR becomes inactive, the counter 52 counts in synchronization with the test clock signal CLKOUT and counts CNT. [N: 0] is output, and (n + 1) FFs 58 [n: 0] connected in series are provided.

  The clear signal CLR is input from the clear signal generation circuit 54 to the inverting reset terminal of the FF 58 [n: 0]. The test clock signal CLKOUT is input from the test clock generator 16 to the inverted clock input terminal of the FF 58 [0]. An inverted signal of the count value CNT [n-1: 0] is output from the inverted data output terminal QB of FF58 [n-1: 0], respectively, and its own data input terminal D and FF58 [n: 1]. Is input to the clock input terminal. From the inverted data output terminal QB of the FF 58 [n], an inverted signal of the count value CNT [n] is output and input to its own data input terminal D. The count value CNT [n: 0] is output from the data output terminal Q of the FF 58 [n: 0].

  The clear signal generation circuit 54 is active when the debug mode signal DEBUG_MODE indicates the normal operation mode, and when the debug mode signal DEBUG_MODE indicates the test mode and the count value CNT [n: 0] becomes a constant value. When the debug mode signal DEBUG_MODE indicates the test mode and the count value CNT [n: 0] is not a constant value, the clear signal CLR that becomes inactive is generated, and (n−1) Each AND circuit 60 [n−1: 1], a NAND circuit 62, a plurality of buffer circuits 64 connected in series, and an AND circuit 66 in the output stage are provided.

Of the AND circuit 60 [n−1: 1], the count value CNT [1: 0] is input to the AND circuit 60 [1] from the data output terminal Q of the FF 58 [1: 0] of the counter 52. . The AND circuit 60 [n-1: 2] has an output signal from the AND circuit 60 [n-2: 1] and a count value CNT [n from the data output terminal Q of the FF 58 [n-1: 2]. −1: 2] is input.
The NAND circuit 62 receives the output signal of the AND circuit 60 [n−1] and the count value CNT [n] from the data output terminal Q of the FF 58 [n].
The output signal of the NAND circuit 62 is input to the buffer circuit 64 at the first stage of the plurality of buffer circuits 64.
The output stage AND circuit 66 receives the debug mode signal DEBUG_MODE and the output signal of the last stage buffer circuit 64 of the plurality of buffer circuits 64, and the AND circuit 66 outputs a clear signal CLR.

The decoder 56 selects a memory data bit selection signal SEL [m: 0] having a certain number of bits in which only one bit corresponding to the count value CNT [n: 0] is sequentially activated (where m = 2 ^{(n + 1)} − 1) is output.
The count value input terminal CNT [n: 0] of the decoder 56 receives the count value CNT [n: 0] from the counter 52, and the memory data bit selection signal output terminal SEL [m: 0] receives the memory data bit. The selection signal SEL [m: 0] is output.

Subsequently, the memory data output unit 20 [p: 0] reads the parallel memory data output signal Q [] read in synchronization with the test clock signal CLKOUT from the memory address of the test target memory specified by the test setting data signal. x: 0] is converted into a serial memory data output signal QOUT [p: 0].
For example, the memory data output unit 20 [p] includes an input switching circuit 68 and an output switching circuit 70 as shown in FIG.

  When the debug mode signal DEBUG_MODE indicates the normal operation mode, the input switching circuit 68 inputs an internal signal in the normal operation mode to the test target memory 76, and when the debug mode signal DEBUG_MODE indicates the test mode, The test signal including the test address signal ADR1 [i: 0] and the test clock signal CLKOUT is input to the test target memory 76 so that the parallel memory data output signal Q [x: 0] is read from the memory 76. There are four multiplexers 72A, 72B, 72C, 72D.

The corresponding internal signal (not shown) in the normal operation mode is input to the input terminals 0 of the multiplexers 72A, 72B, 72C, and 72D, and the debug mode signal DEBUG_MODE is input to the selection input terminal. A test signal for testing the memory 76 is input to the input terminals 1 of the multiplexers 72A, 72B, 72C, and 72D. In other words, the input address 1 of the multiplexer 72A is supplied from the memory test setting unit 14 to the test address signal ADR1 [[number of bits corresponding to the number of bits of the address signal of the memory 76] of the test address signal ADR1 [i: 0]. y: 0] is input as the memory address signal A [y: 0], and the test clock signal CLKOUT is input to the input terminal 1 of the multiplexer 72D. Further, in the test mode, the input terminal 1 of the multiplexer 72B is connected to the power supply, and the input terminal 1 of the multiplexer 72C is connected to the ground so that the parallel memory data output signal Q [x: 0] is read from the test target memory 76. It is connected.
The output signals of the multiplexers 72A, 72B, 72C, 72D are respectively sent to the address input terminal A [y: 0] (y ≦ i), the write enable signal input terminal WEN, the chip select input terminal CSN, and the clock input terminal of the memory 76. Have been entered.
A corresponding internal signal (not shown) in the normal operation mode is input to the data input terminal D [x: 0] of the memory 76.

  Here, the type of the memory 76 is not limited at all. For example, various types of RAM (random access memory) such as SRAM (static RAM) and DRAM (dynamic RAM), PROM (programmable ROM), EPROM (erasable programmable ROM). Various ROMs (read-only memories) such as flash memories may be used.

  The output switching circuit 70 converts the bit of the parallel memory data output signal Q [x: 0] corresponding to the bit of the memory data bit selection signal SEL [m: 0] in the active state to the serial memory data output signal QOUT [p]. And (x + 1) multiplexers 74 [x: 0] corresponding to the number of bits of the parallel memory data output signal Q [x: 0] output from the memory 76 (where m ≧ x ).

  Among the multiplexers 74 [x: 0], the input terminal 0 of the multiplexer 74 [x] is connected to the ground, and the input terminal 0 of the multiplexer 74 [x-1: 0] is connected to the multiplexer 74 [x: 1]. Output signal is input. The parallel memory data output signal Q [x: 0] is input from the data output terminal Q [x: 0] of the memory 76 to the input terminal 1 of the multiplexer 74 [x: 0], respectively. From the memory output control unit 18, the memory data bit selection signal SEL [] having the number of bits corresponding to the number of bits of the parallel memory data output signal Q [x: 0] in the memory data bit selection signal SEL [m: 0]. x: 0] is input. The multiplexer 74 [0] outputs a serial memory data output signal QOUT [p].

  The other memory data output unit 20 [p-1: 0] has the same configuration, and the memory data output unit 20 [p: 0] outputs a serial memory data output signal QOUT [p: 0]. ing.

  Subsequently, the input / output control unit 22 sequentially outputs the serial memory data output signal QOUT as the serial data output signal SDO in synchronization with the test clock signal CLKOUT, and sequentially outputs the test clock signal CLKOUT as the serial clock output signal SCLKO. When the test setting data signal is set, the output enable signal ENL that becomes active in synchronization with the test clock signal CLKOUT is output when the test setting data signal is set.

  As shown in FIG. 7, the input / output control unit 22 includes a multiplexer 78, an FF 80A (first holding circuit), an FF 80B (third holding circuit), an FF 80C, and an OR circuit 82 (second holding circuit). ing.

The multiplexer 78 is designated by the memory designation signal ADR2 [j: 0] from the serial memory data output signal QOUT [p: 0] output from each of the plurality of memory data output units 20 [p: 0]. The serial memory data output signal QOUT output from the memory 76 to be tested is output.
The serial memory data output signal QOUT [p: 0] is input from the memory data output unit 20 [p: 0] to the input terminal of the multiplexer 78, and the memory designation signal ADR2 from the memory test setting unit 14 is input to the selection input terminal. [J: 0] is input. From the multiplexer 78, the memory data output designated by the memory designation signal ADR2 [j: 0] from the serial memory data output signal QOUT [p: 0] inputted from the memory data output unit 20 [p: 0]. The serial memory data output signal QOUT of the unit 20 is output.

  The FF 80A is initialized when the reset signal RSTN enters an active state, and holds the serial memory data output signal QOUT output from the multiplexer 78 in synchronization with the test clock signal CLKOUT when the reset signal RSTN enters an inactive state. This is output as the serial data output signal SDO.

  The FF 80B is initialized and deactivated when the reset signal RSTN becomes active, and holds the output enable signal ENL that becomes active in synchronization with the test clock signal CLKOUT when the reset signal RSTN becomes inactive. Output.

  The FF 80C is initialized and deactivated when the reset signal RSTN becomes active, and holds the serial clock output control signal SCLKO_pre that becomes active in synchronization with the test clock signal when the reset signal RSTN becomes inactive. Is. The OR circuit 82 outputs the test clock signal CLKOUT as the serial clock output signal SCLKO when the serial clock output control signal SCLKO_pre becomes active.

  The test clock signal CLKOUT is input from the test clock generator 16 to the inverted clock input terminal of the FF 80A and the clock input terminals of the FFs 80B and 80C, and the reset signal RSTN is input from the memory test setting unit 14 to the inverted set terminal S. ing. The output signal of the multiplexer 78 is input to the data input terminal D of the FF 80A, and the data input terminals of the FFs 80B and 80C are connected to the ground. The OR circuit 82 receives the serial clock output control signal SCLKO_pre from the data output terminal Q of the FF 80 </ b> C, and the test clock signal CLKOUT from the test clock generator 16. A serial data output signal SDO, an output enable signal ENL, and a serial clock output signal SCLKO are output from the FFs 80A and 80B and the OR circuit 82, respectively.

  Next, the schematic operation of the test circuit 10 will be described with reference to the flowchart shown in FIG.

  If the semiconductor device mounted on the printed circuit board does not operate as specified, the debug mode signal DEBUG_MODE is set to L to set the normal operation mode, and the failure state is reproduced in the normal operation mode (step S1).

  If the occurrence of a failure is reproduced in the normal operation mode, the debug mode signal DEBUG_MODE is set to H to set the test mode (step S2).

  When the debug mode signal DEBUG_MODE becomes H representing the test mode, the clear signal CLR of the memory output control unit 18 becomes H (clear release) in an inactive state (step S3).

  When the clear signal CLR becomes H, the clearing of the FF 58 [n: 0] of the memory output control unit 18 and the FFs 40 [i: 0], 42 [j: 0], 44 of the memory test setting unit 14 is released. The However, even if the clear signal CLR of the memory test setting unit 14 is canceled, the reset signal RSTN is maintained at L, so that the output enable signal ENL of the input / output control unit 22 is initialized and is inactive in the H state. The input / output unit 12 is in the input mode. That is, the input / output pins of the serial data SDA and the serial clock SCL are fixed to the input mode (step S4).

  As a result, the test circuit 10 enters a state of waiting for the test setting data signal including the test address signal ADR1 [i: 0], the memory designation signal ADR2 [j: 0], and the reset signal RSTN to be set (step). S5).

  Subsequently, it is determined whether or not to end the test (step S6).

  When the test is continued (No in step S6), it is subsequently determined whether or not a test setting data signal is input (step S7).

  If no test setting data signal is input (No in step S7), the process returns to step S5 and waits for the test setting data signal to be input.

  When the test setting data signal is input (Yes in step S7), serial data input signal SDI and serial clock input signal CLK are sequentially input from the input / output pins of serial data SDA and serial clock SCL of input / output unit 12, respectively. Then, the test setting data signal including the test address signal ADR1 [i: 0], the memory designation signal ADR2 [j: 0], and the reset signal RSTN of the memory test setting unit 14 is set (written) in the shift register 38 ( Step S8).

  Subsequently, it is determined whether or not the most significant bit of the shift register 38, that is, the reset signal RSTN is set to H (1) (step S9).

  If the reset signal RSTN is not set to H (No in step S9), the process returns to step S8 and waits for the setting of the test setting data signal to end.

  When the reset signal RSTN is set to H (Yes in step S9), the test clock signal CLKOUT of the test clock generator 16 starts operation (step S10).

  The output enable signal ENL of the input / output control unit 22 becomes L in synchronization with the test clock signal CLKOUT, and the input / output unit 12 enters the output mode. That is, the input / output pins of the serial data SDA and the serial clock SCL are fixed to the output mode (step S11).

  Subsequently, the parallel memory data output signal Q [x: 0] is read from the memory address of the memory 76 of the memory data output unit 20 specified by the test address signal ADR1 [i: 0]. Each time only one bit sequentially becomes active H in the order of the memory data bit selection signal SEL [x: 0], the corresponding bit of the parallel memory data output signal Q [x: 0] It is converted into an output signal QOUT [p: 0].

  Subsequently, one serial memory data output signal QOUT of the memory data output unit 20 is designated by the memory designation signal ADR2 [j: 0] from the serial memory data output signal QOUT [p: 0], and the serial data output signal Output as SDO. The serial data output signal SDO is output (read out) from the input / output pin of the serial data SDA from the input / output unit 12 (step S12).

  Also, the test clock signal CLKOUT is output as the serial clock output signal SCLKO of the input / output control unit 22. The serial clock output signal SCLKO is output (read) from the input / output unit 12 to the input / output pin of the serial clock SCL (step S12).

  Subsequently, the count value CNT [n: 0] of the counter 52 of the memory output control unit 18 is counted up (+1) (step S13), and the memory data bits corresponding to the counted up value CNT [n: 0] The bit of the selection signal SEL [x: 0] becomes H in the active state.

  Subsequently, it is determined whether or not the count value CNT [n: 0] has become a constant value, which is all 1 which is the maximum value in the example of FIG. 5 (step S14).

  If the count value CNT [n: 0] is not all 1 (No in step S14), the process returns to step S12, and the output of the serial data output signal SDO and the serial clock output signal SCLKO is continued.

  When the count value CNT [n: 0] is all 1 (Yes in step S14), that is, the output of the serial memory data output signal QOUT corresponding to all the bits of the parallel memory data output signal Q [x: 0]. When the process is finished, the clear signal CLR becomes L in the active state (step S15), and the test circuit 10 enters the initial state.

  Then, it returns to step S2 and repeats said operation | movement. That is, in steps S5 to S7, a new test setting data signal is set in the shift register 38, the test target memory and the memory address are changed, and the test is continued.

  If the test is not continued (Yes in step S6), the test is terminated.

  Next, the detailed operation of the test circuit 10 will be described.

  In the normal operation mode, the debug mode signal DEBUG_MODE is set to L.

  When the debug mode signal DEBUG_MODE is set to L representing the normal operation mode, as shown in FIG. 9, the clear signal output from the AND circuit 66 of the output stage constituting the clear signal generation circuit 54 of the memory output control unit 18 CLR becomes L in the active state. When the clear signal CLR becomes L, the counter 52 is reset (initialized), the count value CNT [n: 0] is 0, and (n−1) AND circuits 60 [n−] constituting the clear signal generation circuit 54. 1: 1] is all L, therefore the output signal of the NAND circuit 62 is H, the output signals of the plurality of buffer circuits 64 are also H, and the memory data bit selection signal SEL [0] output from the decoder 56 is active. The state H and the other memory data bit selection signal SEL [m: 1] are in the inactive state L.

  When the clear signal CLR becomes L, the shift register 38 of the memory test setting unit 14 is reset (initialized), and the test address signal ADR1 [i: 0] and the memory designation signal ADR2 [j: 0] are all L ( All 0), the reset signal RSTN becomes L (0) in the active state. Therefore, the OR circuit 36 can output the serial clock input signal CLK input from the input / output unit 12 as the output signal CLKM.

  Further, when the debug mode signal DEBUG_MODE becomes L, the ring oscillator 46 of the test clock generator 16 stops. Since the reset signal RSTN becomes L, the FFs 50 [k] to [0] constituting the counter 48 are reset (initialized), the internal clock signal CLK [k: 0] is all H, and the test clock signal CLKOUT is L. Become. That is, the test clock signal CLKOUT does not operate.

  When the debug mode signal DEBUG_MODE is set to L, the multiplexers 72A, 72B, 72C, and 72D constituting the input switching circuit 68 of the memory data output unit 20 [p: 0], that is, signals input to the input terminal 0, that is, , Internal signals corresponding to the respective normal operation modes are output and input to the memory 76. Since the memory data bit selection signal SEL [0] is H and the other memory data bit selection signals SEL [m: 1] are L, the multiplexer 74 among the multiplexers 74 [x: 0] constituting the output switching circuit 70. From [x: 1], the signal input to the input terminal 0, that is, L is output, and from the multiplexer 74 [0], the signal input to the input terminal 1, that is, the parallel memory data output signal Q [ 0] is output as the serial memory data output signal QOUT [p: 0].

  Since the memory designation signal ADR2 [j: 0] is all L, the multiplexer 78 of the input / output control unit 22 outputs the serial memory data output signal QOUT [0] of the memory data output unit 20 [0]. The Since the reset signal RSTN becomes L, the FFs 80A, 80B, 80C constituting the input / output control unit 22 are set (initialized), the serial data output signal SDO is H, and the serial clock output control signal SCLKO_pre is inactive H The serial clock output signal SCLKO output from the OR circuit 82 is also H, and the output enable signal ENL is H in the inactive state.

  When the debug mode signal DEBUG_MODE becomes L, the signals input to the input terminal 0 from the multiplexers 32A and 34A and the multiplexers 32B and 34B of the input / output unit 12, that is, the corresponding internal signals in the normal operation mode, respectively. Is output.

  On the other hand, in the test mode, the debug mode signal DEBUG_MODE is set to H.

  Since the other input terminal of the AND circuit 66 of the output stage constituting the clear signal generation circuit 54 of the memory output control unit 18 is H, when the debug mode signal DEBUG_MODE becomes H representing the test mode, as shown in FIG. The clear signal CLR becomes H (clear release) in an inactive state. When the clear signal CLR becomes H, the reset of the counter 52 is released, and the count value CNT [n: 0] is sequentially counted up in synchronization with the falling edge of the test clock signal CLKOUT.

  When the clear signal CLR becomes H, the reset of the shift register 38 of the memory test setting unit 14 is released, and the shift register 38 shifts in synchronization with the rise of the output signal CLKM of the OR circuit 36.

  When the debug mode signal DEBUG_MODE becomes H, the ring oscillator 46 of the test clock generator 16 starts generating an oscillation clock. Note that the reset of the counter 48 of the test clock generation unit 16 is not released until the reset signal RSTN is set to H in the inactive state, so the test clock signal CLKOUT remains in the L state.

  Further, when the debug mode signal DEBUG_MODE becomes H, the multiplexer 72A, 72B, 72C, 72D constituting the input switching circuit 68 of the memory data output unit 20 [p: 0], that is, the signal input to the input terminal 1, that is, The multiplexer 72A receives the memory address signal A [y: 0], the multiplexer 72D receives the test clock signal CLKOUT, the multiplexer 72B receives H as the write enable signal WEN, and the multiplexer 72C receives the chip select signal. L in the selected state is output as CSN and input to the corresponding input terminal of the memory 76. That is, the memory 76 can read the parallel memory data output signal Q [x: 0] from the memory address specified by the memory address signal A [y: 0] in synchronization with the rising edge of the test clock signal CLKOUT. become.

  When the debug mode signal DEBUG_MODE becomes H, the serial data output signal SDO is output from the multiplexer 32A of the input / output unit 12, the serial clock output signal SCLKO is output from the multiplexer 32B, and the output enable signal ENL is output from the multiplexers 34A and 34B. Is done. Since the output enable signal ENL is H, the input / output unit 12 is in the input mode, and the input / output pins of the serial data SDA and the serial clock SCL are fixed in the input mode.

  That is, the test circuit 10 waits for the test setting data signal including the test address signal ADR1 [i: 0], the memory designation signal ADR2 [j: 0], and the reset signal RSTN to be set. That is, the serial data input signal SDI and the serial clock input signal CLK can be input from the input / output pins of the serial data SDA and the serial clock SCL, respectively.

  Subsequently, the test setting data signal including the test address signal ADR1 [i: 0], the memory designation signal ADR2 [j: 0], and the reset signal RSTN is set.

  Since the output enable signal ENL is H, the first and second input / output circuits 24A and 24B of the input / output unit 12 are in the input mode. In this state, serial data SDA and serial clock SCL are sequentially input from the input / output pins of serial data SDA and serial clock SCL in synchronization. From the input buffers 26A and 26B, serial data input signal SDI and serial clock input signal CLK corresponding to serial data SDA and serial clock SCL are sequentially output.

  The shift register 38 of the memory test setting unit 14 sequentially shifts the serial data input signal SDI having a certain number of bits sequentially input in synchronization with the rising of the serial clock input signal CLK, that is, the output signal CLKM of the OR circuit 36. Converted into parallel data input signals and held. Thereby, as shown in FIG. 10, the test address signal ADR1 [i: 0], the memory designation signal ADR2 [j: 0], and the reset signal RSTN are set in the shift register 38 as test setting data signals.

Here, as shown in FIG. 11, a case where a17 to a10 are set as the 8-bit test address signal ADR1 [7: 0] and a27 to a20 are set as the memory designation signal ADR2 [7: 0] is taken as an example. I will explain.
The serial data input signal SDI is sequentially input in the order of the reset signal RSTN, the memory designation signal ADR2 [7: 0] a27 to a20, and the test address signal ADR1 [7: 0] a17 to a10. Further, H (1) is always input to the reset signal RSTN.

  As shown in FIG. 12, first, a signal corresponding to H (1) of the reset signal RSTN is input as serial data SDA, that is, a serial data input signal SDI from the state of shift 0 (initial value) shown in FIG. 11 is held in the FF 40 [0] of the shift register 38 in synchronization with the rising of the serial clock SCL, that is, the serial clock input signal CLK, that is, the output signal CLKM of the OR circuit 36, and the shift 1 state shown in FIG. become.

  Subsequently, when a27 of the memory designation signal ADR2 [7] is input as the serial data input signal SDI from the shift 1 state shown in FIG. 11, the FF 40 is synchronized with the rising of the next serial clock input signal CLK. At the same time as H (1) of the reset signal RSTN held in [0] is shifted to the next stage FF40 [1], a27 of the memory designation signal ADR2 [7] is held in FF40 [0]. The state of shift 2 shown in FIG.

  Thereafter, similarly, as shown in shifts 3 to 16 in FIG. 11, every time the serial data input signal SDI is input, FF40 [7: 0] and The signal output from the data output terminal Q of the FF 42 [7: 0] is sequentially shifted to the next stage FF 40 [7: 1], FF 42 [7: 0] and the final stage FF 44 and held.

  Then, as indicated by shift 17 in FIG. 11, the reset signal RSTN H (1) is set in the final stage FF 44, that is, the test address signal ADR1 [7: 0] and the memory designation signal ADR2 [7: 0]. ] Are set to FF40 [7: 0] and FF42 [7: 0], respectively, the output signal CLKM of the OR circuit 36 is fixed to H, and thereafter, the serial clock input signal CLK The shift operation is not performed regardless of the change.

  Subsequently, in the test clock generator 16, as shown in FIG. 13, when the reset signal RSTN becomes H, the counter 48 is released from the reset and operates in synchronization with the rising of the oscillation clock output from the ring oscillator 46. To do.

  In this example, as shown in FIG. 13, the counter 48 is a 4-bit down counter, and the internal clock signal CLK [3: 0] is output from the inverted data output terminal QB of the FF 50 [3: 0]. Will be described.

The counter 48 starts down-counting from the state in which the internal clock signal CLK [3: 0] is all H in synchronization with the rising edge of the oscillation clock after the reset signal RSTN becomes H. When the internal clock signal CLK [3: 0] becomes all-L, it becomes all-H again in synchronization with the rising edge of the next oscillation clock, and thereafter, down-counting is repeated.
The test clock signal CLKOUT is an inverted signal of the internal clock signal CLK [3], and oscillates from the L state at the cycle of the internal clock signal CLK [3].

  Subsequently, in the memory output control unit 18, when the test clock signal CLKOUT starts oscillating, the counter 52 operates in synchronization with the falling edge of the test clock signal CLKOUT.

  As shown in FIG. 14, after the clear signal CLR becomes H, the counter 52 starts counting up from the state where the count value CNT [n: 0] is 0 in synchronization with the fall of the test clock signal CLKOUT. To do.

  When the count value CNT [n: 0] is 0, only the memory data bit selection signal SEL [0] corresponding to 0 of the count value CNT [n: 0] is H in the active state, and other memory data bit selection The signal SEL [m: 1] is L in the inactive state. When the count value CNT [n: 0] becomes 1, only the memory data bit selection signal SEL [1] corresponding to 1 of the count value CNT [n: 0] becomes H, and thereafter the count value CNT [n : 0] is up-counted, only the 1-bit memory data bit selection signal SEL corresponding to the count value CNT [n: 0] sequentially becomes H.

  Subsequently, when the reset signal RSTN is H, that is, the test address signal ADR1 [i: 0] and the memory designation signal ADR2 [j: 0] of the test setting data signal are set in the shift register 38 of the memory test setting unit 14. Among the test address signals ADR1 [i: 0], the test address signal ADR1 [y: 0] having the number of bits corresponding to the number of bits of the address signal of the memory 76 is stored as the memory address signal A [y: 0]. Input to the output unit 20 [p: 0].

  For example, in the memory data output unit 20 [0], the memory address signal A [y: 0] is output from the multiplexer 72A configuring the input switching circuit 68, the test clock signal CLKOUT is output from the multiplexer 72D, and the write enable is output from the multiplexer 72B. H in the disabled state is output as the signal WEN, and L in the selected state is output from the multiplexer 72C as the chip select signal CSN, which is input to the corresponding input terminal of the memory 76. Therefore, as shown in FIG. 15, the parallel memory data output signal Q [x: 0] is read from the memory address specified by the memory address signal A [y: 0] in synchronization with the rising edge of the test clock signal CLKOUT. .

  The memory data bit selection signal SEL [x: 0] is H in which only one bit is sequentially active in the order of the memory data bit selection signal SEL [x: 0] in synchronization with the fall of the test clock signal CLKOUT. As shown in FIG. 16, when only the memory data bit selection signal SEL [0] becomes H, the multiplexer 74 [x: 1] constituting the output switching circuit 70 receives the signal input to the input terminal 0, That is, L is output, and the signal input to the input terminal 1, that is, the parallel memory data output signal Q [0] is output from the multiplexer 74 [0] as the serial memory data output signal QOUT [0]. .

  Subsequently, when only the memory data bit selection signal SEL [1] becomes H, the signal input to the input terminal 0, that is, L is output from the multiplexer 74 [x: 2], from the multiplexer 74 [1]. Is a signal input to the input terminal 1, that is, a parallel memory data output signal Q [1], and the multiplexer 74 [0] inputs to the input terminal 0 as a serial memory data output signal QOUT [0]. That is, the parallel memory data output signal Q [1], which is the output signal of the multiplexer 74 [1], is output.

Thereafter, the same operation is performed. That is, every time when only one bit sequentially becomes H in the order of the memory data bit selection signal SEL [x: 0], the corresponding parallel memory data output signal Q [x: 0] is used as the serial memory data output signal QOUT [0]. ] Bits are sequentially output.
The operation of the other memory data output unit 20 [p: 1] is the same, and the serial memory data output signal QOUT [p: 0] is sequentially output from the memory data output unit 20 [p: 0]. .

  Subsequently, as shown in FIG. 17, the input / output control unit 22 selects the memory designation signal ADR2 [j: from the serial memory data output signal QOUT [p: 0] of the memory data output unit 20 [p: 0]. 0], the serial memory data output signal QOUT of the memory data output unit 20 is output from the multiplexer (MUX) 78. In the example of FIG. 17, the serial memory data output signal QOUT [0] of the memory data output unit 20 [0] is output from the multiplexer (MUX) 78.

Also, as shown in FIG. 18, when the reset signal RSTN becomes H, the set of the FFs 80A, 80B, 80C constituting the input / output control unit 22 is released.
As a result, the output enable signal ENL becomes active L in synchronization with the rising edge of the test clock signal CLKOUT, and the first and second input / output circuits 24A and 24B of the input / output unit 12 enter the output mode. In this case, the serial data output signal SDO and the serial clock output signal SCLKO are output from the output buffers 28A and 28B to the input / output pins of the serial data SDA and the serial clock SCL, respectively.

  As shown in FIG. 19, when the reset signal RSTN becomes H, the serial memory data output signal QOUT output from the multiplexer 78 is sequentially outputted as the serial data output signal SDO in synchronization with the fall of the test clock signal CLKOUT. Is output. The serial data output signal SDO is sequentially output from the output buffer 28A of the first input / output circuit 24A to the input / output pins of the serial data SDA.

  Further, the serial clock output control signal SCLKO_pre becomes L in an active state in synchronization with the rising of the test clock signal CLKOUT, and the test clock signal CLKOUT is sequentially output from the OR circuit 82 as the serial clock output signal SCLKO. The serial clock output signal SCLKO is sequentially output from the output buffer 28B of the second input / output circuit 24B to the input / output pins of the serial clock SCL.

  When the count value CNT [n: 0] of the counter 52 of the memory output control unit 18 is a constant value, which is the maximum value in the example of FIG. 5, as shown in FIG. 20, an AND circuit 60 [ n-1: 1] is all H, the output signal of the NAND circuit 62 is L, the output signals of the plurality of buffer circuits 64 are also L, and the clear signal CLR output from the AND circuit 66 is again L. become.

The operation when the clear signal CLR becomes L is the same as the operation when the clear signal CLR becomes L in the normal operation mode. That is, the test circuit 10 is in an initial state and is in a standby state waiting for the next test setting data signal to be set.
The subsequent operation is the same.

  As shown in FIG. 20, when the clear signal CLR becomes L, the counter 52 of the memory output control unit 18 is reset, and the count value CNT [n: 0] becomes 0, the AND circuit of the clear signal generation circuit 54 The output signal of 60 [n−1: 1] is all L, the output signal of the NAND circuit 62 is H, the output signals of the plurality of buffer circuits 64 are also H, and the clear signal CLR output from the AND circuit 66 is H. Return.

  As described above, in the test circuit 10, by securing two external pins, the memory data read from the memory 76 mounted on the semiconductor device while the semiconductor device is still mounted on the printed circuit board, Can be output sequentially from external pins. For this reason, it is possible to externally observe a state such as whether or not the memory data is stacked at L or H, while avoiding the risk of destruction of the joint portion that occurs when the semiconductor device is peeled from the printed board.

  The specific circuit configurations of the input / output unit, the memory test setting unit, the test clock generation unit, the memory output control unit, the memory data output unit, and the input / output control unit that constitute the test circuit are not limited at all, and the same function The thing of the various structures which implement | achieve can be used.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 Test circuit 12 Input / output part 14 Memory test setting part 16 Test clock generation part 18 Memory output control part 20 Memory data output part 22 Input / output control part 24A 1st input / output circuit 24B 2nd input / output circuit 26A, 26B Input buffer 28A 28B Output buffer 32A, 32B, 34A, 34B, 72A, 72B, 72C, 72D, 74, 78 Multiplexer 36, 82 OR circuit 38 Shift register 40, 42, 44, 50, 58, 80A, 80B, 80C FF
46 Ring oscillator 48, 52 Counter 54 Clear signal generating circuit 56 Decoder 60, 66 AND circuit 62 NAND circuit 64 Buffer circuit 68 Input switching circuit 70 Output switching circuit 76 Memory

Claims (10)

A test circuit for testing a memory mounted on a semiconductor device,
When the output enable signal becomes inactive, the input mode is entered. The serial data input signal and serial clock input signal are input from the first and second input / output pins, respectively, and output when the output enable signal becomes active. An input / output unit configured to output a serial data output signal and a serial clock output signal to the first and second input / output pins, respectively,
Synchronously with the serial clock input signal, the serial data input signal of a certain number of bits sequentially input is converted into a parallel data input signal and set as a test setting data signal;
A test clock generator for generating a test clock signal having a constant frequency;
A memory data output unit for converting a parallel memory data output signal read in synchronization with the test clock signal from a memory address of a memory to be tested designated by the test setting data signal into a serial memory data output signal;
In synchronization with the test clock signal, the serial memory data output signal is sequentially output as the serial data output signal, and the test clock signal is sequentially output as the serial clock output signal. A test circuit comprising: an input / output control unit that outputs the output enable signal that becomes active in synchronization with the test clock signal when the test setting data signal is set in an active state. Furthermore, a count value is initialized when the clear signal is in an active state, and when the clear signal is in an inactive state, the first counter that counts in synchronization with the test clock signal and outputs the count value;
When the debug mode signal represents the normal operation mode, and when the debug mode signal represents the test mode and the count value becomes a constant value, the debug mode signal represents the test mode. 2. The test circuit according to claim 1, further comprising: a clear signal generation circuit configured to generate the clear signal that becomes inactive when the count value is not the constant value.   The memory test setting unit is initialized when the clear signal is in an active state, and when the clear signal is in an inactive state, the serial data having a certain number of bits sequentially input in synchronization with the serial clock input signal. The input signal is sequentially shifted and converted into the parallel data input signal and held, and as the test setting data signal, a test address signal designating a memory address of the memory to be tested and a reset signal in an inactive state The test circuit according to claim 2, further comprising a shift register to be set. The test clock generator is
A ring oscillator that generates an oscillation clock of a constant frequency when the debug mode signal represents the test mode;
4. A second counter that is initialized when the reset signal enters an active state and counts in synchronization with the oscillation clock to generate the test clock signal when the reset signal enters an inactive state. Test circuit described.   5. The test circuit according to claim 3, further comprising a decoder that outputs a memory data bit selection signal having a fixed number of bits in which only one bit corresponding to the count value is sequentially activated. When the debug mode signal represents the normal operation mode, the memory data output unit inputs an internal signal in the normal operation mode to the memory to be tested, and the debug mode signal represents the test mode. An input switching circuit for inputting a test signal including the test address signal and the test clock signal to the test target memory so that the parallel memory data output signal is read from the test target memory;
6. The test circuit according to claim 5, further comprising: an output switching circuit that sequentially outputs, as the serial memory data output signal, the bits of the parallel memory data output signal corresponding to the bits of the memory data bit selection signal in the active state. The input / output control unit
The reset signal is initialized when it is in an active state, and when the reset signal is in an inactive state, the serial memory data output signal is held in synchronization with the test clock signal and is output as the serial data output signal. A holding circuit;
When the reset signal becomes active, it is initialized and becomes inactive, and when the reset signal becomes inactive, the serial clock output control signal that becomes active in synchronization with the test clock signal is held, and the serial signal A second holding circuit that outputs the test clock signal as the serial clock output signal when a clock output control signal is in an active state;
When the reset signal becomes active, it is initialized and becomes inactive. When the reset signal becomes inactive, the output enable signal that becomes active in synchronization with the test clock signal is held and output. A test circuit according to any one of claims 4 to 6, further comprising a 3 holding circuit. The test circuit includes a plurality of the memory data output units,
The shift register of the memory test setting unit is for setting a memory specifying signal for specifying the test target memory from the plurality of memories as the test setting data signal,
The input / output control unit further includes a serial memory output from the test target memory designated by the memory designation signal from among the serial memory data output signals outputted from each of the plurality of memory data output units. It has a multiplexer that outputs the data output signal,
The first holding circuit of the input / output controller holds the serial memory data output signal output from the multiplexer in synchronization with the test clock signal when the reset signal becomes inactive, and the serial data output signal The test circuit according to claim 7, which is output as:   The test circuit according to claim 1, wherein the first and second input / output pins are assigned to input / output pins that do not affect the operation of the semiconductor device in a normal operation mode. . A test method for testing a memory mounted on a semiconductor device,
The input / output control unit sets the output enable signal to an inactive state and sets the input / output unit to the input mode;
The input / output unit inputs a serial data input signal and a serial clock input signal from the first and second input / output pins, respectively;
A memory test setting unit, in synchronization with the serial clock input signal, sequentially converting the serial data input signal having a fixed number of bits into a parallel data input signal, and setting as a test setting data signal;
A step of generating a test clock signal having a constant frequency by a test clock generator;
When the input / output control unit is set to the test setting data signal, in synchronization with the test clock signal, the output enable signal is activated to place the input / output unit in an output mode;
The memory data output unit converts the parallel memory data output signal read in synchronization with the test clock signal from the memory address of the test target memory designated by the test setting data signal into a serial memory data output signal When,
An input / output controller that sequentially outputs the serial memory data output signal as a serial data output signal in synchronization with the test clock signal, and sequentially outputs the test clock signal as a serial clock output signal;
And a step of outputting the serial data output signal and the serial clock output signal to the first and second input / output pins, respectively.

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