JP2006079678A - Memory test circuit and memory test method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory test circuit and a memory test method by which memory test is easily conducted. <P>SOLUTION: Test object addresses and test data are generated by an address/data generating section 2 and the addresses and the data are held by an address holding register 3 and a data holding register 4. Then, the data of test object addresses of the initial value data read from a memory 100 are replaced by the test data and a computing section 8 conducts computations and the result is held in an expected value register 9. Then, the memory 100 is rewritten by a memory rewriting section 5 using the data held in the address holding register 3 and the data holding register 4, data are read from the memory 100 and computations are conducted by the computing section 8 and the result is held in a memory output result register 10. A comparing section 11 compares the values of the memory output result register 10 and the expected value register 9 and outputs a comparison result signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory test circuit and a memory test method for testing a memory built in a semiconductor integrated circuit.

  When testing a semiconductor integrated circuit composed of a combination of a logic circuit and a memory, as a technique for efficiently testing the memory, there is a technique of separating the memory from the logic circuit using a test circuit or the like and testing the memory alone. Commonly used.

  When using this method to monitor the memory output outside the semiconductor integrated circuit, if the memory output is not directly an external output terminal, the monitor allows the memory output to be observed at the external terminal. For example, a circuit is added to the output of the memory. In such a case, if the number of output bits of the memory is large, the scale of the monitor circuit to be added becomes large, which may increase the chip size of the semiconductor integrated circuit.

  Therefore, conventionally, memory output data is compressed by an arithmetic circuit, and compressed data having a bit number smaller than the memory output bit number is observed at an external terminal (see, for example, Patent Document 1). ).

However, when observing such compressed data and determining the quality of the memory circuit, compressed data to be used as an expected value is necessary, and this expected value data must be created in advance using simulation or the like. There was a problem. In particular, when the memory is a DRAM or the like, a wide variety of test patterns must be created for verification of interference between memory cells and bit lines, and expected value data is created for each test pattern. Had to do. Therefore, there is a problem that it takes time and effort to create expected value data.
Japanese Patent Laid-Open No. 10-300824 (second page, FIG. 1)

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a memory test circuit and a memory test method capable of determining whether a memory is good or bad by using a calculation output result of memory output data without preparing expected value data in advance. There is to do.

  According to one aspect of the present invention, an address / data generating means for generating an address and data to be given to a memory, an address holding register for holding a specific address to be tested generated by the address / data generating circuit, A data holding register for holding test data generated by an address / data generation circuit, and data at an address corresponding to the specific address held in the address holding register for holding data read from the memory Replacing the test data held in the register and outputting the data at the other addresses as they are; and the specific address held in the address holding register of the memory as the data holding register Memory for rewriting the test data held in the memory Switching means, selection means for selecting either output data of the data replacement means or data read from the memory, calculation means for performing a predetermined calculation on the output of the selection means, and the selection An expected value register that holds the output of the computing means as an expected value when the means selects the output data of the data replacing means; and the computing means when the selecting means selects the data read from the memory A memory output result register that holds the output of the memory as a memory output result, and a comparison unit that compares the output of the expected value register with the output of the memory output result register and outputs a comparison result signal. A memory test circuit is provided.

  Further, according to one aspect of the present invention, the step of generating test data for rewriting a specific test target address in a memory in which an initial value is written in advance, the step of holding the test data, Sequentially reading data of all addresses of the memory, replacing only the data of the specific address with the held test data, and generating replacement data; and performing predetermined operations on the replacement data A step of holding an operation result for the replacement data as an expected value, a step of rewriting the data at the specific address of the memory with the held test data, and the memory after the rewriting The second read step for sequentially reading the data of all the addresses of the second and the second read A second calculation step for performing the predetermined calculation on the data read from the memory in the step, a step of holding a calculation result of the second calculation step as a memory output result, and the expected value A memory test method comprising: comparing the memory output results and outputting a comparison result signal; and determining whether the operation of the memory with respect to the address is good based on the comparison result signal. Is done.

  According to the present invention, the expected value data is generated using the arithmetic circuit that performs the operation on the output data of the memory. Therefore, it is not necessary to generate the expected value data in advance, and the memory test can be easily performed.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a memory test circuit according to an embodiment of the present invention. The memory circuit 1 according to the present embodiment is a circuit that tests whether or not the memory 100 to be tested performs a correct memory operation, and is a circuit that can determine whether the memory operation is good or bad in units of addresses.

  The memory test circuit 1 includes an address / data generation unit 2 that generates an address to be given to the memory 100 and test data, and an address holding that holds a specific address to be tested among the addresses generated by the address / data generation unit 2 The register 3, the data holding register 4 that holds the test data generated by the address / data generator 2, and the data at the address held in the address holding register 3 among the data stored in the memory 100 And a memory rewriting unit 5 for rewriting the data held in the holding register 4.

  Further, the memory test circuit 1 includes a data replacement unit 6, a selection unit 7, a calculation unit 8, an expected value register 9, a memory result output register 10, and a comparison unit 11.

  The data replacement unit 6 receives the data read from the memory 100, and among the input data, the data at the address corresponding to the address held in the address holding register 3 becomes the data held in the data holding register 4. Replace and output other address data as it is.

  The selection unit 7 selects and outputs either the data output from the data replacement unit 6 or the data read from the memory 100.

  The calculation unit 8 performs, for example, a pattern compression calculation so that the amount of output data is reduced with respect to the data input from the selection unit 7.

  The expected value register 9 holds the output of the calculation unit 8 when the selection unit 7 selects the data output from the data replacement unit 6 as an expected value.

  The memory result output register 10 holds the output of the calculation unit 8 when the selection unit 7 selects the data read from the data memory 100 as a memory output result.

  The comparison unit 11 compares the memory output result held in the memory result output register 10 with the expected value held in the expected value register 9 and outputs a comparison result signal indicating the coincidence / mismatch between the two.

  Next, a method for testing the memory 100 by the memory test circuit 1 of this embodiment will be described with reference to the flowchart of FIG. It is assumed that initial value data is written in the memory 100 prior to the flow shown in FIG.

  First, the address / data generation unit 2 generates an address value and test data to be tested (step S1), the generated address is stored in the address holding register 3, and the test data is stored in the data holding register 4. Hold (step S2). Here, the test data is data that is written to the memory 100 and used for testing the memory operation, and is arbitrary data different from the initial value written in the memory 100.

  Subsequently, the address / data generation unit 2 sequentially generates addresses and sequentially reads all data from the memory 100 (step S3). At this time, data read from the memory 100 is initial value data.

  If the selection unit 7 selects the output from the data replacement unit 6 at the time of reading, the data read from the memory 100 is processed by the data replacement unit 6 and then input to the calculation unit 8. Is done.

  The data replacement unit 6 checks the address given to the memory 100, and the address corresponding to the address held in the address holding register 3 is held in the data holding register 4 instead of the data read from the memory 100. The test data is output (step S4). As a result, only the address of the memory 100 to be tested from now on is input to the arithmetic unit 8 as the test data to be written.

  That is, the data input to the arithmetic unit 8 at this time is data that is expected to be output from the memory 100 when the test data is written to the memory 100.

  Therefore, the calculation unit 8 performs the calculation (step S5), and the calculation result is held in the expected value register 9 as an expected value (step S6).

  Subsequently, the memory rewriting unit 5 rewrites the address held in the address holding register 3, that is, the data of the address to be tested in the memory 100 to the test data held in the data holding register 4 (step S7).

  After the memory 100 is rewritten, the address / data generation unit 2 sequentially generates addresses and sequentially reads all data from the memory 100 (step S8).

  If the selection unit 7 selects an output from the data memory 100 at the time of reading, the data read from the memory 100 is input to the arithmetic unit 8 as it is.

  Therefore, the calculation unit 8 performs the calculation (step S9), and the calculation result is held in the memory output result register 10 as the memory output result (step S10).

  Here, the expected value previously held in the expected value register 9 and the memory output result held in the memory output result register 10 are compared by the comparison unit 11, and a comparison result signal indicating the coincidence / mismatch is output (step). S11).

  If the memory 100 is operating normally, the memory output result matches the expected value, and if the memory 100 is not operating normally, the memory output result does not match the expected value.

  By observing the comparison result signal output from the comparison unit 11, it is determined whether data has been normally written / read to / from the test target address of the memory 100, that is, whether the memory operation is good or bad. (Step S12).

  Next, the operation of the memory test circuit 1 when the memory test is performed by the above-described method will be described with reference to FIGS.

  FIG. 3 is a waveform diagram showing the operation from the generation of a specific test target address and test data by the address / data generation unit 2 until the expected value is held in the expected value register 8. Here, it is assumed that hexadecimal AAH (H is a symbol indicating a hexadecimal number, and so on) is given to the memory 100 as an initial value.

  Assuming that the test target address is 0H and the test data is 55H, first, data is output from the address / data generation unit 1 in the order of 0H and 55H.

  Therefore, the address holding register 3 holds the address 0H, and the data holding register 4 holds the test data 55H.

  Next, addresses are sequentially generated from the address / data generation unit 2 from 0H to the final address nH (n is an arbitrary number), and data in the memory 100 is read. At this time, the data read from the memory 100 is the initial value AAH at all addresses.

  For the data read from the memory 100, the data replacement unit 6 replaces the data at the address 0H held in the address holding register 3 with the test data 55H held in the data holding register 4 and outputs the data. To do.

  The calculation unit 8 sequentially calculates the output of the data replacement unit 6. Then, the output of the arithmetic unit 8 at the time when the output of the data of the final address nH is completed is held in the expected value register 9.

  Next, FIG. 4 is a waveform diagram showing the operation from when the memory 100 is rewritten to test data until the memory output result is held in the memory output result register 9.

  Using the address held in the address holding unit 3 and the test data held in the data holding register 4, the data 55H to be given to the address 0H to be tested is output from the memory rewriting unit 5 and the data in the memory 100 is rewritten. It is done.

  Thereafter, the address / data generation unit 1 sequentially generates addresses from 0H to the final address nH, and sequentially reads data from the memory 100. At this time, if the data read from the memory 100 is normally rewritten and read normally, the data at the address 0H is 55H and the data at the other addresses is AAH. Should be read.

  The calculation unit 8 sequentially calculates the data read from the memory 100. Then, the output of the arithmetic unit 8 at the time when the output of the data of the final address nH is completed is held in the memory output result register 10.

  Finally, the comparison unit 11 compares the memory output result held in the memory output result register 10 with the expected value held in the expected value register 9 and outputs a comparison result signal indicating match / mismatch. .

  According to the memory test circuit and the memory test method of the present embodiment as described above, the expected value is created by the calculation in the circuit, so it is not necessary to prepare the expected value in advance. Also, the test data used for the test can be easily created because only the test target addresses need be generated. Therefore, the labor and time required for preparing the memory test can be reduced, and the memory test can be easily performed.

1 is a block diagram showing an example of the configuration of a memory test circuit according to an embodiment of the present invention. 4 is a flowchart showing an example of a memory test method using the memory test circuit according to the embodiment of the present invention. The wave form diagram which shows the example of operation | movement of the memory test circuit based on the Example of this invention. The wave form diagram which shows the example of operation | movement of the memory test circuit based on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Memory test circuit 2 Address / data generation part 3 Address holding register 4 Data holding register 5 Memory rewriting part 6 Data replacement part 7 Selection part 8 Calculation part 9 Expected value register 10 Memory output result register 11 Comparison part

Claims (3)

Address / data generating means for generating addresses and data to be given to the memory;
An address holding register for holding a specific address to be tested generated by the address / data generation circuit;
A data holding register for holding test data generated by the address / data generation circuit;
The data read from the memory is replaced with the data at the address corresponding to the specific address held in the address holding register with the test data held in the data holding register, and the data at other addresses is Data replacement means to output as it is,
Memory rewriting means for rewriting the specific address held in the address holding register of the memory with the test data held in the data holding register;
Selecting means for selecting either the output data of the data replacing means and the data read from the memory;
Calculation means for performing a predetermined calculation on the output of the selection means;
An expected value register that holds the output of the computing means as an expected value when the selecting means selects the output data of the data replacing means;
A memory output result register for holding, as a memory output result, an output of the calculating means when the selecting means selects data read from the memory;
A memory test circuit comprising: comparing means for comparing the output of the expected value register with the output of the memory output result register and outputting a comparison result signal.   The memory test circuit according to claim 1, wherein the comparison result signal is used as a signal for determining whether the memory operation with respect to the specific address is good or bad. Generating test data for rewriting a specific address to be tested in a memory in which an initial value is written in advance;
Holding the test data;
Sequentially reading data at all addresses in the memory, and replacing only the data at the specific address with the held test data to generate replacement data;
Performing a predetermined operation on the replacement data;
Holding an operation result for the replacement data as an expected value;
Rewriting the data at the specific address in the memory with the stored test data;
A second read step of sequentially reading data of all addresses of the memory after the rewriting;
A second calculation step of performing the predetermined calculation on the data read from the memory in the second read step;
Holding the calculation result of the second calculation step as a memory output result;
Comparing the expected value with the memory output result and outputting a comparison result signal;
And determining whether the operation of the memory with respect to the address is good or not based on the comparison result signal.

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