JP6344516B2 - 撮像ユニット、撮像装置、基板、および電子機器 - Google Patents
撮像ユニット、撮像装置、基板、および電子機器 Download PDFInfo
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- JP6344516B2 JP6344516B2 JP2017156964A JP2017156964A JP6344516B2 JP 6344516 B2 JP6344516 B2 JP 6344516B2 JP 2017156964 A JP2017156964 A JP 2017156964A JP 2017156964 A JP2017156964 A JP 2017156964A JP 6344516 B2 JP6344516 B2 JP 6344516B2
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- H04N23/50—Constructional details
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- H05K1/11—Printed elements for providing electric connections to or between printed circuits
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- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
- H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
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- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
- H05K3/445—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits having insulated holes or insulated via connections through the metal core
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Multimedia (AREA)
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- Solid State Image Pick-Up Elements (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
- Camera Bodies And Camera Details Or Accessories (AREA)
- Insulated Metal Substrates For Printed Circuits (AREA)
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- Studio Devices (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Non-Volatile Memory (AREA)
Description
[先行技術文献]
[特許文献]
[特許文献1] 特開2011−59272号公報
[特許文献2] 特開2012−028496号公報
図1は、第1実施形態に係る撮像ユニット10の模式断面図である。撮像ユニット10は、撮像チップ100と、コア基板120と、環囲部材140と、光学素子の一例としてのカバーガラス160と、電子部品180とを含んで構成される。
図8は、第2実施形態に係る撮像ユニット10の模式斜視図である。撮像ユニット10は、撮像チップ100と、コア基板120と、環囲部材140と、光学素子の一例としてのカバーガラス160とを含んで構成される。図8は、図面を見易くする目的でカバーガラス160が取り外された状態を示している。被写体光束が撮像チップ100へ入射する方向をz軸方向とする。撮像チップ100の長手方向をx軸方向、短手方向をy軸方向とする。なお、コア基板120の一側面(紙面の右側側面)から伸延部151が外側へ伸延する方向をx軸プラス方向とし、x軸プラス方向と逆方向をx軸マイナス方向とする。
第2実施形態で上述したように、撮像ユニットの部品実装面にはコネクタだけでなくバイパスコンデンサが配置されている。そのため、バイパスコンデンサを部品実装面に実装する場合は、バイパスコンデンサの実装面積を確保する必要がある。第3実施形態の撮像ユニットは、バイパスコンデンサの数を減らすことで電子部品の実装面積を確保しつつ、電源も安定させることが可能となる。
Claims (25)
- 被写体を撮像する撮像チップと、
第1弾性率を有し、前記撮像チップが配置される第1層と、前記第1弾性率とは異なる第2弾性率を有する第2層と、前記第1層および前記第2層の間に配置され、前記第1層および前記第2層よりも高い剛性を有する第3層と、を含む基板と、を備え、
前記第1層は、前記撮像チップで発生した熱を前記第3層に伝えるための伝熱部を有する撮像ユニット。 - 前記第1層は、前記撮像チップに接続される第1配線を有する請求項1に記載の撮像ユニット。
- 前記第1配線は、前記撮像チップで撮像された被写体の信号が出力される請求項2に記載の撮像ユニット。
- 前記第1配線は、前記第3層の外縁よりも外側へ伸延した伸延部を有する請求項2又は請求項3に記載の撮像ユニット。
- 前記第2層は、前記第1配線に接続される第2配線を有する請求項3に記載の撮像ユニット。
- 前記第2層は、前記撮像チップを駆動させるための電子部品が配置される請求項1から請求項4のいずれか一項に記載の撮像ユニット。
- 前記電子部品は、前記撮像チップよりも小さい請求項6に記載の撮像ユニット。
- 前記電子部品は、前記撮像チップを駆動させる能動素子を含む請求項7に記載の撮像ユニット。
- 前記能動素子は、前記撮像チップに電力を供給する電源回路の少なくとも一部を構成する請求項8に記載の撮像ユニット。
- 前記第1弾性率は、前記第2弾性率よりも低い請求項1から請求項9のいずれか一項に記載の撮像ユニット。
- 前記伝熱部は、貫通孔を有する請求項1から請求項10のいずれか一項に記載の撮像ユニット。
- 前記第1層および前記第2層のうち、少なくともいずれか一方の層は、ガラスクロスに熱硬化性樹脂を含浸させて形成される請求項1から請求項11のいずれか一項に記載の撮像ユニット。
- 前記第2層および前記第3層の間に配置され、前記第1層および前記第2層よりも高い剛性を有する第4層を備える請求項1から請求項12のいずれか一項に記載の撮像ユニット。
- 前記第3層および前記第4層の間に配置され、前記第3層および前記第4層よりも熱伝導率の低い第5層を備える請求項13に記載の撮像ユニット。
- 前記第3層の熱伝導率は、前記第4層の熱伝導率よりも大きい請求項14に記載の撮像ユニット。
- 前記第4層の比熱容量は、前記第3層の比熱容量よりも大きい請求項14又は請求項15に記載の撮像ユニット。
- 請求項1から請求項15のいずれか一項に記載の撮像ユニットを備える撮像装置。
- 第1弾性率を有する第1層と、
前記第1弾性率とは異なる第2弾性率を有する第2層と、
前記第1層および前記第2層の間に配置され、前記第1層および前記第2層よりも高い剛性を有する第3層と、
前記第2層および前記第3層の間に配置され、前記第1層および前記第2層よりも高い剛性を有する第4層と、を備え、
前記第3層の熱伝導率は、前記第4層の熱伝導率よりも高い基板。 - 第1弾性率を有する第1層と、
前記第1弾性率とは異なる第2弾性率を有する第2層と、
前記第1層および前記第2層の間に配置され、前記第1層および前記第2層よりも高い剛性を有する第3層と、
前記第2層および前記第3層の間に配置され、前記第1層および前記第2層よりも高い剛性を有する第4層と、を備え、
前記第4層の比熱容量は、前記第3層の比熱容量よりも高い基板。 - 前記第3層および前記第4層の間に配置され、前記第3層および前記第4層よりも低い熱伝導率を有する第5層を備える請求項18又は請求項19に記載の基板。
- 前記第1層および前記第2層のうち、少なくともいずれか一方の層は、ガラスクロスに熱硬化性樹脂を含浸させて形成される請求項18から請求項20のいずれか一項に記載の基板。
- 前記第1層は、電子部品に接続される配線を含む請求項18から請求項21のいずれか一項に記載の基板。
- 前記第1層は、半導体素子に接続される配線を含む請求項18から請求項21のいずれか一項に記載の基板。
- 前記配線は、前記第3層の外縁よりも外側へ伸延した伸延部を有する請求項22または請求項23に記載の基板。
- 請求項18から請求項24のいずれか一項に記載の基板を備える電子機器。
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