JP6339404B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device.

  In recent years, with the demand for miniaturization and high performance of power supply equipment in the field of power electronics, there has been a demand for higher breakdown voltage, higher current, and higher speed operation of semiconductor devices used in power supply equipment. As a semiconductor device that realizes such a high breakdown voltage, for example, an LDMOS (Laterally Diffused MOS) transistor having a structure in which an impurity layer in the vicinity of a drain is diffused in a lateral direction as shown in Patent Document 1 below, is used. Are known. In such a semiconductor device, a high resistance layer is added to the offset gate structure using an ion implantation technique to increase the breakdown voltage.

  In addition, in the semiconductor device disclosed in Patent Document 1, in order to realize high-speed operation, an upper portion of a conductive type source / drain layer provided on the substrate and a region not in contact with the impurity diffusion suppression film above the gate electrode are provided. A metal silicide layer for reducing the resistance is formed. In order to form the metal silicide layer only at a necessary location, the metal silicide layer is formed using a silicide block insulating film serving as a mask.

A method for forming a metal silicide layer only at a necessary location using a silicide block insulating film will be described.
FIG. 13 is a cross-sectional view illustrating a configuration example of a semiconductor device 300 according to a conventional example. The semiconductor device 300 includes a lateral diffusion MOS transistor 320 having high breakdown voltage characteristics and high-speed operation characteristics.

  As shown in FIG. 13, the semiconductor device 300 includes, for example, a P-type silicon substrate (P-type substrate) 310, an LDMOS transistor 320 disposed on the P-type substrate 310, and an impurity diffusion layer ( The first element isolation layer 340a and the second element isolation layer 340b that isolate the N-type drift layer from other regions and other elements of the P-type substrate 310, and the LDMOS transistor 320 are disposed on the P-type substrate 310. The interlayer insulating film 350, the first contact electrode 360a and the second contact electrode 360b that pass through the interlayer insulating film 350 and connect to the LDMOS transistor 320, and the first contact electrode 360a and the second contact disposed on the interlayer insulating film 350. A first wiring layer 370a and a second wiring layer 370b respectively connected to the electrode 360b; Includes a protective layer 380 covering the first wiring layer 370a and the second wiring layer 370b are disposed Enmaku 350 on a first well contact layer 390a and the second well contact layer 390b, a.

  The LDMOS transistor 320 includes a P-type well layer (P-type well layer) 321 formed on the P-type substrate 310, and a first gate oxide film 322 a and a second gate oxide film disposed on the P-type well layer 321. 322b, a first gate electrode 323a and a second gate electrode 323b disposed on the first gate oxide film 322a and the second gate oxide film 322b, respectively, and both end surfaces of the first gate oxide film 322a and the first gate electrode 323a A first sidewall 324a and a second sidewall 324b that respectively cover the first and second sidewalls 324b, and a third sidewall 324c and a fourth sidewall 324d that respectively cover both end faces of the first gate oxide film 322b and the second gate electrode 323b. ing.

  The LDMOS transistor 320 includes a source electrode 327 formed in a region between the first gate electrode 323a and the second gate electrode 323b in the P-type well layer 321, and a first gate electrode in the P-type well layer 321. The first drain electrode 328a and the second drain electrode 328b formed in the outer region of the H.323 and the second gate electrode 323b, the second N-type drift layer 326b formed in the region under the source electrode 327, and the first drain electrode The first N-type drift layer 326a and the third N-type drift layer 326c formed to include the region under 328a and the second drain electrode 328b, and the P-type body layer formed in the region under the second N-type drift layer 326b (P-type body layer) 325.

  Furthermore, the LDMOS transistor 320 includes a first silicide block insulating film 329b and a second silicide block formed in regions exposed to the surface of the P-type well layer 321 in the first N-type drift layer 326a and the third N-type drift layer 326c, respectively. The insulating film 329c is formed on the first well contact layer 390a, the first drain electrode 328a, the first gate electrode 323a, the source electrode 327, the second gate electrode 323b, the second drain electrode 328b, and the second well contact layer 390b, respectively. The first metal silicide layer 331a, the second metal silicide layer 331b, the third metal silicide layer 331c, the fourth metal silicide layer 331d, the fifth metal silicide layer 331e, the sixth metal silicide layer 331f, and the seventh metal silicide layer 331g And comprising

Here, in the semiconductor device 300, offset drains (first N-type drift layer 326a and third N-type drift layer 326c) for relaxing an electric field are provided in the peripheral region of the first drain electrode 328a and the second drain electrode 328b. By increasing the distance between the channel region and the drain region, the electric field is relaxed to increase the breakdown voltage.
However, if a metal silicide layer is provided on the first N-type drift layer 326a and the third N-type drift layer 326c, the effect of relaxing the electric field is reduced, and the first N-type drift layer 326a and the third N-type drift layer 326c are provided. The effect of increasing the breakdown voltage will be reduced. Therefore, the first silicide block insulating film 329b and the second silicide block insulating film 329c are provided on the first N-type drift layer 326a and the third N-type drift layer 326c so that the metal silicide layer is not formed.

  14 (a) to 14 (d) and FIGS. 15 (a) to 15 (d), the first metal silicide layer 331a to the seventh metal silicide layer 331g are formed in the semiconductor device 300 according to the conventional example. It is process sectional drawing which shows an example of a method. The P-type well layer 321, the first gate oxide film 322a and the second gate oxide film 322b, the first gate electrode 323a and the second gate electrode 323b, the first sidewall 324a, the second sidewall 324b, and the third sidewall. 324c and fourth sidewall 324d, P-type body layer 325, source electrode 327, first drain electrode 328a and second drain electrode 328b, first N-type drift layer 326a, second N-type drift layer 326b, and third N-type drift layer 326c The first well contact layer 390a and the second well contact layer 390b are formed on the P-type substrate 310 by a conventionally known method.

As shown in FIG. 14A, a silicide block insulating film 329a is formed so as to cover at least the first N-type drift layer 326a and the third N-type drift layer 326c exposed on the surface of the P-type well layer 321. The silicide block insulating film 329a is made of an oxide insulating film such as a silicon oxide film.
As shown in FIG. 14B, a photoresist PR is formed so as to cover the silicide block insulating film 329a.

As shown in FIG. 14C, a part of the photoresist PR is removed. At this time, by using a photolithography technique, a part of the photoresist PR is formed so that a pattern (etching mask) of the photoresist PR remains only in a region on the first N-type drift layer 326a and the third N-type drift layer 326c. Remove.
As shown in FIG. 14D, a part of the silicide block insulating film 329a is removed by using a dry etching technique using the photoresist PR as a mask. Thus, the first silicide block insulating film 329b and the second silicide block insulating film 329c are formed only in the regions on the first N type drift layer 326a and the third N type drift layer 326c, respectively.

As shown in FIG. 15A, the photoresist PR is removed.
As shown in FIG. 15B, at least the first well contact layer 390a, the first drain electrode 328a, the first gate electrode 323a, the source electrode 327, the second gate electrode 323b, the second drain electrode 328b, and the second well contact. A metal film 330 such as cobalt (Co) is formed by a sputtering method so as to cover the layer 390b.

  As shown in FIG. 15C, the metal film 330 is locally silicided by performing heat treatment. Specifically, the first well contact layer 390a, the first drain electrode 328a, the first gate electrode 323a, the source electrode 327, the second gate electrode 323b, the second drain electrode 328b, which are formed including silicon or polysilicon, The metal film 330 on the second well contact layer 390b is silicided. Accordingly, the first metal silicide layer 331a, the second metal silicide layer 331b, the third metal silicide layer 331c, the fourth metal silicide layer 331d, the fifth metal silicide layer 331e, the sixth metal silicide layer 331f, and the seventh metal silicide layer. 331 g is formed. At this time, the metal film 330 formed on the first N-type drift layer 326a and the third N-type drift layer 326c via the first silicide block insulating film 329b and the second silicide block insulating film 329c is not silicided.

As shown in FIG. 15D, the non-silicided metal film 330 is removed.
Finally, by forming the interlayer insulating film 350, the first contact electrode 360a and the second contact electrode 360b, the first wiring layer 370a and the second wiring layer 370b, and the protective layer 380, the semiconductor shown in FIG. A device 300 can be obtained.
Patent Document 2 below discloses an LDMOS transistor that meets the demand for switching loss reduction in order to enable high-speed operation of a semiconductor device. In the LDMOS transistor described in Patent Document 2, the N-type drift layer in the region facing the gate electrode and the gate insulating film can be formed narrower than the conventional one by self-alignment for high speed operation. . For this reason, in the LDMOS transistor described in Patent Document 2, it is not necessary to set the gate length in consideration of the mask alignment accuracy when forming the gate electrode as in the conventional case, and the chip size can be reduced.

JP 2013-021030 A JP 2012-033841 A

  However, when manufacturing the semiconductor device as described in the cited document 1, very high positional accuracy is required when forming the photoresist PR for forming the first silicide block insulating film 329b and the second silicide block insulating film 329c. Is required. When misalignment of the photoresist PR occurs, silicide block insulating films 429a, 429b, and 429c are formed with a deviation from the position where they should originally be formed, as shown in FIG. When the metal silicide layer forming process is performed in a state where the silicide block insulating films 429a, 429b, and 429c are formed, metal silicide layers 431a to 431g are formed. In this case, among the metal silicide layers 431a to 431g, the metal silicide layers 431b and 431e are formed in regions on the N-type drift layers 326a and 326c where the metal silicide layer should not be originally formed in order to increase the breakdown voltage. Problems arise.

  In addition, silicide block insulating films 429b and 429c are formed on a region over the first gate electrode 323a and a partial region of the second drain electrode 328b. For this reason, there arises a problem that the metal silicide layer is not formed on the region on the first gate electrode 323a and the partial region of the second drain electrode 328b where the metal silicide layer should be originally formed for speeding up.

  In other words, in the conventional metal silicide layer forming step, a metal silicide layer is formed on the first N-type drift layer 326a to the third N-type drift layer 326c, which may hinder the high breakdown voltage of the semiconductor device 300. Further, in the conventional metal silicide layer forming step, the metal silicide layer is not formed on the first gate electrode 323a and the second gate electrode 323b, and there is a possibility that the speeding up of the semiconductor device 300 may be hindered.

In particular, as the semiconductor device 300 has a fine structure in order to increase the operation speed of the semiconductor device 300, misalignment of the photoresist PR is more likely to occur, and the higher breakdown voltage and higher speed of the semiconductor device 300 are likely to be hindered.
Moreover, in the semiconductor device described in the cited document 2, the width of the N-type drift layer in the region facing the gate electrode and the gate insulating film is formed narrower than before by self-alignment, so that the semiconductor device operates at high speed. Has been realized. For this reason, the subject regarding formation of a metal silicide layer is not examined.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a metal silicide layer with high accuracy only in a necessary region in a simple process, and An object of the present invention is to provide a semiconductor device manufactured by a manufacturing method.

The present invention has been made in order to achieve such an object, and a method for manufacturing a semiconductor device according to one embodiment of the present invention includes implanting a first conductivity type impurity into a semiconductor substrate to obtain a first conductivity type. A well layer forming step of forming a well layer of
An element isolation layer forming step of forming an element isolation layer on the semiconductor substrate;
A first region forming step of forming a first region in which the well layer is exposed by partially removing the device isolation layer after performing the well layer forming step and the device isolation layer forming step; ,
Forming a gate oxide film on the well layer exposed in the first region, and forming a gate electrode through the gate oxide film; and
A first drift layer forming step of implanting a second conductivity type impurity into the well layer exposed in the first region using the gate electrode as a mask to form a second conductivity type first drift layer;
A second conductivity type impurity is implanted from the second region of the well layer exposed from the element isolation layer and away from the first region into the well layer below the element isolation layer. A second drift layer forming step of forming a conductive type second drift layer;
A drain electrode formation step of forming a second conductivity type drain electrode by injecting a second conductivity type impurity into the second drift layer of the second region;
A source electrode forming step of forming a second conductivity type source electrode by injecting a second conductivity type impurity into the first drift layer;
A metal silicide layer forming step of forming a metal silicide layer on each of the gate electrode, the source electrode, and the drain electrode;
It is characterized by providing.

  In the metal silicide layer forming step included in the method for manufacturing a semiconductor device, the element isolation layer, the gate electrode, the source electrode, and the drain electrode are formed on the semiconductor substrate on a surface. A metal layer is formed without using a mask, and heat treatment is performed so that only the metal layer formed on the gate electrode, the source electrode, and the drain electrode is silicided to form the metal silicide layer. To do.

Further, in the gate forming step included in the method for manufacturing a semiconductor device described above, the gate oxide film and the gate electrode, and one end face of each of the gate oxide film and the gate electrode is on the wall portion of the element isolation layer It is preferable to form it in contact.
In addition, it is preferable to include an insulating sidewall portion forming step of forming an insulating sidewall portion covering the other end face of the gate oxide film and the gate electrode after the gate forming step included in the semiconductor device manufacturing method.

In addition, before the first drift layer forming step included in the method for manufacturing a semiconductor device described above, a first conductivity type impurity is implanted into the first region using the gate electrode as a mask. It is preferable to provide a body layer forming step for forming the body layer.
Further, in the gate forming step included in the method for manufacturing a semiconductor device described above, the gate electrode may be formed from the first region to a part of the region on the surface of the element isolation layer.

Furthermore, a semiconductor device according to one embodiment of the present invention includes a semiconductor substrate,
A first conductivity type well layer formed on the semiconductor substrate;
An element isolation layer formed in a part of the well layer;
A gate electrode formed in a first region exposed from the element isolation layer in the well layer via a gate oxide film;
A second conductivity type source electrode formed in the first region where the well layer is exposed;
A second conductivity type first drift layer formed in a region under the source electrode and having a second conductivity type impurity concentration lower than that of the source electrode;
A drain electrode of a second conductivity type formed in a second region of the well layer exposed from the element isolation layer and distant from the first region;
A second conductivity type second drift layer having a lower concentration of impurities of the second conductivity type than the drain electrode, formed from a region under the drain electrode to a region under the element isolation layer;
A metal silicide layer formed on each of the gate electrode, the source electrode, and the drain electrode , and
One end face of the gate electrode is in contact with the side wall of the element isolation layer,
The source electrode is characterized that you have provided at a position spaced laterally from the portion which is formed in a region below the isolation layer of said second drift layer.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a semiconductor device in which a metal silicide layer is formed with high accuracy only in a necessary region can be obtained with a simple process.

It is sectional drawing which shows one structural example of the semiconductor device which concerns on 1st Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment of this invention. It is sectional drawing which shows one structural example of the semiconductor device which concerns on 1st Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing which shows the example of 1 structure of the semiconductor device which concerns on 3rd Embodiment of this invention. It is sectional drawing which shows one structural example of the semiconductor device which concerns on a prior art example. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on a prior art example. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on a prior art example. It is sectional drawing which shows one structural example of the semiconductor device which concerns on a prior art example.

1. First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
<1-1. Configuration of Semiconductor Device>
FIG. 1 is a cross-sectional view showing a configuration example of the semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 includes an LDMOS (lateral diffusion MOS) transistor 20 having high breakdown voltage characteristics and high-speed operation characteristics by providing a metal silicide layer.

  As shown in FIG. 1, this semiconductor device 100 includes, for example, a P-type substrate 10, an LDMOS transistor 20 disposed on the P-type substrate 10, and an impurity diffusion layer (an N-type drift layer described later) of the LDMOS transistor 20. On the P-type substrate 10, the first element isolation layer 40 b, the second element isolation layer 40 c, the third element isolation layer 40 d, and the fourth element isolation layer 40 e that isolate the substrate from other regions and other elements. An interlayer insulating film 50 that covers the LDMOS transistor 20, a first contact electrode 60 a and a second contact electrode 60 b that penetrate the interlayer insulating film 50 and connect to the LDMOS transistor 20, and an interlayer insulating film 50. The first wiring layer 70a and the second wiring layer 70b connected to the first contact electrode 60a and the second contact electrode 60b, respectively, and the interlayer insulating film 50 Disposed in provided with a protective layer 80 covering the first wiring layer 70a and the second wiring layer 70b, and a first well contact layer 90a and the second well contact layer 90b, a.

The P-type substrate 10 is, for example, a single crystal silicon (Si) substrate.
The first element isolation layer 40b, the second element isolation layer 40c, the third element isolation layer 40d, and the fourth element isolation layer 40e are insulating layers formed by, for example, an STI (Shallow Trench Isolation) method, and a silicon oxide film ( SiO ₂ ). Alternatively, the first element isolation layer 40b and the second element isolation layer 40c may be insulating layers formed by a LOCOS (Local Oxidation of Silicon) method.

The first well contact layer 90a and the second well contact layer 90b are, for example, impurity diffusion regions that are formed simultaneously with the formation of a source electrode and a drain electrode described later. The first well contact layer 90a and the second well contact layer 90b are formed in a P-type well layer 21 described later, and are in contact with an electrode (not shown).
The LDMOS transistor 20 includes a P-type well layer 21 formed on the P-type substrate 10, a third element isolation layer 40 d and a fourth element isolation layer 40 e formed on a part of the P-type well layer 21, and a P-type The first gate oxide film 22b, the second gate oxide film 22c, the first gate oxide film 22b, and the first gate oxide film 22b formed in the region exposed between the third element isolation layer 40d and the fourth element isolation layer 40e on the well layer 21. A first gate electrode 23b and a second gate electrode 23c respectively formed on the second gate oxide film 22c; a first sidewall 24b covering end faces of the first gate oxide film 22b and the first gate electrode 23b; And a second sidewall 24c covering the end surfaces of the gate oxide film 22c and the second gate electrode 23c.

  The LDMOS transistor 20 includes a source electrode (N + layer) 27 formed in a region where the P-type well layer 21 between the first gate electrode 23 b and the second gate electrode 23 c is exposed, and a region below the source electrode 27. A first N-type drift layer (N− layer) 26a formed; and a P-type body layer 25 formed in a region under the first N-type drift layer (N− layer) 26a. Also, the LDMOS transistor 20 is formed in another region of the P-type well layer 21 that is exposed from the third element isolation layer 40d and the fourth element isolation layer 40e and that is away from the region where the source electrode 27 is formed. The first drain electrode (N + layer) 28a, the second drain electrode (N + layer) 28b, and a first drain electrode (N + layer) 28a formed from a region under the first drain electrode (N + layer) 28a to a region under the third element isolation layer 40d. A third N type drift layer (N− layer) 26e formed from a region under the 2N type drift layer (N− layer) 26d and the second drain electrode (N + layer) 28b to a region under the fourth element isolation layer 40e. And comprising.

  Further, the LDMOS transistor 20 is formed on the first well contact layer 90a, the first drain electrode 28a, the first gate electrode 23b, the source electrode 27, the second gate electrode 23c, the second drain electrode 28b, and the second well contact layer 90b. The first metal silicide layer 31a, the second metal silicide layer 31b, the third metal silicide layer 31c, the fourth metal silicide layer 31d, the fifth metal silicide layer 31e, the sixth metal silicide layer 31f, and the seventh metal silicide formed respectively. A layer 31g is provided.

Here, the LDMOS transistor 20 according to the present embodiment includes a silicide that inhibits formation of a metal silicide layer, such as the first silicide block insulating film 329b and the second silicide block insulating film 329c of the semiconductor device 300 shown in FIG. A block insulating film is not provided.
Hereinafter, when the first element isolation layer 40b, the second element isolation layer 40c, the third element isolation layer 40d, and the fourth element isolation layer 40e are not distinguished, they may be referred to as the element isolation layer 40. When the first gate oxide film 22b and the second gate oxide film 22c are not distinguished from each other, they may be referred to as a gate oxide film 22. If the first gate electrode 23b and the second gate electrode 23c are not distinguished, they may be referred to as the gate electrode 23. When the first sidewall 24b and the second sidewall 24c are not distinguished, they may be referred to as sidewalls 24. If the first drain electrode 28a and the second drain electrode 28b are not distinguished, they may be referred to as the drain electrode 28. When the first N-type drift layer 26a, the second N-type drift layer 26d, and the third N-type drift layer 26e are not distinguished, they may be referred to as the N-type drift layer 26. The first metal silicide layer 31a, the second metal silicide layer 31b, the third metal silicide layer 31c, the fourth metal silicide layer 31d, the fifth metal silicide layer 31e, the sixth metal silicide layer 31f, and the seventh metal silicide layer 31g are distinguished. If not, it may be referred to as a metal silicide layer 31. When the first well contact layer 90a and the second well contact layer 90b are not distinguished from each other, they may be referred to as well contact layers 90.

  In the semiconductor device 1 according to this embodiment, the opening 40f is provided as a gate region, and the third element isolation layer 40d and the fourth element isolation layer 40e are formed with the opening 40f interposed therebetween. A first gate oxide film 22b and a second gate oxide film 22c, and a first gate electrode 23b and a second gate electrode 23c are formed in the opening 40f. The first gate electrode 23b and the second gate electrode 23c are provided separately from each other. The first gate oxide film 22b and the first gate electrode 23b are formed so that one end face of the first gate oxide film 22b and the first gate electrode 23b is in contact with the wall portion of the third element isolation layer 40d. The second gate oxide film 22c and the second gate electrode 23c are formed such that one end face of the second gate oxide film 22c and the second gate electrode 23c is in contact with the wall portion of the fourth element isolation layer 40e. . The first gate electrode 23b and the second gate electrode 23c are made of, for example, polysilicon.

The first sidewall 24b and the second sidewall 24c are provided to adjust the formation region of the source electrode 27. The first sidewall 24b and the second sidewall 24c are made of an insulating silicon compound such as silicon nitride or silicon oxide.
The source electrode 27 is formed in a region (a bottom portion of the opening 40f) where the P-type well layer 21 is exposed between the first gate electrode 23b and the second gate electrode 23c. The source electrode 27 is formed so that the impurity concentration is higher than that of the first N-type drift layer 26 a formed in the region under the source electrode 27.

The first N-type drift layer 26 a is formed in a region below the source electrode 27. Therefore, the first N-type drift layer 26 a is formed in the P-type well layer 21 without being exposed on the surface of the P-type well layer 21. The first N-type drift layer 26 a is formed so that the impurity concentration is lower than that of the source electrode 27.
The P-type body layer 25 is formed to extend from below the first N-type drift layer 26a to below a part of the first gate electrode 23b and below a part of the second gate electrode 23c. . The P-type body layer 25 is formed so that the impurity concentration is higher than that of the P-type well layer 21.

  The first drain electrode 28a is formed so that the impurity concentration is higher than that of the second N-type drift layer 26d. The second drain electrode 28b is formed to have a higher impurity concentration than the third N-type drift layer 26e. The first drain electrode 28a and the second drain electrode 28b are preferably formed at the same height as the first gate electrode 23b and the second gate electrode 23c. This is because a wiring process for forming wiring layers such as the first wiring layer 70a and the second wiring layer 70b is facilitated.

  The second N-type drift layer 26d is formed from a region below the first drain electrode 28a to a region below the third element isolation layer 40d. The third N-type drift layer 26e is formed from a region below the second drain electrode 28b to a region below the fourth element isolation layer 40e. That is, the second N-type drift layer 26 d and the third N-type drift layer 26 e are formed in the P-type well layer 21 without being exposed on the surface of the P-type well layer 21.

  In the extended region of the second N-type drift layer 26d that extends below a portion of the first gate electrode 23b, the majority carriers are the first when a positive bias is applied to the first gate electrode 23b. It is attracted to and accumulated on the gate oxide film 22b side. Similarly, in the third N-type drift layer 26e, an extension region extending below a part of the second gate electrode 23c has a large number when a positive bias is applied to the second gate electrode 23c. Carriers are attracted and accumulated on the second gate oxide film 22c side.

  The first metal silicide layer 31a, the second metal silicide layer 31b, the third metal silicide layer 31c, the fourth metal silicide layer 31d, the fifth metal silicide layer 31e, the sixth metal silicide layer 31f, and the seventh metal silicide layer 31g are: For example, it consists of a compound of a metal such as cobalt (Co), titanium (Ti), nickel (Ni), molybdenum (Mo) or tungsten (W) and silicon (Si).

In the semiconductor device 1 according to the present embodiment, the second N-type drift layer 26d and the third N-type drift layer 26e are formed under the regions of the third element isolation layer 40d and the fourth element isolation layer 40e. Therefore, the metal silicide layer 31 is not formed on the surfaces of the second N-type drift layer 26d and the third N-type drift layer 26e.
In the semiconductor device 1 according to the present embodiment, it is not necessary to form a silicide block insulating film to inhibit the formation of the metal silicide layer 31 on the surfaces of the second N-type drift layer 26d and the third N-type drift layer 26e. Therefore, the formation position of the metal silicide layer 31 does not depend on the alignment of the silicide block insulating film, and the metal is formed only on the gate electrode 23, the source electrode 27, the drain electrode 28, and the well contact layer 90 with high positional accuracy. The semiconductor device 1 provided with the silicide layer 31 can be obtained.

<1-2. Manufacturing Method of Semiconductor Device>
Next, a method for manufacturing the semiconductor device 1 shown in FIG. 1 will be described with reference to FIGS. 2 to 6 are process cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 1.
As shown in FIG. 2A, a P-type well layer 21 is formed by ion-implanting a P-type impurity such as boron (B) into the surface of the P-type substrate 10 (first impurity implantation step).
As shown in FIG. 2B, the first trench 21a, the second trench 21b, and the third trench 21c are formed on the surface of the P-type well layer 21 by using, for example, a dry etching technique.
As shown in FIG. 2C, each of the first trench 21a, the second trench 21b, and the third trench 21c is backfilled with an insulating material such as silicon oxide (SiO ₂ ), and element isolation layers 40a, 40b, and 40c are formed. Form. At this time, the surfaces of the P-type well layer 21 and the element isolation layers 40a, 40b, and 40c are flattened by mechanical chemical polishing (CMP) or the like.

As shown in FIG. 2D, a photoresist PR pattern (etching mask) is formed on the surface of the P-type well layer 21 in which the first trench 21a, the second trench 21b, and the third trench 21c are formed. At this time, a pattern of the photoresist PR is formed on a region excluding the central portion of the element isolation layer 40a.
As shown in FIG. 2E, by using a dry etching technique, the element isolation layer 40a is partially removed using the photoresist PR pattern as a mask to form an opening 40f, and the P-type well layer 21 is exposed. Let Thereby, the gate region 40g where the P-type well layer 21 is exposed is formed. In addition, element isolation layers 40d and 40e separated by the opening 40f are formed. Thereafter, the pattern of the photoresist PR is removed. Hereinafter, the element isolation layer 40b is referred to as a first element isolation layer, the element isolation layer 40c is referred to as a second element isolation layer, the element isolation layer 40d is referred to as a third element isolation layer, and the element isolation layer 40e is referred to as a fourth element isolation layer. .

Subsequently, a first gate oxide film 22b and a second gate oxide film 22c, and a first gate electrode 23b and a second gate electrode 23c are formed in the gate region 40g.
As shown in FIG. 3A, by performing a thermal oxidation process, the surface of the P-type well layer 21 exposed on the bottom surface of the opening 40f is thermally oxidized to form a gate oxide film 22a.
As shown in FIG. 3B, the first element isolation layer 40b, the second element isolation layer 40c, the third element isolation layer 40d, and the fourth element isolation layer 40e are formed so as to fill the opening 40f. A polysilicon film 23 a is deposited on the surface of the mold well layer 21. The polysilicon film 23a is formed by, for example, a chemical vapor deposition (CVD) method.

As shown in FIG. 3C, a pattern of a photoresist PR is formed at a predetermined position on the polysilicon film 23a by using a photolithography technique. For example, the photoresist PR is provided in a region inside the opening 40f from the wall of the opening 40f.
As shown in FIG. 3D, the gate oxide film 22a and the polysilicon film 23a are patterned using the photoresist PR as a mask by using a dry etching technique. Thereby, the first gate oxide film 22b and the second gate oxide film 22c, and the first gate electrode 23b and the second gate electrode 23c are formed. At this time, the first gate oxide film 22b and the first gate electrode 23b are formed such that one end face of the first gate oxide film 22b and the first gate electrode 23b is in contact with the side wall of the element isolation layer 40d. The second gate oxide film 22c and the second gate electrode 23c, one end face of the second gate oxide film 22c and the second gate electrode 23c is formed so as to contact with the side walls of the isolation layer 40 c. After the formation of the first gate electrode 23b and the second gate electrode 23c, the photoresist PR shown in FIG. 3C is removed.

  As shown in FIG. 4A, using the first gate electrode 23b and the second gate electrode 23c as a mask, a P-type is formed in a region where the P-type well layer 21 between the first gate electrode 23b and the second gate electrode 23c is exposed. Implant impurities. At this time, a photoresist PR is formed in a region other than the region where the P-type impurity is implanted. Next, a P-type impurity such as boron (B) is selectively ion-implanted into the P-type well layer 21 using an impurity implantation technique (second impurity implantation step).

  As shown in FIG. 4B, with the first gate electrode 23b and the second gate electrode 23c as a mask, a region where P-type impurities such as boron (B) are ion-implanted in the second impurity implantation step is further applied. N-type impurities such as phosphorus (P) are ion-implanted (third impurity implantation step). In the third impurity implantation step, N-type impurities are ion-implanted with lower energy than in the second impurity implantation step. Thereby, the implantation depth of the N-type impurity is made shallower than the implantation depth of the P-type impurity in the second impurity implantation step.

As shown in FIG. 4C, an insulating film 24 a is deposited on the surface of the P-type well layer 21. The insulating film 24a is made of, for example, a silicon compound such as silicon nitride or silicon oxide, and is formed by a chemical vapor deposition (CVD) method.
As shown in FIG. 4D, the first sidewall 24b and the second sidewall 24c are formed by etching back the insulating film 24a using a photolithography technique and a dry etching technique. The first sidewall 24b is an insulating sidewall that covers the other end face of the first gate oxide film 22b and the first gate electrode 23b, and the second sidewall 24c is the second gate oxide film 22c and the second gate electrode 23c. It is an insulation side wall part which covers the other end surface.

  As shown in FIG. 5A, an N-type impurity such as phosphorus (P) is ion-implanted into a partial region of the P-type well layer 21 using a photolithography technique and an impurity implantation technique (fourth impurity). Injection process). In the fourth impurity implantation step, the third region is exposed from the region between the first element isolation layer 40b and the third element isolation layer 40d that is exposed on the surface of the P-type well layer 21 and is separated from the formation region of the source electrode 27 and the like. N-type impurities are ion-implanted over the P-type well layer 21 below the element isolation layer 40d. Further, in the fourth impurity implantation step, from the region between the second element isolation layer 40c and the third element isolation layer 40d that are exposed on the surface of the P-type well layer 21 and that is separated from the formation region of the source electrode 27 and the like. N-type impurities are ion-implanted over the P-type well layer 21 below the region of the fourth element isolation layer 40e. After the fourth impurity implantation step, the photoresist PR is removed.

As shown in FIG. 5B, the regions implanted with the impurities in the second impurity implantation step to the fourth impurity implantation step are heat-treated to thermally diffuse the implanted impurities, and the first N-type drift layer 26a, An N type drift layer 26b that becomes a part of the 2N type drift layer 26d and an N type drift layer 26c that becomes a part of the third N type drift layer 26e are formed.
As shown in FIG. 5C, an N-type impurity such as phosphorus (P) is ion-implanted into a partial region of the P-type well layer 21 using a photolithography technique and an impurity implantation technique (fifth impurity). Injection process). In the fifth impurity implantation step, N-type impurities are ion-implanted into the region between the first element isolation layer 40b and the third element isolation layer 40d and the region between the second element isolation layer 40c and the third element isolation layer 40d. . In the fifth impurity implantation step, N-type impurity ions are implanted with lower energy than in the fourth impurity implantation step, so that the impurity implantation depth is shallower than the implantation depth in the fourth impurity implantation step. After the fifth impurity implantation step, the photoresist PR is removed.

  As shown in FIG. 5D, an N type such as phosphorus (P) is formed in a partial region of each of the P type well layer 21 and the first N type drift layer 26a by using a photolithography technique and an impurity implantation technique. Impurities are ion-implanted (sixth impurity implantation step). In the sixth impurity implantation step, the region between the first N-type drift layer 26a, the first element isolation layer 40b and the third element isolation layer 40d and the area between the second element isolation layer 40c and the third element isolation layer 40d are compared. N-type impurities are ion-implanted. In the sixth impurity implantation step, the N-type impurity ions are implanted with lower energy than in the fifth impurity implantation step, so that the impurity implantation depth is shallower than the implantation depth in the fifth impurity implantation step. After the sixth impurity implantation step, the photoresist PR is removed.

Note that impurities for forming the first well contact layer 90a and the second well contact layer 90b are added to the P-type well layer 21 at the same time as the ion implantation timing of any of FIGS. 5A to 5D. Ion implantation may be performed.
As shown in FIG. 5E, the N-type impurity ion-implanted by performing heat treatment is thermally diffused so that the second N-type drift layer 26d, the third N-type drift layer 26e, the source electrode 27, and the first drain electrode 28a and the second drain electrode 28b are formed. At this time, heat treatment is performed to form the first well contact layer 90a and the second well contact layer 90b which are impurity diffusion regions simultaneously with the source electrode 27 and the like.

Subsequently, a metal silicide layer is formed.
As shown in FIG. 6A, a metal such as cobalt (Co) is formed on the surface of the P-type well layer 21 on which the gate electrode 23, the source electrode 27, the drain electrode 28, and the like are formed by sputtering. A film 30 is formed.
As shown in FIG. 6B, the metal film 30 is silicided locally by performing heat treatment. Specifically, the first well contact layer 90a, the first drain electrode 28a, the first gate electrode 23b, the source electrode 27, the second gate electrode 23c, the second drain electrode 28b, which are formed to include silicon or polysilicon, The metal film 30 on the second well contact layer 90b is silicided. Accordingly, the first metal silicide layer 31a, the second metal silicide layer 31b, the third metal silicide layer 31c, the fourth metal silicide layer 31d, the fifth metal silicide layer 31e, the sixth metal silicide layer 31f, and the seventh metal silicide layer. 31g is formed.

As shown in FIG. 6C, the non-silicided metal film 30 is removed.
Finally, by forming the interlayer insulating film 50, the first contact electrode 60a and the second contact electrode 60b, the first wiring layer 70a and the second wiring layer 70b, and the protective layer 80, the semiconductor shown in FIG. Device 1 can be obtained.

<1-3. Effects of First Embodiment>
The semiconductor device manufacturing method according to the first embodiment described above has the following effects.
(1) It is possible to form the metal silicide layer 31 with high accuracy only in a region where the metal silicide layer is necessary by self-alignment without using a mask for preventing the formation of the metal silicide layer.
(2) Since the first N-type drift layer can be formed without being exposed on the surface of the P-type well layer, the metal silicide layer on the surface of the first N-type drift layer can be formed without using a photolithography technique and a dry etching technique. Formation can be prevented.

(3) Since the first N-type drift layer can be formed without being exposed on the surface of the P-type well layer, it is not necessary to form a silicide block insulating film, and the formation position of the metal silicide layer is not shifted.
(4) From the above, by using the semiconductor device manufacturing method according to the first embodiment, a semiconductor device having high breakdown voltage characteristics and high-speed operation characteristics can be obtained with simple steps.
2. Second embodiment

<2-1. Configuration of Semiconductor Device>
FIG. 7 is a cross-sectional view illustrating a configuration example of the semiconductor device 100 according to the second embodiment. 7, parts corresponding to those of the configuration of the semiconductor device 1 according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. Note that the P-type substrate 10, the P-type well layer 21, the first gate oxide film 22 b and the second gate oxide film 22 c, the P-type body layer 25, and the parts corresponding to the configuration of the semiconductor device 1 according to the first embodiment. First N-type drift layer 26a, second N-type drift layer 26d and third N-type drift layer 26e, source electrode 27, first drain electrode 28a and second drain electrode 28b, interlayer insulating film 50, first contact electrode 60a and second The description of the contact electrode 60b, the first wiring layer 70a and the second wiring layer 70b, the protective layer 80, the first well contact layer 90a and the second well contact layer 90b will be omitted.

As shown in FIG. 7, the semiconductor device 100 according to the second embodiment includes an LDMOS transistor 120.
The LDMOS transistor 120 includes a first gate electrode 123b and a second gate electrode 123c, a first sidewall 124a and a second sidewall 124b that cover the wall of the first gate electrode 123b, and a wall of the first gate electrode 123b, respectively. A third side wall 124c and a fourth side wall 124d.

  The LDMOS transistor 120 is also formed on the first well contact layer 90a, the first drain electrode 28a, the first gate electrode 23b, the source electrode 27, the second gate electrode 23c, the second drain electrode 28b, and the second well contact layer 90b. The first metal silicide layer 131a, the second metal silicide layer 131b, the third metal silicide layer 131c, the fourth metal silicide layer 131d, the fifth metal silicide layer 131e, the sixth metal silicide layer 131f, and the seventh metal silicide formed respectively. A layer 131g is provided.

  The first gate electrode 123b is formed in the gate region, that is, from the region in the opening 40f to a part of the region on the surface of the third element isolation layer 40d. Similarly, the second gate electrode 123c is formed from the gate region, that is, the region in the opening 40f to a part of the region on the surface of the fourth element isolation layer 40e. The first gate electrode 123b and the second gate electrode 123c are made of, for example, polysilicon.

The first sidewall 124a is formed so as to cover the sidewall of the first gate electrode 123b formed in a part of the region on the surface of the third element isolation layer 40d. The fourth sidewall 124d is formed so as to cover the sidewall of the second gate electrode 123c formed in a part of the region on the surface of the third element isolation layer 40e.
The first sidewall 124a, the second sidewall 124b, the third sidewall 124c, and the fourth sidewall 124d cover the first gate electrode 123b and the second gate electrode 123c by using a photolithography technique and a dry etching technique. It is formed by etching back the formed insulating film.

The first sidewall 124a, the second sidewall 124b, the third sidewall 124c, and the fourth sidewall 124d are made of, for example, a silicon compound such as silicon nitride or silicon oxide.
In the semiconductor device 100 of the second embodiment described above, the conductivity type of each layer is not limited to the described conductivity type. For example, the P-type well layer 21 may be an n-type well layer.

<2-2. Manufacturing Method of Semiconductor Device>
The semiconductor device 100 according to the second embodiment can be manufactured by changing the formation width of the photoresist PR for forming the gate oxide film in the method for manufacturing the semiconductor device 1 according to the first embodiment.

A manufacturing method of the semiconductor device 100 shown in FIG. 7 will be described with reference to FIGS. 8 to 11 are process cross-sectional views illustrating an example of a method for manufacturing the semiconductor device 100 of the second embodiment. The process sectional views shown in FIGS. 8 to 11 correspond to the process sectional views of FIGS. 3 to 6 for explaining the manufacturing configuration of the semiconductor device 1 of the first embodiment.
First, the first element isolation layer 40b and the second element isolation layer 40c are formed in the trench formed on the surface of the P-type well layer 21 by the same processes as those in FIGS. 2A to 2E of the first embodiment. The third element isolation layer 40d, the fourth element isolation layer 40e, and the gate region 40g are formed.

Subsequently, a first gate oxide film 22b and a second gate oxide film 22c, and a first gate electrode 123b and a second gate electrode 123c are formed in the gate region 40g.
As shown in FIG. 8A, by performing a thermal oxidation process, the surface of the P-type well layer 21 exposed on the bottom surface of the opening 40f is thermally oxidized to form a gate oxide film 22a.
As shown in FIG. 8B, the first element isolation layer 40b, the second element isolation layer 40c, the third element isolation layer 40d, and the fourth element isolation layer 40e are formed so as to fill the opening 40f. A polysilicon film 123 a is deposited on the surface of the mold well layer 21.

As shown in FIG. 8C, a pattern of a photoresist PR is formed at a predetermined position on the polysilicon film 123a by using a photolithography technique. At this time, the photoresist PR is provided, for example, from a region outside the wall of the opening 40f to a region inside the opening 40f. This point is different from the manufacturing method of the semiconductor device 1 of the first embodiment.
As shown in FIG. 8D, the gate oxide film 22a and the polysilicon film 123a are patterned using the photoresist PR as a mask by using a dry etching technique. Thereby, the first gate oxide film 22b and the second gate oxide film 22c, and the first gate electrode 123b and the second gate electrode 123c are formed.

  At this time, the first gate oxide film 22b and the second gate oxide film 22c are arranged such that one end faces of the first gate oxide film 22b and the second gate oxide film 22c are in contact with the wall portions of the element isolation layers 40d and 40e. It is formed. The first gate electrode 123b is formed from the gate region to a part of the region on the surface of the third element isolation layer 40d, and the second gate electrode 123c is formed from the gate region to the fourth element isolation layer 40e. It is formed over part of the area on the surface. After the formation of the first gate electrode 123b and the second gate electrode 123c, the photoresist PR shown in FIG. 8C is removed.

As shown in FIGS. 9A to 9B, using the first gate electrode 123b and the second gate electrode 123c as a mask, a P-type impurity such as boron (B) is exposed in a region where the P-type well layer 21 is exposed. Then, an N-type impurity such as phosphorus (P) is ion-implanted shallower than the P-type impurity (third impurity implantation step).
As shown in FIG. 9C, an insulating film 124 a is deposited on the surface of the P-type well layer 21.

  As shown in FIG. 9D, the insulating film 124a is etched back using a photolithography technique and a dry etching technique. Thus, the first and second sidewalls 124a and 124b, which are insulating sidewalls covering the end face of the first gate electrode 123b, and the third sidewall 124c and the insulating sidewall part covering the end face of the second gate electrode 123c, A fourth sidewall 124d is formed.

  As shown in FIGS. 10A to 10E, an impurity implantation step (fourth impurity implantation step) similar to that in FIGS. 5A to 5E is performed using a photolithography technique and an impurity implantation technique. To 6th impurity implantation step) and a thermal diffusion step. Thus, the second N-type drift layer 26d and the third N-type drift layer 26e, the source electrode 27, the first drain electrode 28a and the second drain electrode 28b, and the first well contact layer 90a and the second well contact layer 90b are formed. To do.

Subsequently, a metal silicide layer is formed.
As shown in FIG. 11A, the first gate electrode 123b, the second gate electrode 123c, the first sidewall 124a to the fourth sidewall 124d, and the like are formed by sputtering. A metal film 130 is formed on the surface.
As shown in FIG. 11B, the metal film 130 is locally silicided by performing heat treatment. Accordingly, the first metal silicide layer 131a, the second metal silicide layer 131b, the third metal silicide layer 131c, the fourth metal silicide layer 131d, the fifth metal silicide layer 131e, the sixth metal silicide layer 131f, and the seventh metal silicide layer. 131g is formed.

As shown in FIG. 11C, the non-silicided metal film 130 is removed.
Finally, by forming the interlayer insulating film 50, the first contact electrode 60a and the second contact electrode 60b, the first wiring layer 70a and the second wiring layer 70b, and the protective layer 80, the semiconductor shown in FIG. Device 100 can be obtained.

<2-3. Effect of Second Embodiment>
The configuration and manufacturing method of the semiconductor device 100 according to the second embodiment described above have the following effects. The effects (1) to (4) are the same as the effects of the first embodiment.
(1) It is possible to form the metal silicide layer 31 with high accuracy only in a region where the metal silicide layer is required by self-alignment.

(2) Since the first N-type drift layer can be formed without being exposed on the surface of the P-type well layer, the metal silicide layer on the surface of the first N-type drift layer can be formed without using a photolithography technique and a dry etching technique. Formation can be prevented.
(3) Since the first N-type drift layer can be formed without being exposed on the surface of the P-type well layer, it is not necessary to form a silicide block insulating film, and the formation position of the metal silicide layer is not shifted.

(4) From the above, by using the semiconductor device manufacturing method according to the first embodiment, a semiconductor device having high breakdown voltage characteristics and high-speed operation characteristics can be obtained with simple steps.
(5) When the first gate electrode and the second gate electrode are formed, high positional accuracy is not required when forming the photoresist which is the etching mask, so that it is possible to easily align the photoresist.
3. Third embodiment

<3-1. Configuration of Semiconductor Device>
FIG. 12 is a cross-sectional view showing a configuration example of the semiconductor device according to the third embodiment. 12, parts corresponding to those of the semiconductor device according to the first embodiment shown in FIG. Note that the P-type substrate 10, the P-type well layer 21, the first gate oxide film 22 b and the second gate oxide film 22 c, the P-type body layer 25, the first part corresponding to the configuration of the semiconductor device according to the first embodiment. About the 1N-type drift layer 26a, the second N-type drift layer 26d, the third N-type drift layer 26e, the source electrode 27, the first drain electrode 28a, the second drain electrode 28b, the first well contact layer 90a, and the second well contact layer 90b Will not be described. In FIG. 12, the interlayer insulating film, the contact electrode, the wiring layer, and the protective layer are not shown. The interlayer insulating film, contact electrode, wiring layer, and protective layer of the semiconductor device according to the third embodiment are the same as the interlayer insulating film 50, contact electrode 60, wiring layer 70, and protective layer 80 of the semiconductor device 100 according to the first embodiment. It is the same composition.

As shown in FIG. 12, the semiconductor device according to the third embodiment includes an LDMOS transistor 220.
The LDMOS transistor 220 includes first and second gate electrodes 223b and 223c, first and second sidewalls 224a and 224b that cover both end surfaces of the first gate electrode 223b, and both end surfaces of the first gate electrode 223b. 3rd side wall 224c and 4th side wall 224d which cover each.

  Also, the LDMOS transistor 220 is formed on the first well contact layer 90a, the first drain electrode 28a, the first gate electrode 23b, the source electrode 27, the second gate electrode 23c, the second drain electrode 28b, and the second well contact layer 90b. The first metal silicide layer 231a, the second metal silicide layer 231b, the third metal silicide layer 231c, the fourth metal silicide layer 231d, the fifth metal silicide layer 231e, the sixth metal silicide layer 231f, and the seventh metal silicide formed respectively. A layer 231g is provided.

The first gate electrode 223b and the second gate electrode 223c are formed thinner than the first gate electrode 23b and the second gate electrode 23c of the semiconductor device 100 of the first embodiment.
The first gate electrode 223b is a portion of the region on the surface of the third element isolation layer 40d, the side wall of the third element isolation layer 40d, and the P exposed between the third element isolation layer 40d and the fourth element isolation layer 40e. It is formed along a part of the region on the surface of the mold well layer 21. Similarly, the second gate electrode 223c is part of the region on the surface of the fourth element isolation layer 40e, the side wall of the fourth element isolation layer 40e, and between the fourth element isolation layer 40e and the third element isolation layer 40d. It is formed along a part of the region on the surface of the exposed P-type well layer 21. The first gate electrode 223b and the second gate electrode 223c are made of, for example, polysilicon.

The first sidewall 224a is formed so as to cover the outer wall of the first gate electrode 223b formed in a part of the region on the surface of the third element isolation layer 40d. The fourth sidewall 224d is formed so as to cover the outer wall of the second gate electrode 223c formed in a part of the region on the surface of the third element isolation layer 40e.
The second sidewall 224b is formed so as to cover the inner walls of the first gate oxide film 22b and the first gate electrode 223b. The third sidewall 224c is formed so as to cover the inner walls of the second gate oxide film 22c and the second gate electrode 223c.

The first sidewall 224a, the second sidewall 224b, the third sidewall 224c, and the fourth sidewall 224d cover the first gate electrode 123b and the second gate electrode 123c by using a photolithography technique and a dry etching technique. It is formed by etching back the formed insulating film.
The first sidewall 224a, the second sidewall 224b, the third sidewall 224c, and the fourth sidewall 224d are made of, for example, a silicon compound such as silicon nitride or silicon oxide.

<3-2. Manufacturing Method of Semiconductor Device>
The semiconductor device according to the third embodiment can be manufactured by thinly depositing the polysilicon film 23a for forming the gate oxide film in the method for manufacturing the semiconductor device according to the second embodiment.

<3-3. Effect of Third Embodiment>
The configuration and manufacturing method of the semiconductor device according to the third embodiment described above have the following effects. The effects (1) to (4) are the same as the effects of the first embodiment.
(1) It is possible to form the metal silicide layer 31 with high accuracy only in a region where the metal silicide layer is required by self-alignment.
(2) Since the first N-type drift layer can be formed without being exposed on the surface of the P-type well layer, the metal silicide layer on the surface of the first N-type drift layer can be formed without using a photolithography technique and a dry etching technique. Formation can be prevented.

(3) Since the first N-type drift layer can be formed without being exposed on the surface of the P-type well layer, it is not necessary to form a silicide block insulating film, and the formation position of the metal silicide layer is not shifted.
(4) From the above, by using the semiconductor device manufacturing method according to the first embodiment, a semiconductor device having high breakdown voltage characteristics and high-speed operation characteristics can be obtained with simple steps.

(5) When the first gate electrode and the second gate electrode are formed, high positional accuracy is not required when forming the photoresist which is the etching mask, so that it is possible to easily align the photoresist.
(6) By forming the first gate electrode and the second gate electrode thinly, a step between the first gate electrode and the second gate electrode having a metal silicide layer formed on the surface and the surface of the semiconductor substrate such as an element isolation layer is formed. Can be small. This facilitates alignment in the photolithography process after forming the first gate electrode and the second gate electrode.
.

  The scope of the present invention is not limited to the exemplary embodiments shown or described, but includes all embodiments that provide the same effects as those intended by the present invention. Further, the scope of the invention is not limited to the combinations of features of the invention defined by the claims, but can be defined by any desired combination of specific features among all the disclosed features.

10. P-type substrate 20, 120, 220 ... LDMOS transistor 21 ... P-type well layers 21a, 21b, 21c ... Trench 22a, 22b, 22c ... Gate oxide film 23a ... Poly Silicon film 23b, 23c, 123b, 123c, 223b, 223c ... gate electrode 24a ... insulating films 24b, 24c, 124a-124d, 224a-224d ... sidewall 25 ... body layers 26a, 26c, 26e ... Drift layer 27 ... Source electrodes 28a, 28b ... Drain electrode 30 ... Metal films 31a-31g, 131a-131g, 231a-231g ... Metal silicide layers 40a-40e ... Elements Isolation layer 40f ... opening 40g ... gate region 50 ... interlayer insulating films 60a, 60b ... con Transfected electrodes 70a, 70b ... wiring layer 80 ... protective layer 90a, 90b ... well contact layer, 100 ... semiconductor device

Claims (7)

Forming a first conductivity type well layer by injecting a first conductivity type impurity into a semiconductor substrate;
An element isolation layer forming step of forming an element isolation layer on the semiconductor substrate;
A first region forming step of forming a first region in which the well layer is exposed by partially removing the device isolation layer after performing the well layer forming step and the device isolation layer forming step; ,
Forming a gate oxide film on the well layer exposed in the first region, and forming a gate electrode through the gate oxide film; and
A first drift layer forming step of implanting a second conductivity type impurity into the well layer exposed in the first region using the gate electrode as a mask to form a second conductivity type first drift layer;
A second conductivity type impurity is implanted from the second region of the well layer exposed from the element isolation layer and away from the first region into the well layer below the element isolation layer. A second drift layer forming step of forming a conductive type second drift layer;
A drain electrode formation step of forming a second conductivity type drain electrode by injecting a second conductivity type impurity into the second drift layer of the second region;
A source electrode forming step of forming a second conductivity type source electrode by injecting a second conductivity type impurity into the first drift layer;
A metal silicide layer forming step of forming a metal silicide layer on each of the gate electrode, the source electrode, and the drain electrode;
A method for manufacturing a semiconductor device comprising: In the metal silicide layer forming step,
A metal layer is formed on the surface of the semiconductor substrate on which the element isolation layer, the gate electrode, the source electrode, and the drain electrode are formed without using a mask, and heat treatment is performed to thereby form the gate. The method of manufacturing a semiconductor device according to claim 1, wherein only the metal layer formed on the electrode, the source electrode, and the drain electrode is silicided to form the metal silicide layer. 3. The gate forming step, wherein the gate oxide film and the gate electrode are formed such that one end face of each of the gate oxide film and the gate electrode is in contact with a wall portion of the element isolation layer. The manufacturing method of the semiconductor device as described in any one of. 4. The manufacturing of a semiconductor device according to claim 1, further comprising an insulating sidewall forming step of forming an insulating sidewall covering the other end face of the gate oxide film and the gate electrode after the gate forming step. 5. Method. Before the first drift layer forming step, there is provided a body layer forming step of forming a first conductive type body layer by implanting a first conductive type impurity into the first region using the gate electrode as a mask. The method for manufacturing a semiconductor device according to claim 1. 6. The method of manufacturing a semiconductor device according to claim 1, wherein, in the gate formation step, the gate electrode is formed from the first region to a part of a region on the surface of the element isolation layer. 7. . A semiconductor substrate;
A first conductivity type well layer formed on the semiconductor substrate;
An element isolation layer formed in a part of the well layer;
A gate electrode formed in a first region exposed from the element isolation layer in the well layer via a gate oxide film;
A second conductivity type source electrode formed in the first region where the well layer is exposed;
A second conductivity type first drift layer formed in a region under the source electrode and having a second conductivity type impurity concentration lower than that of the source electrode;
A drain electrode of a second conductivity type formed in a second region of the well layer exposed from the element isolation layer and distant from the first region;
A second conductivity type second drift layer having a lower concentration of impurities of the second conductivity type than the drain electrode, formed from a region under the drain electrode to a region under the element isolation layer;
A metal silicide layer formed on each of the gate electrode, the source electrode, and the drain electrode;
Equipped with a,
One end face of the gate electrode is in contact with the side wall of the element isolation layer,
The source electrode, the semiconductor device that are provided at a position spaced laterally from the region in a portion formed under the element isolation layer of said second drift layer.

Images