JP6327098B2 - Method for manufacturing a quantum cascade laser - Google Patents

Description

  The present invention relates to a quantum cascade laser and a method of manufacturing a quantum cascade laser.

  Patent Document 1 discloses a quantum cascade laser having a buried heterostructure. Non-Patent Document 1 discloses electrical characteristics of a semi-insulating InP layer.

JP 2008-218915 A

O. Ostinelli etal., “Growth and characterization of iron-dopedsemi-insulating InP buffer layers for Al-free GaInP / GaInAs high electronmobility transistors”, Journal of Applied Physics, USA, American Institute of Physics, December 2010, Vol.108, p.114502.

  In a buried heterostructure quantum cascade laser, a semi-insulating InP layer is used as a buried region of a semiconductor mesa. Unlike the semiconductor laser for communication, the quantum cascade laser requires high voltage resistance in the buried region. In order to improve the voltage resistance of the buried region, the buried region is thickened. However, if the semiconductor mesa is also increased in accordance with the thickness of the buried region, side etching occurs in the semiconductor mesa when the semiconductor mesa is etched, and the mesa width becomes non-uniform.

  An object of one aspect of the present invention is to provide a quantum cascade laser having a structure capable of reducing the height of a semiconductor mesa and increasing the thickness of a buried region. Another aspect of the present invention aims to provide a method of manufacturing this quantum cascade laser.

  A quantum cascade laser according to one aspect of the present invention is provided on a main surface of a substrate and includes a semiconductor mesa including an active layer for the quantum cascade laser, and a method of the main surface of the substrate provided on the main surface of the substrate. A buried region including a first portion and a second portion arranged in order in a line direction; and a conductor region provided on the buried region in contact with the upper surface of the semiconductor mesa. The semiconductor mesa is embedded, the second part has an opening, the semiconductor mesa and the opening are arranged in order in the normal direction of the main surface of the substrate, the conductor region is located at the opening, and at the upper end of the second part The first width of the opening is larger than the second width of the opening at the lower end of the second portion, the width of the opening monotonously changes from the first width to the second width, and the conductor region is made of metal or semiconductor.

  A method of manufacturing a quantum cascade laser according to another aspect of the present invention includes a step of growing a semiconductor stack including an active layer for a quantum cascade laser on a main surface of a substrate, and forming a mask on the semiconductor stack. A step of forming a semiconductor mesa from the semiconductor stack by a reactive ion etching method using a mask, and growing a lower buried region in which the semiconductor mesa is embedded while supplying a semiconductor source gas and a halogen-based gas to the growth reactor And forming an upper buried region on the lower buried region and growing a buried region having an opening on the semiconductor mesa on the main surface, and removing the mask after growing the buried region. And exposing the upper surface of the semiconductor mesa to the opening, and forming a conductor region including at least one of a semiconductor and a metal in the opening of the buried region after removing the mask. The first portion of the thickness of embedding semiconductor mesa is substantially the same as the height of the upper surface of the semiconductor mesa, the conductor region is in contact with the upper surface of the semiconductor mesa.

  According to one aspect of the present invention, one aspect of the present invention can provide a quantum cascade laser having a structure capable of reducing the height of a semiconductor mesa and increasing the thickness of a buried region. Another aspect of the present invention can provide a method of manufacturing this quantum cascade laser.

1 is a cross-sectional view schematically showing a quantum cascade laser according to a first embodiment of the present invention. It is a flowchart which shows the method of manufacturing the quantum cascade laser which concerns on 1st Embodiment of this invention. It is sectional drawing which shows the product in the main processes of the method shown in FIG. 2 which concerns on 1st Embodiment of this invention. It is sectional drawing which shows the product in the main processes of the method shown in FIG. 2 which concerns on 1st Embodiment of this invention. It is a figure which shows the shape of the mask formed on the main surface of the semiconductor lamination on the board | substrate which concerns on the Example of this invention. It is a figure which shows typically the cross section of the embedding area | region grown so that a semiconductor mesa might be embedded, without adding the halogen-type gas which concerns on the Example of this invention. It is a figure which shows the relationship between the withstand voltage of the buried region which concerns on the Example of this invention, and the thickness of a buried region. It is sectional drawing which showed schematically the quantum cascade laser which concerns on 2nd Embodiment of this invention. It is a flowchart which shows the method of manufacturing the quantum cascade laser which concerns on 2nd Embodiment of this invention. It is sectional drawing which shows the product in the main processes of the method shown in FIG. 9 which concerns on 2nd Embodiment of this invention. It is sectional drawing which showed roughly the quantum cascade laser which concerns on 3rd Embodiment of this invention. It is a flowchart which shows the method of manufacturing the quantum cascade laser which concerns on 3rd Embodiment of this invention. It is sectional drawing which shows the product in the main processes of the method shown in FIG. 12 which concerns on 3rd Embodiment of this invention. It is sectional drawing which showed schematically the quantum cascade laser which concerns on a comparative example with the quantum cascade laser which concerns on 1st Embodiment of this invention.

  A quantum cascade laser according to one aspect of the present invention is provided on a main surface of a substrate and includes a semiconductor mesa including an active layer for the quantum cascade laser, and a method of the main surface of the substrate provided on the main surface of the substrate. A buried region including a first portion and a second portion arranged in order in a line direction; and a conductor region provided on the buried region in contact with the upper surface of the semiconductor mesa. The semiconductor mesa is embedded, the second part has an opening, the semiconductor mesa and the opening are arranged in order in the normal direction of the main surface of the substrate, the conductor region is located at the opening, and at the upper end of the second part The first width of the opening is larger than the second width of the opening at the lower end of the second portion, the width of the opening monotonously changes from the first width to the second width, and the conductor region is made of metal or semiconductor.

  According to this quantum cascade laser, in the buried region, the second portion is provided on the first portion, and the second portion is provided so that the thickness of the buried region exceeds the height of the semiconductor mesa. Can do. For this reason, the quantum cascade laser can provide a structure having a buried region with a thickness necessary for withstand voltage while suppressing the height of the semiconductor mesa so that the mesa width can be uniform. Further, the first width of the opening at the upper end of the second portion is larger than the second width of the opening at the lower end of the second portion, and the width of the opening changes monotonously from the first width to the second width. It is filled with a conductor region, and good heat dissipation performance can be provided through this conductor region.

  In the above quantum cascade laser, the semiconductor mesa preferably includes a diffraction grating above or below the active layer. According to this quantum cascade laser, it is excellent in monochromaticity and can oscillate in a single longitudinal mode.

  In the above quantum cascade laser, the height from the main surface of the substrate to the upper surface of the first portion of the buried region may be substantially the same as the height from the main surface of the substrate to the upper surface of the semiconductor mesa.

  In the above quantum cascade laser, the conductor region preferably includes a III-V group compound semiconductor. According to this quantum cascade laser, the semiconductor mesa is electrically connected to the upper electrode through the conductor region containing the III-V group compound semiconductor.

  In the above quantum cascade laser, the conductor region preferably contains Ti, Pt, and Au. According to this quantum cascade laser, the conductor region containing Ti, Pt, and Au electrically connects the semiconductor mesa and the upper electrode. In addition, this conductor region provides better heat dissipation performance.

  The quantum cascade laser further includes an intermediate portion having an intermediate opening between the first portion and the second portion of the buried region, and the width of the intermediate opening is substantially the same as the width of the semiconductor mesa. Also good.

  A method of manufacturing a quantum cascade laser according to another aspect of the present invention includes a step of growing a semiconductor stack including an active layer for a quantum cascade laser on a main surface of a substrate, and forming a mask on the semiconductor stack. A step of forming a semiconductor mesa from the semiconductor stack by a reactive ion etching method using a mask, and growing a lower buried region in which the semiconductor mesa is embedded while supplying a semiconductor source gas and a halogen-based gas to the growth reactor And forming an upper buried region on the lower buried region and growing a buried region having an opening on the semiconductor mesa on the main surface, and removing the mask after growing the buried region. And exposing the upper surface of the semiconductor mesa to the opening, and forming a conductor region including at least one of a semiconductor and a metal in the opening of the buried region after removing the mask. The first portion of the thickness of embedding semiconductor mesa is substantially the same as the height of the upper surface of the semiconductor mesa, the conductor region is in contact with the upper surface of the semiconductor mesa.

  According to the method for manufacturing the quantum cascade laser, the semiconductor source gas and the halogen-based gas are supplied to the growth furnace to grow the buried region. Therefore, a buried region thicker than the height of the semiconductor mesa is grown while suppressing abnormal growth in the vicinity of the upper edge of the semiconductor mesa. Furthermore, the semiconductor mesa and the conductor region are electrically coupled well by the opening.

  A quantum cascade laser and a method of manufacturing the quantum cascade laser according to some embodiments will be described below with reference to the drawings. In the following description, the same reference numerals are given to the same elements in the description of the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing a quantum cascade laser according to the first embodiment. In FIG. 1, a buried heterostructure (BH) type quantum cascade laser is shown as the quantum cascade laser. The quantum cascade laser 1 includes a substrate 10, a semiconductor mesa 20, a buried region 30, and a conductor region 40. In the present embodiment, the conductor region 40 includes an upper clad 41 and a contact layer 42.

  The substrate 10 is made of a group III-V compound semiconductor, and the group III-V compound semiconductor can be, for example, InP, GaAs, GaSb, InSb, or the like. The substrate 10 is doped with Sn or the like as an n-type dopant. The thickness of the substrate 10 is, for example, 100 μm. The semiconductor mesa 20 of the first embodiment has a mesa upper surface 20A and can include a part 10P of the substrate 10. In the semiconductor mesa 20, the active layer 12 for the quantum cascade laser and the cladding layer 13 are arranged in order on the height 20H of the semiconductor mesa 20 (part 10P of the substrate 10. From the upper surface 10A of the substrate 10). The distance to the mesa upper surface 20A of the semiconductor mesa 20 is, for example, 2 μm to 4 μm. In the present embodiment, the height 20H of the semiconductor mesa 20 is 4 μm. The mesa width 20W of the semiconductor mesa 20 is, for example, 3 μm to 10 μm. The semiconductor mesa 20 extends, for example, along the <011> direction of the III-V group semiconductor of the substrate 10. The semiconductor mesa 20 is provided on the main surface of the substrate 10, and this main surface has, for example, a (100) surface.

  In the quantum cascade laser 1, the semiconductor mesa 20 is embedded by the embedded region 30. The surface of the buried region 30 is constituted by an upper surface 30A, a first inclined surface 30C, and a second inclined surface 30D. The first inclined surface 30C and the second inclined surface 30D are inclined with respect to the upper surface 30A. The thickness 30H of the buried region 30 (distance from the upper surface 10A of the substrate 10 to the upper surface 30A of the buried region 30) is higher than the height 20H of the semiconductor mesa 20, for example, 5 μm to 10 μm. In this embodiment, the thickness 30H of the buried region 30 is 8 μm. For example, a (100) plane appears on the upper surface 30A of the buried region 30. In the buried region 30, for example, a (1-11B) plane appears on the first slope 30C and the second slope 30D. The buried region 30 includes a first portion 31, a second portion 32, and an intermediate portion 33 that are sequentially arranged in the normal direction of the main surface of the substrate 10. The first portion 31 has a first opening 34 reaching the main surface of the substrate 10, and the second portion 32 has a second opening (opening) 35 connected to the first opening 34. The intermediate portion 33 is located between the first portion 31 and the second portion 32 and has an intermediate opening 36. The first opening 34 is connected to the second opening 35 via the intermediate opening 36. The intermediate opening 36 may have substantially the same width as the width of the first opening 34 (the width of the upper surface of the semiconductor mesa 20). The semiconductor mesa 20 is located in the first opening 34, and the upper cladding 41 of the conductor region 40 is located in the second opening 35. The first opening 34, the intermediate opening 36, and the second opening 35 extend in the normal direction Nx of the main surface of the substrate 10.

  The first width W1 at the upper end 35A of the second opening 35 is larger than the second width W2 at the lower end 35B of the second opening 35, and the width of the second opening 35 monotonously changes from the first width W1 to the second width W2. doing. In the present embodiment, the second opening 35 gradually expands in the normal direction Nx of the main surface. The first inclined surface 30 </ b> C and the second inclined surface 30 </ b> D extend in the waveguide direction so as to define the second opening 35. The width of the second opening 35 is defined in a direction orthogonal to the extending direction Ax1 of the semiconductor mesa 20 and the normal direction Nx of the main surface of the substrate 10.

  According to the quantum cascade laser 1 of the first embodiment, in the embedded region 30, the second portion 32 is provided on the first portion 31, and the thickness of the embedded region 30 is the semiconductor mesa. It can be provided to exceed the height 20H of 20. For this reason, the quantum cascade laser 1 has a structure having the buried region 30 having a thickness necessary for withstand voltage while suppressing the height 20H of the semiconductor mesa 20 so as to obtain the uniformity of the mesa width 20W. Can provide. The first width W1 at the upper end 35A of the second opening 35 is larger than the second width W2 at the lower end 35B of the second opening 35, and the width of the second opening 35 is monotonous from the first width W1 to the second width W2. Therefore, the second opening 35 is filled with the conductor region 40, and good heat dissipation performance can be provided through the conductor region 40.

  The buried region 30 is made of, for example, a semi-insulating III-V group compound, and more specifically, can be made of, for example, semi-insulating InP. Semi-insulating InP includes a dopant such as Fe, and ferrocene is used as a raw material for the Fe doping. As the InP raw material, for example, a group III raw material trimethylindium and a group V raw material phosphine are used.

  In the semiconductor mesa 20, the active layer 12 has a superlattice structure, and the superlattice structure includes, for example, InGaAs and AlInAs. The active layer 12 has a laminated structure of several hundred layers including, for example, a light emitting part and an injection part. The thickness of the active layer 12 is 2 μm, for example. The clad layer 13 is made of a III-V group compound semiconductor and includes, for example, InP. The clad layer 13 includes a dopant such as Si, and can be made of n-type InP. The thickness of the cladding layer 13 is, for example, 500 nm. The thickness of the part 10P of the substrate 10 is, for example, 500 nm.

  An upper cladding 41 of the conductor region 40 is provided on the cladding layer 13 and the buried region 30. The conductor region 40 extends in the waveguide direction at the second opening 35. The upper clad 41 is made of, for example, a III-V compound semiconductor. The upper clad 41 includes a dopant such as Si, and can be made of n-type InP. Of the thickness of the upper clad 41, the thickness 41D from the upper surface 41A of the upper clad 41 to the upper surface 30A of the buried region 30 is, for example, 1 μm. A thickness 41H from the upper surface 41A of the upper cladding 41 to the mesa upper surface 20A of the semiconductor mesa 20 is, for example, 2 μm to 7 μm. The upper clad 41 is accommodated in the second opening 35. In this embodiment, the contact layer 42 of the conductor region 40 is provided on the upper clad 41. The contact layer 42 is made of, for example, a III-V compound semiconductor and includes, for example, InGaAs. The contact layer 42 includes a dopant such as Si, and can be made of n-type InGaAs. The contact layer 42 has a thickness of, for example, 500 nm.

  A passivation film 43 is provided on the contact layer 42. The passivation film 43 is made of, for example, a Si-based inorganic insulating layer such as SiN or SiON. The thickness of the passivation film 43 is, for example, 300 nm. An opening 44 is provided in the passivation film 43. The opening 44 is located on the semiconductor mesa 20.

  An upper electrode 45 is formed in the quantum cascade laser 1. The upper electrode 45 is made of, for example, a metal film, and the metal film has a laminated structure made of, for example, Ti, Pt, and Au. A thickness 45D from the upper surface 45A of the upper electrode 45 to the upper surface 42A of the passivation film 43 is, for example, 5 μm. The upper electrode 45 has a pad electrode 45E. In the quantum cascade laser 1, the lower electrode 46 is provided on the back surface 10 </ b> B of the substrate 10. The lower electrode 46 is made of, for example, AuGeNi, Ti, and Au. The lower electrode 46 can be formed by, for example, a vapor deposition method. The thickness of the lower electrode 46 is, for example, 1 μm.

  FIG. 2 is a flowchart showing a method of manufacturing the quantum cascade laser according to the first embodiment. 3 and 4 are cross-sectional views showing products in main steps of the method M1 shown in FIG. Subsequently, the manufacture of the quantum cascade laser 1 shown in FIG. 1 as a quantum cascade laser will be described. In this description, for ease of understanding, reference numerals of the components of the quantum cascade laser 1 shown in FIG. 1 are used where possible.

  First, for example, an InP wafer is prepared as the substrate 10. In step S <b> 1, the semiconductor stack 11 is grown on the substrate 10. As shown in part (a) of FIG. 3, in step S <b> 1, the semiconductor stack 11 is epitaxially grown on the main surface in the plane orientation (100) of the substrate 10. In this growth, the active layer 12 is grown on the main surface of the substrate 10 in step S1a. In the following description, for example, molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD) can be applied to crystal growth of the semiconductor layer. In step S1b, the cladding layer 13 is grown on the active layer 12. In step S <b> 1 c, the cap layer 14 is grown on the cladding layer 13. The cap layer 14 includes, for example, n-type InGaAs doped with Si. The thickness of the cap layer 14 is 10 nm, for example. In this embodiment, the active layer 12, the clad layer 13, and the cap layer 14 constitute the semiconductor stack 11.

In step S <b> 2, as shown in FIG. 3B, a mask 21 for forming the semiconductor mesa 20 is formed on the semiconductor stack 11. The mask 21 includes, for example, a Si-based inorganic insulating layer, and more specifically includes, for example, a SiN film, SiON, and SiO ₂ . In this embodiment, a SiN film is used for the mask 21, and this SiN film is formed by, for example, a plasma CVD method. The thickness of the SiN film is, for example, 500 nm.

  FIG. 5 is a diagram showing the shape of a mask formed on the main surface of the semiconductor stack on the substrate. In the figure, the X direction represents the <011> axis, and the Y direction represents the <0-1-1> axis. The mask 21 has, for example, a stripe pattern 21P. The stripe pattern 21P is transferred by, for example, photolithography, and extends in the X direction perpendicular to the plane orientation (0-1-1) of the substrate 10, for example. The stripe pattern 21P has a line width 21W of 5 μm, for example.

In step S3, as shown in part (c) of FIG. 3, the semiconductor stack 11 is etched to form the semiconductor mesa 20 by, for example, etching using an inductively coupled reactive ion etching (ICP-RIE) apparatus. . As an etching gas for etching, for example, a halogen gas such as Cl ₂ , SiCl ₄ , HI, HCl, BCl ₃ is used. In forming the semiconductor mesa 20, not only the semiconductor stack 11 but also the upper surface 10 </ b> A of the substrate 10 is etched, so that the semiconductor mesa 20 includes a part of the substrate 10, the active layer 12, the cladding layer 13, and the cap layer 14. Have.

In step S4, as shown in part (d) of FIG. 3, the buried region 30 is grown without removing the mask 21. In this buried growth, for example, a halogen-based gas is supplied to the growth furnace in addition to the semiconductor source gas to grow the buried region 30. As this halogen gas, for example, Cl _2, HCl, CBr _{4 and the} like can be used. When InP buried crystal growth is performed while adding a halogen-based gas, the buried region 30 thicker than the semiconductor mesa 20 can be formed while forming an opening on the mask 21 on the mesa upper surface 20A of the semiconductor mesa 20. Further, the addition of the halogen-based gas suppresses abnormal growth in the crystal growth related to the first side surface 20C and the second side surface 20D of the semiconductor mesa 20, and the opening on the mask 21 and the upper surface 30A of the buried region 30 are flat. (100) plane can be formed. Further, the addition of the halogen-based gas allows the buried region 30 to grow beyond the height of the semiconductor mesa 20 without forming a deposition on the mask 21. The addition of the halogen-based gas may be started when the first portion 31 is grown, or may be started when the intermediate portion 33 is grown on the first portion 31 or when the intermediate portion 33 is grown.

  FIG. 6 is a diagram schematically showing a cross section of a buried region grown so as to bury a semiconductor mesa without adding a halogen-based gas. If the halogen-based gas is not added, the buried region 30Y grows also on the mask 21 and the upper surface of the mask 21 is covered. According to this shape, the thickness of the buried region 30 cannot exceed the height of the semiconductor mesa 20. The effective thickness of the buried region 30Y is, for example, about the same as the height of the semiconductor mesa 20.

  In step S5, as shown in FIG. 3E, the mask 21 and the cap layer 14 are removed after the buried region 30 is grown. In this embodiment, the mask 21 is removed by, for example, hydrofluoric acid, and the cap layer 14 is removed by, for example, a mixed solution of phosphoric acid and hydrogen peroxide solution.

  In step S6, as shown in part (f) of FIG. 3, the conductor region 40 is grown. An upper cladding 41 is grown as a conductor region 40 on the cladding layer 13 and the buried region 30, and subsequently, a contact layer 42 is grown on the upper cladding 41. The contact layer 42 can be, for example, InGaAs.

  In step S7, as shown in FIG. 4A, a passivation film 43 is formed. The passivation film 43 is formed on the contact layer 42 using, for example, a plasma CVD method.

  In step S8, an opening 44 is formed in the passivation film 43 as shown in FIG. 4B. The opening 44 is located on the semiconductor mesa 20. For example, the opening 44 is formed in the passivation film 43 by etching using, for example, a hydrofluoric acid solution, using a mask formed by photolithography.

  In step S9, as shown in part (c) of FIG. 4, after the opening 44 is formed, the upper electrode 45 is formed in the opening 44. The upper electrode 45 is formed on the passivation film 43 by lift-off. Specifically, a metal film for the upper electrode 45 is formed by, for example, a vapor deposition method. After a lift-off mask having a pattern is produced by photolithography, the pad electrode 45E is formed by removing the mask.

  In step S10, as shown in FIG. 4D, the back surface 10B of the substrate 10 is polished. The thickness of the substrate 10 after polishing is, for example, 100 μm. The lower electrode 46 is formed on the polished back surface 10B by, for example, vapor deposition, and a substrate product is formed by these steps. The substrate product is then separated, for example by cleaving, to form a laser chip. Through the step S10, the quantum cascade laser 1 is completed.

FIG. 7 is a diagram showing the relationship between the withstand voltage of the buried region and the thickness of the buried region. The buried region 30 is made of Fe-doped InP. The concentration of the InP dopant is 1 × 10 ¹⁶ cm ⁻³ . In FIG. 7, the withstand voltage of the buried region 30 increases with the thickness 30H of the buried region 30. For example, when the thickness 30H is 5 μm, the buried region 30 has a withstand voltage of about 200V. For example, when the thickness 30H is 8 μm, the buried region 30 has a withstand voltage of about 450V.

  In the present embodiment, the semiconductor mesa 20 has a low height of, for example, 4 μm, while the buried region 30 can have a thickness of, for example, 8 μm or more independently of the height 20H of the semiconductor mesa 20. . When the height 20H of the semiconductor mesa 20 is about 4 μm, the etching variation of the height 20H in many semiconductor mesas 20 arranged in the wafer surface is, for example, within 0.2 μm. On the other hand, since the thickness 30H of the buried region 30 is a value larger than the height 20H of the semiconductor mesa 20, for example, 8 μm or more, it has a desired withstand voltage. Further, since the (100) plane of InP appears on the upper surface 30A of the buried region 30, the upper surface 30A of the buried region 30 is substantially flat, not only in terms of thickness, but also by this flatness. However, in the buried region 30, the concentration of the electric field is reduced and the dielectric breakdown voltage is increased.

  According to the method M1 for manufacturing the quantum cascade laser of the first embodiment, the semiconductor source gas and the halogen-based gas are supplied to the growth furnace to grow the buried region 30. Therefore, the buried region 30 that is thicker than the height of the semiconductor mesa 20 is grown while suppressing abnormal growth in the vicinity of the upper edge of the semiconductor mesa 20. Furthermore, the second opening 35 allows the semiconductor mesa 20 and the conductor region 40 to be electrically coupled well.

(Second Embodiment)
FIG. 8 is a cross-sectional view schematically showing a quantum cascade laser according to the second embodiment. Referring to FIG. 8, there is shown a BH type quantum cascade laser 2 that is different from the first embodiment in the shape of the upper electrode. The quantum cascade laser 2 includes a substrate 10 and a semiconductor mesa 20. The substrate 10 is made of, for example, InP having a (100) main surface to which Sn is added. The semiconductor mesa 20 is provided on the main surface of the substrate 10. The thickness of the substrate 10 is, for example, 100 μm. The semiconductor mesa 20 of the second embodiment includes a part 10P of the substrate 10 at the bottom thereof, and has an active layer 12, a cladding layer 13, and a cap layer 14 on the part 10P of the substrate 10. The height 20H of the semiconductor mesa 20 is, for example, 2 μm to 4 μm. The mesa width 20W of the semiconductor mesa 20 is, for example, 3 μm to 10 μm. The semiconductor mesa 20 is provided along the <011> direction perpendicular to the plane orientation (0-1-1) of the substrate 10, for example.

  The semiconductor mesa 20 is embedded by the embedded region 30 as in the first embodiment. Similar to the first embodiment, the thickness 30H of the buried region 30 is higher than the height 20H of the semiconductor mesa 20, and a (100) plane, for example, appears on the upper surface 30A of the buried region 30. Further, for example, the (11-1) B surface appears on the first inclined surface 30C and the second inclined surface 30D of the embedded region 30. The buried region 30 includes a first portion 31 and a second portion 32 that are sequentially arranged in the normal direction of the main surface of the substrate 10. In the second embodiment, unlike the first embodiment, a passivation film 43L is provided on the cap layer 14, the flat upper surface 30A of the buried region 30, the first inclined surface 30C, and the second inclined surface 30D. The passivation film 43L is made of, for example, a Si-based inorganic insulating layer such as SiN or SiON. The thickness of the passivation film 43L is, for example, 300 nm.

  In the passivation film 43L, an opening 44L is provided on the semiconductor mesa 20, and an upper electrode 45L as a conductor region 40 is provided on the cap layer 14 through the passivation film 43L and the opening 44L. The upper electrode 45L includes a metal film formed by, for example, a vapor deposition method, and has a laminated structure made of, for example, Ti, Pt, and Au. Of the thickness of the upper electrode 45L of the second embodiment, the thickness 45H from the upper surface 45A of the upper electrode 45 to the cap layer 14 is, for example, 8 μm to 11 μm. Of the thickness of the upper electrode 45L of the second embodiment, the thickness 45D from the upper surface 45A of the upper electrode 45 to the upper surface 42A of the passivation film 43L is, for example, 5 μm. The thickness 45H has a larger value than the thickness 45D. A pad electrode 45E is formed on the upper electrode 45L. A lower electrode 46 made of, for example, AuGeNi, Ti, and Au is provided on the back surface 10B of the substrate 10. The lower electrode 46 can be a deposited film, for example. The thickness of the lower electrode 46 is, for example, 1 μm.

  FIG. 9 is a flowchart showing a method of manufacturing the quantum cascade laser according to the second embodiment. FIG. 10 is a cross-sectional view showing products in the main steps of the method M2 shown in FIG. Another type of quantum cascade laser 2 is manufactured as the quantum cascade laser.

  In 2nd Embodiment, the product to the (d) part of FIG. 3 is obtained according to process S1-S4 similar to 1st Embodiment first. Subsequently, in the second embodiment, in step S25, as shown in part (a) of FIG. 10, after the growth of the buried region 30 in step S4, the mask 21 is removed by, for example, hydrofluoric acid. In the second embodiment, the cap layer 14 is not removed.

  In step S26, a passivation film 43L is formed as shown in part (b) of FIG. The passivation film 43L is formed on the cap layer 14 and the buried region 30 by using, for example, a plasma CVD method.

  In step S27, as shown in FIG. 10C, an opening 44L is formed in the passivation film 43L. The opening 44L is located on the semiconductor mesa 20. In step S27, a mask for the opening 44L is formed using, for example, a photolithography method. Next, the shape of the opening 44L is formed according to the pattern for the opening 44L by etching using a mask and etching with a hydrofluoric acid solution.

  In step S28, as shown in FIG. 10D, the upper electrode 45L of the conductor region 40 is formed after the opening 44L is formed. Specifically, the upper electrode 45L is formed on the passivation film 43L and the cap layer 14 by lift-off. A pad electrode 45E is formed on the upper electrode 45L.

  In step S29, as shown in part (e) of FIG. 10, a laser chip is formed by polishing the back surface 10B of the substrate 10, forming the lower electrode 46, and separating by cleaving. Through these steps, the quantum cascade laser 2 is completed.

  In the quantum cascade laser 2 of the second embodiment, the quantum cascade laser 2 has a high withstand voltage because the thickness 30H of the buried region 30 is large as in the quantum cascade laser 1 of the first embodiment. In addition, since the upper electrode 45L of the second embodiment is in contact with the semiconductor mesa 20, the quantum cascade laser 2 is more excellent in heat dissipation. In the quantum cascade laser 2, the pad electrode 45 </ b> E provided on the upper electrode 45 </ b> L draws the electrode to the forward tapered surface instead of the vertical surface, and thus is more difficult to disconnect.

(Third embodiment)
FIG. 11 is a cross-sectional view schematically showing a quantum cascade laser according to the third embodiment. In FIG. 11, a BH type distributed feedback (DFB) quantum cascade laser 3 is shown as a quantum cascade laser. The DFB quantum cascade laser 3 includes a substrate 10 and a semiconductor mesa 20. The DFB quantum cascade laser 3 includes a diffraction grating layer 15 and a planarization semiconductor layer 16 on the active layer 12 in the semiconductor mesa 20. The height 20H of the semiconductor mesa 20 is, for example, 3 μm to 4 μm. The mesa width 20W of the semiconductor mesa 20 is, for example, 3 μm to 10 μm. The semiconductor mesa 20 is provided, for example, along the <011> direction of the semiconductor of the substrate 10.

  The diffraction grating layer 15 has a diffraction grating structure. The diffraction grating layer 15 is made of, for example, a group III-V compound semiconductor, and specifically includes, for example, InGaAs or InGaAsP. The diffraction grating layer 15 can include a dopant such as Si, and can be made of n-type InGaAs or InGaAsP. The thickness of the diffraction grating layer 15 is, for example, 500 nm.

  The diffraction grating 15G is embedded with a semiconductor layer 16 for planarization. The semiconductor layer 16 is made of a III-V group compound semiconductor such as InP, and further includes a dopant such as Si, more specifically, n-type InP. The thickness 16H of the semiconductor layer 16 is, for example, 500 nm.

  The semiconductor mesa 20 of the DFB quantum cascade laser 3 is embedded by the embedded region 30 as in the first embodiment. Similar to the first embodiment, the thickness 30H of the buried region 30 is higher than the height 20H of the semiconductor mesa 20, and a (100) plane, for example, appears on the upper surface 30A of the buried region 30. In addition, for example, a (100) B surface appears on the first inclined surface 30 </ b> C and the second inclined surface 30 </ b> D of the embedded region 30. The buried region 30 includes a first portion 31 and a second portion 32 that are sequentially arranged in the normal direction of the main surface of the substrate 10.

  A conductor region 40 is provided on the semiconductor layer 16 and the buried region 30. The conductor region 40 includes an upper clad 41 and a contact layer 42. The upper clad 41 can be made of, for example, n-type InP. Of the thickness of the upper clad 41, the thickness 40D from the upper surface 40A of the upper clad 41 to the upper surface 30A of the buried region 30 is, for example, 1 μm. A thickness 41H from the upper surface 40A of the upper clad 41 to the mesa upper surface 20A of the semiconductor mesa 20 is, for example, 2 μm to 7 μm. The contact layer 42 includes, for example, a dopant such as Si, and can be made of n-type InGaAs. The contact layer 42 has a thickness of, for example, 500 nm. A passivation film 43 is provided on the contact layer 42. The passivation film 43 is made of, for example, a Si-based inorganic insulating layer such as SiN or SiON. The thickness of the passivation film 43 is, for example, 300 nm.

  In the passivation film 43, an opening 44 is provided on the semiconductor mesa 20, and an upper electrode 45 is provided on the cap layer 14 through the passivation film 43 and the opening 44. The upper electrode 45 includes a metal film formed by, for example, a vapor deposition method, and has a laminated structure made of, for example, Ti, Pt, and Au. A pad electrode 45E is formed on the upper electrode 45. A lower electrode 46 made of, for example, AuGeNi, Ti, and Au is provided on the back surface 10B of the substrate 10. The lower electrode 46 can be a deposited film, for example. The thickness of the lower electrode 46 is, for example, 1 μm. In the DFB quantum cascade laser 3 of the third embodiment, since the thickness of the buried layer that is an insulator can be made larger than the mesa height, the variation in the insulation performance in the buried region 30 is further reduced. A thickness 45D from the upper surface 45A of the upper electrode 45 of the third embodiment to the upper surface 42A of the passivation film 43 is, for example, 5 μm. The semiconductor mesa 20 of the third embodiment can be applied to the semiconductor mesa 20 of the first embodiment.

  FIG. 12 is a flowchart showing a method of manufacturing the quantum cascade laser according to the third embodiment. FIG. 13 is a cross-sectional view showing a cross-sectional view showing a product in the main process of the method M3 shown in FIG. In FIG. 13, an XYZ coordinate system is drawn, and the direction of the product is indicated by the XYZ coordinate system. In the third embodiment, a DFB quantum cascade laser 3 is manufactured as a quantum cascade laser.

  In step S31 of the method M3 of the third embodiment, the semiconductor stack 11 is grown. As shown in part (a) of FIG. 13, in step S <b> 31 a, the active layer 12 is grown on the main surface of the surface orientation (100) of the substrate 10. A semiconductor layer 17 for the diffraction grating is grown on the active layer 12. The semiconductor layer 17 for the diffraction grating is made of a III-V group compound semiconductor and includes, for example, InGaAs or InGaAsP. The semiconductor layer 17 for the diffraction grating comprises a dopant such as Si, and can be n-type InGaAs or InGaAsP. The thickness of the semiconductor layer 17 for the diffraction grating is, for example, 500 nm.

In step S31b, as shown in part (b) of FIG. 13, the diffraction grating mask 18 for forming the diffraction grating is formed on the semiconductor layer 17 for the diffraction grating. The diffraction grating mask 18 includes, for example, a Si-based inorganic insulating layer, and more specifically includes, for example, a SiN film, SiO ₂ , and SiON. For example, the SiN film is formed by a plasma CVD method. The thickness of the SiN film is, for example, 100 nm. The diffraction grating mask 18 has a diffraction grating pattern (pattern for the diffraction grating 15G) transferred by, for example, a photolithography method. The diffraction grating pattern is formed such that the diffraction grating 15G extends in a direction parallel to the plane orientation (0-1-1) of the substrate 10, for example. The diffraction grating pattern 16P can be, for example, a line and space pattern with a line width 15W of 3 μm to 10 μm.

  In step S31c, a diffraction grating 15G is formed as shown in part (c) of FIG. An etching gas such as a halogen gas is supplied into the ICP-RIE apparatus, and a diffraction grating 15G is formed in the semiconductor layer 17 for the diffraction grating by etching. The height 15H of the diffraction grating 15G is, for example, 50 to 400 nm.

  In step S31d, as shown in FIG. 13D, the semiconductor layer 16 is grown so as to fill the diffraction grating 15G. In step S <b> 31 d, the cap layer 14 is further grown on the semiconductor layer 16. The cap layer 14 is made of, for example, a group III-V compound semiconductor, and specifically includes InGaAs or the like. The cap layer 14 includes a dopant such as Si, and can be made of n-type InGaAs or the like. The thickness of the cap layer 14 is 10 nm, for example.

  In the manufacturing method of the third embodiment, after the step S31, the same manufacturing steps as those after the step S2 of the method M1 shown in FIG. 2 in the first embodiment can be applied to the manufacture of the DFB quantum cascade laser 3. In step S10, the substrate product is separated by cleaving or the like to form a laser chip. After these steps, as shown in FIG. 13E, the DFB quantum cascade laser 3 is completed.

  Since the DFB quantum cascade laser 3 of the third embodiment includes the diffraction grating 15G, the DFB quantum cascade laser 3 is excellent in monochromaticity and can oscillate in a single longitudinal mode. In the present embodiment, the diffraction grating 15G is formed on the active layer 12, but may be formed below the active layer.

  FIG. 14 is a cross-sectional view schematically showing a quantum cascade laser according to a comparative example together with the quantum cascade laser according to the first embodiment. Part (a) of FIG. 14 shows a cross section of the quantum cascade laser according to the comparative example, and part (b) of FIG. 14 shows a cross section of the quantum cascade laser according to the first embodiment. In FIG. 14A, a high resistance buried (SIBH) type quantum cascade laser 4 is shown as a quantum cascade laser. The quantum cascade laser 4 includes a substrate 10 made of InP doped with Sn, and a semiconductor mesa 20M on the main surface of the plane orientation (100) of the substrate 10. The thickness of the substrate 10 is about 100 μm. The semiconductor mesa 20 of the comparative example includes a part 10P of the substrate 10 at the lowermost part, and has an active layer 12M, a cladding layer 13M, and a cap layer 14M on the part 10P of the substrate 10. The thickness of the part 10P of the substrate 10 is about 500 nm. The height 20H of the semiconductor mesa 20M is about 7 μm. The mesa width 20W of the semiconductor mesa 20M is about 5 μm. The semiconductor mesa 20M is provided along the <011> direction perpendicular to the plane orientation (0-1-1) of the substrate 10.

  The quantum cascade laser 4 includes an embedded region 30M, and the semiconductor mesa 20M is embedded by the embedded region 30M. The thickness 30H of the buried region 30M is substantially equal to the height 20H of the semiconductor mesa 20M and is about 7 μm. The buried region 30M is made of a semi-insulating III-V group compound layer. The semi-insulating III-V compound layer is made of semi-insulating InP doped with Fe. A passivation film 43M is provided on the cap layer 14M and the buried region 30M. The thickness of the passivation film 43 is about 300 nm. The passivation film 43 is provided with an opening 44M. The opening 44M is located on the semiconductor mesa 20. An upper electrode 45M is formed in the quantum cascade laser 4. The thickness of the upper electrode 45M is about 500 nm. The upper electrode 45M has a pad electrode 45E. A lower electrode 46M is provided. The thickness of the lower electrode 46M is about 1 μm.

  In this comparative example, since the thickness 30H of the buried region 30 is about 7 μm or more, it can have high voltage tolerance in the buried region 30M required when the quantum cascade laser is driven. However, in this comparative example, the height 20H of the semiconductor mesa 20M is also approximately the same as the thickness 30H of the buried region 30M. Therefore, in the semiconductor chips of many quantum cascade lasers on the wafer for manufacturing the quantum cascade laser, The variation in the wafer with the height 20H of the mesa 20M is about 0.5 μm or more. For this reason, the fluctuation of the insulation performance in the produced quantum cascade laser becomes large, and the yield of the semiconductor chip is lowered.

  In the quantum cascade lasers 1, 2, and 3 of the embodiment, the height 20H of the semiconductor mesa 20 is made lower than the thickness 30H of the buried region 30. The buried region 30 includes a first portion 31 for embedding the semiconductor mesa 20 and a second portion 32 having a second opening 35 located on the mesa upper surface 20A of the semiconductor mesa 20. The second opening 35 of the second portion 32 includes a portion having a width that widens in the direction from the substrate 10 to the conductor region 40. The second opening 35 is filled with a conductor region, and good heat dissipation performance can be provided through this conductor region.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

  According to the present embodiment, it is possible to provide a quantum cascade laser having a structure capable of reducing the height of the semiconductor mesa and increasing the thickness of the buried region. In addition, a method for manufacturing the quantum cascade laser can be provided.

DESCRIPTION OF SYMBOLS 1 ... Quantum cascade laser, 10 ... Board | substrate, 11 ... Semiconductor laminated layer, 12 ... Active layer, 13 ... Cladding layer, 20 ... Semiconductor mesa, 20A ... Mesa upper surface (upper surface of semiconductor mesa), 30 ... Buried region, 31 ... 1st 1 part, 32 ... 2nd part, 34 ... 1st opening, 35 ... 2nd opening (opening), 35A ... upper end, 35B ... lower end, 40 ... conductor area | region, W1 ... 1st width, W2 ... 2nd width.

Claims (2)

A method of manufacturing a quantum cascade laser comprising:
Growing a semiconductor stack including an active layer for the quantum cascade laser on a main surface of the substrate;
Forming a mask on the semiconductor stack;
Forming a semiconductor mesa from the semiconductor stack by a reactive ion etching method using the mask;
While supplying a semiconductor source gas and a halogen-based gas to a growth furnace, a first portion for embedding the semiconductor mesa is grown and a second portion is grown on the first portion, and an opening is formed on the semiconductor mesa. Forming a buried region on the main surface;
Removing the mask and exposing an upper surface of a semiconductor mesa in the opening after growing the buried region;
Forming a conductor region including at least one of a semiconductor and a metal in the opening of the buried region after removing the mask;
With
The thickness of the first portion embedding the semiconductor mesa is substantially the same as the height to the upper surface of the semiconductor mesa,
The method of manufacturing a quantum cascade laser, wherein the conductor region is in contact with the upper surface of the semiconductor mesa. In the step of forming a buried region on the main surface, after growing the first portion and before growing the second portion, further growing an intermediate portion on the first portion;
The intermediate portion has an intermediate opening on the upper surface of the semiconductor mesa by removing the mask;
The method of manufacturing a quantum cascade laser according to claim 1, wherein a width of the intermediate opening is substantially the same as a width of the semiconductor mesa.

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