JP6313500B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

As a semiconductor device used for power converters such as inverters, MOS (Metal-Oxide-Se)
miconductor) transistors, IGBTs (Insulated Gate Bipolar Transistors), diodes, and the like. Diode is IG for reflux
Used in antiparallel with BT. Therefore, the diode in this case is called FWD (Free W
heeling Diode).

In addition to improving the characteristics of MOS transistors and IGBTs, FW
It is important to improve the characteristics of D, for example, the electrical characteristics such as switching time, on-voltage and leakage current.

JP 2010-098189 A

  Embodiments of the present invention provide a semiconductor device capable of improving electrical characteristics.

  A plurality of first semiconductor layers of a first conductivity type provided between the first electrode, the second electrode, the first electrode and the second electrode, and in ohmic contact with the first electrode; At least one first region in contact with the electrode and the first semiconductor layer, and partially located between the adjacent first semiconductor layers, in Schottky contact with the first electrode, and with the first electrode A second semiconductor layer of a first conductivity type provided between the second electrode and an effective impurity concentration provided between the second semiconductor layer and the second electrode; A third semiconductor layer of a first conductivity type lower than the effective impurity concentration of the first conductivity type, and a second conductivity type second semiconductor layer provided between the third semiconductor layer and the second electrode and in contact with the second electrode. 4 provided between the semiconductor layer, the third semiconductor layer, and the second electrode, and in contact with the second electrode. A fifth semiconductor layer of a second conductivity type having an effective impurity concentration higher than an effective impurity concentration of the fourth semiconductor layer, and at least one or more first electrodes in contact with the second electrode and the fifth semiconductor layer. The width of the first semiconductor layer is longer than the width of the fifth semiconductor layer in a direction parallel to the top surface of the first electrode, and the total area of the first region is A semiconductor device larger than the total area of the second regions.

FIG. 1A is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment, and FIG. 1B is a schematic plan view excluding the cathode electrode along the line AA ′ shown in FIG. It is. It is a graph which illustrates the ohmic contact and Schottky contact of a metal and a semiconductor. FIG. 4 is an enlarged view illustrating the operation of a region B shown in FIG. 1A in the semiconductor device according to the first embodiment. FIG. 4A and FIG. 4B are diagrams illustrating energy bands in the semiconductor device according to the first embodiment. FIG. 6 is a schematic view illustrating the impurity concentration distribution of the semiconductor device according to the first embodiment and the carrier distribution when a forward bias is applied. 6 is a graph illustrating the impurity concentration distribution of the semiconductor device according to the first embodiment and the carrier distribution in a transient state when a reverse bias is applied. FIG. It is a graph which illustrates the calculation result of the switching current, switching voltage, and switching characteristic from 200 ampere (A) steady conduction current of the semiconductor device concerning a 1st embodiment and a comparative example mentioned below. FIG. 8A is a graph illustrating the relationship between the switching loss and the forward voltage of the semiconductor device according to the first embodiment, and FIG. 8B is a graph illustrating the temperature characteristic of the leakage current. is there FIG. 9A is a schematic cross-sectional view illustrating a semiconductor device according to a modification of the first embodiment. FIG. 9B is a diagram excluding the cathode electrode taken along the line AA ′ shown in FIG. It is a plane schematic diagram. 6 is a cross-sectional view illustrating a semiconductor device according to a comparative example of the first embodiment; FIG. FIG. 11A is a graph illustrating the impurity concentration distribution of the semiconductor device according to the comparative example of the first embodiment and the carrier distribution when a forward bias is applied, and FIG. It is a graph which illustrates the carrier distribution of the transient state at the time of applying a reverse bias. FIG. 6 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. FIG. 13A is a schematic plan view of the semiconductor device according to the second embodiment, excluding the anode electrode taken along line AA ′ shown in FIG. 12, and FIG. 13B is a line BB ′ shown in FIG. It is a plane schematic diagram except the cathode electrode by. FIG. 6 is a graph illustrating an impurity concentration distribution of a semiconductor device according to a second embodiment and a carrier distribution when a forward bias is applied. In the semiconductor device concerning 2nd Embodiment and a comparative example, it is a graph which illustrates the calculation result of the carrier distribution in the steady conduction state of about 100 A / cm < ² > when a forward bias is applied, and a horizontal axis is a semiconductor The position in the thickness direction of the layer is shown, and the vertical axis shows the carrier concentration (cm ⁻³ ). FIG. 16A is a graph illustrating the switching current of the semiconductor device according to the second embodiment, and FIG. 16B illustrates the switching current of the semiconductor device according to the comparative example of the first embodiment. FIG. It is a cross-sectional schematic diagram which illustrates the semiconductor device which concerns on the 1st modification of 2nd Embodiment. FIG. 18A is a schematic plan view of the semiconductor device according to the first modification of the second embodiment, excluding the anode electrode taken along the line AA ′ shown in FIG. 17, and FIG. It is a plane schematic diagram except the cathode electrode by BB 'line shown in FIG. It is a cross-sectional schematic diagram which illustrates the semiconductor device which concerns on the 2nd modification of 2nd Embodiment. FIG. 20A is a schematic plan view of the semiconductor device according to the second modification of the second embodiment, excluding the anode electrode taken along line AA ′ shown in FIG. 19, and FIG. It is a plane schematic diagram except the cathode electrode by BB 'line shown in FIG. It is a cross-sectional schematic diagram which illustrates the semiconductor device which concerns on the 3rd modification of 2nd Embodiment. FIG. 22A is a schematic view illustrating a semiconductor device according to a third embodiment, FIG. 22A is a schematic cross-sectional view, and FIG. 22B is a schematic plan view at the position of the BB ′ line in FIG. It is. FIG. 10 is a schematic cross-sectional view illustrating the operation of the semiconductor device according to the third embodiment. FIG. 24A is a schematic view illustrating a semiconductor device according to a first modification of the third embodiment, FIG. 24A is a schematic cross-sectional view, and FIG. 24B is the position of the BB ′ line in FIG. FIG. FIG. 15 is a schematic cross-sectional view illustrating the operation of the semiconductor device according to the first modification example of the third embodiment. FIG. 26A is a schematic diagram illustrating a semiconductor device according to a second modification and a third modification of the third embodiment, FIG. 26A is a schematic cross-sectional view of the second modification, and FIG. It is a cross-sectional schematic diagram of 3 modifications. It is a graph which illustrates the switching current and voltage of a semiconductor device concerning a 3rd embodiment. FIG. 28A is a schematic cross-sectional view illustrating the semiconductor device according to the first example of the fourth embodiment, and FIG. 28B illustrates the semiconductor device according to the second example of the fourth embodiment. It is a cross-sectional schematic diagram. FIG. 29 is a schematic cross-sectional view illustrating the semiconductor device according to the first example of the fifth embodiment. FIG. 30A is a schematic cross-sectional view illustrating a semiconductor device according to a second example of the fifth embodiment, and FIG. 30B illustrates a semiconductor device according to the third example of the fifth embodiment. It is a cross-sectional schematic diagram. FIG. 31 is a schematic perspective view illustrating a semiconductor device according to a fourth example of the fifth embodiment. FIG. 32A is a schematic cross-sectional view illustrating a semiconductor device according to the sixth embodiment, and FIG. 32B is a graph showing an impurity concentration profile of the semiconductor device according to the sixth embodiment. FIG. 33A is a schematic perspective view illustrating the semiconductor device according to the first example of the seventh embodiment, and FIG. 33B illustrates the semiconductor device according to the second example of the seventh embodiment. It is a perspective schematic diagram. FIG. 34 is a schematic cross-sectional view illustrating a semiconductor device according to the eighth embodiment. FIG. 35 is a schematic plan view of the semiconductor device according to the ninth embodiment. It is a cross-sectional schematic diagram which illustrates the semiconductor device which concerns on 10th Embodiment. FIG. 37A is a schematic plan view of the semiconductor device according to the tenth embodiment, excluding the gate electrode, the source electrode, and the insulating film along the line AA ′ shown in FIG. 36, and FIG. FIG. 36 is a schematic plan view excluding a drain electrode taken along line BB ′ shown in FIG. FIG. 34 is a schematic cross-sectional view illustrating a semiconductor device according to a first modification and a second modification of the tenth embodiment. FIG. 39A is a schematic plan view of the semiconductor device according to the first modification of the tenth embodiment, excluding the gate electrode, the source electrode, and the insulating film along the line AA ′ shown in FIG. FIG. 39B is a schematic plan view excluding the drain electrode along the line BB ′ shown in FIG. FIG. 40A is a schematic plan view of the semiconductor device according to the second modification of the tenth embodiment, excluding the gate electrode, the source electrode, and the insulating film along the line AA ′ shown in FIG. FIG. 39B is a schematic plan view excluding the drain electrode along the line BB ′ shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate. The example of each figure is an example, and the example which combined each figure as much as possible technically is also included in this embodiment. Moreover, in each figure, an anode electrode and a cathode electrode may not be displayed for convenience of explanation.

(First embodiment)
First, the first embodiment will be described.

FIG. 1A is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment.
) Is a schematic plan view excluding the cathode electrode taken along line AA ′ shown in FIG.

As shown in FIG. 1A, the semiconductor device 1 according to this embodiment includes a cathode electrode 11 (first electrode), an n ⁺ cathode layer 12 (first semiconductor layer), and an n cathode layer 13 (second semiconductor). layer),
An n base layer 14 (third semiconductor layer), a p ⁺ anode layer 15 (fourth semiconductor layer), and an anode electrode 16 (second electrode) are provided. The n ⁺ cathode layer 12, the n cathode layer 13, the n base layer 14, and the p ⁺ anode layer 15 are provided between the cathode electrode 11 and the anode electrode 16. The semiconductor device 1 is a diode, for example. n ⁺ cathode layer 12, n
The cathode layer 13, the n base layer 14 and the p ⁺ anode layer 15 are collectively referred to as a semiconductor layer 10.

The cathode electrode 11 contains a metal, for example, aluminum. The shape of the cathode electrode 11 is, for example, a plate shape. On the cathode electrode 11, for example, on the plate surface of the cathode electrode 11, a plurality of n ⁺ cathode layers 12 are arranged separately from each other.

As shown in FIG. 1B, each n ⁺ cathode layer 12 has, for example, a rectangular parallelepiped shape extending in one direction on the cathode electrode 11. A region 11a (first region) in contact with each n ⁺ cathode layer 12 in the cathode electrode 11 also extends in one direction. For example, the n ⁺ cathode layer 12 is located in a region immediately above the region 11a, that is, in a region directly above the region 11a. In this case, the width Wn of the ^{n +} cathode layer 12, i.e., the ^{n +} cathode layer 12
The length in the direction orthogonal to the direction in which the region extends is equal to the width Wn of the region 11a. The width Wn is, for example, 100 micrometers (μm) or less. Each n ⁺ cathode layer 12 thickness, i.e., the length between the upper and lower ends of each n ⁺ cathode layer 12 is, for example, 5 micrometers (mu
m) or less.

The interval between each n ⁺ cathode layer 12 and each region 11a is, for example, 50 micrometers (μ
m) or less. The n ⁺ cathode layer 12 includes a semiconductor, for example, silicon. n ⁺
The cathode layer 12 contains an impurity serving as a donor, for example, phosphorus. The conductivity type of the n ⁺ cathode layer 12 is n-type (first conductivity type). The effective concentration of impurities on the surface of the n ⁺ cathode layer 12, that is, the surface impurity concentration is higher than 3 × 10 ¹⁷ cm ⁻³ , for example, 1 × 10 ¹⁹ cm ⁻³ or more.

In this specification, “effective impurity concentration” refers to the concentration of impurities that contribute to the conductivity of a semiconductor material. For example, the semiconductor material contains both impurities that serve as donors and impurities that serve as acceptors. In some cases, the concentration is the amount of the activated impurity minus the offset between the donor and acceptor. Hereinafter, the effective impurity concentration is also simply referred to as impurity concentration.

The cathode electrode 11 and the n ⁺ cathode layer 12 form an ohmic contact. The ohmic contact refers to a contact between a metal and a semiconductor having a contact resistance that is negligibly small compared to the series resistance due to the resistance of the semiconductor bulk. The ohmic contact is a non-rectifying contact.

FIG. 2 is a graph illustrating ohmic contact and Schottky contact between a metal and a semiconductor. The vertical axis indicates the specific contact resistance (Ω · cm ² ), and the horizontal axis indicates the impurity concentration (10 ⁻¹⁰ cm
^3/2 and cm ⁻³ ). Solid lines L1, L2, L3, and L4 indicate theoretical values, and circles and squares indicate experimental values.

As shown in FIG. 2, when the impurity concentration in the semiconductor is higher than 3 × 10 ¹⁷ cm ⁻³ , the metal and the semiconductor are in ohmic contact. In the semiconductor device 1, since the effective surface impurity concentration in the n ⁺ cathode layer 12 is higher than 3 × 10 ¹⁷ cm ⁻³ , the cathode electrode 11 and the n ⁺ cathode layer 12 are in ohmic contact.

The n cathode layer 13 is disposed on the n ⁺ cathode layer 12 and the cathode electrode 11.
Therefore, the n cathode layer 13 includes a portion 13 a disposed on the n ⁺ cathode layer 12 and a portion 13 b in contact with the cathode electrode 11. Portion 13a is n ⁺ cathode layer 1
2 and the anode electrode 16. The portion 13 b is provided between the cathode electrode 11 and the anode electrode 16. The thickness of the portion in contact with the cathode electrode 11 in the n cathode layer 13 is several to several tens of micrometers (μm), for example, 1 to 20 micrometers (μm), or 0.5 to 20 μm.

The n cathode layer 13 includes a semiconductor, for example, silicon. The n cathode layer 13 contains an impurity serving as a donor, for example, phosphorus. The conductivity type of the n cathode layer 13 is
n-type. The effective surface impurity concentration in the n cathode layer 13 is n ⁺ cathode layer 1.
2 is lower than the effective surface impurity concentration. Cathode electrode 11 of n cathode layer 13
The surface concentration of phosphorus in the portion in contact with the surface is, for example, 3 × 10 ¹⁷ cm ⁻³ or less. The cathode electrode 11 and the n cathode layer 13 are in Schottky contact. The Schottky contact is a contact between a metal and a semiconductor and has a Schottky barrier between the metal and the semiconductor. The Schottky contact is a rectifying contact.

As shown in FIG. 2, the effective surface impurity concentration in the semiconductor is 3 × 10 ¹⁷ cm ^−.
In the case of ³ or less, the metal and the semiconductor are in Schottky contact. In this embodiment,
Since the effective surface impurity concentration in the n cathode layer 13 is 3 × 10 ¹⁷ cm ⁻³ or less, the cathode electrode 11 and the n cathode layer 13 are in Schottky contact.

The n base layer 14 is disposed on the n cathode layer 13. The n base layer 14 is provided between the n cathode layer 13 and the anode electrode 16. The thickness of the n base layer 14 is, for example, 10 to 500 micrometers (μm), and is designed according to the breakdown voltage of the element. n
The base layer 14 includes a semiconductor, for example, silicon. The n base layer 14 contains an impurity serving as a donor, for example, phosphorus. The conductivity type of the n base layer 14 is n type. The effective impurity concentration in the n base layer 14 is lower than the effective impurity concentration in the n cathode layer 13.

The p ⁺ anode layer 15 is disposed on the n base layer 14. p ⁺ anode layer 15 is
It is provided between the n base layer 14 and the anode electrode 16. The thickness of the p ⁺ anode layer 15 is several to several tens of micrometers (μm), for example, 1 to 20 micrometers (μm).
It is. The p ⁺ anode layer 15 includes a semiconductor, for example, silicon. The p ⁺ anode layer 15 contains an impurity serving as an acceptor, for example, boron. The conductivity type of the p ⁺ anode layer 15 is p-type (second conductivity type). The effective impurity surface concentration in the p ⁺ anode layer 15 is higher than 3 × 10 ¹⁷ cm ⁻³ , for example, 1 × 10 ¹⁹ cm ^−3.
That's it.

The anode electrode 16 is disposed on the p ⁺ anode layer 15. The anode electrode 16 is
Contains metal, for example, aluminum. The shape of the anode electrode 16 is, for example, a plate shape. Since the anode electrode 16 contains aluminum and the effective impurity concentration in the p ⁺ anode layer 15 is higher than 3 × 10 ¹⁷ cm ⁻³ , the anode electrode 16 and the p ⁺ anode layer 15 are in ohmic contact. ing.

In the semiconductor device 1, the configuration shown in FIGS. 1A and 1B is repeatedly arranged.

Next, the operation of the semiconductor device 1 according to this embodiment will be described.
A forward bias, that is, a voltage having the anode electrode 16 side as a positive electrode is applied to the cathode electrode 11 between the anode electrode 16 and the cathode electrode 11. n cathode layer 13
Electrons are injected into the n base layer 14 from the side. Holes are injected into the n base layer 14 from the p anode layer 15 side. Thereby, the anode electrode 16 and the cathode electrode 11 are in a conductive state.

FIG. 3 is an enlarged view illustrating the operation of the region B shown in FIG. 1A in the semiconductor device according to the first embodiment.

FIG. 4A is a diagram illustrating energy bands of the cathode electrode 11 and the n cathode layer 13 in the semiconductor device according to the first embodiment, and FIG. 4B is an n ⁺ cathode layer 12.
4 is a diagram illustrating an energy band of n cathode layer 13. FIG.

As shown in FIG. 3, holes are injected from the p ⁺ anode layer 15 into the n base layer 14. Thereby, a hole current 19 is formed.

As shown in FIG. 4A, the Fermi level 42 in the n cathode layer 13 has a valence band V
Between B and conduction band CB, it is located on the conduction band CB side. A Schottky barrier is formed between the cathode electrode 11 and the n cathode layer 13. However, it is not an energy barrier for holes. Accordingly, holes flow into the cathode electrode 11 via the n base layer 14 and the n cathode layer 13 to form a hole current 19.

As shown in FIG. 4 (b), the n cathode layer 13 corresponds to the holes 13 h of the n cathode layer 13.
And n ⁺ cathode layer 12 is an energy barrier. Therefore, the hole 13h is n ⁺
It is difficult to flow into the cathode layer 12. Therefore, the holes in the n cathode layer 13 move on the n ⁺ cathode layer 12 in the lateral direction, that is, in the other direction orthogonal to one direction in a plane parallel to the plate surface of the cathode electrode 11.

Due to the movement of holes in the n cathode layer 13 in the other direction, the portion 13 a disposed on the n ⁺ cathode layer 12 becomes a positive electrode with respect to the portion 13 b in contact with the cathode electrode 11, that is, the cathode electrode 11. To be biased.

The bias formed between the portion 13a and the cathode electrode 11, the energy barrier between the n cathode layer 13 and the n ⁺ cathode layer 12 in the n ⁺ cathode layer 12 on the lower. As a result, electrons are injected from the n ⁺ cathode layer 12 into the n cathode layer 13. The electrons injected into the n cathode layer 13 form an electron current 18.

FIG. 5 is a schematic view illustrating the impurity concentration distribution of the semiconductor device according to the first embodiment and the carrier distribution when a forward bias is applied. The vertical axis indicates the position of the semiconductor layer in the thickness direction. The horizontal axis indicates the impurity concentration and the carrier concentration.

As shown in FIG. 5, the impurity concentration in the n ⁺ cathode layer 12 and the p ⁺ anode layer 15 is higher than the impurity concentration in the n cathode layer 13 and the n base layer 14. Impurity concentration is
In the n ⁺ cathode layer 12, the n cathode layer 13 and the n base layer 14, for example, the concentration of phosphorus, and in the p ⁺ anode layer 15, for example, the concentration of boron. The impurity concentration in the n ⁺ cathode layer 12 is highest at the lower end of the ^{n +} cathode layer 12. The impurity concentration in the p ⁺ anode layer 15 is highest at the top of the ^{p +} anode layer 15.

The impurity concentration of the n cathode layer 13 is an intermediate value between the impurity concentrations of the n ⁺ cathode layer 12 and the n base layer 14. The impurity concentration in the arrangement portion 13a on the n ⁺ cathode layer 12 is the highest portion in contact with the n ⁺ cathode layer 12. The impurity concentration in the portion 13b in contact with the cathode electrode 11 is highest at the lower end.

  The impurity concentration of the n base layer 14 is a substantially constant value except that the impurity concentration rapidly decreases at the upper end.

As shown in FIG. 5, the carrier distribution 20 when a forward bias is applied is represented by the n base layer 14.
, The impurity concentration of the n base layer 14 is higher than that of the n ⁺ cathode layer 12 and p ^+.
The concentration distribution is lower than that of the upper end of the anode layer 15.

By providing the n cathode layer 13, the amount of electrons injected from the n ⁺ cathode layer 12 is reduced. Therefore, the carrier distribution 20 when the forward bias is applied is located on the lower concentration side than the carrier distribution 120 of the semiconductor device according to the comparative example described later. In particular, the value on the cathode electrode 11 side is significantly reduced. Thereby, the carrier distribution 20 becomes flatter than the carrier distribution 120 of the comparative example described later.

FIG. 6 is a graph illustrating the impurity concentration distribution of the semiconductor device according to the first embodiment and the transient carrier distribution when a reverse bias is applied, and the vertical axis indicates the thickness direction of the semiconductor layer. The horizontal axis represents the impurity concentration and the carrier concentration.

As shown in FIG. 6, when a forward bias is applied between the anode electrode 16 and the cathode electrode 11, a reverse bias, that is, when the cathode electrode 11 is applied positively to the anode electrode 16. In this case, the holes present in the n base layer 14 are formed by the anode electrode 16.
Move to the side. The electrons existing in the n base layer 14 move to the cathode electrode 11 side.

Thereby, the carrier distribution 20 in the n base layer 14 recedes to the cathode electrode 11 side. Further, the depletion layer is n from the interface between the p ⁺ anode layer 15 and the n base layer 14.
The base layer 14 extends. Thereby, conduction between the anode electrode 16 and the cathode electrode 11 in the semiconductor device 1 is interrupted.

Next, the effect of this embodiment will be described.
In the present embodiment, since the n cathode layer 13 includes a portion 13a disposed on the n ⁺ cathode layer 12 and a portion 13b in contact with the cathode electrode 11, the amount of injected electrons is suppressed. Therefore, the carrier concentration on the cathode electrode 11 side in the conductive state is reduced.

Moreover, in the semiconductor device 1 according to the present embodiment, the carrier distribution 20 is reduced without introducing a lifetime killer.

FIG. 7 is a graph illustrating the calculation results of the switching current, the switching voltage, and the switching characteristics from the steady-state conduction current of 200 amperes (A) of the semiconductor device according to the first embodiment and a comparative example described later. Indicates current (A), voltage (V) and loss (J),
The horizontal axis indicates time (sec).

As shown in FIG. 7, in the first embodiment, the switching current A in the semiconductor device 1
The recovery period and tail period of 1 are shorter than the recovery period and tail period of the switching current A101 in the case of the semiconductor device 101 according to the comparative example described later. Also,
The switching voltage V1 in the semiconductor device 1 decreases more quickly and reaches a constant value than the switching voltage V101 in the case of a semiconductor device according to a comparative example described later. The switching loss J1 in the semiconductor device 1 is 60% or less compared to the switching loss J101 in the case of a semiconductor device according to a comparative example described later.

FIG. 8A is a graph illustrating the relationship between the switching loss and the forward voltage of the semiconductor device according to the first embodiment. The vertical axis indicates the switching loss _Err , and the horizontal axis indicates the forward voltage. VF is shown.

As shown in FIG. 8A, the switching of the semiconductor device 1 is faster than the semiconductor device 101 according to the comparative example described later.

FIG. 8B is a graph illustrating the temperature characteristics of the leakage current of the semiconductor device according to the first embodiment, where the vertical axis indicates the magnitude of the leakage current (log μA / cm ² ), and the horizontal axis indicates , Temperature (K
).

As shown in FIG. 8B, since the lifetime killer is not introduced into the semiconductor device 1 according to the present embodiment, the leakage current is reduced as compared with the semiconductor device 101 according to the comparative example described later. Can do. This allows safe operation, particularly at high temperatures.

In FIG. 1A and FIG. 1B, the width of the n ⁺ cathode layer 12 is larger than the width of the portion 13b in contact with the cathode electrode 11 in the n cathode layer 13, but this is not restrictive. For example, the width of the n ⁺ cathode layer 12 may be smaller than the width of the portion 13b.

(Modification of the first embodiment)
Next, a modification of the first embodiment will be described.

FIG. 9A is a schematic cross-sectional view illustrating a semiconductor device according to a modification of the first embodiment.
FIG. 9B is a schematic plan view excluding the cathode electrode along the line AA ′ shown in FIG.

This modification is an example in which the shape and arrangement of the n ⁺ cathode layer 12 and the n cathode layer 13 are different.

As shown in FIGS. 9A and 9B, in the semiconductor device 1a in the present modification,
The plurality of n ⁺ cathode layers 12 are circular when viewed from above. A region 11a in contact with the n ⁺ cathode layer 12 in the cathode electrode 11 is also circular. The outer diameter of each cathode electrode 11 and each region 11a is, for example, 100 micrometers (μm) or less. The plurality of n ⁺ cathode layers 12 and the plurality of regions 11 a are arranged in a matrix in one direction and the other direction on the cathode electrode 11.

The thickness of the n ⁺ cathode layer 12 is, for example, 5 micrometers (μm) or less. Each n
The distance between the ⁺ cathode layer 12 and each region 11a is, for example, 50 micrometers (μm) or less. The configuration other than the above in the present modification is the same as that in the first embodiment.

Next, the operation of this modification will be described.
In this modification, the holes that have reached the portion 13a disposed on the n ⁺ cathode layer 12 in the n cathode layer 13 are radiated in all directions in the horizontal direction, that is, in the direction parallel to the plate surface of the cathode electrode 11. It moves with the component of. Then, the holes that have reached the portion 13 b in contact with the cathode electrode 11 in the n cathode layer 13 flow into the cathode electrode 11. Operations other than those described above in the present modification are the same as those in the first embodiment described above.

Next, the effect of this modification will be described.
In this modification, since the area of the n + cathode layer 12 can be reduced, the amount of electron injection can be further suppressed and higher speed can be realized. Furthermore, since the horizontal component of the hole current is not limited to the other direction, the hole current can be made uniform. The effects of the present modification other than those described above are the same as those of the first embodiment.

In FIG. 9B, the region 11a in contact with the n ⁺ cathode layer 12 in the cathode electrode 11 has a circular shape, but this is not restrictive. A region 11b in contact with the n cathode layer 13 in the cathode electrode 11 may be circular. That is, the n ⁺ cathode layer 12 has
The cross-sectional shape of the surface parallel to the plate surface of the cathode electrode 11 is circular, and a plurality of through holes penetrating the n ⁺ cathode layer 12 vertically are formed. The lower end of the n cathode layer 13 may be brought into contact with the cathode electrode 11 through the through hole.

(Comparative example)
Next, a comparative example of the first embodiment will be described.

  FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a comparative example of the first embodiment.

As shown in FIG. 10, the semiconductor device 101 according to this comparative example includes a cathode electrode 11, n ⁺
A cathode layer 92, an n base layer 14, a p ⁺ anode layer 15 and an anode electrode 16 are provided. In this comparative example, the semiconductor layer 10 includes an n ⁺ cathode layer 92, an n base layer 14, and a p ⁺ anode layer 15.

The n ⁺ cathode layer 92 is disposed on the cathode electrode 11. The n base layer 14 has n
⁺ Arranged on the cathode layer 92. Therefore, in this comparative example, the plurality of n ⁺ cathode layers 12 are not formed on the cathode electrode 11 so as to be separated from each other. The n ⁺ cathode layer 92 is formed in layers on the upper surface of the cathode electrode 11.

The n base layer 14 is provided on the n ⁺ cathode layer 92. The n cathode layer 13 is not provided between the n base layer 14 and the n ⁺ cathode layer 92. A lifetime killer, for example, a heavy metal element is introduced into the n base layer 14. Other configurations in the comparative example are the same as those in the first embodiment.

Next, the operation of the semiconductor device 101 according to the comparative example will be described.
A voltage having the anode electrode 16 side as a positive electrode is applied between the anode electrode 16 and the cathode electrode 11 with respect to the cathode electrode 11 side. Electrons are injected into the n base layer 14 from the n ⁺ cathode layer 92 side. Holes are injected into the n base layer 14 from the p ⁺ anode layer 15 side. As a result, the cathode electrode 11 and the anode electrode 16 become conductive.

FIG. 11A is a graph illustrating the impurity concentration distribution of the semiconductor device according to the comparative example of the first embodiment and the carrier distribution when a forward bias is applied. The vertical axis represents the semiconductor layer. The position in the thickness direction is shown, and the horizontal axis shows the concentration.

As shown in FIG. 11A, in this comparative example, the n cathode layer 13 is not provided, and the carrier concentration on the cathode electrode 11 side cannot be reduced.

In addition, when a lifetime killer is introduced, the value of the central portion of the n base layer 14 in the carrier distribution 120 is low.

FIG. 11B is a graph illustrating the impurity concentration distribution of the semiconductor device according to the comparative example of the first embodiment and the carrier distribution in the transient state when a reverse bias is applied. The position of the semiconductor layer in the thickness direction is shown, and the horizontal axis shows the concentration.

As shown in FIG. 11B, when the forward bias is applied, the reverse bias, that is, when the cathode electrode 11 is applied positively to the anode electrode 16,
The holes injected into the n base layer 14 move to the anode electrode 16 side. This
The carrier distribution 120 in the n base layer 14 recedes toward the cathode electrode 11 side. Further, the depletion layer is formed from the interface between the p ⁺ anode layer 15 and the n base layer 14 as the starting point.
To spread.

Thereby, conduction between the anode electrode 16 and the cathode electrode 11 in the semiconductor device 101 is interrupted. Here, compared with the reduction of the carrier concentration on the cathode electrode 11 side in the conductive state in the semiconductor device 1 of the present embodiment described with reference to FIGS. 5 and 6, in FIG. 11, the carrier on the cathode electrode 11 side in the conductive state is shown. Even when the concentration is high and the depletion layer spreads to the cathode electrode 11 side, the carrier concentration on the cathode electrode 11 side is high, so the speed cannot be increased.

In this comparative example, it is necessary to introduce a lifetime killer in order to reduce the lifetime. Thereby, as shown in FIG.8 (b), the leakage current at the time of OFF increases. Therefore, the applicable temperature range of the semiconductor device 101 is narrow.

(Second Embodiment)
Next, a second embodiment will be described.

  FIG. 12 is a schematic cross-sectional view illustrating a semiconductor device according to the second embodiment.

FIG. 13A is a schematic plan view of the semiconductor device according to the second embodiment, excluding the anode electrode taken along line AA ′ shown in FIG. 12, and FIG. 13B is a line BB ′ shown in FIG. It is a plane schematic diagram except the cathode electrode by.

As shown in FIG. 12, FIG. 13A and FIG. 13B, the semiconductor device 2 according to the present embodiment.
, A p anode layer 17 (fifth semiconductor layer) is provided on the n base layer 14. The thickness of the p anode layer 17 is several to several tens of micrometers (μm), for example, 1 to 20
Micrometer (μm). The p anode layer 17 includes a semiconductor, for example, silicon. The p anode layer 17 contains an impurity serving as an acceptor, for example, boron. The conductivity type of the p anode layer 17 is p type. The effective impurity concentration in the p anode layer 17 is lower than the effective impurity concentration in the p ⁺ anode layer 95 (fourth semiconductor layer). The surface concentration of boron in the p anode layer 17 is, for example, 3 × 10 ¹⁷ cm ^−3.
It is as follows.

A plurality of p ⁺ anode layers 95 are arranged on the p anode layer 17 so as to be separated from each other. Each p ⁺ anode layer 95 has, for example, a plurality of rectangular parallelepiped shapes extending in one direction.
The upper part of the p anode layer 17 is sandwiched between the p ⁺ anode layers 95. The width Wp of each p ⁺ anode layer 95 is, for example, 10 micrometers (μm) or less. The thickness of each p ⁺ anode layer 95 is, for example, 5 micrometers (μm) or less. The width Wn is larger than the width Wp. The interval between the p ⁺ anode layers 95 is, for example, 100 micrometers (
μm) or less. The semiconductor layer 10 includes an n ⁺ cathode layer 12, an n cathode layer 13, an n base layer 14, a p anode layer 17, and a p ⁺ anode layer 95.

The anode electrode 16 is disposed on the p ⁺ anode layer 95 and the p anode layer 17.
Therefore, the p anode layer 17 is disposed between the n base layer 14 and the anode electrode 16 and between the n base layer 14 and the p ⁺ anode layer 95. Also, the p anode layer 17 is p
⁺ A portion 17a disposed below the anode layer 95 and a portion 1 in contact with the anode electrode 16
7b. The portion 17 a is provided between the p ⁺ anode layer 95 and the n base layer 14. The portion 17 b is provided between the n base layer 14 and the anode electrode 16. The anode electrode 16 and the p ⁺ anode layer 95 are in ohmic contact.

A region 16a (second region) in contact with the p ⁺ anode layer 95 in the anode electrode 16 also extends in one direction. For example, the p ⁺ anode layer 95 is in the region immediately below the region 16a, that is,
It is located in the region directly below the region 16a. Therefore, the width of the region 16a is also the width Wp. The width Wn is larger than the width Wp. Therefore, the area of each region 11a is larger than the area of each region 16a. For example, the total area Sn of the areas 11a is larger than the total area Sp of the areas 16a. The interval between the regions 16a is equal to the interval between the p ⁺ anode layers 95, and is, for example, 100 micrometers (μm) or less.

Since the anode electrode 16 contains aluminum and the effective surface impurity concentration in the p anode layer 17 is 3 × 10 ¹⁷ cm ⁻³ or less, the anode electrode 16 and the p anode layer 1
7 is a Schottky contact. Other configurations in the present embodiment are the same as those in the first embodiment.

Next, the operation of the semiconductor device according to the second embodiment will be described.
Between the anode electrode 16 and the cathode electrode 11, a forward bias, that is, a voltage having the anode electrode 16 side as a positive electrode is applied to the cathode electrode 11 side. n cathode layer 1
Electrons are injected into the n base layer 14 from the third side. Holes are injected into the n base layer 14 from the p anode layer 17 side. Thereby, the anode electrode 16 and the cathode electrode 11 are in a conductive state.

As described above, electrons are injected from the n ⁺ cathode layer 12 through the n cathode layer 13 into the n base layer 14.

The p anode layer 17 and the anode electrode 16 do not form an energy barrier for electrons. Therefore, the electrons injected into the n base layer 14 flow into the anode electrode 16 via the p anode layer 17 and form an electron current.

Between the p anode layer 17 and the p ⁺ anode layer 95 is an energy barrier against electrons. Therefore, electrons in the p anode layer 17 are unlikely to flow into the p ⁺ anode layer 95. Therefore, the electrons in the p anode layer 17 are located below the p ⁺ anode layer 95 in the lateral direction,
That is, it moves in the other direction within a plane parallel to the plate surface of the anode electrode 16.

Due to the movement of electrons in the p anode layer 17 in the other direction, the portion 17 a disposed below the p ⁺ anode layer 95 becomes a negative electrode with respect to the portion 17 b in contact with the anode electrode 16, that is, the anode electrode 16. Are forward-biased.

The bias formed between the portion 17a and the anode electrode 16, an energy barrier is lowered to holes between the p anode layer 17 and the p ⁺ anode layer 95 below the p ⁺ anode layer 95. As a result, holes are injected from the p ⁺ anode layer 95 into the p anode layer 17. The holes injected into the p anode layer 17 form a hole current.

FIG. 14 is a graph illustrating the impurity concentration distribution of the semiconductor device according to the second embodiment and the carrier distribution when a forward bias is applied, and the vertical axis indicates the position of the semiconductor layer in the thickness direction. The horizontal axis indicates the concentration.

FIG. 15 is a graph illustrating the calculation result of the carrier distribution in a steady conduction state of about 100 A / cm ² when a forward bias is applied in the semiconductor device according to the second embodiment and the comparative example. An axis | shaft shows the position of the thickness direction of a semiconductor layer, and a vertical axis | shaft shows carrier concentration (cm ^<-3 >).

As shown in FIG. 14, the impurity concentration in the n ⁺ cathode layer 12 and the p ⁺ anode layer 95 is higher than the impurity concentration in the n cathode layer 13, the n base layer 14 and the p anode layer 17.

The impurity concentration of the p anode layer 17 is an intermediate concentration between the p ⁺ anode layer 95 and the n base layer 14. The impurity concentration in the portion 17a arranged below the p ⁺ anode layer 95 is p
^{+ The} portion in contact with the anode layer 95 is the highest. The impurity concentration in the portion 17b in contact with the anode electrode 16 is highest at the upper end.

In addition to reducing the amount of electrons injected by the n cathode layer 13, the amount of holes injected from the p ⁺ anode layer 95 is also reduced by providing the p anode layer 17. Thereby, as shown in FIG. 15, the carrier distribution 20 is the carrier distribution 12 of the semiconductor device according to the comparative example described above.
It is flatter than 0.

When the forward bias is applied between the anode electrode 16 and the cathode electrode 11 and the reverse bias, that is, when the cathode electrode 11 is applied positively to the anode electrode 16, the n base layer The holes present in 14 move to the anode electrode 16 side. n
Electrons present in the base layer 14 move to the cathode electrode 11 side.

Thereby, the carrier distribution 20 in the n base layer 14 recedes to the cathode electrode 11 side. Furthermore, the depletion layer extends to the n base layer 14 starting from the interface between the p anode layer 17 and the n base layer 14. Thereby, conduction between the anode electrode 16 and the cathode electrode 11 in the semiconductor device 1 is interrupted.

FIG. 16A is a graph illustrating a switching current from a small conduction current of about several amperes (A) of the semiconductor device according to the second embodiment, where the vertical axis indicates the current and the horizontal axis indicates FIG. 16B is a graph illustrating the switching current from a small conduction current of about several amperes (A) of the semiconductor device according to the comparative example of the first embodiment, and the vertical axis represents the current. The horizontal axis indicates time.

When width Wn> width Wp of this embodiment shown in FIG. 16A, the n base layer 1 is immediately after applying a reverse bias between the anode electrode 16 and the cathode electrode 11 in the semiconductor device 2.
Current flows in the opposite direction due to the holes and electrons present in 4. The amount of current in the reverse direction is the maximum value. Thereafter, the reverse current decreases. After the reverse current decreases to a predetermined value, it gradually decreases. Then, the current value becomes zero.

Immediately after applying the reverse bias, the period from when the current becomes zero until the reverse current amount reaches the maximum value and the slope becomes gentle is referred to as a recovery period 43. The period from when the current gradually decreases with a predetermined slope until the current value becomes zero is called a tail period 44.

By reducing the amount of holes injected on the anode electrode 16 side, the recovery period 43 is shortened. By reducing the amount of electrons injected on the cathode electrode 11 side, the tail period 44 is shortened.

When width Wn> width Wp, the amount of electrons injected on the cathode electrode 11 side is set to the anode electrode 16.
It can be made larger than the amount of holes injected on the side. That is, the amount of accumulated carriers in the steady state on the cathode electrode 11 side can be made larger than the amount of accumulated carriers in the steady state on the anode electrode 16 side. Thus, carriers can remain on the cathode electrode 11 side of the n base layer 14 in the transition period. In this way, current oscillation in the current waveform is suppressed.

In order to make the injection amount of electrons on the cathode electrode 11 side larger than the injection amount of holes on the anode electrode 16 side, the width Wn of the region 11a is made larger than the width Wp of the region 16a. That is, the relationship of width Wn> width Wp is satisfied. Further, the area Sn is made larger than the area Sp.

FIG. 16B shows a case where the width Wn is equal to or smaller than the width Wp, that is, the case where the width Wn ≦ the width Wp.
In this case, carriers cannot be left on the cathode electrode 11 side of the n base layer 14 in the transition period. This is because the amount of electrons injected on the cathode electrode 11 side in the steady conduction state is smaller than the amount of holes injected on the anode electrode 16 side. This is because the accumulated carrier on the 11th side is also gone.

Thereby, for example, at the end of the recovery period 43, a current oscillation in which the direction of current changes in small increments occurs. In this case, noise increases. Thus, several amperes (A)
In a switching current from a small conduction current of a certain degree, unlike the steady conduction current, the carrier density is low and thus vibration is likely to occur.

Next, the effect of this embodiment will be described.
In the semiconductor device 2 according to the present embodiment, since the n cathode layer 13 and the p anode layer 17 are provided, the amount of electron injection and the amount of hole injection can be suppressed. Therefore, the carrier distribution on the cathode electrode 11 side and the anode electrode 16 side is reduced. This makes the switching operation faster.

In the present embodiment, the width Wn in the semiconductor device 2 is larger than the width Wp.
Further, the area Sn is made larger than the area Sp. Further, the lateral current path in the portion 13a is made longer than the lateral current path in the portion 17a to increase the bias between the portion 13a and the portion 13b.

In this way, the amount of electrons injected into the n cathode layer 13 is made larger than the amount of holes injected into the p anode layer 17. As a result, the carrier concentration on the p anode layer 17 side is reduced as compared with the n cathode layer 13 side. For this reason, the tail current is greatly reduced during turn-off switching. In addition, the switching loss is reduced to 60% or less.

In addition, the occurrence of current oscillation when switching from forward bias to reverse bias can be suppressed. Thereby, generation | occurrence | production of noise is suppressed. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

The p ⁺ anode layer 95 and the region 16a are arranged so as to extend in one direction, but are not limited thereto. The p ⁺ anode layer 95 and the region 16a may extend in one direction or in another direction intersecting with one direction. The structure when intersecting will be described later.

(First Modification of Second Embodiment)
Next, a first modification of the second embodiment will be described.

  FIG. 17 is a schematic cross-sectional view illustrating a semiconductor device according to a first modification of the second embodiment.

FIG. 18A is a schematic plan view of the semiconductor device according to the first modified example of the second embodiment, excluding the anode electrode 10 taken along the line AA ′ shown in FIG. 17, and FIG. It is a plane schematic diagram except the cathode electrode by BB 'line shown in FIG.

This modification is an example in which the shapes and arrangements of the n ⁺ cathode layer 12 and the n cathode layer 13 and the p ⁺ anode layer 95 and the p anode layer 17 are different.

As shown in FIGS. 17 and 18 (a), in the semiconductor device 2a according to this modification, a plurality of p ⁺ anode layers 95 are provided on the p anode layer 17 so as to be separated from each other. Each p
^{The +} anode layer 95 has a circular shape when viewed from above. P at the anode electrode 16
Each region 16a in contact with the ⁺ anode layer 95 is also circular.

The radius R16 of each p ⁺ anode layer 95 and each region 16a is, for example, 10 micrometers (μm) or less. The plurality of p ⁺ anode layers 95 and the plurality of regions 16 a are arranged in a matrix in one direction and the other direction below the anode electrode 16. p
The thickness of ⁺ anode layer 95 is, for example, less than 5 micrometers ([mu] m). The interval between each p ⁺ anode layer 95 and each region 16a is, for example, 50 micrometers (μm) or less.

As shown in FIG. 18B, a plurality of n ⁺ cathode layers 12 are provided on the cathode electrode 11. Each n ⁺ cathode layer 12 has a circular shape when viewed from above. Each region 11a in contact with the n ⁺ cathode layer 12 in the cathode electrode 11 is also circular.
The radius R11 of each n ⁺ cathode layer 12 and each region 11a is, for example, 100 micrometers (μm) or less. The plurality of n ⁺ cathode layers 12 and the plurality of regions 11 a are arranged in a matrix in one direction and the other direction on the cathode electrode 11.

The thickness of the n ⁺ cathode layer 12 is, for example, 5 micrometers (μm) or less. Each n
The distance between the ⁺ cathode layer 12 and each region 11a is, for example, 50 micrometers (μm) or less.

The radius R11 is made larger than the radius R16. Further, the area Sn is made larger than the area Sp. Further, the distance from the center of gravity of each region 11a to the edge of each region 11a is set to each region 16a.
It is made larger than the distance from the center of gravity to the edge of each region 16a.

  The configuration other than the above in the present modification is the same as that of the second embodiment described above.

Next, the operation of the semiconductor device 2a according to this modification will be described.
In this modification, electrons that have reached the region immediately below the p ⁺ anode layer 95 in the p anode layer 17 move in a horizontal direction, that is, in a direction parallel to the plate surface of the anode electrode 16 with components in all directions radially. . Then, the electrons that have reached the portion other than the region immediately below the p ⁺ anode layer 95 flow into the anode electrode 16.

In addition, the holes that have reached the region immediately above the n ⁺ cathode layer 12 in the n cathode layer 13 move in a horizontal direction, that is, in a direction parallel to the plate surface of the cathode electrode 11 with components in all directions radially. Then, the holes reaching the portion other than the region immediately above the n ⁺ cathode layer 12 flow into the cathode electrode 11.

The radius R11 of the n ⁺ cathode layer 12 and the region 11a is changed to the p ⁺ anode layer 95 and the region 16.
Since the radius a is larger than the radius R16, the injection amount of electrons on the cathode electrode 11 side is larger than the injection amount of holes on the anode electrode 16 side. Further, each region 11 is determined from the center of gravity of each region 11a.
Since the distance to the edge of a is larger than the distance from the center of gravity of each region 16a to the edge of each region 16a, the current path in the portion 13a is larger than the current path in the portion 17a.

  Operations other than those described above in the present modification are the same as those in the first embodiment described above.

Next, the effect of this modification will be described.
In the present modification, the horizontal component of the hole current and the electron current is not limited to the other direction, so that the hole current and the electron current can be made uniform. Further, the current path in the portion 13a is larger than the current path in the portion 17a. Therefore, part 13a and part 1
The bias between 3b is larger than the bias between the portion 17a and the portion 17b.
As a result, the hole injection amount is smaller than the electron injection amount, and the switching loss is reduced. The effects of the present modification other than those described above are the same as those of the first embodiment.

(Second Modification of Second Embodiment)
Next, a second modification of the second embodiment will be described.

  FIG. 19 is a schematic cross-sectional view illustrating a semiconductor device according to a second modification of the second embodiment.

FIG. 20A is a schematic plan view of the semiconductor device according to the second modification of the second embodiment, excluding the anode electrode taken along line AA ′ shown in FIG. 19, and FIG. It is a plane schematic diagram except the cathode electrode by BB 'line shown in FIG.

This modification is another example in which the shapes and arrangements of the n ⁺ cathode layer 12 and the n cathode layer 13 and the p ⁺ anode layer 95 and the p anode layer 17 are different.

As shown in FIGS. 19 and 20A, in the semiconductor device 2b according to this modification, the region 16b in contact with the p anode layer 17 in the anode electrode 16 has a circular shape. That is, the p anode layer 17 includes a plurality of portions 17 b in contact with the anode electrode 16.
The portion 17b is circular when viewed from above. The plurality of portions 17 b are connected to a portion 17 a disposed below the p ⁺ anode layer 95 in the p anode layer 17.

Further, as shown in FIG. 20B, the region 11b of the cathode electrode 11 in contact with the n cathode layer 13 is formed into a circular shape. That is, the n cathode layer 13 includes a plurality of portions 13 b in contact with the cathode electrode 11. The portion 13b has a circular shape when viewed from above. The plurality of portions 13 b are portions 13 arranged on the n ⁺ cathode layer 12 in the n cathode layer 13.
connected to a.

Then, the interval D11 between the adjacent portions 13b and the interval D11 between the adjacent regions 11b are made larger than the interval D16 between the adjacent portions 17b and the interval D16 between the adjacent regions 17b. The configuration other than the above in the present modification is the same as that of the second embodiment described above.

Next, the operation of the semiconductor device according to this modification will be described.
In this modification, the holes in the portion 17 a of the p anode layer 17 move radially with components in all directions in the horizontal direction, that is, in the direction parallel to the plate surface of the anode electrode 16. And the hole which reached the part 17b passes through the part 17b, and anode electrode 1
Flows into 6.

Further, the holes in the portion 13a of the n cathode layer 13 move radially with components in all directions in the horizontal direction, that is, in the direction parallel to the plate surface of the cathode electrode 11.
Then, the holes that have reached the contact portion 13b flow into the cathode electrode 11 through the portion 13b.

The interval D11 is larger than the interval D16. Therefore, the current path in the portion 13a is made larger than the current path in the portion 17a. Further, the area Sn is made larger than the area Sp. Thereby, the injection amount of electrons on the cathode electrode 11 side is made larger than the injection amount of holes on the anode electrode 16 side. Operations and effects other than those described above in the present modification are the same as those in the second embodiment described above.

It is also possible to combine the first modification and the second modification. That is, for example, the p ⁺ anode layer 95 is circular when viewed from above, and n in the cathode electrode 11
For example, the region 11b in contact with the cathode layer 13 has a circular shape. In this case as well, the distance D
11 may be larger than the diameter 2 × R11. Further, the area Sn may be made larger than the area Sp.

(Third Modification of Second Embodiment)
Next, a third modification of the second embodiment will be described.

  FIG. 21 is a schematic cross-sectional view illustrating a semiconductor device according to a third modification of the second embodiment.

As shown in FIG. 21, in this modification, a p ⁺ absorption layer 96 (sixth semiconductor layer: also expressed as p ⁺ cathode layer 96) is formed between each n ⁺ cathode layer 12 on the cathode electrode 11. Has been. The planar shape viewed from below excluding the cathode electrode 11 by the AA ′ line is the same as the second embodiment, the first modification of the second embodiment, and the stripe shape, the polka dots, as in the second modification of the second embodiment. Any shape is acceptable. The stripe shape and the polka dot shape include the lower surface of the p ⁺ suction layer 96. The stripe shape and the polka dot shape may include the lower surface of the portion in contact with the cathode electrode 11 in the n cathode layer 13, in addition to the lower surface of the p ⁺ sucking layer 96.

The thickness of the p ⁺ sucking layer 96 is, for example, 5 micrometers (μm) or less. The p ⁺ absorption layer 96 includes a semiconductor, for example, silicon. The p ⁺ absorption layer 96 contains an impurity serving as an acceptor, for example, boron. The conductivity type of the p ⁺ absorbing layer 96 is p-type. The surface concentration of boron in the portion in contact with the cathode electrode 11 of the p ⁺ sucking layer 96 is, for example, 3 × 10 ¹⁷ cm ⁻³ or more. The cathode electrode 11 and the p ⁺ suction layer 96 are in ohmic contact.

An n cathode layer 98 is provided on the n ⁺ cathode layer 12 and the p ⁺ sucking layer 96.
The n cathode layer 98 includes a semiconductor, for example, silicon. The n cathode layer 98 includes
Impurities serving as donors, such as phosphorus, are contained. The conductivity type of the n cathode layer 13 is n
It is a shape. The effective impurity concentration in the n cathode layer 13 is lower than the effective impurity concentration in the n ⁺ cathode layer 12. The surface concentration of phosphorus in the portion in contact with the cathode electrode 11 of the n cathode layer 98 is, for example, 3 × 10 ¹⁷ cm ⁻³ or less.

Next, operations and effects of the semiconductor device according to this modification will be described.
The p ⁺ sucking layer 96 of this modification does not serve as a barrier to holes injected from the p ⁺ anode layer 15 and functions to discharge holes. As a result, as described in the first embodiment, holes are
It can flow into the cathode electrode 11 via the n base layer 14, the n cathode layer 13, and the p ⁺ absorption layer 96 to suppress the amount of injected electrons. Therefore, similar effects can be obtained by taking similar dimensions in combination with the second embodiment.

(Third embodiment)
The structure for adjusting the carrier injection on the cathode side is not limited to the structure described above.

22 is a schematic view illustrating a semiconductor device according to the third embodiment, FIG. 22 is a schematic cross-sectional view, and FIG. 22 (b) is a schematic plan view at the position of the line BB ′ in FIG. 22 (a). FIG.

The semiconductor device 3a according to the third embodiment further includes a p ⁺ cathode layer 25 (seventh semiconductor layer) in addition to the configuration of the semiconductor device 1 (FIG. 1) described above. The p ⁺ cathode layer 25 is provided on the cathode electrode 11. The p ⁺ cathode layer 25 is in ohmic contact with the cathode electrode 11. The p ⁺ cathode layer 25 is in contact with the n ⁺ cathode layer 12.

The n cathode layer 13 is provided on the cathode electrode 11, the p ⁺ cathode layer 25, and the n ⁺ cathode layer 12. The n cathode layer 13 is in contact with the cathode electrode 11, the p ⁺ cathode layer 25, and the n ⁺ cathode layer 12. The effective impurity concentration of the p ⁺ cathode layer 25 is higher than the effective impurity concentration of the p ⁺ anode layer 15.

The thickness of the p ⁺ cathode layer 25 is, for example, 5 micrometers (μm) or less. p ⁺
The cathode layer 25 includes a semiconductor, for example, silicon. p ⁺ cathode layer 25 includes
Impurities that serve as acceptors, such as boron, are contained. The conductivity type of the p ⁺ cathode layer 25 is p-type. The surface concentration of boron in the portion in contact with the cathode electrode 11 of the p ⁺ cathode layer 25 is, for example, 3 × 10 ¹⁷ cm ⁻³ or more. In the semiconductor device 3a,
The width of the n ⁺ cathode layer 12 is defined by Wn, and the width of the p ⁺ cathode layer 25 is defined by Wp ⁺ .

Next, the operation of the semiconductor device 3a according to the third embodiment will be described.
FIG. 23 is a schematic cross-sectional view illustrating the operation of the semiconductor device according to the third embodiment.

FIG. 23A illustrates the operation when a forward bias is applied between the anode electrode and the cathode electrode. FIG. 23B illustrates the operation when a forward bias is applied between the anode electrode and the cathode electrode. The operation immediately after (at the time of recovery) is illustrated.

As shown in FIG. 23A, at the time of forward bias, holes are transferred from the p ⁺ anode layer 15 to n.
Implanted into the base layer 14. Thereafter, holes flow into the cathode electrode 11 via the n base layer 14 and the n cathode layer 13 to form a hole current 19. That is, for holes, the Schottky contact between the cathode electrode 11 and the n cathode layer 13 does not become an energy barrier (see FIG. 4A).

Further, the p ⁺ cathode layer 25 is provided in the semiconductor device 3a. p ⁺ cathode layer 2
5 does not serve as a barrier against holes injected from the p ⁺ anode layer 15. That is, holes flow to the cathode electrode 11 via the n base layer 14, the n cathode layer 13, and the p ⁺ cathode layer 25.

However, the junction between the n cathode layer 13 and the n ⁺ cathode layer 12 becomes an energy barrier for the holes 13h (see FIG. 4B). Therefore, the holes 13 h are difficult to flow into the n ⁺ cathode layer 12. Therefore, the holes flowing through the n cathode layer 13 are n ⁺ cathode layer 1
2 is moved in the lateral direction, that is, in another direction orthogonal to one direction in a plane parallel to the plate surface of the cathode electrode 11.

Due to the movement of the holes in the n cathode layer 13 in the other direction, the portion 13 a disposed on the n ⁺ cathode layer 12 becomes a positive electrode with respect to the portion 13 b in contact with the cathode electrode 11, that is, the cathode electrode 11. Biased to be

The bias formed between the portion 13a and the cathode electrode 11, the energy barrier between the n cathode layer 13 and the n ⁺ cathode layer 12 in the n ⁺ cathode layer 12 on the lower. As a result, electrons are injected from the n ⁺ cathode layer 12 into the n cathode layer 13. The electrons injected into the n cathode layer 13 form an electron current 18.

In the semiconductor device 3a, since the n cathode layer 13 is provided, the amount of electrons injected from the n ⁺ cathode layer 12 is reduced when a forward bias is applied. Therefore, the carrier distribution 20 when the forward bias is applied is the carrier distribution 120 of the semiconductor device according to the comparative example described above.
It is located on the lower concentration side. In this way, the carrier injection amount is suppressed at the time of turning on.

On the other hand, when a reverse bias is applied (at the time of recovery), as shown in FIG. 23B, the holes present in the n base layer 14 move to the anode electrode 16 side and enter the n base layer 14. The existing electrons move to the cathode electrode 11 side.

Immediately after recovery, the pn junction between the n cathode layer 13 and the p ⁺ cathode layer 25 becomes an energy barrier for electrons. Therefore, the electrons 13 e are less likely to flow into the p ⁺ cathode layer 25.

However, the junction between the n cathode layer 13 and the n ⁺ cathode layer 12 does not become an energy barrier for electrons. Therefore, the electrons 13e flowing in the n cathode layer 13 move on the p ⁺ cathode layer 25 in the lateral direction, that is, in another direction orthogonal to one direction in a plane parallel to the plate surface of the cathode electrode 11. .

Thereafter, the electrons 13 e flow to the cathode electrode 11 via the n ⁺ cathode layer 12. Then, by movement of electrons in the n cathode layer 13 in the other direction, the portion 13c disposed on the p ⁺ cathode layer 25 becomes a negative electrode with respect to the portion 13a in contact with the n ⁺ cathode layer 12. Biased. Since the n ⁺ cathode layer 12 and the cathode electrode 11 are in ohmic contact, the portion 13 c is eventually biased with respect to the cathode electrode 11 so as to be negative.

As a result, the bias formed between the portion 13c and the cathode electrode 11 causes p to
The energy barrier between the portion 13c on the ⁺ cathode layer 25 and the p ⁺ cathode layer 25 is lowered. As a result, holes, that is, carriers are reinjected from the p ⁺ cathode layer 25 into the n cathode layer 13. Thus, in the semiconductor device 3a, the amount of injected carriers is adjusted even when the semiconductor device 3a is turned off.

By reducing the energy barrier between the portion 13c and the p ⁺ cathode layer 25, p ⁺
In order to reinject carriers from the cathode layer 25 into the n cathode layer 13, Wp ⁺ needs to be a predetermined length or more. For example, Wp ⁺ is preferably 10 μm or more,
Further, it is more preferably 30 μm or more.

Thereafter, the carrier distribution 20 (see FIG. 6) in the n base layer 14 is expressed by the cathode electrode 11.
Retreat to the side. Furthermore, the depletion layer extends to the n base layer 14 starting from the interface between the p ⁺ anode layer 15 and the n base layer 14. As a result, the conduction between the anode electrode 16 and the cathode electrode 11 in the semiconductor device 3a is interrupted.

According to such a structure, carriers can be more reliably left on the cathode electrode 11 side of the n base layer 14 in the transition period by reinjecting the carriers at the time of recovery. Thereby, for example, at the end of the recovery period 43, current oscillation in which the direction of current changes in small increments is less likely to occur. As a result, the generation of noise is further suppressed.

The difference between the third embodiment described above and the third modification of the second embodiment described above is that in the structure of the cathode side of the third embodiment, the n cathode layer 13, the n ⁺ cathode layer 12, and the p ⁺ The cathode layer 25 is in contact with the cathode electrode 11, and in the structure of the third modified example of the second embodiment, only the n ⁺ cathode layer 12 and the p ⁺ sucking layer 96 are in contact with the cathode electrode 11. As described above, the provision of the n cathode layer 13 is effective in that the width of the n ⁺ cathode layer 12 and the width of the p ⁺ cathode layer 25 can be independently designed regardless of the element pitch. It is effective in suppressing noise generation in current.

(First Modification of Third Embodiment)
FIG. 24 is a schematic view illustrating a semiconductor device according to a first modification of the third embodiment.
FIG. 24A is a schematic sectional view, and FIG. 24B is a schematic plan view at the position of the BB ′ line in FIG.

The semiconductor device 3b according to the first modification of the third embodiment further includes a p ⁺ cathode layer 25 in addition to the configuration of the semiconductor device 1 (FIG. 1) described above. The p ⁺ cathode layer 25 is provided on the cathode electrode 11. The p ⁺ cathode layer 25 is in ohmic contact with the cathode electrode 11. In the first modification, the n ⁺ cathode layer 12 and the p ⁺ cathode layer 25 are not in contact with each other. That is, the n ⁺ cathode layer 12 and the p ⁺ cathode layer 25 are provided separately from each other. In other words, the portion 13 b of the n cathode layer 13 is sandwiched between the n ⁺ cathode layer 12 and the p ⁺ cathode layer 25.

The n cathode layer 13 is provided on the cathode electrode 11, the p ⁺ cathode layer 25, and the n ⁺ cathode layer 12. The effective impurity concentration of the p ⁺ cathode layer 25 is higher than the effective impurity concentration of the p ⁺ anode layer 15.

The operation at the time of recovery of the semiconductor device 3b will be described.
FIG. 25 is a schematic cross-sectional view illustrating the operation of the semiconductor device according to the first variation of the third embodiment.

As shown in FIG. 25A, when a reverse bias is applied (at the time of recovery), holes present in the n base layer 14 move to the anode electrode 16 side and exist in the n base layer 14. The electrons move to the cathode electrode 11 side.

Immediately after recovery, the pn junction between the n cathode layer 13 and the p ⁺ cathode layer 25 becomes an energy barrier for electrons. Therefore, the electrons 13 e are less likely to flow into the p ⁺ cathode layer 25. Furthermore, for electrons traveling from the n cathode layer 13 to the cathode electrode 11, the Schottky contact between the cathode electrode 11 and the n cathode layer 13 becomes an energy barrier (see FIG. 4A).

However, the junction between the n cathode layer 13 and the n ⁺ cathode layer 12 does not become an energy barrier for electrons. Therefore, the electrons 13e flowing in the n cathode layer 13 move on the p ⁺ cathode layer 25 in the lateral direction, that is, in another direction orthogonal to one direction in a plane parallel to the plate surface of the cathode electrode 11. .

Thereafter, the electrons 13 e flow to the cathode electrode 11 via the n ⁺ cathode layer 12. Then, by movement of electrons in the n cathode layer 13 in the other direction, the portion 13c disposed on the p ⁺ cathode layer 25 becomes a negative electrode with respect to the portion 13a in contact with the n ⁺ cathode layer 12. Biased. Since the n ⁺ cathode layer 12 and the cathode electrode 11 are in ohmic contact, the portion 13 c is eventually biased with respect to the cathode electrode 11 so as to be negative.

As a result, the bias formed between the portion 13c and the cathode electrode 11 causes p to
The energy barrier between the portion 13c on the ⁺ cathode layer 25 and the p ⁺ cathode layer 25 is lowered. As a result, holes, that is, carriers are reinjected from the p ⁺ cathode layer 25 into the n cathode layer 13. Thus, also in the first modification, the carrier injection amount is adjusted at the time of off.

However, when the cathode electrode 11 and the n cathode layer 13 are in Schottky contact,
It becomes difficult for the electrons 13e to flow to the cathode electrode 11 via the portion 13b. Therefore, there is a possibility that the length of substantial width of the p ⁺ cathode layer 25 is the sum of the width of Wp ⁺ and portion 13b of the p ⁺ cathode layer 25. In this case, an excessive amount of holes, that is, carriers may be reinjected from the cathode side.

FIG. 25B illustrates an operation when the cathode electrode 11 and the n cathode layer 13 are in ohmic contact instead of Schottky contact.

In this case, immediately after recovery, the pn junction between the n cathode layer 13 and the p ⁺ cathode layer 25 becomes an energy barrier for electrons. Therefore, the electrons 13 e are less likely to flow into the p ⁺ cathode layer 25.

However, for electrons, the junction between the cathode electrode 11 and the n cathode layer 13 does not become an energy barrier due to ohmic contact. Therefore, the electrons 13e from the n cathode layer 13 toward the cathode electrode 11 can flow to the cathode electrode 11 via the portion 13b.

Therefore, the electrons 13e flowing in the n cathode layer 13 move on the p ⁺ cathode layer 25 in the lateral direction, that is, in another direction orthogonal to one direction in a plane parallel to the plate surface of the cathode electrode 11. . Thereafter, the electrons 13e flow to the cathode electrode 11 via the portion 13b. Then, by movement of electrons in the n cathode layer 13 in the other direction, the portion 13c disposed on the p ⁺ cathode layer 25 becomes a negative electrode with respect to the portion 13a in contact with the n ⁺ cathode layer 12. Biased. Since the n ⁺ cathode layer 12 and the cathode electrode 11 are in ohmic contact, the portion 13 c is eventually biased with respect to the cathode electrode 11 so as to be negative.

As a result, the bias formed between the portion 13c and the cathode electrode 11 causes p to
The energy barrier between the portion 13c on the ⁺ cathode layer 25 and the p ⁺ cathode layer 25 is lowered. Thereby, holes, that is, carriers are reinjected from the p ⁺ cathode layer 25 to the n cathode layer 13. Thus, also in the first modification, the carrier injection amount is adjusted at the time of off.

In the example of FIG. 25B, the cathode electrode 11 and the n-cathode layer 13 are brought into ohmic contact, thereby suppressing an excessive amount of holes from the cathode side, that is, excessive carrier reinjection.

As described above, according to the first modification of the third embodiment, carriers can be more reliably left on the cathode electrode 11 side of the n base layer 14 in the transition period by reinjecting carriers. Thereby, for example, at the end of the recovery period 43, current oscillation in which the direction of current changes in small increments is less likely to occur. As a result, the generation of noise is further suppressed.

(Second and third modifications of the third embodiment)
FIG. 26 is a schematic view illustrating a semiconductor device according to a second modification and a third modification of the third embodiment. FIG. 26A is a schematic cross-sectional view of the second modification, and FIG. b) is a schematic cross-sectional view of a third modification.

A semiconductor device 3c according to the second modification of the third embodiment illustrated in FIG. 26A is a combination of the semiconductor device 2 according to the second embodiment and the semiconductor device 3a according to the third embodiment. Semiconductor device.

According to such a structure, in addition to the operational effect obtained with the semiconductor device 2, the operational effect obtained with the semiconductor device 3a is further exhibited. That is, by setting the width Wn> the width Wp, the amount of electrons injected on the cathode electrode 11 side can be made larger than the amount of holes injected on the anode electrode 16 side. Thereby, the amount of accumulated carriers in the steady state on the cathode electrode 11 side is
The amount of accumulated carriers in the steady state on the anode electrode 16 side can be made larger. As a result, carriers remain on the cathode electrode 11 side of the n base layer 14 in the transition period.

Further, at the time of recovery, carriers can be reliably left on the cathode electrode 11 side of the n base layer 14 in the transition period by reinjecting the carriers. This makes it difficult for current oscillation to occur at the end of the recovery period 43. As a result, the generation of noise is further suppressed.

The semiconductor device 3d according to the third modification example of the third embodiment illustrated in FIG. 26B includes the semiconductor device 2 according to the second embodiment and the semiconductor device 3b according to the first modification example of the third embodiment. And a composite device.

According to such a structure, in addition to the function and effect obtained by the semiconductor device 2, the function and effect obtained by the semiconductor device 3b are exhibited. That is, by setting the width Wn> the width Wp, the amount of electrons injected on the cathode electrode 11 side can be made larger than the amount of holes injected on the anode electrode 16 side. Thereby, the amount of accumulated carriers in the steady state on the cathode electrode 11 side is
The amount of accumulated carriers in the steady state on the anode electrode 16 side can be made larger. As a result, carriers remain on the cathode electrode 11 side of the n base layer 14 in the transition period.

Further, at the time of recovery, carriers can be reliably left on the cathode electrode 11 side of the n base layer 14 in the transition period by reinjecting the carriers. This makes it difficult for current oscillation to occur at the end of the recovery period 43. As a result, the generation of noise is further suppressed.

FIG. 27 is a graph illustrating the switching current and voltage of the semiconductor device according to the third embodiment.
FIG. 27 illustrates the switching current and voltage of the semiconductor device 3c as an example.

FIG. 27A illustrates the switching current and voltage when Wn is 30 μm and Wp ⁺ is 20 μm. In FIG. 27B, Wn is 45 μm,
The characteristics of switching current and voltage when Wp ⁺ is 30 μm are illustrated. W
n> Wp.

As shown in FIG. 27, no current oscillation or voltage oscillation occurred in the recovery period 43 and the tail time 44. The other semiconductor devices 3a, 3b, and 3d showed the same tendency.

(Fourth embodiment)
Further, the structure for reducing noise by reinjecting carriers from the cathode side during recovery is not limited to the structure shown in FIGS. 22, 24, 26 (a), and (b).

FIG. 28A is a schematic cross-sectional view illustrating the semiconductor device according to the first example of the fourth embodiment, and FIG. 28B illustrates the semiconductor device according to the second example of the fourth embodiment. It is a cross-sectional schematic diagram.

For example, in the semiconductor device 4a shown in FIG. 28A, a plurality of p ⁺ cathode layers 96 (p ⁺ cathode layers 96a and 96b) are provided between the cathode electrode 11 and the n cathode layer 98. Yes. The p ⁺ cathode layer 96 includes a semiconductor such as silicon, for example. The p ⁺ cathode layer 96 contains an impurity (for example, boron) serving as an acceptor. The surface concentration of boron in the portion of the p ⁺ cathode layer 96 in contact with the cathode electrode 11 is, for example, 3 × 1.
It is 0 ¹⁷ cm ⁻³ or more. The p ⁺ cathode layer 96 is in ohmic contact with the cathode electrode 11.

The p ⁺ cathode layer 96 includes, for example, two types of p ⁺ cathode layers having different widths. For example, the p ⁺ cathode layer 96 is a group of p ⁺ cathode layers having a width Wpa (first width) in a direction (Y direction in the figure) that intersects the direction (X direction in the figure) in which the p ⁺ cathode layer 96 extends. 96a
And another group of p ⁺ cathode layers 96b having a width Wpb (second width) in the Y direction. The width Wpa is wider than the width Wpb.

Here, the width Wpa is adjusted so that carriers (holes) are reinjected from the cathode side during recovery, and the width Wpb is adjusted so that carriers (holes) are not reinjected from the cathode side during recovery. Yes. The width Wpa is, for example, 10 μm or more, and more preferably 30 μm or more. Further, the width Wpb is smaller than 10 μm, for example.

According to such a structure, carriers are reinjected by the p ⁺ cathode layer 96a at the time of recovery, and the carriers can be reliably left on the cathode electrode 11 side of the n base layer 14 in the transition period. Thereby, for example, at the end of the recovery period 43, current oscillation in which the direction of current changes in small increments is less likely to occur. As a result, the generation of noise is further suppressed.

On the other hand, if carrier reinjection is excessive during recovery, recovery loss may increase and diode characteristics may deteriorate. In the fourth embodiment, the carrier reinjection amount at the time of recovery is optimized by providing the p ⁺ cathode layer 96b in which carriers are not reinjected at the time of recovery.

Further, each of the p ⁺ cathode layer 96a and the p ⁺ cathode layer 96b has the same impurity concentration. Each of the p ⁺ cathode layer 96a and the p ⁺ cathode layer 96b is simultaneously formed by ion implantation. Accordingly, as in the semiconductor device 2c of FIG. 21, the number of manufacturing steps is the same as when the p ⁺ cathode layer 96 is formed alone. That, ^{p +} even other cathode layer 96a was formed ^{p +} cathode layer 96b, nor the production cost is increased.

Further, like the semiconductor device 4b shown in FIG. 28B, the anode side is connected to the semiconductor device 2 (FIG. 1).
By adopting the same structure as in 2), carrier injection during conduction is suppressed, and higher speed operation becomes possible.

(Fifth embodiment)
Further, the structure for reducing noise by reinjecting carriers from the cathode side during recovery is not limited to the structure shown in FIGS.

FIG. 29 is a schematic cross-sectional view illustrating the semiconductor device according to the first example of the fifth embodiment.
In addition to the p ⁺ cathode layer 96, the semiconductor device 5a shown in FIG. 29 further includes a p ⁻ cathode layer 97 (seventh semiconductor layer) in contact with the n ⁺ cathode layer 12 and in Schottky contact with the cathode electrode 11.

The p ⁻ cathode layer 97 includes, for example, a semiconductor such as silicon. The p ⁻ cathode layer 97 contains an impurity (for example, boron) serving as an acceptor. p ^- cathode layer 97
The effective impurity concentration at is lower than the effective impurity concentration at the p ⁺ cathode layer 96. The surface concentration of boron in the p ⁻ cathode layer 97 is, for example, 3 × 10 ¹⁷ cm ^−3.
It is as follows.

Here, the impurity concentration of the p ⁺ cathode layer 96 is adjusted to such an extent that carriers (holes) are reinjected from the cathode side during the recovery, and the impurity concentration of the p ⁻ cathode layer 97 is changed from the cathode side during the recovery. (Holes) are adjusted so as not to be reinjected.

According to such a structure, carriers are reinjected by the p ⁺ cathode layer 96 at the time of recovery, and the carriers can reliably remain on the cathode electrode 11 side of the n base layer 14 in the transition period. Thereby, for example, current oscillation or voltage oscillation is less likely to occur at the end of the recovery period 43. As a result, the generation of noise is further suppressed.

On the other hand, if carrier reinjection is excessive during recovery, recovery loss may increase and diode characteristics may deteriorate. In the fourth embodiment, carriers (holes) are used during recovery.
By providing the p ⁻ cathode layer 97 that does not reinject, the carrier reinjection amount at the time of recovery is optimized.

FIG. 30A is a schematic cross-sectional view illustrating a semiconductor device according to a second example of the fifth embodiment, and FIG. 30B illustrates a semiconductor device according to the third example of the fifth embodiment. It is a cross-sectional schematic diagram.

The semiconductor device 5b depicted in FIG. 30 (a) includes a first placement region ^{501 p +} cathode layer 96 is disposed, a second arrangement region ^{502 p +} cathode layer 97 is disposed, the. In the semiconductor device 5b, the distance d1 between adjacent p ⁺ anode layers 95 in the first arrangement region 501 is shorter than the distance d2 between adjacent p ⁺ anode layers 95 in the second arrangement region 502.

According to such a structure, holes injected from the p ⁺ cathode layer 96 at the time of recovery are efficiently emitted to the anode electrode 16 through the p ⁺ anode layer 95. This is because the distance d1 <
For the distance d2, the occupancy of the upper ^{p +} anode layer 95 of ^{p +} cathode layer 96 is p ^-
This is because the occupation rate of the p ⁺ anode layer 95 above the cathode layer 97 is higher.
Thereby, the recovery tolerance of the semiconductor device 5b is further improved.

Further, in the semiconductor device 5c shown in FIG. 30B, the effective impurity concentration of the p ⁺ anode layer 95 in the first arrangement region 501 is equal to the effective impurity concentration of the p ⁺ anode layer 95 in the second arrangement region 502. Higher than. That is, in the semiconductor device 5c, the effective impurity concentration of the p ⁺ anode layer 95 in the first arrangement region 501 is set higher than that of the semiconductor device 5b, and the hole resistance of the p ⁺ anode layer 95 is lowered.

As a result, holes injected from the p ⁺ cathode layer 96 are more efficiently emitted to the anode electrode 16 through the p ⁺ anode layer 95. As a result, the recovery tolerance of the semiconductor device 5c is further improved.

  FIG. 31 is a schematic perspective view illustrating a semiconductor device according to a fourth example of the fifth embodiment.

The semiconductor device 5d illustrated in FIG. 31 includes the p ⁺ anode layer 95a in the first arrangement region 501.
(8th semiconductor layer) is further provided. The p ⁺ anode layer 95a is in contact with the anode electrode 16,
At least a part other than the part in contact with the anode electrode 16 is surrounded by the p ⁺ anode layer 95. For example, the side of the ^{p +} anode layer 95a is surrounded by the ^{p +} anode layer 95. The effective impurity concentration of the p ⁺ anode layer 95a is higher than the effective impurity concentration of the p ⁺ anode layer 95.

The semiconductor device 5d further includes a p ⁺⁺ anode layer 95b in the first arrangement region 502. The p ⁺ anode layer 95 b is in contact with the anode electrode 16, and at least a part other than the portion in contact with the anode electrode 16 is surrounded by the p ⁺ anode layer 95. effective impurity concentration of the p ⁺ anode layer 95b is higher than the effective impurity concentration of the p ⁺ anode layer 95.

According to such a structure, the width of the p ⁺ anode layers 95a and 95b in the Y direction becomes narrower, and hole injection at the time of ON is further suppressed. This further increases the switching speed of the semiconductor device. At the time of recovery, holes injected from the p ⁺ cathode layer 96 are efficiently emitted to the anode electrode 16 through the p ⁺ anode layers 95a and 95b. Thereby, the recovery tolerance of the semiconductor device 5d is further improved.

Further, in the first arrangement region 501, the p ⁺ anode layer 95a is dispersed in the X direction as a plurality of p ⁺ layers. Thereby, the p ⁺ anode layer 9 in the first arrangement region 501 is obtained.
The ballast resistance on the lower side of 5 increases, and local concentration of hole current during recovery is suppressed.
As a result, the recovery tolerance of the semiconductor device 5d is further improved.

(Sixth embodiment)
FIG. 32A is a schematic cross-sectional view illustrating the semiconductor device according to the sixth embodiment.
(B) is a graph showing the impurity concentration profile of the semiconductor device of 6th Embodiment.
FIG. 32B shows an impurity concentration profile at the positions of the XX ′ cross section and the YY ′ cross section of FIG.

In the embodiment, an n cathode layer 13 is provided on the cathode side in addition to the n ⁺ cathode layer 12 in order to suppress the electron injection from the cathode side at the time of ON.

However, as in the impurity concentration profile 600 according to the reference example, when the impurity concentration in the n cathode layer 13 is gradually decreased from the cathode side toward the anode side, the depletion layer generated at the turn-off is excessively extended, and the depletion layer Reaches the cathode electrode 11. In this case, so-called punch-through occurs, and the breakdown voltage of the semiconductor device deteriorates.

On the other hand, in the semiconductor device 6, the impurity concentration in the n cathode layer 13 once increases from the cathode side toward the anode side, and then gradually decreases. For example, the n cathode layer 13 in the direction from the cathode electrode 11 toward the anode electrode 16 (Z direction)
The peak of the impurity concentration profile is located between the n ⁺ cathode layer 12 and the n base layer 14.

With such a structure, while the Schottky contact on the surface is maintained, the extension of the depletion layer generated at the time of turn-off is suppressed, and the depletion layer does not reach the cathode electrode 11. As a result, it is possible to prevent the breakdown voltage of the semiconductor device from deteriorating.

(Seventh embodiment)
In addition, each of the n ⁺ cathode layer 12 and the p ⁺ anode layer 95 may intersect in the extending direction.

FIG. 33A is a schematic perspective view illustrating the semiconductor device according to the first example of the seventh embodiment, and FIG. 33B illustrates the semiconductor device according to the second example of the seventh embodiment. It is a perspective schematic diagram.

For example, in the semiconductor device 7a shown in FIG. 33A, the direction in which the n ⁺ cathode layer 12 extends intersects with the direction in which the p ⁺ anode layer 95 extends. For example, the n ⁺ cathode layer 12 extends in the Y direction, and the p ⁺ anode layer 95 extends in the X direction orthogonal to the Y direction. The width Wn is larger than the width Wp.

Further, each of the n ⁺ cathode layer 12 and the p ⁺ anode layer 95 may be divided in the extending direction.

For example, in the semiconductor device 7b shown in FIG. 33B, the n ⁺ cathode layer 12 extending in the Y direction is interrupted. In addition, portions of the p ⁺ anode layer 95 extending in the X direction are interrupted.

Even with such a structure, the presence of the n-type cathode layer 13 on the cathode side and the presence of the p-type anode layer 17 on the anode side can suppress the amount of electron injection and hole injection at the on time. As a result, the switching operation becomes faster.

(Eighth embodiment)
Further, the junction between the p anode layer 17 and the n base layer 14 does not have to be flat, and a part of the junction may protrude toward the cathode. Here, the p anode layer 17 and the n base layer 14
The junction between the semiconductor and the p anode layer 17 and the n base layer 14 in the direction from the p anode layer 17 to the n base layer 14 is where the semiconductor conductivity is switched from p-type to n-type. .

FIG. 34 is a schematic cross-sectional view illustrating a semiconductor device according to the eighth embodiment.
For example, in the semiconductor device 8 shown in FIG. 34, the p anode layer 17 is replaced with the p anode layer 17.
c and p anode layer 17d. The positional relationship between the p ⁺ anode layer 95 and the n ⁺ cathode layer 12, the width Wn, and the width Wp are the same as those of the semiconductor device 2, for example.

In the semiconductor device 8, the junction A between the p anode layer 17c and the n base layer 14 is flat, but the junction B protrudes to the cathode side. That is, at least a part of the joint B is bent.

With this structure, if an avalanche current is generated during recovery,
This avalanche current is easily concentrated on the p anode layer 17d. This is because at least a part of the joint B is bent. The avalanche current is applied to the p anode layer 17d.
It is efficiently emitted to the anode electrode 16 via the p ⁺ anode layer 95 provided inside.
As a result, the recovery tolerance of the semiconductor device 8 is further improved.

(Ninth embodiment)
FIG. 35 is a schematic plan view of the semiconductor device according to the ninth embodiment.

FIG. 35 shows semiconductor devices 2, 2a, 2b, 2c, 3c, 3d, 4b, 5a, 5b, 5c.
A schematic plane of the semiconductor chip 900 including any one of 5d, 7a, 7b, and 8 is shown.

The semiconductor chip 900 includes an active region 901 and a peripheral region 902 that surrounds the active region 901.
And comprising. Here, the active region 901 is a region where the semiconductor device can function as an element (diode).

The total contact area Sn1 (cm ² ) where all n ⁺ cathode layers 12 in the active region 901 are in contact with the cathode electrode 11 is the total contact area Sp1 (cm ² ) in which all p ⁺ anode layers 95 in the active region 901 are in contact with the anode electrode 16. ² ) (Sn1> Sp1).

Further, the total contact area Sn2 (cm ² ) in which the n ⁺ cathode layer 12 in contact with the cathode electrode 11 in the unit area of the active region 901 is the total contact area Sp2 in which the p ⁺ anode layer 95 in contact with the anode electrode 16 in the unit area ( cm ² ) (Sn2> Sp2).

Further, the occupation ratio Pn1 (%) of all the n ⁺ cathode layers 12 in the active region 901 is larger than the occupation ratio Pp1 (%) of all the p ⁺ anode layers 95 in the active region 901 (P
n1> Pp1). Here, the occupation ratio of the part B in a certain area A is a percentage obtained by dividing the area occupied by all the parts B in the area A in the area A by the area of the area A.

In addition, the occupation rate Pn2 (%) of the n ⁺ cathode layer 12 in the unit area of the active region 901 is larger than the occupation rate Pp2 (%) of the p ⁺ anode layer 95 in the unit area (Pn2>).
Pp2).

Further, an arbitrary region 903 is selected from the active region 901. The arbitrary region 903 is, for example, a 100 μm square region selected at random from within the active region 901. Region 90
3, the semiconductor device of this embodiment is disposed.

The total contact area Sn′1 (cm ² ) in which all the n ⁺ cathode layers 12 in the region 903 are in contact with the cathode electrode 11 is that all the p ⁺ anode layers 95 in the region 903 are the anode electrode 1.
6 is larger than the total contact area Sp′1 (cm ² ) in contact with 6 (Sn′1> Sp′1).

In addition, the occupation ratio Pn′1 (%) of all the n ⁺ cathode layers 12 in the region 903 is larger than the occupation ratio Pp′1 (%) of all the p ⁺ anode layers 95 in the region 903 (Pn ′).
1> Pp′1).

In addition, each of Pp1, Pp2, and Pp′1 is 20% or less, and preferably 10% or less. Each of Pn1, Pn2, and Pn′1 is 20%
Greater than.

(10th Embodiment)
Next, a semiconductor device according to a tenth embodiment will be described. In the present embodiment, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Trans) including a pin diode structure is provided.
istor: metal oxide semiconductor field effect transistor). The above-described diode structure and dimensions of each part can also be applied to the MOSFET.

FIG. 36 is a schematic cross-sectional view illustrating the semiconductor device according to the tenth embodiment.
FIG. 37A is a schematic plan view of the semiconductor device according to the tenth embodiment, excluding the gate electrode, the source electrode, and the insulating film along the line AA ′ shown in FIG. 36, and FIG. 36 is a schematic plan view excluding the drain electrode 31 taken along line BB ′ shown in FIG.

As shown in FIGS. 36, 37A, and 37B, the semiconductor device 9 includes a drain electrode 31, an n ⁺ drain layer 32 (first drain layer), and an n drain layer 33 (second drain layer). )
, N base layer 34 (first base layer), p base layer 35 (second base layer), n source layer 37
A source electrode 36, a gate electrode 38, and an insulating film 39 are provided. The semiconductor device 9 is
For example, a MOSFET having an upper and lower electrode structure. That is, n ⁺ drain layer 32 (first drain layer), n drain layer 33 (second drain layer), n base layer 34 (first base layer), p base layer 35 (second base layer), n source layer 37, the source electrode 36, the gate electrode 38, and the insulating film 39 are provided between the drain electrode 31 and the source electrode 36.

The drain electrode 31 contains a metal, for example, aluminum. The shape of the drain electrode 31 is, for example, a plate shape. On the drain electrode 31, for example, on the plate surface of the drain electrode 31, a plurality of n ⁺ drain layers 32 are arranged to be separated from each other.

For example, the n ⁺ drain layer 32 has a rectangular parallelepiped shape extending in one direction on the drain electrode 31. Region 3 in contact with each n ⁺ drain layer 32 in the drain electrode 31
1a also extends in one direction. The width Wn of each n ⁺ drain layer 32 and the width Wn of each region 31a are, for example, 100 micrometers (μm) or less. The thickness of each n ⁺ drain layer 32 is, for example, 5 micrometers (μm) or less.

The interval between each n ⁺ drain layer 32 and each region 31a is, for example, 50 micrometers (μ
m) or less. The n ⁺ drain layer 32 includes a semiconductor, for example, silicon. n ⁺
The drain layer 32 contains an impurity serving as a donor, for example, phosphorus. The conductivity type of the n ⁺ drain layer 32 is n-type (first conductivity type). The effective impurity concentration in the n ⁺ drain layer 32 is higher than 3 × 10 ¹⁷ cm ⁻³ , for example, 1 × 10 ¹⁹ cm ⁻³ or more. Since the drain electrode 31 contains aluminum and the effective impurity concentration in the n ⁺ drain layer 32 is higher than 3 × 10 ¹⁷ cm ⁻³ , the drain electrode 31 and the n ⁺ drain layer 32 are in ohmic contact. Yes.

The n drain layer 33 is disposed on the n ⁺ drain layer 32 and the drain electrode 31.
Therefore, the n drain layer 33 includes a portion 33 a disposed on the n ⁺ drain layer 32 and a portion 33 b in contact with the drain electrode 31. The thickness of the portion 33b in contact with the drain electrode 31 in the n drain layer 33 is several to several tens of micrometers (μm), for example, 1 to 20 micrometers (μm), or 0.5 to 20 μm.

The n drain layer 33 includes a semiconductor, for example, silicon. The n drain layer 33 contains an impurity serving as a donor, for example, phosphorus. The conductivity type of the n drain layer 33 is
n-type. The effective surface impurity concentration in the n drain layer 33 is n ⁺ drain layer 3.
2 is lower than the effective surface impurity concentration. The surface concentration of phosphorus in the n drain layer 33 is, for example, 3 × 10 ¹⁷ cm ⁻³ or less. The drain electrode 31 contains aluminum, and the effective surface impurity concentration of the n drain layer 33 is 3 × 10 ¹⁷ cm ^−3.
Since it is below, the drain electrode 31 and the n drain layer 33 are in Schottky contact.

The n base layer 34 is disposed on the n drain layer 33. The thickness of the n base layer 34 is
For example, it is 10-500 micrometers (micrometer), and is designed according to the proof pressure of an element. The n base layer 34 includes a semiconductor, for example, silicon. The n base layer 34 contains an impurity serving as a donor, for example, phosphorus. The conductivity type of the n base layer 34 is n type. The effective impurity concentration in the n base layer 34 is lower than the effective impurity concentration in the n drain layer 33.

On the n base layer 34, a plurality of p base layers 35 are arranged apart from each other. Each p
The base layer 35 has a shape extending in one direction on the n base layer 34. An upper portion of the n base layer 34 is sandwiched between the p base layers 35. The lower side and the side of the p base layer 35 are in contact with the n base layer 34.

The thickness of the p base layer 35 is several micrometers (μm), for example, 1 to 5 micrometers (μm). The p base layer 35 includes a semiconductor, for example, silicon. The p base layer 35 contains an impurity serving as an acceptor, for example, boron. The conductivity type of the p base layer 35 is p-type. The effective impurity surface concentration in the p base layer 35 is larger than 3 × 10 ¹⁷ cm ⁻³ , for example, 5 × 10 ¹⁷ cm ⁻³ or more.

The n source layer 37 is disposed on the p base layer 35. The n source layer 37 has a shape extending in one direction on the p base layer 35. The lower and lateral sides of the n source layer 37 are in contact with the p base layer 35. The thickness of the n source layer 37 is 0.1 to several micrometers (μm), for example, 0.5 micrometers (μm). The n source layer 37 includes a semiconductor, for example, silicon. In the n source layer 37, an impurity serving as a donor, for example,
Contains phosphorus or arsenic. The conductivity type of the n source layer 37 is n-type. n source layer 3
7 has an effective surface concentration of impurities higher than 3 × 10 ¹⁷ cm ⁻³ , for example, 1
X10 ¹⁹ cm ⁻³ or more.

The n ⁺ drain layer 32, the n drain layer 33, the n base layer 34, the p base layer 35, and the n source layer 37 constitute a semiconductor layer 30. For example, the upper surface of the semiconductor layer 30 is constituted by the upper surface of the n source layer 37, the upper surface of the p base layer 35, and the upper surface of the n base layer 34. On the upper surface of the semiconductor layer 30, the upper surface of the n base layer 34 extends in one direction. A p base layer 35 is exposed on both sides of the n base layer 34 on the upper surface of the semiconductor layer 30. On the upper surface of the semiconductor layer 30, the n source layer 3 is disposed on the opposite side of the p base layer 35 from the n base layer 34.
7 is exposed. On the upper surface of the semiconductor layer 30, the p base layer 35 is exposed on both sides of the n source layer 37.

The gate electrode 38 is disposed on the semiconductor layer 30. For example, the gate electrode 38 has a plate shape extending in one direction on the semiconductor layer 30. The gate electrode 38 is disposed on the upper surface of the semiconductor layer 30 where the n base layer 34 is exposed. Both end portions of the gate electrode 38 in a direction orthogonal to one direction reach the n source layer 37. Therefore, the n base layer 34, the p base layer 35, and the n source layer 37 are exposed in the semiconductor layer 30 immediately below the gate electrode 38.

The source electrode 36 is disposed on the semiconductor layer 30 and the gate electrode 38. The source electrode 36 contains a metal, for example, aluminum. Source electrode 36 and n source layer 3
7 and the p base layer 35 are in ohmic contact.

An insulating film 39 is disposed between the gate electrode 38 and the source electrode 36 and between the gate electrode 38 and the semiconductor substrate 30. That is, the insulating film 39 is disposed between the gate electrode 38 and the n base layer 34, between the gate electrode 38 and the p base layer 35, and between the gate electrode 38 and the n source layer 37. A portion of the insulating film 39 between the gate electrode 38 and the semiconductor substrate 30 is referred to as a gate insulating film. The insulating film 39 includes, for example, silicon dioxide.

In the semiconductor device 9, the configurations shown in FIGS. 36, 37 (a), and 37 (b) are repeatedly arranged.

Next, the operation of the semiconductor device 9 according to this embodiment will be described.
A voltage having the source electrode 36 side as a positive electrode is applied between the source electrode 36 and the drain electrode 31. In the semiconductor device 9, there are an n ⁺ drain layer 32, an n drain layer 33, and an n base layer 3.
4 and a diode including the p base layer 35 as a constituent element. Therefore, since a forward bias is applied to the diode, the source electrode 3 is, for example, at the time of reflux.
A current can flow from 6 toward the drain electrode 31.

Further, by applying a voltage higher than the threshold to the gate electrode 38 of the semiconductor device 9, p
An inversion layer is formed on the base layer 35. And between the source electrode 36 and the drain electrode 31,
A voltage having a positive electrode on the drain electrode 31 side is applied. As a result, a current can flow from the drain electrode 31 toward the source electrode 36.

Next, the effect of this embodiment will be described.
In the present embodiment, by forming the n drain layer 33 and the n ⁺ drain layer 32, the carrier concentration on the drain electrode 31 side is reduced. Therefore, the pin diode built in the MOSFET is driven at higher speed. Further, since the speed can be increased without introducing a lifetime killer, high temperature operation can be improved. The effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

(First Modification of Tenth Embodiment)
Next, a semiconductor device according to a first modification of the tenth embodiment will be described. In the present embodiment, a MOSFET (Metal-Oxide-Semiconductor Field-
Effect Transistor: Metal oxide semiconductor field effect transistor).

FIG. 38 is a schematic cross-sectional view illustrating a semiconductor device according to a first modification of the tenth embodiment.

FIG. 39A is a schematic plan view of the semiconductor device according to the first modification of the tenth embodiment, excluding the gate electrode, the source electrode, and the insulating film along the line AA ′ shown in FIG.
FIG. 39B is a schematic plan view excluding the drain electrode along the line BB ′ shown in FIG.

As shown in FIGS. 38, 39 (a) and 39 (b), the semiconductor device 9 includes a drain electrode 31, an n ⁺ drain layer 32, an n drain layer 33, an n base layer 34, a p base layer 35, n
^{In addition to the +} source layer 37, the gate electrode 38, the insulating film 39, and the source electrode 36, a p ⁺ contact layer 99 is provided. The semiconductor device 9a is, for example, a MOSFET.

The p ⁺ contact layer 99 is disposed on each p base layer 35. In addition, the p ⁺ contact layer 99 is disposed adjacent to, for example, the end of the n ⁺ source layer 37 opposite to the end covered with the gate electrode 38. The p ⁺ contact layer 99 has, for example, a rectangular parallelepiped shape extending in one direction. The thickness of the p ⁺ contact layer 99 is 0.1 to several micrometers (μm), for example, 0.5 micrometers (μm).

The p ⁺ contact layer 99 includes a semiconductor, for example, silicon. The p ⁺ contact layer 99 contains an impurity serving as an acceptor, for example, boron. The conductivity type of the p ⁺ contact layer 99 is p-type (second conductivity type). The effective impurity surface concentration in the p ⁺ contact layer 99 is higher than 3 × 10 ¹⁷ cm ⁻³ , for example, 1 × 10 ¹⁹ cm ^−.
3 or more. Further, the effective impurity surface concentration in the p base layer 35 is 3 × 1.
0 ¹⁷ cm ⁻³ or less.

The n ⁺ drain layer 32, n drain layer 33, n base layer 34, p base layer 35, n source layer 37 and p ⁺ contact layer 99 constitute a semiconductor layer 30. For example, the upper surface of the semiconductor layer 30 is constituted by the upper surface of the n source layer 37, the upper surface of the p base layer 35, the upper surface of the n base layer 34, and the upper surface of the p ⁺ contact layer 99. On the upper surface of the semiconductor layer 30, the upper surface of the n base layer 34 extends in one direction. A p base layer 35 is exposed on both sides of the n base layer 34 on the upper surface of the semiconductor layer 30. On the upper surface of the semiconductor layer 30, an n source layer 37 is exposed on the opposite side of the p base layer 35 from the n base layer 34. Semiconductor layer 30
P ⁺ contact layer 99 on the opposite side of the n source layer 37 to the p base layer 35.
Is exposed.

In the semiconductor device 9a, the configurations shown in FIGS. 38, 39A, and 39B are repeatedly arranged. The upper surface of the p ⁺ contact layer 99 is in contact with the source electrode 36 between the adjacent gate electrodes 38. The p base layer 35 has a portion in contact with the source electrode 36 (not shown). The effective surface impurity concentration in the p ⁺ contact layer 99 is 3 ×
Since it is higher than 10 ¹⁷ cm ⁻³ , the source electrode 36 and the p ⁺ contact layer 99 are in ohmic contact. The effective surface impurity concentration in the p base layer 35 is 3 × 10 ^17.
Since it is cm ⁻³ or less, the source electrode 36 and the p base layer 35 are in Schottky contact.

The p ⁺ contact layer 99 may be part of the second base layer described above. That is, the second base layer includes a p base layer 35 having a low impurity concentration (first portion of the second base layer) and a p ⁺ contact layer 99 having a high impurity concentration (second portion of the second base layer). ,including.

Next, the operation and effect of this modification will be described.
In this modification, since the anode structure is the same as that of the semiconductor device 2 according to the second embodiment, the amount of holes injected from the anode side can be controlled, so that high speed can be realized. In addition to this, the p ⁺ contact layer 99 has a function of discharging holes. This allows, for example,
When the bias is changed from the forward direction to the reverse direction, holes can be made to flow quickly to the source electrode 36 via the n base layer 34, the p base layer 35, and the p ⁺ contact layer 99. . Operations and effects other than those described above in the present modification are the same as those in the tenth embodiment described above.

(Second Modification of Tenth Embodiment)
Next, a second modification of the tenth embodiment will be described.
A schematic cross-sectional view illustrating a semiconductor device according to this variation is the same as FIG. 38 of the first variation of the tenth embodiment described above.

FIG. 40A is a schematic plan view of the semiconductor device according to the second modification of the tenth embodiment, excluding the gate electrode, the source electrode, and the insulating film along the line AA ′ shown in FIG.
FIG. 39B is a schematic plan view excluding the drain electrode 31 by BB ′ shown in FIG.

As shown in FIGS. 40A and 40B, in this modification, the p ⁺ contact layer 9
9 is arranged on a part of the upper surface of the semiconductor layer 30 on the side opposite to the p base layer 35 of the n source layer 37. A p base layer 35 is disposed on both sides of the p ⁺ contact layer 99 in one direction. In this modification, since the hole injection of the diode built in the MOSFET can be further suppressed, the switching characteristics of the diode can be improved as compared with the second modification of the tenth embodiment and the tenth embodiment. . Other configurations, operations, and effects are the same as those in the tenth embodiment.

Note that the structure of the MOSFET is not limited to the structure described above.
For example, in FIGS. 36 and 38, the p ⁺ cathode layer 25 illustrated in FIG. 22 may be provided on the drain electrode 31. However, in the MOSFET, the p ⁺ cathode layer 25 is “
The term “p ⁺ drain layer 25 (third drain layer)” is used instead. p ⁺ drain layer 25
Is in ohmic contact with the drain electrode 31. The n drain layer 33 is provided on the drain electrode 31, the n ⁺ drain layer 32, and the p ⁺ drain layer 25. The n drain layer 33 has a portion that contacts the drain electrode 31 and a portion that contacts the p ⁺ drain layer 25 and the n ⁺ drain layer 32.

The effective impurity concentration contained in the p ⁺ drain layer 25 is the same as the impurity concentration of the p ⁺ cathode layer 25. The p ⁺ drain layer 25 and the n ⁺ drain layer 32 may be arranged in contact with each other or may be arranged apart from each other like the p ⁺ cathode layer 25 and the n ⁺ cathode layer 12. .

According to the embodiment described above, it is possible to provide a semiconductor device capable of improving electrical characteristics. Moreover, although the above numerical examples are based on silicon materials, SiC and Ga
The characteristics can be improved by applying the structure according to the present invention to a diode using a material other than silicon, such as N material, by appropriately changing numerical values.

As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and without departing from the spirit of the invention,
Various omissions, replacements, and changes can be made. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

1, 1a, 2, 2a, 2b, 2c, 3a, 3b, 3c, 3d, 4a, 4b, 5a, 5b
5c, 5d, 6, 7a, 7b, 8, 9, 101: semiconductor device, 10: semiconductor layer, 11:
Cathode electrode, 11a, 11b, 16a, 16b, 31a: region, 12, 92: n ⁺ cathode layer, 13, 98: n cathode layer, 13a, 13b, 13c, 17a, 17b, 33a
33b: part, 13h: hole, 14: n base layer, 15, 95, 95a, 95b: p ⁺
Anode layer, 16: anode electrode, 17, 17c, 17d: p anode layer, 18: electron current,
19: hole current, 20, 120: carrier distribution, 25: p ⁺ cathode layer, 30: semiconductor layer,
31: drain electrode, 32: n ⁺ drain layer, 33: n drain layer, 34: n base layer,
35: p base layer, 36: source electrode, 37: n source layer, 38: gate electrode, 39: insulating film, 42: Fermi level, 43: recovery period, 44: tail period, 96, 96a,
96b: p ⁺ sucking layer (p ⁺ cathode layer), 97: p ⁻ cathode layer, 99: p ⁺ contact layer,
501: First arrangement region, 502: Second arrangement region, 600: Impurity concentration profile, CB
: Conduction band, D11, D16: interval, E _rr : switching loss, L1, L2, L3, L4
: Solid line, R11, R16: radius, VB: valence band, Sn, Sp: area, Wn, Wp: width,
VF: forward voltage

Claims (2)

A first electrode;
A second electrode;
A plurality of first semiconductor layers of a first conductivity type provided between the first electrode and the second electrode and in ohmic contact with the first electrode;
At least one first region in contact with the first electrode and the first semiconductor layer;
A second semiconductor layer of a first conductivity type located partially between the adjacent first semiconductor layers, in Schottky contact with the first electrode, and provided between the first electrode and the second electrode When,
A third semiconductor layer of a first conductivity type provided between the second semiconductor layer and the second electrode and having an effective impurity concentration lower than an effective impurity concentration of the second semiconductor layer;
A fourth semiconductor layer of a second conductivity type provided between the third semiconductor layer and the second electrode and in contact with the second electrode;
A second conductivity type second electrode provided between the third semiconductor layer and the second electrode and in contact with the second electrode, wherein the effective impurity concentration is higher than the effective impurity concentration of the fourth semiconductor layer. 5 semiconductor layers;
At least one second region in contact with the second electrode and the fifth semiconductor layer;
With
In a direction parallel to the upper surface of the first electrode, the width of the first semiconductor layer is longer than the width of the fifth semiconductor layer,
A semiconductor device in which an area obtained by summing up the areas of the first regions is larger than an area obtained by summing up the areas of the second regions .   The semiconductor device according to claim 1, wherein the fifth semiconductor layer is located on the first semiconductor layer in a direction perpendicular to an upper surface of the first electrode.

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