JP6283709B2 - Semiconductor device - Google Patents

Description

  The technology disclosed in this specification relates to a semiconductor device.

  A semiconductor device often includes a trench type or planar type insulated gate portion. In such a semiconductor device, the electric field concentrates on the gate insulating film at the drain side end of the insulated gate. In Patent Document 1, in order to alleviate such electric field concentration, a p-type electric field relaxation region is formed so as to be in contact with the bottom portion of the trench-type insulated gate portion, that is, the gate insulating film at the drain side end portion of the insulated gate portion. The technique to provide is disclosed. The electric field relaxation region can relieve the electric field concentrated on the gate insulating film at the drain side end of the insulated gate portion.

Japanese Patent Laid-Open No. 10-98188

  However, even if the electric field relaxation region is provided, there is a concern that the gate insulating film may be broken down due to the electric field concentrated on the gate insulating film at the drain side end of the insulating gate portion, thereby reducing the reliability of the semiconductor device. . It is an object of the present specification to provide a highly reliable semiconductor device in which breakdown of a gate insulating film is suppressed.

  One embodiment of a semiconductor device disclosed in this specification includes a semiconductor substrate and an insulated gate portion. The semiconductor substrate has a first conductivity type drain region, a first conductivity type drift region, a second conductivity type body region, a first conductivity type source region, and a second conductivity type electric field relaxation region, The drain region, the drift region, the body region, and the source region are arranged in this order. The insulated gate portion has a gate insulating film and a first conductivity type gate electrode. The gate insulating film is in contact with the drift region, the body region, and the source region. The gate electrode opposes at least a body region located between the drift region and the source region via a gate insulating film. The electric field relaxation region is disposed closer to the drain region than the gate insulating film, is in contact with the gate electrode and the drift region, and separates the gate electrode and the drift region.

  One feature of the semiconductor device of the above embodiment is that the electric field relaxation region is arranged on the drain region side of the gate insulating film and is in contact with the drift region and the gate electrode. For this reason, the semiconductor device of the above embodiment is configured such that the gate insulating film existing at the drain side end of the conventional structure is replaced with the electric field relaxation region. As described above, in the semiconductor device of the above embodiment, since the gate insulating film does not exist at a place where electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film is suppressed. One feature of the semiconductor device of the above embodiment is that the gate electrode is of the first conductivity type. Thus, a pair of diodes are formed in which the first conductivity type drift region, the second conductivity type electric field relaxation region, and the first conductivity type gate electrode are connected in opposite directions. For this reason, in the semiconductor device of the above-described embodiment, even when the gate insulating film is partially replaced with the electric field relaxation region, the leakage current is suppressed and stable on and off operations are performed. Can do.

FIG. 2 schematically shows a cross-sectional view of the main part of the semiconductor device of Example 1; The principal part sectional drawing of the semiconductor device of the modification of Example 1 is shown typically. The principal part sectional drawing of the semiconductor device of the modification of Example 1 is shown typically. The principal part sectional drawing of the semiconductor device of Example 2 is shown typically.

  The technical features disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

  As a semiconductor device disclosed in this specification, a vertical or horizontal MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is exemplified. One embodiment of a semiconductor device disclosed in this specification may include a semiconductor substrate and an insulated gate portion. The semiconductor substrate has a first conductivity type drain region, a first conductivity type drift region, a second conductivity type body region, a first conductivity type source region, and a second conductivity type electric field relaxation region, The drain region, the drift region, the body region, and the source region are arranged in this order. When the semiconductor device is a vertical type, the drain region, the drift region, the body region, and the source region are arranged in this order along the thickness direction of the semiconductor substrate. When the semiconductor substrate is a horizontal type, the drain region, the drift region, the body region, and the source region are arranged in this order along the surface direction of the semiconductor substrate. If necessary, other semiconductor regions may be interposed between these semiconductor regions. The insulated gate portion has a gate insulating film and a first conductivity type gate electrode. The gate insulating film is in contact with the drift region, the body region, and the source region. The gate electrode opposes at least a body region located between the drift region and the source region via a gate insulating film. The electric field relaxation region is disposed closer to the drain region than the gate insulating film, is in contact with the gate electrode and the drift region, and separates the gate electrode and the drift region.

  In one embodiment of the semiconductor device, the gate electrode may include a high concentration gate electrode having a relatively high impurity concentration and a low concentration gate electrode having a relatively low impurity concentration. In this case, the high-concentration gate electrode faces the entire range of the body region located between the drift region and the source region via the gate insulating film. Further, a low concentration gate electrode is provided between the electric field relaxation region and the high concentration gate electrode. According to this aspect, the high-concentration gate electrode can face the region of the body region where the inversion layer is formed. Therefore, when the semiconductor device is on, a sufficient electric field can be applied to the body region, a high-density inversion layer is formed in the body region, and a low channel resistance is realized.

  In one embodiment of the semiconductor device, the drain region, the drift region, the body region, and the source region are arranged in this order along the thickness direction of the semiconductor substrate, and may be a vertical type. In this case, the insulated gate portion is provided in a trench that penetrates the source region and the body region from the surface of the semiconductor substrate and enters the drift region. The gate insulating film covers the side surface of the trench. The gate electrode is exposed on the bottom surface of the trench. The electric field relaxation region is in contact with the gate electrode exposed on the bottom surface of the trench. According to this aspect, since the gate insulating film does not exist at the bottom of the insulating gate part, that is, the drain side end of the insulating gate part, the dielectric breakdown of the gate insulating film is suppressed.

  As shown in FIG. 1, the semiconductor device 1 is a power semiconductor element called MOSFET, and includes a semiconductor substrate 10, a drain electrode 22 covering the back surface of the semiconductor substrate 10, and a source electrode covering the surface of the semiconductor substrate 10. 24 and a trench type insulated gate portion 30 provided in the surface layer portion of the semiconductor substrate 10.

The semiconductor substrate 10 is a substrate made of silicon carbide (SiC), and includes an n ⁺ type drain region 11, an n ⁻ type drift region 12, a p type body region 13, a p ⁺ type body contact region 14, It has an n ⁺ type source region 15 and a p ⁺ type electric field relaxation region 16. The drain region 11, the drift region 12, the body region 13, and the source region 15 are arranged in this order along the thickness direction of the semiconductor substrate 10.

The drain region 11 is disposed in the back layer portion of the semiconductor substrate 10 and is exposed on the back surface of the semiconductor substrate 10. The drain region 11 is also a base substrate for the drift region 12 to grow epitaxially. The drain region 11 is in ohmic contact with the drain electrode 22 that coats the back surface of the semiconductor substrate 10. In one example, the drain region 11 preferably has a thickness of about 1 to 300 μm and an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ⁻³ .

The drift region 12 is provided on the drain region 11. The drift region 12 is in contact with the side surface of the insulated gate portion 30. The drift region 12 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique. In one example, it is desirable that the drift region 12 has a thickness of about 5 to 200 μm and an impurity concentration of about 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ⁻³ .

The body region 13 is provided on the drift region 12 and is disposed on the surface layer portion of the semiconductor substrate 10. Body region 13 is in contact with the side surface of insulated gate portion 30. Body region 13 is formed by crystal growth from the surface of drift region 12 using an epitaxial growth technique. In one example, it is desirable that the body region 13 has a thickness of about 1 to 5 μm and an impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

The body contact region 14 is provided on the body region 13, is disposed on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. The body contact region 14 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 10 using an ion implantation technique. The body contact region 14 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. In one example, the body contact region 14 has a dose amount of about 1 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² and a peak concentration of about 1 × 10 ¹⁹ to 2 × 10 ²⁰ cm ^−3. desirable.

The source region 15 is provided on the body region 13, is disposed on the surface layer portion of the semiconductor substrate 10, and is exposed on the surface of the semiconductor substrate 10. Source region 15 is separated from drift region 12 by body region 13. The source region 15 is in contact with the side surface of the insulated gate portion 30. The source region 15 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 10 using an ion implantation technique. The source region 15 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor substrate 10. In one example, the source region 15 preferably has a dose of about 1 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² and a peak concentration of about 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ^−3. .

The insulated gate portion 30 extends from the surface of the semiconductor substrate 10 toward the deep portion, and includes a gate insulating film 32 and a gate electrode 34. The insulated gate portion 30 is provided in a trench 30T that penetrates the source region 15 and the body region 13 and enters a part of the drift region 12. The gate insulating film 32 covers the side surface of the trench 30T and is made of silicon oxide. The gate insulating film 32 is formed by forming a trench 30T in the surface layer portion of the semiconductor substrate 10 and then selectively depositing the trench 30T on a side surface of the trench 30T using a vapor deposition technique. The gate electrode 34 is separated from the source region 15, the body region 13 and the drift region 12 by the gate insulating film 32, and is made of n ⁻ type polysilicon. In particular, the gate electrode 34 is opposed to the body region 13 located between the drift region 12 and the source region 15, and is configured to form an inversion layer in this opposed portion. The gate electrode 34 is exposed on the bottom surface of the trench 30 </ b> T and is in contact with the electric field relaxation region 16. In one example, the gate electrode 34 preferably has an impurity concentration of about 1 × 10 ¹³ to 1 × 10 ¹⁷ cm ⁻³ .

The electric field relaxation region 16 is disposed corresponding to the bottom of the insulating gate portion 30, is disposed closer to the drain region 11 than the gate insulating film 32, and is separated from the drain region 11 and the body region 13 by the drift region 12. It has been. The electric field relaxation region 16 is disposed between the drift region 12 and the gate electrode 34, is in contact with the drift region 12 and the gate electrode 34, and separates the drift region 12 and the gate electrode 34. As described above, the n ⁻ type drift region 12, the p ⁺ type electric field relaxation region 16, and the n ⁻ type gate electrode 34 are continuously arranged. Thereby, the drift region 12 and the electric field relaxation region 16 constitute one diode, and the electric field relaxation region 16 and the gate electrode 34 constitute one diode, and these diodes are arranged in the opposite directions. The electric field relaxation region 16 is formed by forming the trench 30T in the surface layer portion of the semiconductor substrate 10 and then selectively depositing it on the bottom surface of the trench 30T using an epi growth technique. In one example, it is desirable that the electric field relaxation region 16 has a thickness of about 0.1 to 2 μm and an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ⁻³ .

  Next, the operation of the semiconductor device 1 will be described. When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 34 of the insulated gate portion 30 is grounded, the semiconductor device 1 is off. At this time, in the semiconductor device 1, since a reverse bias is applied to the diode constituted by the drift region 12 and the electric field relaxation region 16, the depletion layer extends from the pn junction between the drift region 12 and the electric field relaxation region 16. For this reason, the drain electrode 22 and the gate electrode 34 are insulated from each other, and the leakage current between the drain electrode 22 and the gate electrode 34 is suppressed. Therefore, the semiconductor device 1 can perform a stable off operation. Further, the electric field at the bottom of the insulating gate portion 30 is relaxed by the depletion layer extending from the pn junction between the drift region 12 and the electric field relaxation region 16. In particular, in the semiconductor device 1, the gate insulating film 32 is not provided on the bottom of the insulating gate portion 30. The bottom of the insulated gate 30, that is, the drain side end of the insulated gate 30 is a place where electric field concentration tends to occur. In the semiconductor device 1, since the gate insulating film 32 does not exist in the place where electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film 32 is suppressed. As described above, the semiconductor device 1 can have high reliability because the dielectric breakdown of the gate insulating film 32 of the insulating gate portion 30 is suppressed.

  When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage that is more positive than the source electrode 24 is applied to the gate electrode 34 of the insulated gate portion 30, the semiconductor device 1 is on. At this time, in the semiconductor device 1, since a reverse bias is applied to the diode composed of the electric field relaxation region 16 and the gate electrode 34, the depletion layer extends from the pn junction between the electric field relaxation region 16 and the gate electrode 34. For this reason, the drain electrode 22 and the gate electrode 34 are insulated from each other, and the leakage current between the drain electrode 22 and the gate electrode 34 is suppressed. Therefore, the semiconductor device 1 can perform a stable on operation.

  As described above, the semiconductor device 1 can perform a stable on-operation and off-operation, and can suppress the dielectric breakdown of the gate insulating film 32 and have high reliability. Further, in the semiconductor device 1, since the gate insulating film 32 does not exist at the bottom of the insulating gate portion 30, the feedback capacitance is extremely small and the switching speed is improved.

FIG. 2 shows a modified semiconductor device 2. The gate electrode 34 of the semiconductor device 2 includes a high concentration gate electrode 34a having a relatively high impurity concentration and a low concentration gate electrode 34b having a relatively low impurity concentration. The high concentration gate electrode 34a is disposed in the upper portion of the trench 30T, and the low concentration gate electrode 34b is disposed in the lower portion of the trench 30T. The boundary between the high-concentration gate electrode 34a and the low-concentration gate electrode 34b is preferably at the same depth as the boundary depth between the drift region 12 and the body region 13 or at a position deeper than the boundary depth. In other words, the high-concentration gate electrode 34a faces the entire body region 13 located between the drift region 12 and the source region 15 with the gate insulating film 32 interposed therebetween, and the low-concentration gate electrode 34b is opposed to the electric field relaxation region 16. And the high-concentration gate electrode 34a. In one example, the high concentration gate electrode 34a preferably has an impurity concentration of about 1 × 10 ¹⁸ to 1 × 10 ²³ cm ⁻³ , and the low concentration gate electrode 34b has an impurity concentration of about 1 × 10 ¹³ to 1 × 10 ^17. Desirably it is cm ⁻³ .

  In the semiconductor device 2, the depletion layer extending from the pn junction between the electric field relaxation region 16 and the low-concentration gate electrode 34b is suppressed from extending deeply into the high-concentration gate electrode 34a when turned on. For this reason, in the semiconductor device 2, since a constant gate voltage is applied over the entire high concentration gate electrode 34 a, a sufficient electric field can be applied to the body region 13. For this reason, a high-density inversion layer is formed over the entire range of the body region 13 located between the drift region 12 and the source region 15, and a low channel resistance is realized. In order to obtain such an effect, a low-resistance conductor may be provided in the upper portion of the trench 30T. For example, a metal may be used instead of the high-concentration gate electrode 34a.

  FIG. 3 shows a modified semiconductor device 3. The electric field relaxation region 16 of the semiconductor device 3 is configured as a diffusion region. The electric field relaxation region 16 is formed by forming the trench 30T in the surface layer portion of the semiconductor substrate 10 and then introducing aluminum or boron into the bottom surface of the trench 30T using an ion implantation technique. The electric field relaxation region 16 configured as a diffusion region covers the drain side end portion of the gate insulating film 32 covering the side surface of the trench 30T. For this reason, the electric field concentration of the gate insulating film 32 in this portion can be relaxed, and the dielectric breakdown of the gate insulating film 32 in this portion can be suppressed. The semiconductor device 3 can have higher reliability.

  As shown in FIG. 4, the semiconductor device 4 is a power semiconductor element called a MOSFET, and includes a semiconductor substrate 100, a drain electrode 122 covering a part of the surface of the semiconductor substrate 100, and a surface of the semiconductor substrate 100. And a planar type insulated gate part 130 which is a part of the surface of the semiconductor substrate 100 and is disposed between the drain electrode 122 and the source electrode 124.

The semiconductor substrate 100 is a substrate made of silicon carbide (SiC), and includes an n ⁺ type drain region 111, an n ⁻ type drift region 112, a p type body region 113, a p ⁺ type body contact region 114, An n ⁺ -type source region 115 and a p ⁺ -type electric field relaxation region 116 are included. The drain region 111, the drift region 112, the body region 113, and the source region 115 are arranged in this order along the surface direction of the semiconductor substrate 10.

  The drain region 111 is disposed on the surface layer portion of the semiconductor substrate 100 and is exposed on the surface of the semiconductor substrate 100. The drain region 111 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique. The drain region 111 is in ohmic contact with the drain electrode 122 that coats the surface of the semiconductor substrate 100.

  The drift region 112 is provided between the drain region 111 and the body region 113 and is exposed on the surface of the semiconductor substrate 100. The drift region 112 is in contact with the lower surface of the insulated gate portion 130. The drift region 112 is configured as a remaining portion in which another semiconductor region of the semiconductor substrate 100 is formed.

  The body region 113 is disposed on the surface layer portion of the semiconductor substrate 10, is provided between the drift region 112 and the source region 115, and is exposed on the surface of the semiconductor substrate 100. Body region 113 is in contact with the lower surface of insulated gate portion 130. The body region 113 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique.

  The body contact region 114 is provided on the body region 113, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. The body contact region 114 is formed by introducing aluminum or boron into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique. The body contact region 114 is in ohmic contact with the source electrode 124 that coats the surface of the semiconductor substrate 100.

  The source region 115 is provided on the body region 113, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. Source region 115 is separated from drift region 112 by body region 113. The source region 115 is in contact with the lower surface of the insulated gate portion 130. The source region 115 is formed by introducing nitrogen or phosphorus into the surface layer portion of the semiconductor substrate 100 using an ion implantation technique. The source region 115 is in ohmic contact with the source electrode 124 that coats the surface of the semiconductor substrate 100.

  The insulated gate portion 130 is provided on the surface of the semiconductor substrate 100 and includes a gate insulating film 132 and a gate electrode 134. The gate insulating film 132 covers the surface of the semiconductor substrate 100 and is made of silicon oxide. The gate electrode 134 is separated from the source region 115, the body region 113, and the drift region 112 by the gate insulating film 132, and is made of polysilicon. The gate electrode 134 includes a high concentration gate electrode 134a having a relatively high impurity concentration and a low concentration gate electrode 134b having a relatively low impurity concentration. The boundary between the high-concentration gate electrode 134a and the low-concentration gate electrode 134b is preferably the same as the boundary between the drift region 112 and the body region 113, or located closer to the drain region 111 than the boundary. In other words, the high-concentration gate electrode 134a is opposed to the entire range of the body region 113 located between the drift region 112 and the source region 115 via the gate insulating film 132, and the low-concentration gate electrode 134b is opposed to the electric field relaxation region 116. And the high-concentration gate electrode 134a.

The electric field relaxation region 116 is provided on the drift region 112, is disposed on the surface layer portion of the semiconductor substrate 100, and is exposed on the surface of the semiconductor substrate 100. The electric field relaxation region 116 is disposed corresponding to the drain side end of the insulated gate portion 130, and is disposed closer to the drain region 111 than the gate insulating film 132, and the drain region 111 and the body region are formed by the drift region 112. It is separated from 113. The electric field relaxation region 116 is disposed between the drift region 112 and the gate electrode 134, is in contact with the drift region 112 and the gate electrode 134, and separates the drift region 112 and the gate electrode 134. As described above, the n ⁻ type drift region 112, the p ⁺ type electric field relaxation region 116, and the n ⁻ type gate electrode 134 are continuously arranged. Thereby, the drift region 112 and the electric field relaxation region 116 constitute one diode, and the electric field relaxation region 116 and the gate electrode 134 constitute one diode, and these diodes are arranged in the opposite directions. The electric field relaxation region 116 is formed as a semiconductor layer containing aluminum or boron that spreads on the surface layer portion of the semiconductor substrate 100 using a crystal growth technique or an ion implantation technique, and then is used to etch the drift region 112 using an etching technique. It is formed so as to remain on a part of the surface.

  Next, the operation of the semiconductor device 4 will be described. When a positive voltage is applied to the drain electrode 122, the source electrode 124 is grounded, and the gate electrode 134 of the insulated gate portion 130 is grounded, the semiconductor device 4 is off. At this time, in the semiconductor device 4, since a reverse bias is applied to the diode constituted by the drift region 112 and the electric field relaxation region 116, the depletion layer extends from the pn junction between the drift region 112 and the electric field relaxation region 116. For this reason, the drain electrode 122 and the gate electrode 134 are insulated from each other, and leakage current between the drain electrode 122 and the gate electrode 134 is suppressed. Therefore, the semiconductor device 4 can perform a stable off operation. Further, the electric field at the drain side end of the insulated gate portion 130 is relaxed by the depletion layer extending from the pn junction between the drift region 112 and the electric field relaxation region 116. In particular, in the semiconductor device 4, the gate insulating film 132 is not provided at the drain side end portion of the insulating gate portion 130. The drain side end of the insulated gate 130 is a location where electric field concentration is likely to occur. In the semiconductor device 4, since the gate insulating film 132 does not exist at a place where electric field concentration is likely to occur, the dielectric breakdown of the gate insulating film 132 is suppressed. As described above, the semiconductor device 4 can have high reliability because the dielectric breakdown of the gate insulating film 132 of the insulating gate portion 130 is suppressed.

  When a positive voltage is applied to the drain electrode 122, the source electrode 124 is grounded, and a voltage that is more positive than the source electrode 124 is applied to the gate electrode 134 of the insulated gate portion 130, the semiconductor device 4 is on. At this time, in the semiconductor device 4, since a reverse bias is applied to the diode composed of the electric field relaxation region 116 and the gate electrode 134, the depletion layer extends from the pn junction between the electric field relaxation region 116 and the gate electrode 134. For this reason, the drain electrode 122 and the gate electrode 134 are insulated from each other, and leakage current between the drain electrode 122 and the gate electrode 134 is suppressed. Therefore, the semiconductor device 4 can perform a stable on operation.

  As described above, the semiconductor device 4 can perform stable on and off operations, and can suppress the dielectric breakdown of the gate insulating film 132 and have high reliability. Similarly to the semiconductor device 2 shown in FIG. 2, since the gate electrode 134 includes the high concentration gate electrode 134 a and the low concentration gate electrode 134 b, the body region 113 located between the drift region 112 and the source region 115. A high-density inversion layer is formed over the entire range, and a low channel resistance is realized.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1: Semiconductor device 10: Semiconductor substrate 11: Drain region 12: Drift region 13: Body region 14: Body contact region 15: Source region 16: Electric field relaxation region 22: Drain electrode 24: Source electrode 30: Insulated gate portion 30T: Trench 32: Gate insulating film 34: Gate electrode

Claims (2)

A first conductivity type drain region; a first conductivity type drift region; a second conductivity type body region; a first conductivity type source region; and a second conductivity type electric field relaxation region; A semiconductor substrate in which the drift region, the body region, and the source region are arranged in this order;
An insulating gate portion facing the drift region, the body region, and the source region;
The insulated gate portion is
A gate insulating film in contact with the drift region, the body region, and the source region;
A gate electrode of a first conductivity type facing at least the body region located between the drift region and the source region via the gate insulating film;
The electric field relaxation region is disposed closer to the drain region than the gate insulating film, is in contact with the drift region and the gate electrode, and separates the drift region and the gate electrode ,
The gate electrode has a high concentration gate electrode having a relatively high impurity concentration and a low concentration gate electrode having a relatively low impurity concentration,
The high-concentration gate electrode is opposed to the entire range of the body region located between the drift region and the source region via the gate insulating film;
The semiconductor device , wherein the low concentration gate electrode is provided between the electric field relaxation region and the high concentration gate electrode . The drain region, the drift region, the body region, and the source region are arranged in this order along the thickness direction of the semiconductor substrate,
The insulated gate portion is provided in a trench that penetrates the source region and the body region from the surface of the semiconductor substrate and enters the drift region;
The gate insulating film covers a side surface of the trench;
The gate electrode is exposed on the bottom surface of the trench,
The semiconductor device according to claim 1 , wherein the electric field relaxation region is in contact with the gate electrode exposed at a bottom surface of the trench.

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