JP6271951B2 - Transmitting device, receiving device, digital broadcasting system, and chip - Google Patents

Description

  The present invention relates to a transmission device, a reception device, a digital broadcasting system, and a chip.

  In the ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) system, which is a terrestrial digital broadcasting system in Japan, data after error correction encoding is performed by performing error correction encoding on data before error correction encoding (video data and audio data). Is generated. The transmission bit string is mapped on the IQ plane by carrier modulation (for example, Non-Patent Document 1).

"Transmission standard for digital terrestrial television broadcasting" ARIB STD-B31

  By the way, in the next-generation terrestrial broadcasting system, it is considered to use LDPC (Low Density Parity Check) encoding processing as error correction encoding processing. In the LDPC encoding process, post-error correction encoded data is generated from pre-error correction encoded data using a parity check matrix composed of M × N components.

  Here, it is known that the larger the parity check matrix size, the stronger the error correction strength. However, when the parity check matrix size is large, the memory capacity used in the LDPC code decoding process increases.

  Therefore, the present invention has been made to solve the above-described problem, and a transmission device and a reception device that can increase the error correction strength while suppressing an increase in the memory capacity used in the LDPC code decoding process. An object is to provide a device, a digital broadcasting system, and a chip.

  The first feature is an error correction encoding unit that generates data after error correction encoding from data before error correction encoding by LDPC encoding processing using a check matrix composed of M × N components; And a mapping unit that maps the error-correction-encoded data output from the error-correction encoding unit on an IQ plane, wherein the component constituting the check matrix is configured by 1 or 0 In the parity check matrix, a plurality of target ranges configured by pX × Y components are defined as ranges that can include one component, and the plurality of target ranges are defined in the row direction of the parity check matrix. Are adjacent to each other in the diagonal direction of the parity check matrix, and a pair of target ranges adjacent to each other in the row direction of the parity check matrix is a column direction of the parity check matrix It is summarized as the shifting by X in.

  The second feature is that, from the demapping unit, a demapping unit that demappings the symbols mapped on the IQ plane to data before error correction code decoding and a parity check matrix composed of M × N components are used. An error correction code decoding unit that generates data after error correction code decoding from the output data before error correction code decoding by LDPC code decoding processing, and the component constituting the check matrix is 1 or A plurality of target ranges configured by pX × Y components are defined as ranges that can include one component in the parity check matrix, and the plurality of target ranges are defined as the test matrix. While being adjacent to each other in the row direction of the matrix, they are arranged along the diagonal direction of the parity check matrix and adjacent to each other in the row direction of the parity check matrix Scope of pairs is summarized in that the shifting by X in the column direction of the parity check matrix.

  A third feature is a chip mounted on the receiving apparatus, which is configured by a demapping unit that demappings symbols mapped on the IQ plane to data before error correction code decoding, and M × N components. An error correction code decoding unit that generates post-error correction code decoding data from the pre-error correction code decoding data output from the demapping unit using a check matrix, and constructs the check matrix The component to be configured is 1 or 0, and in the parity check matrix, a plurality of target ranges configured by pX × Y components are defined as a range that can include one component, The target ranges are arranged along the diagonal direction of the parity check matrix while being adjacent to each other in the row direction of the parity check matrix, and in the row direction of the parity check matrix. 1 pair of target range adjacent Te is summarized in that the shifting by X in the column direction of the parity check matrix.

  A fourth feature is a digital broadcasting system including a transmission device and a reception device, wherein the transmission device uses a parity check matrix composed of M × N components to perform error correction from data before error correction coding. An error correction encoding unit for generating encoded data by LDPC encoding processing, and a mapping unit for mapping the error correction encoded data output from the error correction encoding unit on an IQ plane, The receiving apparatus uses the demapping unit for demapping the symbol mapped to the IQ plane to the data before error correction code decoding and the data before error correction code decoding output from the demapping unit using a check matrix And an error correction code decoding unit that generates data after error correction code decoding by LDPC code decoding processing, and constitutes the parity check matrix The minute is composed of 1 or 0, and in the parity check matrix, a plurality of target ranges configured by pX × Y components are defined as a range that can include one component, and the plurality of targets The ranges are arranged along the diagonal direction of the parity check matrix while being adjacent to each other in the row direction of the parity check matrix, and a pair of target ranges adjacent to each other in the row direction of the parity check matrix is a column of the parity check matrix The gist is that the direction is shifted by X.

  According to the present invention, it is possible to provide a transmission device, a reception device, a digital broadcasting system, and a chip that can increase the error correction strength while suppressing an increase in the memory capacity used in the LDPC code decoding process.

FIG. 1 is a block diagram illustrating a transmission device 10 according to the first embodiment. FIG. 2 is a block diagram illustrating the receiving device 20 according to the first embodiment. FIG. 3 is a diagram for explaining the parity check matrix H according to the first embodiment. FIG. 4 is a diagram for explaining LDPC code decoding processing according to the first embodiment. FIG. 5 is a diagram for explaining LDPC code decoding processing according to the first embodiment. FIG. 6 is a diagram for explaining LDPC code decoding processing according to the first embodiment. FIG. 7 is a diagram for explaining LDPC code decoding processing according to the first embodiment. FIG. 8 is a diagram for explaining LDPC code decoding processing according to the first embodiment. FIG. 9 is a diagram for explaining LDPC code decoding processing according to the first embodiment. FIG. 10 is a diagram for explaining LDPC code decoding processing according to the first embodiment. FIG. 11 is a diagram for explaining LDPC code decoding processing according to the first embodiment. FIG. 12 is a diagram showing experimental results. FIG. 13 is a diagram illustrating a check matrix H according to the embodiment. FIG. 14 is a diagram illustrating a parity check matrix H according to the embodiment. FIG. 15 is a diagram illustrating a check matrix H according to the embodiment.

  Next, an embodiment of the present invention will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and ratios of dimensions and the like are different from actual ones.

  Accordingly, specific dimensions and the like should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

[Outline of Embodiment]
The transmission apparatus according to the embodiment generates an error-correction-encoded data from an error-correction-encoded data by an LDPC encoding process using a parity check matrix composed of M × N components. And a mapping unit that maps the error correction encoded data output from the error correction encoding unit on an IQ plane. The component constituting the parity check matrix is composed of 1 or 0. In the parity check matrix, a plurality of target ranges configured by pX × Y components are defined as ranges that can include one component. The plurality of target ranges are arranged along the diagonal direction of the parity check matrix while being adjacent to each other in the row direction of the parity check matrix. A pair of target ranges adjacent to each other in the row direction of the parity check matrix is shifted by X in the column direction of the parity check matrix. Here, p is an integer of 2 or more.

  In the embodiment, in the parity check matrix, the plurality of target ranges are arranged along the diagonal direction of the parity check matrix while being adjacent to each other in the row direction of the parity check matrix. A pair of target ranges adjacent to each other in the row direction of the parity check matrix is shifted by X in the column direction of the parity check matrix.

  Therefore, the receiving apparatus can perform the LDPC code decoding process using a range corresponding to pX × pY components as a decoding unit, and can suppress an increase in memory capacity used in the LDPC code decoding process. On the other hand, since a parity check matrix composed of M × N components larger than the decoding unit defined by pX × pY components can be used as the parity check matrix, the error correction strength can be increased. it can.

[First Embodiment]
(Digital broadcasting system)
Hereinafter, the digital broadcast system according to the first embodiment will be described. FIG. 1 is a block diagram illustrating a transmission device 10 according to the first embodiment, and FIG. 2 is a block diagram illustrating a reception device 20 according to the first embodiment. The digital broadcasting system includes a transmission device 10 and a reception device 20.

  In the embodiment, the digital broadcasting system is a digital broadcasting system compatible with the next generation terrestrial broadcasting system. For example, in a digital broadcasting system, MIMO (Multiple Input Multiple Output) technology and OFDM (Orthogonal Frequency Division Multiplexing) technology are applied. In the digital broadcast system, hierarchical data (for example, 1 segment, 13 segments) belonging to a plurality of layers is transmitted from the transmission device 10 to the reception device 20.

  As illustrated in FIG. 1, the transmission device 10 includes a storage 11, an LDPC encoder 12, a mapping unit 13, and a MIMO-OFDM modulation unit 14. The transmission device 10 is provided in, for example, a broadcasting station.

  The storage 11 stores a check matrix H composed of M × N components. The component constituting the check matrix H is composed of 1 or 0. In the parity check matrix H, the ratio of one component is at least half or less. However, M and N are integers.

  Specifically, as illustrated in FIG. 3, in the parity check matrix H, a plurality of target ranges configured by pX × Y components are defined as ranges that can include one component. FIG. 3 illustrates a case where p = 2. However, X and Y are integers. X is determined such that an integer multiple of X is M, and Y is determined so that an integer multiple of Y is N.

  Here, the plurality of target ranges are arranged along the diagonal direction of the check matrix H while being adjacent to each other in the row direction of the check matrix H. A pair of target ranges adjacent to each other in the row direction of the parity check matrix H are shifted by X in the column direction of the parity check matrix H.

The LDPC encoder 12 uses the parity check matrix H stored in the storage 11 to configure an error correction encoding unit that generates data after error correction encoding from data before error correction encoding by LDPC encoding processing. Specifically, the LDPC encoder 12 uses post-error correction encoded data composed of N data bits and M parity bits based on pre-error correction encoded data composed of N bits. Is generated. Specifically, the LDPC encoder 12 generates a generator matrix G that satisfies the relationship of G · H ^T = 0. Subsequently, the LDPC encoder 12 generates data after error correction coding using w = c · G. Here, c is a bit string constituting the data before error correction coding, and w is a bit string constituting the data after error correction coding.

  The data before error correction coding is input data such as a TS (Transport Stream) having a predetermined format, for example. The data after error correction coding may constitute an error correction code block having a fixed length. The error correction code block includes a header, a payload, and parity bits, and has a bit length of 64800, for example.

  The mapping unit 13 maps the error correction encoded data (bit string) output from the LDPC encoder 12 on the IQ plane. Specifically, the mapping unit 13 maps a bit string composed of a predetermined number of bits determined according to the modulation multi-level number of the carrier modulation process on the IQ plane. As the carrier modulation processing, 32QAM, 128QAM, 512QAM, 2048QAM or the like that maps an odd bit string as one or a plurality of symbols is used. Alternatively, 64QAM, 256QAM, 1024QAM, or the like that maps an even number of bit strings as one or a plurality of symbols may be used as carrier modulation processing.

  The MIMO-OFDM modulation unit 14 generates an OFDM frame (transmission frame) composed of symbols output from the mapping unit 13. An OFDM frame (transmission frame) is defined by a predetermined number of subcarriers (frequency axis) and a predetermined number of symbols (time axis).

  Subsequently, the MIMO-OFDM modulation unit 14 performs space-time coding processing on each symbol constituting the OFDM frame to generate two systems of signals, and performs carrier modulation and IFFT on the two systems of signals. Radio signals Tx1 and Tx2 are generated by performing processing and orthogonal transformation. The MIMO-OFDM modulation unit 14 transmits the radio signals Tx1 and Tx to the reception device 20 using a plurality of antennas. The two signals may be the same signal, but are preferably different signals from the viewpoint of transmission efficiency.

  Here, the OFDM frame (transmission frame) includes control signals such as a TMCC (Transmission and Multiplexing Configuration Control) signal and an AC (Auxiliary Channel) signal. For example, the TMCC signal includes a signal indicating transmission parameters (modulation method, number of segments, coding rate, etc.) of a plurality of layers, and a synchronization signal for synchronizing an OFDM frame (transmission frame).

  As illustrated in FIG. 2, the reception device 20 includes a frequency conversion unit 21, an orthogonal demodulation unit 22, a MIMO-OFDM demodulation unit 23, a log likelihood ratio calculation unit 24, a storage 25, and an LDPC code decoder 26. With. The receiving device 20 is provided, for example, in a receiver fixedly installed in a home or a mobile terminal that can be carried by a user.

  The frequency converter 21 receives the radio signals Rx1 and Rx2 using a plurality of antennas. Specifically, the frequency converter 21 converts the radio signals Rx1 and Rx2 into baseband signals by frequency conversion and digitizes them by AD conversion or the like.

  In the first embodiment, since the radio signals Rx1 and Rx2 are received by a plurality of antennas, the receiving device 20 includes a frequency converter 21A that processes the radio signal Rx1 and a frequency converter 21B that processes the radio signal Rx2. .

  The orthogonal demodulation unit 22 performs orthogonal demodulation of the frequency component converted by the frequency conversion unit 21.

  In the first embodiment, since the radio signals Rx1 and Rx2 are received by a plurality of antennas, the receiving device 20 processes the signal corresponding to the radio signal Rx2 and the frequency converter 21A that processes the signal corresponding to the radio signal Rx1. Frequency conversion unit 21B.

  The MIMO-OFDM demodulation unit 23 performs FFT processing, MIMO decoding processing, and carrier demodulation processing on the two systems of signals output from the frequency conversion unit 21A and the frequency conversion unit 21B, and performs a predetermined number of subcarriers (frequency axis). And an OFDM frame (transmission frame) defined by a predetermined number of symbols (time axis). The synchronization of the OFDM frame (transmission frame) is performed by the above-described TMCC signal.

  The log likelihood ratio calculation unit 24 acquires a bit string corresponding to the symbol position output from the MIMO-OFDM demodulation unit 23, and calculates an LLR (Log Likelihood Ratio) for each bit constituting the acquired bit string. That is, in the first embodiment, the log likelihood ratio calculation unit 24 includes a function of a demapping unit that demappings symbols mapped on the IQ plane to pre-error correction code decoding data (LLR).

  Similar to the storage 11, the storage 25 stores a parity check matrix H composed of M × N components. The component constituting the check matrix H is composed of 1 or 0. In the parity check matrix H, the ratio of one component is at least half or less.

  Specifically, as illustrated in FIG. 3, in the parity check matrix H, a plurality of target ranges configured by pX × Y components are defined as ranges that can include one component. FIG. 3 illustrates a case where p = 2. However, X and Y are integers. X is determined such that an integer multiple of X is M, and Y is determined so that an integer multiple of Y is N.

  Here, the plurality of target ranges are arranged along the diagonal direction of the check matrix H while being adjacent to each other in the row direction of the check matrix H. A pair of target ranges adjacent to each other in the row direction of the parity check matrix H are shifted by X in the column direction of the parity check matrix H.

  The LDPC code decoder 26 uses the parity check matrix H stored in the storage 25 to convert the error-corrected code-decoded data from the error-corrected code-decoded data (LLR) output from the log likelihood ratio calculation unit 24 into an LDPC code. An error correction code decoding unit generated by the decoding process is configured. Specifically, the LDPC code decoder 26 is configured by N data bits based on LLR corresponding to N data bits and LLR error correction code corresponding to M parity bits before decoding. Data after error correction code decoding is generated.

  Specifically, the LDPC code decoder 26 performs row processing using the following equation (1) and then performs column processing using the following equation (2). Subsequently, the LDPC code decoder 26 performs data bit estimation processing using the following equation (3). The LDPC code decoder 26 performs a predetermined number of cycles (i) with one cycle of row processing, column processing, and estimation processing.

Here, i is the number of repetitions of a cycle constituted by row processing, column processing, and estimation processing. n means the n-th column (or LLR corresponding to the n-th data bit) in the check matrix H. m means the m-th row (or LLR corresponding to the m-th parity bit) in the check matrix H. The value of z _{mn ′} used in the first cycle is the LLR output from the log likelihood ratio calculation unit 24, that is, F _n . The value of z _{mn ′} used in the second and subsequent cycles is an LLR recalculated based on x ^{^} . F is an LLR output from the log likelihood ratio calculation unit 24.

A method for recalculating the LLR based on x ^{^} is described in, for example, “A Coded Modulation Scheme Based on Low Density Parity Check Code” IEICE TRANS. FUNDAMENTALS VOL. E84-1 NO. Known methods described in 10 OCTOBER 2001 can be used. It should be noted that such processing is more effective as the number of modulation levels increases.

  Under the premise described above, the LDPC code decoder 26 performs an LDPC code decoding process using a range corresponding to pX × pY components as a decoding unit, as shown in FIG. FIG. 4 illustrates a case where p = 2. Here, the LDPC code decoding process needs to be performed in a range including one component in the parity check matrix H. However, since the target range that can include one component is determined as described above, pX × pY components Note that the range corresponding to can be used as a decoding unit. In other words, the row processing described above may be performed within a decoding unit as shown in FIG. 5, and the column processing described above may be performed within a decoding unit as shown in FIG.

  Specifically, first, as shown in FIG. 7, the LDPC code decoder 26 includes a target range # 1 (target range # 1-1 and target range # 1-2) and a part of the target range # 2. The LLR corresponding to the portion (target range # 2-1) is read out. Subsequently, the LDPC code decoder 26 performs an LDPC code decoding process using the read LLR.

  Secondly, as shown in FIG. 8, the LDPC code decoder 26 copies the processing result (only the row processing result) of the target range # 2-1 and deletes the processing result of the target range # 1.

  Thirdly, as shown in FIG. 9, the LDPC code decoder 26, the remaining part of the target range # 2 (target range # 2-2) and a part of the target range # 2 (target range # 3-1) LLR corresponding to is read.

  Fourth, the LDPC code decoder 26 performs an LDPC code decoding process using the read LLR as shown in FIG. Here, since the row processing of the target range # 2-1 has already been completed, the LDPC code decoder 26 performs the column processing of the target range # 2-1 and the target range # 2-2 and the target range # 2-2. And the row processing of the target range 3-1 is performed.

  As illustrated in FIG. 11, the LDPC code decoder 26 performs LDPC code decoding processing by using the parity check matrix H configured by M × N components by repeating the processing illustrated in FIGS. 7 to 10. be able to.

  As described above, after the error correction code decoding unit performs the nth LDPC code decoding process, the LDPC code decoder 26 shifts the decoding unit by Y in the row direction of the parity check matrix, and After shifting the decoding unit by X in the direction, the (n + 1) th LDPC code decoding process is performed.

(Function and effect)
In the first embodiment, in the parity check matrix H, a plurality of target ranges are arranged along the diagonal direction of the parity check matrix H while being adjacent to each other in the row direction of the parity check matrix H. A pair of target ranges adjacent to each other in the row direction of the parity check matrix H are shifted by X in the column direction of the parity check matrix H.

  Therefore, the receiving apparatus 20 can perform the LDPC code decoding process using a range corresponding to pX × pY components as a decoding unit, and can suppress an increase in memory capacity used in the LDPC code decoding process. On the other hand, as the check matrix H, a check matrix H composed of M × N components larger than the decoding unit defined by pX × pY components can be used, so that the error correction strength is increased. be able to.

[Experimental result]
Hereinafter, the experimental results will be described. In the experiment, the relationship between the carrier noise ratio (CNR) and the channel capacity was examined for the example using the parity check matrix H described in the first embodiment and the comparative example using the existing parity check matrix. As an existing parity check matrix, a parity check matrix in which one component is dispersed throughout is used. Further, the coding rate is changed as the carrier noise ratio (CNR) increases, and three types of coding rates of 2/3, 3/4, and 5/6 were examined.

  The result of such an experiment is shown in FIG. As shown in FIG. 12, it was confirmed that the channel capacity of the example increased compared to the comparative example. That is, it has been confirmed that the channel capacity increases by arranging the target range that can include one component along the diagonal direction of the parity check matrix H.

[Example]
Examples will be described below. In the following, an example of the parity check matrix H used in the LDPC encoding process and the LDPC code decoding process when the coding rates are three types of 2/3, 3/4, and 5/6 is shown.

  First, when the coding rate is 2/3, the parity check matrix H shown in FIG. 13 can be used. It should be noted that a part of the check matrix H is extracted in FIG. For example, the parity check matrix is defined by M = 90720 and N = 172800. The target range is defined by X = 4320 and Y = 8640.

  Second, when the coding rate is 3/4, a parity check matrix H shown in FIG. 14 can be used. It should be noted that a part of the check matrix H is extracted in FIG. For example, the parity check matrix is defined by M = 68040, N = 194400. The target range is defined by X = 3240 and Y = 9720.

  Second, when the coding rate is 5/6, the parity check matrix H shown in FIG. 15 can be used. It should be noted that a part of the check matrix H is extracted in FIG. For example, the parity check matrix is defined by M = 45360, N = 26000. The target range is defined by X = 2160 and Y = 10800.

[Other Embodiments]
Although the present invention has been described with reference to the above-described embodiments, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  Although not specifically indicated in the embodiment, the above-described embodiment is not limited to a system in which a MIMO (Multiple Input Multiple Output) technique is used, but also in a MISO (Multiple Input Single Output) technique or a SISO (Single Input Single Output) technique. It may be applied to a system where is used.

  Although not particularly mentioned in the embodiment, an LDPC code using a parity check matrix H in which a plurality of target ranges are arranged along a diagonal direction may be referred to as a spatially coupled LDPC. In addition, the values of X and Y that define the target range are preferably determined according to the size of the memory of the receiving device 20. Here, when the relationship of K = M / X and L = N / Y is satisfied, K and L are integers that are determined so that the ratio of one component in the check matrix H is at least half or less (at least It should be noted that 2 or more). In the example shown in FIGS. 13 to 15, K = 21 and L = 20.

  In the embodiment, the case where p = 2 is mainly exemplified. However, the embodiment is not limited to this. p may be an integer of 3 or more. However, from the viewpoint of suppressing an increase in memory capacity used in the LDPC code decoding process, it is preferable that p = 2.

  Although not particularly mentioned in the embodiment, a program for causing a computer to execute each process performed by the transmission device 10 and the reception device 20 may be provided. The program may be recorded on a computer readable medium. If a computer-readable medium is used, a program can be installed in the computer. Here, the computer-readable medium on which the program is recorded may be a non-transitory recording medium. The non-transitory recording medium is not particularly limited, but may be a recording medium such as a CD-ROM or a DVD-ROM.

  Or the chip | tip comprised by the memory which memorize | stores the program for performing each process which the transmitter 10 and the receiver 20 perform, and the processor which executes the program memorize | stored in memory may be provided.

  DESCRIPTION OF SYMBOLS 10 ... Transmission apparatus, 11 ... Storage, 12 ... LDPC encoder, 13 ... Mapping part, 14 ... MIMO-OFDM modulation part, 20 ... Reception apparatus, 21 ... Frequency conversion part, 22 ... Orthogonal demodulation part, 23 ... MIMO-OFDM Demodulator 24 ... log likelihood ratio calculator 25 ... storage 26 ... LDPC code decoder

Claims (2)

A demapping unit for demapping the symbols mapped on the IQ plane to data before error correction code decoding;
Error correction code decoding that generates data after error correction code decoding from the data before error correction code decoding output from the demapping unit by LDPC code decoding processing using a check matrix composed of M × N components With
The component constituting the parity check matrix is composed of 1 or 0,
In the parity check matrix, as a range that can include one component, a plurality of target ranges each constituted by 2 X × Y components are defined,
The plurality of target ranges are arranged along the diagonal direction of the parity check matrix while being adjacent to each other in the row direction of the parity check matrix,
A pair of target ranges adjacent to each other in the row direction of the parity check matrix is shifted by X in the column direction of the parity check matrix ,
The error correction code decoding unit performs the LDPC code decoding process using a range corresponding to 2X × 2Y components as a decoding unit,
After performing the nth LDPC code decoding process, the error correction code decoding unit shifts the decoding unit by Y in the row direction of the parity check matrix, and converts the decoding unit to X in the column direction of the parity check matrix. After shifting by n + 1, the (n + 1) th LDPC code decoding process is performed,
In the n-th LDPC code decoding process, the error correction code decoding unit performs an LDPC code decoding process using a range corresponding to the entire n-th target range and a part of the n + 1-th target range as the decoding unit. ,
The error correction code decoding unit uses the processing result of a part of the n + 1th target range in the nth LDPC code decoding process in the n + 1th LDPC code decoding process, When the receiving apparatus, wherein the line Ukoto the LDPC code decoding processing a range corresponding to a portion of the n + 2 of the target range and the decoding unit. A chip mounted on a receiving device,
A demapping unit for demapping the symbols mapped on the IQ plane to data before error correction code decoding;
Error correction code decoding that generates data after error correction code decoding from the data before error correction code decoding output from the demapping unit by LDPC code decoding processing using a check matrix composed of M × N components With
The component constituting the parity check matrix is composed of 1 or 0,
In the parity check matrix, as a range that can include one component, a plurality of target ranges each constituted by 2 X × Y components are defined,
The plurality of target ranges are arranged along the diagonal direction of the parity check matrix while being adjacent to each other in the row direction of the parity check matrix,
A pair of target ranges adjacent to each other in the row direction of the parity check matrix is shifted by X in the column direction of the parity check matrix ,
The error correction code decoding unit performs the LDPC code decoding process using a range corresponding to 2X × 2Y components as a decoding unit,
After performing the nth LDPC code decoding process, the error correction code decoding unit shifts the decoding unit by Y in the row direction of the parity check matrix, and converts the decoding unit to X in the column direction of the parity check matrix. After shifting by n + 1, the (n + 1) th LDPC code decoding process is performed,
In the n-th LDPC code decoding process, the error correction code decoding unit performs an LDPC code decoding process using a range corresponding to the entire n-th target range and a part of the n + 1-th target range as the decoding unit. ,
The error correction code decoding unit uses the processing result of a part of the n + 1th target range in the nth LDPC code decoding process in the n + 1th LDPC code decoding process, chip, wherein the row Ukoto the LDPC code decoding processing a range corresponding to a portion of the n + 2 of the target range and the decoding unit.

Images