JP6260145B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device having a heat treatment step and a semiconductor device.

  In recent years, in the field of power semiconductor devices, research and development of products using a wide band gap semiconductor such as a nitride-based semiconductor, for example, a gallium nitride (GaN) -based semiconductor, has been actively carried out and has already been put into practical use. It is well known that a wide bandgap semiconductor is superior to silicon (Si) that has been used in the past, that a high-breakdown-voltage semiconductor device can be made with low on-resistance and that high-temperature operation is possible. Because of these advantages, nitride-based semiconductors are expected as materials for power devices such as inverters and converters that replace Si-based materials.

  In the manufacturing process of a nitride semiconductor device manufactured using this nitride semiconductor, a heat treatment at a high temperature for crystal recovery and impurity activation, that is, activation annealing is required after ion implantation. become. However, when activation annealing is performed on a nitride-based semiconductor such as a GaN-based semiconductor, when the heating temperature is set to 800 ° C. or higher, nitrogen (N) as a composition is released from the nitride-based semiconductor, so-called nitrogen release. Occurs and decomposition begins.

  On the other hand, conventionally, a method is known in which activation annealing is performed after a protective film (cap layer) made of a material having higher heat resistance is formed on the nitride-based semiconductor layer by sputtering. Patent Documents 1 and 2 and Non-Patent Document 1 disclose a method in which an AlN layer is used as a protective film and heat treatment is performed in nitrogen while surface protection is performed.

  Further, in activation annealing after impurity doping such as ion implantation, heating at a temperature about 2/3 of the melting point of the material constituting the semiconductor layer is required. Specifically, when a nitride semiconductor such as GaN is used as the semiconductor material, a heating temperature of about 1500 to 1700 ° C. is expected.

JP-A-8-186332 Japanese Patent No. 2540791

J.C.Zolper et al., “Sputtered AlN encapsulant for high-temperature of GaN”, Appl. Phys. Lett. 69 (4), 22 July 1996 pp.538-540. X.A.Cao et al., “Ultrahigh Si + implant activation efficiency in GaN using a high-temperature rapid thermal process system”, APPLIED PHYSICS LETTERS 73 (1998) pp.229-231. K.A. Jones et al., “The Properties of Annealed AlN Films Deposited by Pulsed Laser Deposition”, Journal of ELECTRONIC MATERIALS, Vol.29, No.3 2000 pp.262-267.

  However, it has been reported that in such a high temperature range, even if an AlN layer is used as a protective film, pits are generated or decomposed in the AlN layer, so that it does not function as a protective film (for example, non-protective film). (See Patent Documents 2 and 3). For example, Non-Patent Document 2 reports that pits are generated in the AlN layer by heating at a temperature of 1400 ° C. or higher as an example of heating at a temperature of 1500 ° C. or lower as a high temperature region. Thus, when pits are generated in the AlN layer used as the protective film during the heat treatment, there is a high possibility that nitrogen constituting the lower nitride semiconductor layer is released from the pits.

  Furthermore, even when a nitride-based semiconductor layer such as an AlN layer formed by sputtering is used as a protective film for the upper layer of the nitride-based semiconductor layer against high-temperature activation annealing, the lower-layer nitride during the heat treatment It was difficult to suppress nitrogen escape from the semiconductor layer. According to the knowledge of the present inventor, this cause is due to the poor film quality of the nitride-based semiconductor layer formed by the sputtering method. Therefore, the present inventor has conceived a method for suppressing nitrogen escape by forming a protective film having a dense film quality by an epitaxial growth method.

  However, when a nitride-based semiconductor layer such as an AlN layer as a protective film is formed on the nitride-based semiconductor layer with a dense film quality by an epitaxial growth method, cracks may occur when the film thickness is increased. . For this reason, the thickness of the protective film is limited to about 4 nm to 10 nm at the maximum, and only a thin protective film can be formed, and there are cases where the effect of suppressing nitrogen loss cannot be obtained sufficiently.

  For these reasons, in the prior art, the activation annealing temperature is limited to about 1300 ° C. However, when activation annealing is performed after impurity doping such as ion implantation, at a heating temperature of about 1300 ° C., it is difficult to sufficiently activate impurities and restore crystallinity in the semiconductor layer. Therefore, in the prior art, for example, a decrease in carrier mobility in a manufactured semiconductor device becomes a problem. In particular, when a p-type region is formed by ion implantation, there is a problem that a sufficient p-type carrier concentration cannot be obtained with respect to the amount of implanted impurities due to the compensation effect of n-type carriers generated by defects. there were.

The present invention has been made in view of the above, and an object of the present invention is to stably and effectively perform heat treatment at a high temperature while preventing nitrogen desorption from the nitride-based semiconductor layer constituting the semiconductor device. is to provide a manufacturing how a semiconductor device capable of performing.

In order to solve the above-described problems and achieve the above object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a nitride-based semiconductor layer, wherein Al _x Ga _1-x N is formed on a substrate. A first forming step of forming a first nitride-based semiconductor layer, an impurity introducing step of introducing an impurity into the first nitride-based semiconductor layer, and Al _y Ga _1-y on the first nitride-based semiconductor layer A second forming step of forming a second nitride-based semiconductor layer made of N, and a third formation of forming a third nitride _- based semiconductor layer made of Al _z Ga _1-z N on the second nitride-based semiconductor layer And a heat treatment step of performing heat treatment on the first nitride semiconductor layer, the second nitride semiconductor layer, and the third nitride semiconductor layer after the third formation step, The Al composition ratio y of the material-based semiconductor layer is greater than the Al composition ratio x of the first nitride-based semiconductor layer. Hear, and being greater than the Al composition ratio z of the third nitride semiconductor layer.

The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the first nitride-based semiconductor layer is Al _x Ga _1-x N (0 ≦ x <0.5). In this configuration, the method for manufacturing a semiconductor device according to the present invention is characterized in that the first nitride-based semiconductor layer is Al _x Ga _1-x N (0 ≦ x <0.2).

The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the second nitride semiconductor layer is Al _y Ga _1-y N (0.5 ≦ y ≦ 1). In this configuration, the method for manufacturing a semiconductor device according to the present invention is characterized in that the second nitride-based semiconductor layer is Al _y Ga _1-y N (0.8 ≦ y ≦ 1).

The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the third nitride-based semiconductor layer is Al _z Ga _1-z N (0 ≦ z <0.5). In this configuration, the method for manufacturing a semiconductor device according to the present invention is characterized in that the third nitride-based semiconductor layer is Al _z Ga _{1 -zN} (0 ≦ z <0.2).

  The method of manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the substrate has a substrate made of gallium nitride.

  In the method of manufacturing a semiconductor device according to the present invention, in the above invention, the film thickness of the second nitride-based semiconductor layer is a critical film thickness at room temperature in a single layer when the third nitride-based semiconductor layer is not provided. It is characterized by being larger.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the thickness of the third nitride-based semiconductor layer is 50 nm or more.

  The method for manufacturing a semiconductor device according to the present invention is the above invention, wherein the first nitride-based semiconductor layer, the second nitride-based semiconductor layer, and the third nitride-based semiconductor layer are formed by metal organic vapor phase epitaxy. It is characterized by doing.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the impurity introduction step is an ion implantation step of selectively ion-implanting impurities into the first nitride-based semiconductor layer. The semiconductor device manufacturing method according to the present invention is characterized in that, in this configuration, the impurity is an element including at least one kind selected from the group consisting of magnesium, zinc, and beryllium.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that, in the above invention, the heat treatment temperature in the heat treatment is 800 ° C. or higher and 2000 ° C. or lower.

  In the above invention, the method for manufacturing a semiconductor device according to the present invention further includes a removing step of removing at least a part of the second nitride-based semiconductor layer and the third nitride-based semiconductor layer after the heat treatment step. Features. The method for manufacturing a semiconductor device according to the present invention is characterized in that, in this removing step, the second nitride semiconductor layer is removed by a wet etching method. The method for manufacturing a semiconductor device according to the present invention is characterized in that, in this removing step, the third nitride-based semiconductor layer is removed by a dry etching method.

  A semiconductor device according to the present invention is manufactured by the method for manufacturing a semiconductor device according to the above invention.

According to the manufacturing how the semiconductor device according to the present invention, it is possible to perform heat treatment at a high temperature stable and effectively while preventing elimination of nitrogen from the nitride-based semiconductor layer.

FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. FIG. 2A is a schematic diagram for explaining the heat treatment method according to Embodiment 1 of the present invention. FIG. 2B is a schematic diagram for explaining the heat treatment method according to Embodiment 1 of the present invention. FIG. 2C is a schematic diagram for explaining the heat treatment method according to Embodiment 1 of the present invention. FIG. 2D is a schematic diagram for explaining the heat treatment method according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view of a substrate to be processed for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited by this embodiment. Moreover, in each drawing, the same code | symbol is attached | subjected suitably to the same or corresponding element. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships between elements may differ from actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included.

(Embodiment 1)
(Semiconductor device)
First, the semiconductor device according to the first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a configuration of a vertical MOSFET as a semiconductor device according to the first embodiment. As shown in FIG. 1, a semiconductor device 1 according to the first embodiment is formed on an n-type gallium nitride (n-GaN) substrate 11 doped with an n-type impurity and on the n-GaN substrate 11 by, for example, an epitaxial growth method. is, n-type impurity and an _{n-Al x Ga 1-x} n layer 12 as a first nitride semiconductor layer doped. The impurity concentration of the n-Al _x Ga _{1 -x} N layer 12 is preferably lower than that of the n-GaN substrate 11. The Al composition of the n-Al _x Ga _1-x N layer 12 is typically 0 or more and less than 0.5 (0 ≦ x <0.5), preferably 0 or more and less than 0.2 (0 ≦ x <0.2), and specifically in the first embodiment, for example, an n-GaN layer.

The n-Al _x Ga _1-x N layer 12 is selectively doped with a p-type impurity at a higher concentration in the p-type well region 13 that is selectively doped with the p-type impurity. The p ⁺ type well region 14 and the n ⁺ type source region 15 selectively doped with n type impurities are formed in the p type well region 13 and the p ⁺ type well region 14.

In addition, a gate electrode 16 is provided between the pair of p-type well regions 13 in the surface portion of the n-Al _x Ga _{1 -x} N layer 12. The gate electrode 16 is on the surface of the _{n-Al x Ga 1-x} N layer 12, are provided through the bottom, for example, silicon oxide (SiO ₂₎ gate insulating film 17 made of an insulating material, such as. A pair of source electrodes 18 are provided on the n-Al _x Ga _{1 -x} N layer 12 so as to be sandwiched between the gate electrode 16 and the gate insulating film 17 while being separated from them. On the other hand, a drain electrode 19 is provided on the back surface of the n-GaN substrate 11. With the above configuration, in the semiconductor device 1, a channel is formed from the upper p-type well region 13 to the n-GaN substrate 11 during driving.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 1 according to the first embodiment configured as described above will be described. 2A, FIG. 2B, FIG. 2C, and FIG. 2D are schematic views of the substrate to be processed for explaining the method of manufacturing the semiconductor device 1 according to the first embodiment.

That is, first, as shown in FIG. 2A, while doping an n-type impurity on an n-GaN substrate 11 as a base, Al _x Ga _1-x N is formed by, for example, metal organic chemical vapor deposition (MOCVD). by growing to form an _{n-Al x Ga 1-x} n layer 12, such as for example n-GaN layer. Instead of the n-GaN substrate 11, a sapphire substrate, a SiC substrate, or the like may be used. Further, the n-Al _x growth of Ga _1-x N layer 12, in place of the MOCVD method, a halide vapor phase epitaxy (HVPE) or molecular beam epitaxy method (MBE method) or the like may be used.

Next, the p-type well region 13 and the high impurity concentration p ⁺ -type well region 14 are selectively formed with respect to the n-Al _x Ga _{1 -x} N layer 12 by ion implantation, for example. A p-type impurity is sequentially doped. As the p-type impurity, at least one element selected from the group consisting of magnesium (Mg), beryllium (Be), zinc (Zn), and the like is used. Thereafter, an n-type impurity such as silicon (Si) is selectively applied to a region where the n ⁺ -type source region 15 in the p-type well region 13 and the p ⁺ -type well region 14 is to be formed by, eg, ion implantation. Dope.

Next, as shown in FIG. 2B, the surface of the _{n-Al x Ga 1-x} N layer 12, the first cap layer 2a as the second nitride semiconductor layer, and a third nitride semiconductor layer The second cap layer 2b is sequentially regrown. Here, suitable materials are selected for the n-Al _x Ga _1-x As material of the first cap layer 2a and the second cap layer 2b to protect the surface of the N layer 12, after the heat treatment step .

The specific material of the first cap layer 2a, high heat resistance than the lower layer of _{n-Al x Ga 1-x} N layer 12, no peeling in the heat treatment the degree to _{n-Al x Ga 1-x} N A dense material that has good adhesion to the layer 12, does not easily react with the n-Al _x Ga ₁ -xN layer 12, and does not easily diffuse impurities is preferable. Therefore, in this embodiment in the embodiment 1, as the material constituting the first cap layer 2a, a lower layer of n-Al _x Ga _1-x N layer 12 of high Al composition ratio y in comparison with the Al composition ratio x of Al _y Ga _1-y N is preferred. In this case, the lattice constant of the material constituting the first cap layer 2 a is smaller than the lattice constant of the material constituting the lower n-Al _x Ga _{1 -x} N layer 12. The Al composition ratio y is typically 0.5 or more and 1 or less (0.5 ≦ y ≦ 1), preferably 0.8 or more and 1 or less (0.8 ≦ y ≦ 1), In the first embodiment, for example, aluminum nitride (AlN) with an Al composition ratio y of 1 is used as the material of the first cap layer 2a. When the first cap layer 2a is made of AlN, the etching selectivity can be increased when the lower layer is a GaN layer, which is preferable from the viewpoint of easily removing the first cap layer 2a.

Also, considering that the first cap layer 2a is a dense film so as to obtain a higher surface protection effect, the first cap layer 2a is formed by regrowth by an epitaxial growth method such as MOCVD, HVPE, or MBE. Is desirable. Therefore, in the first embodiment, the first cap layer 2a as the protective film made of the Al _y Ga _1-y N layer is formed on the surface of the n-Al _x Ga _1-x N layer 12 by, eg, MOCVD. To do. Here, in the formation of the first capping layer 2a by the MOCVD method, for example, Al raw material _{(trimethylaluminum; TMA; Al (CH 3)} 3) gas and a Ga source (trimethyl _{gallium; TMGa; Ga (CH 3)} 3 ) A mixed gas containing at least one raw material gas and ammonia (NH ₃ ) gas is used. Further, the heating temperature in the formation of the first cap layer 2a is preferably lower than the heat treatment temperature (heating temperature) in the activation annealing performed later, specifically, for example, 800 to 1200 ° C., and the atmospheric pressure is, for example, 5 kPa to 20 kPa. The thickness of the first cap layer 2a is carried out to a nitrogen exit film thickness can be suppressed from activation annealing underlying _{n-Al x Ga 1-x} N layer 12 in the desirable after. Specifically, the film thickness of the first cap layer 2a is a critical film thickness at room temperature in the case of a single layer where at least the second cap layer 2b is not provided, specifically, for example, a film thickness larger than 3 nm. When the second cap layer 2b is composed of a GaN layer as will be described later and the first cap layer 2a is composed of an AlN layer, the film thickness of the first cap layer 2a is specifically 15 nm or more, preferably Is preferably 30 nm or more.

Further, as a material of the second cap layer 2b, the first cap layer 2a, which is likely to generate cracks, is restrained from stress by suppressing the stress and the first cap layer 2b is not formed. A material that can form the layer 2a thick and has good adhesion to such an extent that peeling does not occur during high-temperature heat treatment is preferable. Therefore, in the first embodiment, the material constituting the second cap layer 2b is smaller than the Al composition ratio y of the Al _y Ga _1-y N layer constituting the lower first cap layer 2a. The Al composition ratio z is Al _z Ga _{1 -z} N. As a result, the lattice constant of the material constituting the second cap layer 2b is larger than the lattice constant of the material constituting the first cap layer 2a, so that the stress generated in the first cap layer 2a is suppressed and the distortion is reduced. Is done. The Al composition ratio z is typically 0 or more and less than 0.5 (0 ≦ y <0.5), preferably 0 or more and less than 0.2 (0 ≦ z <0.2). In the first embodiment, GaN having an Al composition ratio z of 0 is used as the material of the second cap layer 2b. From the viewpoint of suppressing the generation of stress in the first cap layer 2a, the Al _z Ga _1-z N constituting the second cap layer 2b is the same as the n-Al _x Ga _1-x N layer 12 (x = Z) or a close (x≈z) composition.

The second cap layer 2b may be formed by an epitaxial growth method such as MOCVD method, HVPE method, MBE method, etc. in consideration of making it a dense film so as to obtain a protective effect for the first cap layer 2a. desirable. Therefore, in the first embodiment, the second cap layer 2b made of an Al _z Ga _{1 -z} N layer is formed on the first cap layer 2a by, for example, the MOCVD method. Here, in the formation of the second cap layer 2b by the MOCVD method, for example, Al raw material _{(trimethylaluminum; TMA; Al (CH 3)} 3) gas and a Ga source (trimethyl _{gallium; TMGa; Ga (CH 3)} 3 ) A mixed gas containing at least one raw material gas and ammonia (NH ₃ ) gas is used. Further, the heating temperature in the formation of the second cap layer 2b is preferably lower than the heat treatment temperature (heating temperature) in the activation annealing performed later, specifically, for example, 800 to 1200 ° C., and the atmospheric pressure is, for example, 20 kPa to 50 kPa. The film thickness of the second cap layer 2b can be reduced by suppressing the generation of stress in the first cap layer 2a, and more than the film thickness at which the second cap layer 2b remains by activation annealing performed later. Specifically, for example, it is desirable to set it to 50 nm or more.

  Thus, the substrate 2 to be processed is obtained. The first cap layer 2a and the second cap layer 2b are each formed by epitaxially growing a nitride-based semiconductor crystal, so that the crystallinity is good and suitable as a protective film against activation annealing. Can be used.

Next, a heat treatment step for heating the substrate 2 to be processed, that is, activation annealing as a high-temperature heat treatment for activating impurities contained in the substrate 2 to be processed is performed. This activation annealing is a high-temperature heat treatment in which the heating temperature is, for example, 800 ° C. or higher, preferably 1200 ° C. or higher, more preferably 1500 ° C. or higher, and the upper limit is 2000 ° C. or lower. Here, when the heat treatment temperature is 800 ° C. or higher, the decomposition of the n-Al _x Ga _1-x N layer 12 starts, so that the surface protection effect by the first cap layer 2a and the second cap layer 2b is ensured. It is valid. Furthermore, it is desirable that the pressure in the heat treatment apparatus on which the substrate 2 to be processed is placed be, for example, 0.1 to 1000 MPa (1 to 10,000 atmospheres). By the activation annealing described above, impurities such as Mg, Be, or Zn doped in the n-Al _x Ga _1-x N layer 12 are activated, and the p-type well region 13, the p ⁺ -type well region 14, and An n ⁺ type source region 15 is formed.

  Thereafter, as shown in FIG. 2C, at least a part, preferably all, of the second cap layer 2b is removed by, for example, a dry etching method using a chlorine-based gas. When removing a part of the second cap layer 2b, a mask (not shown) is formed on the second cap layer 2b by, for example, a photolithography process, and dry etching is performed using this mask as an etching mask. .

Subsequently, as shown in FIG. 2D, a _first etching is performed from the substrate 2 to be processed by a wet etching method using a solution having high etching selectivity between Al _x Ga _1-x N and Al _y Ga _1-y N. At least a part, preferably all, of the cap layer 2a is removed. When a part of the first cap layer 2a is removed, a mask (not shown) is formed on at least one of the first cap layer 2a and the second cap layer 2b by, for example, a photolithography process. Etching may be performed using this mask as an etching mask, or etching may be performed using the second cap layer 2b as a mask. Further, the _{n-Al x Ga 1-x} N layer 12 is composed of n-GaN, in the case where the first cap layer 2a was formed from AlN, high etch selectivity by using a potassium hydroxide (KOH) aqueous solution Can be secured.

Next, a gate insulating film 17 made of, for example, a SiO ₂ film is grown on the upper surface of the n-Al _x Ga _{1 -x} N layer 12 by, eg, PECVD (Plasma Enhanced CVD). The thickness of the gate insulating film 17 is, for example, about 100 nm. In addition to the SiO ₂ film, an insulating film such as a SiN _x film, a SiON film, an Al ₂ O ₃ film, a MgO film, a GaO _x film, and a GdO _x film, or a laminated film including any of these films. May be.

  Next, after or when a polycrystalline silicon film is formed on the gate insulating film 17 by, for example, LPCVD (low pressure chemical vapor deposition), n-type impurities such as phosphorus (P) and arsenic (As) are added. Doping. As a result, the polycrystalline silicon film exhibits conductivity. The doping of the n-type impurity into the polycrystalline silicon film is performed by ion-implanting the n-type impurity after forming the polycrystalline silicon film or introducing the n-type impurity into the growth atmosphere during the growth of the polycrystalline silicon film. Can be done by. The doped n-type impurity is activated and diffused into the polycrystalline silicon film by heat treatment.

Subsequently, by patterning the polycrystalline silicon film and the gate insulating film 17 by a photolithography process and an etching process, the n-Al _x Ga _1-x N layer 12 other than the formation region of the gate insulating film 17 and the gate electrode 16 is formed. To expose the surface. The etching process is performed by, for example, the RIE (reactive ion etching) method or the ICP (inductive coupling method) -RIE method. As the gate electrode 16, a metal film such as gold (Au), platinum (Pt), nickel (Ni), or an alloy film thereof is used in addition to the polycrystalline silicon film doped with n-type impurities. It is possible.

Next, an n ⁺ type source formed in the n-Al _x Ga _1-x N layer 12 in a region sandwiched between the surface of the exposed n-Al _x Ga _1-x N layer 12 while being separated from the gate electrode 16. A pair of source electrodes 18 that are in ohmic contact with the region 15 and the p ⁺ -type well region 14 are selectively formed. As the source electrode 18, for example, a laminated metal film made of Ti / Al in which titanium (Ti) and aluminum (Al) are sequentially laminated can be used. Note that the configuration of the source electrode 18 is not limited to this, and may be any conductive film that can form an ohmic junction or a low-resistance junction close to an ohmic junction with the n ⁺ -type source region 15 and the p ⁺ -type well region 14. It is possible to use any metal material. The source electrode 18 may have a different configuration in the n ⁺ type source region 15 and the p ⁺ type well region 14. The source electrode 18 can be formed using a lift-off method, a selective growth method, or the like.

Next, a surface opposite to the source electrode _{18 n-Al x Ga 1-} x N layer 12 is formed on the back surface of the n-GaN substrate 11, a laminated metal film of e.g. Ti / Al A drain electrode 19 is formed. Thereafter, the semiconductor device 1 shown in FIG. 1 is manufactured by separating the elements into individual pieces.

According to the first embodiment of the present invention described _{above, n-Al x Ga 1-} x after doping the impurity in the N-layer 12, the lattice than the material of the _{n-Al x Ga 1-x} N layer 12 as a protective film and a first cap layer 2a, and the Al _y Ga _1-y N lattice constant becomes a large Al _z Ga _1-z N from the second cap layer 2b are sequentially epitaxially grown constant becomes a small Al _y Ga _1-y N by there, it is possible to mitigate the distortion of the first cap layer 2a which is sandwiched between the _{n-Al x Ga 1-x} n layer 12 and the second cap layer 2b. Therefore, the film thickness of the first cap layer 2a is greater than the film thickness functioning as a protective film against activation annealing, and at least larger than the critical film thickness at room temperature in the case where the second cap layer 2b is not provided. possible since, also maintain the surface protective effect against _{n-Al x Ga 1-x} n layer 12 in the activation annealing heat treatment temperature becomes high, the nitrogen exits suppression from _{n-Al x Ga 1-x} n layer 12 can do. Therefore, activation annealing can be stably and effectively performed in the manufacture of a semiconductor device, and the operating characteristics of the manufactured semiconductor device 1 can be further improved.

(Embodiment 2)
Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. FIG. 3 is a cross-sectional view showing the substrate 3 to be processed according to the second embodiment.

In the second embodiment, unlike the first embodiment, the first cap layer 2a and the second cap layer 2b are sequentially formed on the surface of the n-Al _x Ga _{1 -x} N layer 12 by, for example, MOCVD. For example, by MOCVD, the _first surface made of Al _y Ga _1-y N as a back surface protective film is formed on the back surface of the n-GaN substrate 11 opposite to the laminated surface of the n-Al _x Ga _1-x N layer 12. sequentially forming a second cap layer 3b made of a cap layer 3a and the Al _z Ga _1-z N. That is, each of the back surface of the _{n-Al x} Ga _1-x surface of the N layer 12 and the n-GaN substrate 11, the first cap layer 2a as a protective film, 3a, and the second cap layer 2b, 3b are provided The substrate to be processed 3 is formed.

Thereafter, activation annealing at a high temperature is performed on the substrate 3 to be processed in the same manner as in the first embodiment, thereby activating the impurities doped in the n-Al _x Ga _{1 -x} N layer 12. Since other semiconductor device manufacturing methods and manufactured semiconductor devices are the same as those in the first embodiment, description thereof will be omitted.

  According to the method of manufacturing a semiconductor device according to the second embodiment, activation annealing is performed after the first cap layer 2a and the second cap layer 2b are formed as in the first embodiment. The effect similar to that of Embodiment 1 can be obtained, and activation annealing is performed in a state where the first cap layer 3a and the second cap layer 3b are also formed on the back surface of the n-GaN substrate 11. Since the doped impurities can be activated while suppressing the generation of nitrogen from the n-GaN substrate 11 by the heat treatment, the characteristics of the semiconductor device manufactured using the substrate to be processed 3 can be further improved. Can do.

  Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible. For example, the numerical values and materials given in the above embodiment are merely examples, and different numerical values and materials may be used as necessary.

For example, in the embodiment described above, the impurity doping for _{n-Al x Ga 1-x} N layer 12 is performed by ion implantation, doping process of impurity is not necessarily limited to ion implantation method Alternatively, for example, other impurity doping methods such as introducing impurities into the growth atmosphere during the epitaxial growth of the n-Al _x Ga _{1 -x} N layer 12 may be employed.

In the above-described embodiment, the high-temperature heat treatment according to the present invention is performed in the activation annealing performed after the impurity doping, specifically, to activate the impurity doped in the n-Al _x Ga _{1 -x} N layer 12. However, the present invention is not necessarily limited to the activation annealing, and annealing after forming the gate oxide film (Post Deposition Anneal (PDA)), or It is also possible to apply to any heat treatment for other semiconductor layers such as metal sintering.

  For example, in the above-described embodiment, the vertical MOSFET is described as an example of the semiconductor device. However, the semiconductor device is not necessarily limited to the vertical MOSFET, and is manufactured by a manufacturing method having a heat treatment step. Various semiconductor devices such as other transistors, diodes, power supply circuits, and inverters may be used.

In the first and second embodiments described _{above, n-Al x Ga 1-} x surface of the N layer 12 or the protective film is laminated on the back surface of the n-GaN substrate 11, the first cap layer 2a (3a) The second cap layer 2b (3b) is not limited to two layers. That is, the surface of the _{n-Al x Ga 1-x} N layer 12 or on each of the back surface of the n-GaN substrate 11, a plurality of sets first cap layer 2a (3a) and the second cap layer 2b and (3b) as a set It is also possible to form a protective film against these front and back surfaces by laminating. In addition, the first cap layer 2a (3a) and the second cap layer 2b (3b) may be sequentially formed under the above-described reduced pressure atmosphere and heating temperature without being exposed to the air, thereby suppressing cracks and preventing surface contamination. Desirable in terms.

In the second embodiment described above, the first cap layer 2 a and the second cap layer 2 b are sequentially formed on the surface of the n-Al _x Ga _{1 -x} N layer 12, and then the back surface of the n-GaN substrate 11. The first cap layer 3a and the second cap layer 3b are sequentially formed. However, not necessarily limited thereto, after the first capping layer 3a and a second cap layer 3b are successively formed on the back surface of the n-GaN substrate 11, the _{n-Al x Ga 1-x} N layer 12 The first cap layer 2a and the second cap layer 2b may be sequentially formed on the surface. Further, even if the second cap layer 2b and the second cap layer 3b are formed simultaneously after the first cap layer 2a and the first cap layer 3a are formed simultaneously, the first cap layer 2a and the first cap layer 3a are formed. Even if the second cap layer 2b and the second cap layer 3b are formed in separate steps, the second cap layer 2b and the second cap layer are formed after the first cap layer 2a and the first cap layer 3a are formed at the same time. The second cap layer 2b and the second cap layer 3b may be formed at the same time after the first cap layer 2a and the first cap layer 3a are formed in another step. .

1 semiconductor device 2, 3 the target substrate 2a, 3a first cap layer 2b, 3b second cap layer 11 n-type gallium nitride (n-GaN) substrate _{12 n-Al x Ga 1-} x N layer 13 p-type well region 14 p ⁺ type well region 15 n ⁺ type source region 16 gate electrode 17 gate insulating film 18 source electrode 19 drain electrode

Claims (17)

In a method for manufacturing a semiconductor device having a nitride-based semiconductor layer,
A first forming step of forming a first nitride-based semiconductor layer made of Al _x Ga _1-x N on a substrate by an epitaxial growth method;
An impurity introduction step of introducing impurities into the first nitride-based semiconductor layer;
A second forming step of forming a second nitride-based semiconductor layer made of Al _y Ga _1-y N on the first nitride-based semiconductor layer by an epitaxial growth method;
A third forming step of forming a third nitride-based semiconductor layer made of Al _z Ga _1-z N by epitaxial growth on the second nitride-based semiconductor layer;
Carried out after the third formation step, the first nitride semiconductor layer, the second nitride semiconductor layer and for the third nitride semiconductor layer, a heat treatment at 1 5 00 ° C. above the heat treatment temperature A heat treatment step,
An Al composition ratio y of the second nitride semiconductor layer is greater than an Al composition ratio x of the first nitride semiconductor layer and greater than an Al composition ratio z of the third nitride semiconductor layer;
The method of manufacturing a semiconductor device, wherein the thickness of the second nitride-based semiconductor layer is larger than the critical thickness at room temperature in a single layer when the third nitride-based semiconductor layer is not provided.   The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the third nitride-based semiconductor layer is 50 nm or more. In a method for manufacturing a semiconductor device having a nitride-based semiconductor layer,
A first forming step of forming a first nitride-based semiconductor layer made of Al _x Ga _1-x N on a substrate by an epitaxial growth method;
An impurity introduction step of introducing impurities into the first nitride-based semiconductor layer;
A second forming step of forming a second nitride-based semiconductor layer made of Al _y Ga _1-y N on the first nitride-based semiconductor layer by an epitaxial growth method;
A third forming step of forming a third nitride-based semiconductor layer made of Al _z Ga _1-z N by epitaxial growth on the second nitride-based semiconductor layer;
Carried out after the third formation step, the first nitride semiconductor layer, the second nitride semiconductor layer and for the third nitride semiconductor layer, a heat treatment at 1 5 00 ° C. above the heat treatment temperature A heat treatment step,
An Al composition ratio y of the second nitride semiconductor layer is greater than an Al composition ratio x of the first nitride semiconductor layer and greater than an Al composition ratio z of the third nitride semiconductor layer;
The method of manufacturing a semiconductor device, wherein the third nitride-based semiconductor layer has a thickness of 50 nm or more. The manufacturing method of the semiconductor device according to claim 1, wherein the first nitride-based semiconductor layer is Al _x Ga _1-x N (0 ≦ x <0.5). Method. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the first nitride-based semiconductor layer is Al _x Ga _1-x N (0 ≦ x <0.2). The semiconductor device according to claim 1, wherein the second nitride-based semiconductor layer is Al _y Ga _1-y N (0.5 ≦ y ≦ 1). Method. The method for manufacturing a semiconductor device according to claim 6, wherein the second nitride-based semiconductor layer is Al _y Ga _1-y N (0.8 ≦ y ≦ 1). The semiconductor device according to claim 1, wherein the third nitride-based semiconductor layer is Al _z Ga _1-z N (0 ≦ z <0.5). Method. The third nitride semiconductor layer is, the method of manufacturing a semiconductor device according to claim 8, characterized in that the _{Al z Ga 1-z N (} 0 ≦ z <0.2).   The method for manufacturing a semiconductor device according to claim 1, wherein the base includes a substrate made of gallium nitride.   The first nitride semiconductor layer, the second nitride semiconductor layer, and the third nitride semiconductor layer are formed by metal organic vapor phase epitaxy. A method for manufacturing a semiconductor device according to claim 1.   12. The semiconductor device according to claim 1, wherein the impurity introduction step is an ion implantation step of selectively ion-implanting the impurity into the first nitride-based semiconductor layer. Production method.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the impurity is an element including at least one kind selected from the group consisting of magnesium, zinc, and beryllium.   The method for manufacturing a semiconductor device according to claim 1, wherein a heat treatment temperature in the heat treatment is 2000 ° C. or lower.   15. The method according to claim 1, further comprising a removal step of removing at least a part of the second nitride semiconductor layer and the third nitride semiconductor layer after the heat treatment step. The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   16. The method of manufacturing a semiconductor device according to claim 15, wherein, in the removing step, the second nitride semiconductor layer is removed by a wet etching method.   17. The method of manufacturing a semiconductor device according to claim 15, wherein, in the removing step, the third nitride-based semiconductor layer is removed by a dry etching method.

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