JP2008135700A - Manufacturing method of group iii nitride film, and group iii nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a group III nitride film which attains improvement in a modulus of activation after ion implantation into the group III nitride film, for a short time while preventing deterioration of a crystal quality. <P>SOLUTION: The group III nitride film is efficiently activated for a short period through a process to implant ions into the group III nitride film, and a process to activate the nitride film by performing high-temperature annealing treatment (Fig. 4 (b)) of the group III nitride film 21 after ion implantation, for 10 seconds or more but 30 minutes or less, according to temperature, at the temperature of 1,100°C or more but 1,350°C or less. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a group III nitride film, and more particularly, a method for activating a contact layer used as a group III nitride compound semiconductor device and a group III nitride using the group III nitride film manufactured thereby. The present invention relates to a physical semiconductor device.

  Wide band gap semiconductors typified by III-V nitrides have high breakdown voltage, good electron transport properties, good thermal conductivity, and are very useful as device materials for large power at high temperatures. Some transistors, which are laser diodes and electronic devices in the short wavelength region, have been put into practical use. Especially in electronic devices, AlGaN / GaN HFETs or MISFETs have been used so far. These have higher breakdown voltage and saturation mobility than conventional group III compound semiconductors such as Si, GaAs, and InP, and are suitable for power devices.

  However, these Group III-nitride transistors have a problem that the contact resistance between the source and the drain is increased due to the work function difference from the metal because the material is a wide gap.

For example, in the case of a group III nitride field effect transistor, a thermal diffusion method (Non-Patent Document 1) or a selective growth method (Non-Patent Document) is used to reduce the contact resistance between a source electrode and a drain electrode and a Group III nitride. 2) is used. Some use Schottky junction (Non-patent Document 3).
S. Jang et al. J. Electronic Materials 35 (2006) 685 Yoshida Kiyoteru, Electric Works Times, No. 109, 2002 HB Lee et al. IEEE Trans. Dev. Lett. 27 (2006) 81

  However, in the thermal diffusion method described in Non-Patent Document 1, the thermal diffusion method is used after the silicon is deposited on the surface of the group III nitride film. However, the annealing temperature is as low as 900 ° C., which is 120 minutes. A long annealing time is required, and a reduction in production efficiency becomes a problem.

  Further, when the selective growth method described in Non-Patent Document 2 is used, there is a problem that the growth rate of the selected region is very fast compared to the surroundings, and it is difficult to adjust the film thickness.

  Further, the method using the Schottky junction of Non-Patent Document 3 has a problem that the on-resistance cannot be lowered sufficiently because the contact resistance of the Schottky junction is high.

  The present invention has been made in view of the above problems, and can improve the activation rate after ion implantation into a group III nitride film in a short time while preventing deterioration of crystal quality. It is an object of the present invention to provide a method for producing a film and a group III nitride semiconductor device using a group III nitride film produced by this method.

  The first aspect of the present invention for solving the above-described problems is that a dopant is ion-implanted into a group III nitride film, and the group III nitride film after ion implantation is performed at a temperature of 1100 ° C. or higher and 1350 ° C. or lower. And an activation step of performing high-temperature annealing for a period of 10 seconds or more and 30 minutes or less depending on the temperature. The activation rate can be greatly improved by annealing at a high temperature for a short time.

  According to a second aspect of the present invention, in the activation step of the method for producing a group III nitride film according to the first aspect, the annealing temperature is 1250 ° C. or higher and 1350 ° C. or lower and the time is 10 seconds or longer and 30 seconds or shorter. An activation process is performed.

  According to a third aspect of the present invention, in the activation step of the method for producing a group III nitride film according to the first aspect, an activation treatment is performed at an annealing temperature of 1150 ° C. or higher and 1250 ° C. or lower for 30 seconds or longer. It is characterized by.

  According to a fourth aspect of the present invention, in the activation step of the method for producing a group III nitride film according to any one of the first to third aspects, activation is performed at 1100 ° C. for 30 minutes to 90 minutes. Annealing treatment is performed.

  According to a fifth aspect of the present invention, in the method for producing a group III nitride film according to any one of the first to fourth aspects, the ion implantation step includes at least a lattice site of a group III element and a lattice site of nitrogen. It is characterized in that ions of elements that can be introduced into any of them are implanted. For example, the lattice site of the group III element is Ga, and the lattice site of nitrogen is N.

  According to a sixth aspect of the present invention, there is provided an ion of an element that can be introduced into a lattice site of a group III element in the ion implantation step of the method for producing a group III nitride film according to any one of the first to fourth aspects. And an ion of an element that can be introduced into a lattice site of nitrogen.

  According to a seventh aspect of the present invention, in the method for producing a group III nitride film according to any one of the first to sixth aspects, after the ion implantation step and before the annealing step, A step of covering the surface of the group III nitride film with a cap layer of a dielectric film is provided. For example, it is possible to form the dielectric film using SiO2, SiN, AlN, graphite or the like. The film thickness can be about 500 nm, for example. By providing such a cap layer, it is possible to obtain an effect of suppressing the detachment of nitrogen during annealing.

  According to an eighth aspect of the present invention, in the method for manufacturing a group III nitride film according to any one of the first to seventh aspects, the annealing step performs a high-temperature annealing treatment in a nitrogen-pressurized atmosphere. It is characterized by that.

According to a ninth aspect of the present invention, in the method for producing a group III nitride film according to the eighth aspect, the annealing step is performed in a nitrogen-pressurized atmosphere of 1013 hPa or more.
A tenth aspect of the present invention is the method of manufacturing a group III nitride film according to any one of the first, fifth, sixth, seventh, eighth, and ninth aspects, wherein the ion implantation is performed. In the step, dopant is ion-implanted into a group III nitride film grown on a silicon substrate, and in the activation step performed after the ion implantation, the sheet resistance after activation annealing is set to 70 W / sq. Or more and 300 W / It is characterized by performing a heat treatment to be sq.

  An eleventh aspect of the present invention is a group III nitride semiconductor device using a group III nitride film formed by the method according to any one of the first to tenth aspects. is there.

  According to a twelfth aspect of the present invention, in the group III nitride semiconductor device according to the eleventh aspect, silicon is ion-implanted into a p-type or i-type nitride semiconductor and then activated by high-temperature annealing. An FET type compound semiconductor device in which a source region and a drain region are formed by the above.

  According to the present invention, the ion implantation layer can be activated in a very short time by high-temperature annealing, and the production efficiency is improved. Further, it is preferable to provide an effective protective film for preventing nitrogen escape as a protective film.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, in order to clarify the position of the present invention, an example of an application situation of the present invention will be described using a method for manufacturing a gallium nitride (GaN) semiconductor element having a MOSFET structure.

  1 and 2 show a manufacturing process for manufacturing a nitride compound semiconductor transistor (group III nitride semiconductor device) having a MOSFET structure using the method for manufacturing a group III nitride film according to the first embodiment of the present invention. FIG. In the example of FIGS. 1 and 2, gallium nitride (GaN) doped with a p-type impurity is used as the nitride compound. In the manufacturing process of this MOSFET, the features of the present invention are most apparent in the processing steps shown in FIGS. 1 (c) to 2 (a).

First, as shown in FIG. 1A, a buffer layer 2 made of AlN or GaN and having a thickness of about 20 nm is formed on a substrate 1 made of sapphire, SiC, Si or the like by, for example, metal organic chemical vapor deposition (MOCVD). Then, a p-GaN layer having a thickness of about 1 μm is grown in order (all of these film thicknesses are examples). For example, Mg is used as the p-type dopant, and the dopant concentration can be set to 1 × 10 ¹⁶ to 1 × 10 ¹⁷ / cm ³ , for example.

  Note that GaN or the like grown on the substrate is not limited to the MOCVD method, and other growth methods such as a hydride vapor phase epitaxy (HVPE) method and a molecular beam epitaxy (MBE) method may be used. The same applies to other embodiments.

  Subsequently, a silicon oxide film 4 is formed on the p-GaN layer by PCVD or the like in order to protect the GaN surface from damage during an implantation process by an ion implantation process described later and to adjust the position of the implantation depth. To do.

Next, as shown in FIG. 1B, a photoresist 5 is applied on the silicon oxide film 4, and this is exposed and developed with a mask pattern to form openings in the source region and the drain region. Thereafter, an n-type dopant, for example, silicon is implanted through the opening to form an n ⁺ -type source region 6s and an n ⁺ -type drain region 6d. In this case, the n-type dopant concentration is, for example, 1 × 10 ¹⁸ to 2 × 10 ²⁰ / cm ³ .

As shown in FIG. 1C, after removing the photoresist 5 and then removing the silicon oxide film 4 with a solvent such as hydrofluoric acid, in order to suppress GaN crystal deterioration during activation annealing, FIG. As shown in (d), a SiO ₂ cap 7 as a cap layer of a dielectric film is deposited to a thickness of about 500 nm.

  Thereafter, as shown in FIG. 2A, activation annealing is performed at a temperature of 1100 ° C. to 1300 ° C. for a predetermined period according to each temperature. The relationship between the annealing temperature and time will be described in detail later. In order to more effectively suppress the generation of pits due to the annealing treatment, it is preferable to perform activation annealing in a nitrogen-pressurized atmosphere higher than normal pressure.

When the activation annealing is completed, the SiO ₂ cap 7 is removed with a solvent such as hydrofluoric acid, and as shown in FIG. 2B, a silicon oxide film 8 for forming a gate insulating film is formed by PCVD or the like. Note that an alumina (Al ₂ O ₃ ) film may be formed instead of the silicon oxide film 8.

  Thereafter, a conductive film 9 is formed on the silicon oxide film 8. Polysilicon is generally used as the conductive film 9, but a metal film such as Ni / Al or WSi may be used. In the case of polysilicon, As, P (phosphorus), B (boron) or the like is doped and grown by the CVD method, and in the case of a metal film, it is formed by sputtering or the like.

  Further, a photoresist 10 is applied on the conductive film 9, exposed and developed to leave it in the gate region, and removed from the source region 6s and drain region 6d.

  Then, as shown in FIG. 2C, the conductive film 9 and the silicon oxide film 8 are etched using the patterned photoresist 10 as a mask, and the conductive film 9 left in the gate region becomes the gate electrode 9g. The silicon oxide film 8 under the gate electrode 9g functions as a gate insulating film.

  Subsequently, after removing the photoresist 10 as shown in FIG. 2D, a lift-off method using another photoresist (not shown) is performed on the source region 6s as shown in FIG. At the same time as forming the source electrode 11s, the drain electrode 11d is formed on the drain region 6d.

  The source electrode 11s and the drain electrode 11d are made of a film such as Ti / Al, Ti / AlSi, and Mo, and are in ohmic contact with the n + -GaN layer constituting the drain region 6d and the source region 6s.

Through the above process, a normally-off type MOSFET is formed.
In the MOSFET, since the drain region 6d and the source region 6s are sufficiently activated and pits are suppressed, the sheet resistance can be greatly improved.

  In the above embodiment, the p-GaN layer is formed as the channel region. However, an n-type GaN layer may be used, and other group III-V nitride compound semiconductor layers may be formed.

  In order to verify the manufacturing method of the group III nitride film of the present invention, the activation rate, the sheet resistance, and the like were measured by changing various annealing conditions. Hereinafter, the manufacturing process of the group III nitride film to be measured in the experiment will be described with reference to FIGS.

First, a p-type GaN layer (p-GaN layer) 21 as shown in FIG. 3A is epitaxially grown on the sapphire substrate 20 by metal organic chemical vapor deposition (MOCVD). An AlN-based buffer layer was grown to 100 nm on a sapphire substrate at 1100 ° C. using trimethylaluminum (TMA) and ammonium (NH ₃ ), and then Mg was doped using cyclopentagenier magnesium (Cp ₂ Mg). GaN is grown by 1 μm to form p-GaN 21. The amount of Mg added is 5 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁷ cm ⁻³ . For the measurement, undoped GaN (un-GaN) not doped with Mg is also used.

  Instead of the MOCVD method described above, an HVPE method (halide vapor phase epitaxy method), an MBE method (molecular beam epitaxy method), or the like may be used.

Thereafter, as shown in FIG. 3B, a SiO ₂ film 22 is formed on the p-GaN layer 21 to a thickness of 20 nm. Next, as shown in FIG. 3C, a Si ion implantation layer 23 is formed by ion implantation of Si from the top of the SiO ₂ film 22 by ion implantation. In the ion implantation, the first dose is 3 × 10 ¹⁴ cm ⁻³ , the acceleration voltage is 30 keV, the second dose is 4 × 10 ¹⁴ cm ⁻³ , the acceleration voltage is 60 keV, and the third dose is 8 × 10 ¹⁴ cm. ^-3 , an acceleration voltage of 120 keV, and the fourth time, a dose of 1.5 × 10 ¹⁵ cm ^-3 and an acceleration voltage of 190 keV were performed four times.

Thereafter, as shown in FIG. 4A, after the SiO ₂ film 22 is removed by hydrofluoric acid, a cap layer 24 made of SiO ₂ is formed on the Si ion implanted layer 23 to cover the surface. Thereafter, as shown in FIG. 4 (b), in order to produce various group III nitride films (FIG. 4 (c)) to be measured with the cap layer 24 made of SiO ₂ formed, the temperature and time A high temperature annealing process was performed while changing the temperature. Thereafter, as shown in FIG. 4C, the cap layer 24 made of SiO ₂ was removed, and the activation layer 25 was measured.

  In order to form various Group III nitride films to be measured, those that were heat-treated (annealed) at 1300 ° C. for 5 seconds, 10 seconds, and 30 seconds were manufactured. Each of the manufactured group III nitride films manufactured by annealing at 1200 ° C. for 5 seconds, 1100 ° C. for 10 seconds−5 minutes−30 minutes, and 1000 ° C. for 10 seconds are manufactured. The activation rate and sheet resistance were measured and calculated. As for the annealing process, an annealing furnace was used for the annealing process at 1100 ° C. or higher, and RTA was used for the other annealing processes. The heating rate is 120 ° C./second. The activation annealing was performed in a nitrogen atmosphere chamber sealed at 1 atm (≈1013 hPa).

  FIG. 5 shows the relationship between temperature and time from sample introduction by RTA when the temperature is 1000 ° C. to 1200 ° C. as a target, and FIG. 6 shows the sample by RTA when the temperature is 1300 ° C. The relationship between temperature from introduction to temperature rise and cooling and time is shown. The sample is heated to 200 ° C. or 400 ° C. by residual heat from the sample introduction, and then the temperature is increased at a temperature rising rate of 90 ° C. to 130 ° C./second. Then, after heating for a predetermined time (5 seconds to 30 seconds) which is a target heating time, the sample is taken out by cooling. Thereby, the sample used as a measuring object is formed. RTA was performed using a lamp annealing apparatus.

  The results of these experiments are shown in FIGS. FIG. 7 is a diagram showing the activation rate after activation annealing, and FIG. 8 is a diagram showing the sheet resistance value after annealing. Normal numerical values indicate the case of ion implantation into the p-GaN layer 21, and <> indicates a measurement result when ions are implanted into the un-GaN layer. Looking at the annealing treatment result at 1300 ° C. for 10 seconds, both the activation rate and the sheet resistance are 2 to 3% higher for the un-GaN layer than the p-GaN layer 21, and the sheet resistance is lower. ing. From the difference between the amount of Mg and the dose of Si, it is presumed that the same tendency is observed at other temperatures and also in the annealing time.

  The reason why the activation rate when heated at 1300 ° C. for 30 seconds as shown in FIG. 6 exceeds 100% is that the hole measurement becomes impossible because the activated carrier concentration becomes high. Further, “NG” in FIG. 7 indicates that effective activation was not recognized. Furthermore, the display of “-UN-” in FIGS. 7 and 8 indicates that data measurement was not performed for various reasons.

  As can be seen from FIGS. 7 and 8, the activation rate increases and the sheet resistance decreases as the annealing time is increased for a long time at a high temperature. In particular, at 1300 ° C. for 30 seconds, a sheet resistance of 26Ω / sq. Was obtained. It was proved that a much better numerical value was obtained compared to the conventional 82Ω / sq. (Activation rate 86%).

Further, as described above, it has been found that even if Si ions are implanted through the SiO ₂ film 22 at 190 keV, the surface of the group III nitride is hardly damaged.

However, for example, it was confirmed that a large amount of pits were generated on the surface of the group III nitride film when annealing was performed for a predetermined period of time at 1100 ° C. or more and 1300 ° C. or less. For this reason, when a semiconductor device is formed using a group III nitride film that has been subjected to activation annealing under the above-described conditions, there is a concern about an increase in leakage current. In particular, in the case of a field effect transistor, there are problems such as a decrease in inversion carrier mobility and an increase in interface states due to damage on the GaN surface directly under the gate oxide film.

  The generation of such pits due to the high temperature annealing is considered to be due to nitridation desorption in the group III nitride film. In particular, a nitride film contains high-density crystal defects and the interatomic bonding force at the defect site is fragile. Therefore, it is considered that desorption of nitrogen is easily promoted at, for example, 1050 ° C. or higher.

Therefore, in the experiment of the present invention, the surface of the group III nitride film was covered with the cap layer 24 made of SiO ₂ , but more effectively, a protective film effective for preventing nitrogen escape, such as SiN, etc. It is desirable to prevent desorption of nitrogen during high-temperature annealing by covering with a cap layer (cap layer of dielectric film). Further, even if covered with a cap layer of a dielectric film, it is difficult to completely suppress the desorption of nitrogen. Therefore, instead of the cap layer of the dielectric film or in addition to the cap layer of the dielectric film, a nitrogen atmosphere By performing high-temperature annealing under pressure, it is possible to further suppress nitrogen desorption. In this case, under nitrogen atmosphere pressurization is a concept that includes not only nitrogen alone but also an atmosphere in which other gases are mixed.

  FIG. 9 shows determination results of appropriate conditions of annealing temperature and time for activating the group III nitride film in manufacturing a semiconductor device based on the measurement data shown in FIGS. ○ represents an appropriate annealing temperature and time, and x represents an inappropriate temperature. In addition, (◯) and (×) indicate that there is no measurement data, but the prediction is made based on the tendency of change in the measurement data. The shaded area indicates that the RTA apparatus cannot be experimented due to apparatus limitations, and data cannot be obtained.

  As can be seen from FIGS. 7 to 9, at a temperature of 1300 ° C., activation can be achieved by annealing in an extremely short time of about 10 seconds to 30 seconds, in particular, by annealing for 30 seconds. The sheet resistance can be greatly reduced. Actually, it is considered that an approximate result can be obtained even in a certain temperature range (for example, 1250 ° C. to 1350 ° C.).

  In addition, even when the temperature is around 1200 ° C., the sheet resistance can be reduced to a predetermined value or less by annealing for 30 seconds or more, and even at 1100 ° C., by annealing for 30 minutes, A group III nitride film having good sheet resistance can be obtained.

  In addition, by providing a protective film effective for preventing nitrogen escape on the surface of the group III nitride film, for example, a cap layer of a thick silicon nitride film of about 500 nm before activation annealing, pits caused by high-temperature annealing are provided. Can be suppressed. In order to further suppress the generation of pits, it is desirable to further anneal in a nitrogen pressurized atmosphere. In this case, the cap layer of the dielectric film may be omitted.

  Note that when RTA is used in the annealing process, the temperature can be increased in a short time and the activation annealing process can be performed in a short time, but is not suitable for pressurization in a nitrogen atmosphere. On the other hand, an electric furnace can be pressurized but takes time to reach a high temperature. Therefore, it is desirable to select a method for performing the activation annealing according to the impurity concentration, the target activation rate, and the like.

  Next, a method for manufacturing a group III nitride film according to the second embodiment of the present invention will be described. Here, using the method for manufacturing a group III nitride film according to the second embodiment, a nitride compound semiconductor transistor (group III nitride semiconductor device) having a MOSFT structure is manufactured as in the first embodiment. The process will be described.

In the method for producing a group III nitride film according to the present embodiment, a silicon (Si) substrate is used as the substrate 1 shown in FIG.
First, an AlN buffer layer 2 is epitaxially grown 100 nm on a silicon (Si) substrate by MOCVD (metal organic chemical vapor deposition) at 1100 ° C. using trimethylaluminum (TMA) and ammonia (NH ₃ ). .

Thereafter, the Mg-doped p-GaN layer 3 is grown by 1 mm using cyclopentadienyl magnesium (Cp ₂ Mg). The addition amount of Mg is set to 5 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁷ cm ⁻³ .
Instead of the MOCVD method described above, an HVPE method (halide vapor phase epitaxy method), an MBE method (molecular beam epitaxy method), or the like may be used.
Thereafter, a 20 nm thick silicon oxide film (SiO ₂ ) 4 is formed on the p-GaN layer 3.

Next, as shown in FIG. 1B, a photoresist 5 is applied on the silicon oxide film 4, and this is exposed and developed with a mask pattern to form openings in the source region and the drain region. Thereafter, an n-type dopant, for example, silicon is implanted through the opening to form an n ⁺ -type source region 6s and an n ⁺ -type drain region 6d. In this case, Si is implanted by ion implantation at a dose of 3x10 ¹⁵ cm ^-2 and an acceleration voltage of 190 keV to produce a 300 nm deep BOX layer.

Next, as shown in FIG. 1C, after removing the photoresist 5 and then removing the silicon oxide film 4 with a solvent such as hydrofluoric acid, in order to suppress GaN crystal deterioration during activation annealing. As shown in FIG. 1D, a SiO ₂ cap 7 as a cap layer of a dielectric film is deposited to a thickness of about 500 nm.

Thereafter, as shown in FIG. 4B, in order to generate various group III nitride films (FIG. 4C) to be measured with the cap layer 24 made of SiO ₂ formed, after ion implantation, In the activation step to be performed, high-temperature annealing is performed so that the sheet resistance after activation annealing is 70 W / sq. Or more and 300 W / sq. Or less.

Specifically, activation annealing (high-temperature annealing) was performed at 900 ° C. to 1300 ° C. for 5 seconds to 2 minutes under an Ar flow using an annealing furnace or RTA apparatus. The heating rate is 120 ° C./sec. Here, the activation annealing may be performed using an electric furnace or the like instead of the annealing furnace or the RTA apparatus.
Thereafter, as shown in FIG. 4C, the cap layer 24 made of SiO ₂ was removed, and the activation layer 25 was measured.

  10 and 11 show the results of an experiment in the case where the activation annealing (high temperature annealing treatment) is performed using an annealing furnace. FIG. 12 and FIG. 13 show the results of experiments when the activation annealing is performed using an RTA apparatus. From these experimental results, it can be seen that the activation rate is improved and the sheet resistance is decreased as the high-temperature annealing treatment is performed for a long time at a high temperature.

  FIG. 15 is a photograph of the surface state after activation annealing when the activation annealing (high temperature annealing treatment) is performed under the conditions of (1) 1300 ° C. for 30 seconds. From this photograph, it can be seen that round peeling and peeling are observed on the surface of the GaN layer. On the other hand, FIG. 14 is a photograph of the surface state after activation annealing when the activation annealing is performed under the conditions of (2) 1200 ° C. for 10 seconds. From this photograph, it can be seen that the surface of the GaN layer is a mirror surface. For this reason, in the sample subjected to activation annealing under the severer conditions of 1300 ° C and 30 seconds (1), the sheet resistance is extremely low at 40 W / sq., But the surface of the GaN layer is peeled off. A trade-off was confirmed. On the other hand, in the sample subjected to activation annealing at 1200 ° C for 10 seconds (2), the sheet resistance is 100 W / sq., Which is practically acceptable (for example, the on-resistance of the FET does not increase dramatically). ) Is obtained with good reproducibility.

  As described above, in the second embodiment, in the ion implantation step, dopant is ion-implanted into the group III nitride film grown on the silicon (Si) substrate, and after the activation annealing in the activation step performed after the ion implantation. High-temperature annealing is performed so that the sheet resistance is 70 W / sq. Or more and 300 W / sq. Or less. Specifically, in the activation annealing process after ion implantation, the sheet resistance is 70 W / sq. Or more and 300 W / sq. Or less under conditions of 900 ° C to 1500 ° C and 1 second to 1 hour. High temperature annealing is performed. By this method, peeling of the GaN layer formed on the silicon (Si) substrate, that is, occurrence of peeling on the surface of the GaN layer as shown in FIG. 15 can be suppressed, and a high activity rate can be achieved.

  Further, when the activation annealing is performed under the conditions of (3) 1300 ° C. for 10 seconds, peeling occurs at the interface between the GaN layer and the silicon (Si) substrate as shown in the photograph of FIG. According to the second embodiment, the occurrence of such peeling at the interface between the GaN layer and the silicon (Si) substrate can be suppressed, and a high activity rate can be achieved.

  In the above description, the case where n-type ions (silicon) are implanted into the p-type nitride film has been described. However, p-type ions (eg, Mg, Zn, Be, etc.) are implanted into the n-type nitride film. It is also possible to do. That is, it is possible to implant ions of an element that can be introduced into at least one of a group III element lattice site and a nitrogen lattice site. It is also possible to implant both ions of elements that can be introduced into the lattice sites of group III elements and ions of elements that can be introduced into the lattice sites of nitrogen.

It is sectional drawing (the 1) which shows a part of manufacturing process which manufactures the nitride compound semiconductor transistor of MOSFET structure using the manufacturing method which concerns on 1st Embodiment of this invention. It is sectional drawing which shows a part (the 2) of the manufacturing process which manufactures the nitride compound semiconductor transistor of MOSFET structure using the formation method which concerns on 1st Embodiment of this invention. It is sectional drawing which shows a part (the 1) of the manufacturing process of the group III nitride film formed by changing various temperature-time conditions for data measurement. It is sectional drawing which shows a part (the 2) of the manufacturing process of the group III nitride film formed by changing various temperature-time conditions for data measurement. FIG. 7 is a graph showing the relationship between the time from sample introduction by RTA to temperature rise and cooling when temperature 1000 ° C. and 1200 ° C. are targets. FIG. 5 is a diagram showing the relationship between the temperature and time from sample introduction by RTA to temperature rise and cooling when a temperature of 1300 ° C. is targeted. It is a figure which shows the activation rate after activation annealing. It is a figure which shows the sheet resistance value after annealing. It is a figure which shows the determination result of the appropriate conditions of annealing temperature and time for activating the group III nitride film at the time of manufacturing a semiconductor device. The experimental result when the annealing temperature is changed is shown as an experimental result when the activation annealing of the manufacturing method according to the second embodiment of the present invention is performed using an annealing furnace. The same experimental results as in FIG. 10 show the experimental results when the annealing time is changed. The experimental result when the annealing temperature is changed is shown as an experimental result when activation annealing of the manufacturing method according to the second embodiment of the present invention is performed using an RTA apparatus. The experimental result similar to FIG. 12 shows the experimental result when the annealing time is changed. A photograph of the surface condition after activation annealing when activation annealing was performed at 1200 ° C for 10 seconds. A photograph of the surface state after activation annealing when activation annealing was performed at 1300 ° C for 30 seconds. A photograph of the interface between the GaN layer and the silicon (Si) substrate after activation annealing when activation annealing was performed at 1300 ° C for 10 seconds.

Explanation of symbols

1: Substrate 2: Buffer layer 3: GaN layer 4: Silicon participation film 5: Photoresist 6s: Source region 6d: Drain region 7: Silicon oxide film 8: Silicon oxide film (gate insulating film)
9: Conductive film 9g: Gate electrode 10: Photoresist 11s: Source electrode 11d: Drain electrode 20: Sapphire substrate 21: p-GaN
22: Silicon oxide film 23: Si injection layer 24: Silicon oxide film 25: Activation layer

Claims (12)

A step of ion-implanting a dopant into the group III nitride film;
An activation step of activating the nitride film by subjecting the group III nitride film after ion implantation to a high temperature annealing treatment at a temperature of 1100 ° C. to 1350 ° C. for a period of 10 seconds to 90 minutes depending on the temperature. When,
A method for producing a group III nitride film comprising:   2. The method for producing a group III nitride film according to claim 1, wherein in the activation step, annealing is performed at an annealing temperature of 1250 ° C. or higher and 1350 ° C. or lower for 10 seconds or longer and 30 seconds or shorter.   2. The method for producing a group III nitride film according to claim 1, wherein in the activation step, annealing is performed at an annealing temperature of 1150 ° C. or more and 1250 ° C. or less for a time of 30 seconds or more and 30 minutes or less.   2. The method for producing a group III nitride film according to claim 1, wherein in the activation step, activation annealing is performed at 1100 ° C. for 30 minutes to 90 minutes. 3.   5. The III according to claim 1, wherein the ion implantation step implants ions of an element that can be introduced into at least one of a group III element lattice site and a nitrogen lattice site. A method for producing a group nitride film.   5. The ion implantation step of implanting both ions of an element that can be introduced into a lattice site of a group III element and ions of an element that can be introduced into a lattice site of nitrogen. 2. A method for producing a group III nitride film according to item 1.   7. The method according to claim 1, further comprising a step of covering the surface of the group III nitride film with a cap layer of a dielectric film after the ion implantation step and before the annealing step. 2. A method for producing a group III nitride film according to item 1.   The method of manufacturing a group III nitride film according to any one of claims 1 to 7, wherein in the annealing step, high-temperature annealing is performed in a nitrogen-pressurized atmosphere.   9. The method for producing a group III nitride film according to claim 8, wherein the annealing step is performed in a nitrogen pressure atmosphere of 1013 hPa or more. In the ion implantation step, a dopant is ion-implanted into a group III nitride film grown on a silicon substrate,
The high temperature annealing treatment is performed in the activation step performed after the ion implantation so that the sheet resistance after the activation annealing is 70 W / sq. Or more and 300 W / sq. Or less. , 6, 7, 8, and 9. The method for producing a group III nitride film according to any one of the above.   A group III nitride semiconductor device comprising a group III nitride film formed by the method according to claim 1.   12. An FET type compound semiconductor device in which a source region and a drain region are formed by ion-implanting silicon into a p-type or i-type nitride semiconductor and then activating by high-temperature annealing. The group III nitride semiconductor device described in 1.