JP6233954B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply device in which the efficiency of a power transistor is increased.

  The switching power supply device is configured as shown in FIG. 8 in a step-down type using a PMOS transistor as a power transistor. Reference numeral 10C denotes a switching power supply circuit body composed of an IC, which includes an input terminal 11, an output terminal 12, a ground terminal 13, and a feedback terminal 14 for an input voltage VIN. A control circuit 15 generates a PWM (pulse width modulation) signal corresponding to the feedback voltage VFB input to the feedback terminal 14. Reference numeral 16 denotes a Pch driver circuit which drives the PMOS transistor MP1 which is a power transistor on / off based on a PWM signal input from the control circuit 15. Reference numeral 17H denotes a driver regulator that supplies the drive voltage VDRV to the Pch driver 16. The output terminal 12 is connected to the cathode of the diode D1 and one end of the inductor L1. The other end of the inductor L1 is connected in parallel with an output capacitor C1 and resistors RB1 and RB2 for detecting the output voltage VOUT.

  In the switching power supply device, when the power transistor MP1 is turned on, energy is stored in the inductor L1 and electric charge is stored in the output capacitor C1 by the current flowing by the input voltage VIN. Further, when the power transistor MP1 is turned off, the back electromotive force generated in the inductor L1 is rectified by the diode D1 and stored in the output capacitor C1. By repeating these steps, an output voltage VOUT is generated and supplied to the load.

  The output voltage VOUT is converted into a feedback voltage VFB divided by the resistors RB1 and RB2, and is taken into the control circuit 15. The control circuit 15 amplifies an error between the fetched feedback voltage VFB and an internally set output reference voltage (not shown) by an operational amplifier, and the obtained error voltage is generated by a triangular wave voltage generated by an oscillator and a comparator. The PWM signal is generated by comparison. The Pch driver 16 amplifies the PWM signal to drive on / off of the power transistor MP1. In this way, the on / off of the power transistor MP1 is controlled by the PWM signal, so that the output voltage VOUT is controlled to be a constant voltage corresponding to the above-described reference voltage.

By the way, the gate loss PG of the power transistor MP1 in the switching power supply circuit is
PG = QG ・ VGS
= CGS ・ VGS ²・ FS (1)
(For example, refer nonpatent literature 1). QG is a gate input charge (C), CGS is a gate-source capacitance (F), VGS is a gate-source voltage (V), and FS is a switching frequency (Hz).

Yasuo Inaba, “Basics and Practice of Power MOSFET Utilization”, 41 pages, CQ Publisher, published February 1, 2010

  As described above, in the power transistor, the gate loss increases in proportion to the square of the gate-source voltage VGS, and the loss is significant when the load current of the switching power supply circuit is small.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a switching power supply device that can reduce the gate loss and greatly improve the efficiency of the power transistor by changing the voltage level for driving the power transistor in accordance with the load current. It is.

In order to achieve the above object, the switching power supply device of the invention according to claim 1 includes current detection means for detecting a load current flowing directly to a power transistor that is turned on so as to store energy from the power supply to the inductor, In a switching power supply device that sets a drive voltage level for turning on the power transistor according to the value of the load current detected by the current detection means, a proportionality that generates a current proportional to the current detected by the current detection means Current generating means; and reference voltage changing means for sampling and holding a voltage corresponding to the current generated by the proportional current generating means immediately before the power transistor is turned off. The voltage sampled and held by the reference voltage changing means Correspondingly, the level of the drive voltage can be determined by changing the reference voltage. To.
According to a second aspect of the present invention, in the switching power supply device according to the first aspect, the reference voltage changing unit corresponds to the current sampled and held with respect to a transistor connected to a resistance element that generates the reference voltage. The reference voltage is changed by flowing a current to be applied.

  According to the present invention, since the level of the drive voltage of the power transistor changes according to the magnitude of the load current, the efficiency of the power transistor can be improved. This is particularly effective when a power transistor having a large gate input charge for a large-capacity switching power supply device is used. Further, the efficiency can be improved while maintaining the PWM control without changing the control method such as switching to PFM (pulse frequency modulation) control.

1 is a circuit diagram of a step-down switching power supply device according to a first embodiment of the present invention that uses a PMOS transistor as a power transistor. FIG. 1 is a circuit diagram of a switching power supply device that embodies a voltage monitoring circuit portion in the switching power supply device according to Embodiment 1; FIG. It is a circuit diagram of the switching power supply of another example which actualized the part of the voltage monitoring circuit in the switching power supply of Example 1. FIG. 3 is a circuit diagram embodying a current detection circuit and a current / voltage conversion circuit of the switching power supply device according to the first embodiment. FIG. 5 is a circuit diagram of another example in which the current detection circuit and the current / voltage conversion circuit of the switching power supply device according to the first embodiment are embodied. It is the circuit diagram which actualized the driver regulator of the switching power supply device of Example 1. FIG. It is a circuit diagram of another example which actualized the driver regulator of the switching power supply of Example 1. It is a circuit diagram of another example which actualized the driver regulator of the switching power supply of Example 1. It is a circuit diagram of another example which actualized the driver regulator of the switching power supply of Example 1. It is a circuit diagram of the switching power supply device of Example 2 of the present invention using a PMOS transistor as a power transistor. It is the circuit diagram which actualized the current monitoring circuit and driver regulator of the switching power supply device of Example 2. It is a specific circuit diagram of the driver regulator applied to the step-up type switching power supply device according to the third embodiment of the present invention that uses NMOS transistors. FIG. 12 is a specific circuit diagram of another example of the driver regulator of the switching power supply device according to the third embodiment. It is a circuit diagram of a conventional step-down switching power supply device using a PMOS transistor as a power transistor.

<Example 1>
FIG. 1 shows a configuration of a step-down switching power supply device according to a first embodiment of the present invention. The same components as those described in FIG. 8 are denoted by the same reference numerals, and detailed description thereof is omitted. Reference numeral 17 denotes a driver regulator for supplying a variable drive voltage VDRV to the Pch driver 16. The value of the voltage VDRV output from the driver regulator 17 is set according to the result of monitoring the current value detected by the current detection circuit 18 that detects the load current flowing through the power transistor MP1 by the current monitoring circuit 19.

  As a result, when the load current increases, the voltage VDRV is controlled to be low, and the gate-source voltage VGS of the power transistor MP1 increases. Conversely, when the load current is reduced, the voltage VDRV is controlled to be high, and the gate-source voltage VGS of the power transistor MP1 is reduced. Thus, the gate loss of the power transistor MP1 is reduced by controlling the gate-source voltage VGS of the power transistor MP1 according to the load current.

  FIG. 2A shows a configuration of a switching power supply apparatus having a current monitoring circuit 19A that embodies the current monitoring circuit 19 of FIG. The current monitoring circuit 19A includes a current / voltage conversion circuit 191 that converts the current detected by the current detection circuit 18 into a voltage, and n output voltages V1 of the current / voltage conversion circuit 191 (n is 2 or more). A window comparator 192 that determines the magnitude of the input voltage V1 by comparing with reference voltages Vref11 to Vref1n (Vref11 <Vref12 <... <Vref1n) and n of the window comparators 192. Are held by the clock CLK from the control circuit 15 and output as signals P1 to Pn, and latch circuits LT1 to LTn are provided.

  In the voltage monitoring circuit 19A, if the output voltage V1 of the current / voltage conversion circuit 191 is, for example, Vref11 ≦ V1 <Vref12, the output P1 of the lowest latch LT1 becomes “H”, and the remaining latches LT2 to LTn The outputs P2 to Pn are “L”. If Vref12 ≦ V1 <Vref13, the output P2 of the second latch LT2 is “H”, and the outputs P1, P3 to Pn of the remaining latches LT1, LT3 to LTn are “L”. That is, V1 <Vref11 does not detect that the load current is zero, and only one latch corresponding to the voltage V1 indicating Vref11 or higher holds the output “H” even when the power transistor MP1 is off. To do. As a result, the drive voltage VDRV output from the driver regulator 17A is varied in multiple values (n values) according to the number n of outputs from the voltage monitoring circuit 19A.

  FIG. 2B shows a configuration of a switching power supply apparatus having a current monitoring circuit 19B of another example in which the current monitoring circuit 19 of FIG. 1 is embodied. The difference from the voltage monitoring circuit 19A of FIG. 2A is that the window comparator 192 is replaced with n individual comparators CP1 to CPn. As a result, the voltage monitoring circuit 19B outputs a thermometer signal. For example, if Vref13 ≦ V1 <Vref14, the outputs of the comparators CP1 to CP3 are “H” and the outputs of the remaining comparators CP4 to CPn are “L”. The thermometer signal is held by the latch circuits LT1 to LTn even when the power transistor MP1 is off, and is input to the driver regulator 17B as signals Q1 to Qn. As a result, the drive voltage VDRV output from the driver regulator 17B (or 17C, 17D) is varied in multiple values (n values) according to the number n of outputs from the voltage monitoring circuit 19B.

  FIG. 3A shows specific examples of the current detection circuit 18 and the current / voltage conversion circuit 191. The current detection circuit 18 includes a detection resistor R1 and a detection PMOS transistor MP2 to which an input voltage VIN is applied to the source via the detection resistor R1, and the transistor MP2 has a gate and a drain commonly connected to the power transistor MP1. ing.

  In addition, the current / voltage conversion circuit 191 has a PMOS transistor MP3 whose source is applied with the input voltage VIN via the resistor R2 and whose drain is connected to the ground via the resistor R3, the voltage V2 of the source of the transistor MP2 and the transistor The operational amplifier OP1 controls the gate of the transistor MP3 according to the difference of the source voltage V3 of the MP3, and the current flowing through the transistor MP3 is controlled so that the voltage V3 becomes equal to the voltage V3. A voltage V1 proportional to the load current flowing through the power transistor MP1 is generated at the drain of the transistor.

  FIG. 3B shows a specific example of the current detection circuit 18A and the current monitoring circuit 191 in the case of using the power transistor MP1A externally attached to the switching power supply circuit main body 10A that does not incorporate the power transistor. Here, the detection resistor R4 connected to the source of the power transistor MP1A is used as the current detection circuit 18A for detecting the load current, the voltage V2 ′ generated at the source of the transistor MP1A is taken in from the current detection terminal 20, and the operational amplifier OP1 In comparison with the voltage V3, a voltage V1 proportional to the load current flowing through the power transistor MP1A is generated at the drain of the transistor MP3 by the same control as in FIG. 3A. The gate of power transistor MP1A is connected to drive terminal 21 to which the output side of Pch driver 16 is connected.

  FIG. 4A shows a specific circuit of the driver regulator 17A. The driver regulator 17A has one reference voltage Vref21 to Vref2n (Vref21 <Vref22 <... <Vref2n) selected by one of the signals P1 to Pn output from the current monitoring circuit 19A of FIG. 2A. The operational amplifier OP2 whose reference voltage is input to the non-inverting input terminal and the voltage V4 on the non-ground side of the resistor R4 are controlled to be the same as the voltage at the non-inverting terminal of the operational amplifier OP2 according to the output voltage of the operational amplifier OP2. The voltage V5 at the common connection point of the NMOS transistor MN1, the common connection point between the drain of the transistor MN1 and the resistor R5 is input to the non-inverting input terminal, and the voltage V6 at the common connection point between the resistors R6 and R7 is the same as the voltage V5. A PMOS transistor MP4 that operates so as to become a transistor M4 And a MOS transistor MN2 to flow a drain current depending fourth drain and the voltage V7 at the common junction of resistor R8. The drive voltage VDRV output to the Pch driver 16 is extracted from the drain of the transistor MN2.

Here, when the voltage generated in the resistor R5 is Va (= VIN−V5) and the voltage generated in the series circuit of the resistors R6 and R7 is Vb (= VIN−VDRV),
Vb = Va × (1 + R7 / R6) (2)
Given in. The voltage Va is generated by the resistor R5 and the current I5 flowing therethrough,
Va = R5 × I5 (3)
It becomes. Also,
I5 = V4 / R4 (4)
So
Vb = R5 × I5 × (1 + R7 / R6)
= R5 × (V4 / R4) × (1 + R7 / R6) (5)
It becomes. Therefore, to change the voltage Vb, that is, the drive voltage VDRV, the voltage V4 and the resistors R4 to R7 may be changed. 4A shows an example of changing the voltage V4, FIG. 4B to be described later shows an example of changing the resistor R4, FIG. 4C shows an example of changing the resistor R5, and FIG. 4D shows an example of changing the resistor R6.

  In the driver regulator 17A of FIG. 4A, when the load current flowing through the power transistor MP1 is maximum, the output of the current monitoring circuit 19A is that the signal Pn is “H” and the remaining P1 to Pn−1 are “L”. The highest reference voltage Vref2n is selected. As a result, the voltage V4 = Vref2n becomes the maximum, the voltage V5 becomes the minimum value accordingly, and the drive voltage VDRV of the Pch driver 16 becomes the minimum value. As a result, the gate voltage VG when the power transistor MP1 is turned on becomes the minimum value, and the gate-source voltage VGS becomes the maximum value. Thus, when the load current flowing through the power transistor MP1 is large, the gate-source voltage VGS of the power transistor MP1 becomes the maximum value.

  On the other hand, when the load current flowing through the power transistor MP1 is the minimum, the output of the current monitoring circuit 19A is such that the signal P1 is “H” and the remaining P2 to Pn are “L”, so the lowest reference voltage Vref21 is selected. Is done. As a result, the voltage V4 = Vref21 is minimized, and the voltages V5 and V6 are maximized accordingly, and the drive voltage VDRV of the Pch driver 16 is maximized. As a result, the gate voltage VG when the power transistor MP1 is turned on becomes the maximum value, and the gate-source voltage VGS becomes the minimum value. Thus, when the load current flowing through the power transistor MP1 is small, the gate-source voltage VGS of the power transistor MP1 becomes small, and the gate loss is reduced.

  FIG. 4B shows a specific circuit of another example of the driver regulator 17B. Here, the resistor R4 in the driver regulator 17A of FIG. 4A is composed of n resistors R41 to R4n, and among them, the output signal Q1 to Qn of the current monitoring circuit 19B of FIG. 2B becomes “H”. A resistor corresponding to the signal is connected in parallel. The reference voltage input to the operational amplifier OP2 is set to the lowest reference voltage Vref21 of the driver regulator 17 in FIG. 4A, and the total resistance value when all the resistors R41 to R4n are connected in parallel becomes equal to the resistance value R4 in FIG. 4A. Set as follows.

  Thus, when the load current flowing through the power transistor MP1 is maximum, the output signals Q1 to Qn of the current monitoring circuit 19B are all “H”, so that all the resistors R41 to R4n are connected in parallel, and the voltage V4 = Vref21. As a result, the current I5 flowing through the resistor R5 is maximized, so that the voltages V5 and V6 are the same as the lowest values in FIG. 4A, the drive voltage VDRV supplied to the Pch driver 16 is the lowest value, and the gate- The source-to-source voltage VGS is controlled to a large voltage.

  On the other hand, when the load current flowing through the power transistor MP1 is minimum, the output signal Q1 of the current monitoring circuit 19B is "H" and the rest is "L", so only the resistor R41 is connected and the voltage V4 = Vref21. However, since the current flowing through the resistor R5 is minimized, the voltages V5 and V6 have the highest values, the drive voltage VDRV supplied to the Pch driver 16 has the highest value, and the gate-source voltage VGS of the power transistor MP1 becomes a small voltage. Controlled and gate loss is reduced.

  FIG. 4C shows a specific circuit of another example of the driver regulator 17C. Here, the resistor R5 in the driver regulator 17A of FIG. 4A is configured by connecting resistors R51 to R5n in series, and any one or more of them are inverted signals of the output signals Q1 to Qn of the current monitoring circuit 19B of FIG. 2B. Short-circuiting is performed by XQ1 to XQn. The reference voltage input to the operational amplifier OP2 is set to the lowest reference voltage Vref21 of the driver regulator 17A in FIG. 4A, and the total resistance value when all the resistors R51 to R5n are connected in series is the resistance value R5 in FIG. 4A. Set to be equal.

  As a result, when the load current flowing through the power transistor MP1 is maximum, the output signals Q1 to Qn of the current monitoring circuit 19B are all “H”, so that the inverted signals XQ1 to XQn are all “L”, Resistors R51 to R5n are connected in series. For this reason, the voltage V5 becomes the lowest value, thereby the voltage V6 also becomes the lowest value, the drive voltage VDRV supplied to the Pch driver 16 becomes the lowest value, and the gate-source voltage VGS of the power transistor MP1 is controlled to a large voltage. .

  On the other hand, when the load current flowing through the power transistor MP1 is minimum, only the output signal Q1 of the current monitoring circuit 19B becomes “H” and the rest becomes “L”, so that the inverted signal XQ1 is “L” and the rest is “ H ", the resistor R51 is connected, and the resistors R52 to R5n are short-circuited. For this reason, the voltage V5 becomes the maximum value, the voltage V6 also becomes the maximum value, the drive voltage VDRV supplied to the Pch driver 16 becomes the maximum value, and the gate-source voltage VGS of the power transistor MP1 is controlled to a small voltage, Gate loss is reduced.

  FIG. 4D shows a specific circuit of another example of the driver regulator 17D. Here, the resistor R6 in the driver regulator 17A of FIG. 4A is composed of one resistor R60 and n resistors R61 to R6n, which are connected in parallel by the output signals Q1 to Qn of the current monitoring circuit 19B of FIG. 2B. I have to. The reference voltage input to the operational amplifier OP2 is set to the lowest reference voltage Vref21 of the driver regulator 17 in FIG. 4, and the total resistance value when the resistors R60 to R6n are connected in parallel is equal to the resistance value R6 in FIG. 4A. Set it.

  Thus, when the load current flowing through the power transistor MP1 is maximum, the output signals Q1 to Qn of the current monitoring circuit 19B are all "H", so that all the resistors R60 to R6n are connected and exhibit the minimum resistance value. . Since the voltage V6 is equal to the voltage V5, the drive voltage VDRV supplied to the Pch driver 16 becomes the lowest value, and the gate-source voltage VGS of the power transistor MP1 is controlled to a large voltage.

  On the other hand, when the load current flowing through the power transistor MP1 is minimum, the output signal Q1 of the current monitoring circuit 19B indicates “H” and the remaining Q2 to Qn indicate “L”, so that the resistors R60 and R61 are connected. Indicates the maximum resistance value. Since the voltage V6 is equal to the voltage V5, the driving voltage VDRV supplied to the Pch driver 16 becomes the maximum value, the gate-source voltage VGS of the power transistor MP1 is controlled to a small voltage, and the gate loss is reduced.

<Example 2>
FIG. 5 shows the configuration of the switching power supply device according to the second embodiment of the present invention. Reference numeral 10B denotes a switching power supply device body constituted by an IC. In FIGS. 4A to 4D described above, the example in which the voltage VDRV output to the driver regulators 17A to 17D is changed to the n value has been described. However, in the second embodiment, the voltage VDRV output to the driver regulator 17 is This is an example of changing to linear. Here, the current monitoring circuit 19 includes a proportional current generation circuit 193 that generates a current proportional to the load current, and a reference voltage change circuit 194 that changes the voltage V5 according to an output signal of the proportional current generation circuit 193. Yes. Since the voltage V5 is a voltage linked to the reference voltage Vref2n, it can be handled as a reference voltage (described as a second reference voltage in the claims).

  FIG. 6 shows a specific circuit thereof. The proportional current generation circuit 193 includes an operational amplifier OP4, a transistor MP5, and a resistor R9 that control the source voltage V8 of the PMOS transistor MP5 to be equal to the voltage V2 output from the current detection circuit 18, and is connected to the drain of the transistor MP5. A current Ia proportional to the voltage V2 is output. The reference voltage changing circuit 194 includes a current mirror circuit composed of PMOS transistors MP6 and MP7, and a sample and hold circuit 195 that samples and holds the drain voltage of the transistor MP6 and inputs it to the gate of the transistor MP7. The drains of the transistors MP5 and MP6 are commonly connected to the current source I1.

The drain current Ia of the transistor MP5 is
Ia = (VIN−V2) / R9 (6)
Therefore, the drain current Ib of the transistor MP6 is
Ib = I1-Ia (7)
It becomes. When the current Ia exceeds the current I1, the current Ib stops flowing. When the power transistor MP1 is turned off, the load current does not flow, so the voltage V2 is not generated and the current Ia does not flow. However, by holding the drain voltage of the immediately preceding transistor MP6 by the sample hold circuit 195, The transistor MP7 continuously flows the drain current Ib.

  Therefore, since the current Ia increases as the load current of the power transistor MP1 increases, the output current Ib of the reference voltage changing circuit 194 decreases and the voltage V5 decreases. For this reason, the drive voltage VDRV output to the Pch driver 16 also decreases, and the gate-source voltage VGS of the power transistor MP1 is controlled to a large voltage.

  On the other hand, when the load current of the power transistor MP1 decreases, the current Ia decreases, so the output current Ib of the reference voltage changing circuit 194 increases and the voltage V5 increases. For this reason, the voltage VDRV output to the Pch driver 16 also rises, the gate-source voltage VGS of the power transistor MP1 is controlled to a small voltage, and the gate loss is reduced.

<Example 3>
FIG. 7A shows a specific driver regulator 17F of the switching power supply device according to the third embodiment of the present invention. The third embodiment is applied to a step-up switching power supply device (specific configuration is omitted). In this switching power supply circuit, an NMOS transistor is used as the power transistor. Therefore, the VGS of the power transistor increases when the output voltage VDRV of the driver regulator 17F increases, and decreases when the output voltage VDRV decreases.

In FIG. 7A, the driver regulator 17F receives signals P1 to Pn output from the current monitoring circuit 19A shown in FIG. 2A from among n reference voltages Vref31 to Vref3n (Vref31 <Vref32 <. The operational amplifier OP11 in which one selected reference voltage is input to the non-inverting input terminal, and the voltage V11 at the common connection point of the resistors R12 and R13 according to the output voltage of the operational amplifier OP11 is the same as the voltage at the non-inverting terminal of the operational amplifier OP11. NMOS transistors MN11 and MN12 controlled so as to become a resistor R11. The drive voltage VDRV output to the Nch driver (not shown) is extracted from the source of the transistor MN12. This voltage VDRV is
VDRV = V11 × (1 + R12 / R13) (8)
It becomes.

  Thus, when the load current flowing through the NMOS power transistor is maximum, the output signal Pn of the current monitoring circuit 19A in FIG. 2A is “H” and the rest is “L”, so the maximum reference voltage Vref3n is connected. The For this reason, the voltage V11 becomes the highest value, thereby the driving voltage VDRV supplied to the Nch driver becomes the highest value, and the gate-source voltage VGS of the NMOS power transistor is controlled to a large voltage.

  On the other hand, when the load current flowing through the NMOS power transistor is minimum, the output signal P1 of the current monitoring circuit 19A is "H" and the rest is "L", so the lowest reference voltage Vref31 is connected. For this reason, the voltage V11 becomes the lowest value, thereby the drive voltage VDRV supplied to the Nch driver becomes the lowest value, the gate-source voltage VGS of the NMOS power transistor is controlled to a small voltage, and the gate loss is reduced.

  FIG. 7B shows a specific driver regulator 17G of another example of the switching power supply device according to the third embodiment of the present invention. In the third embodiment, the maximum reference voltage Vref3n of FIG. 7A is connected as the reference voltage of the operational amplifier OP11. The resistor R12 in FIG. 7A is configured by connecting a resistor R120 and n resistors R121 to R12n in series, and any one or more of the signals Q1 to Qn output from the current monitoring circuit 19B of FIG. The selection is made by the inversion signals XQ1 to XQn.

  As a result, when the load current flowing through the NMOS power transistor is maximum, all of the output signals Q1 to Qn of the current monitoring circuit 19B of FIG. 2B are "H", and the inverted signals XQ1 to XQn are "L". Therefore, all of the resistors R120 to R12n are connected, and the total resistance value is maximized. For this reason, the drive voltage VDRV output to the Nch driver is set to the maximum value. Therefore, the gate-source voltage VGS of the NMOS power transistor is controlled to a large voltage.

  On the other hand, when the load current flowing through the NMOS power transistor is minimum, the inverted signal XQ1 of the output signal of the current monitoring circuit 19B in FIG. 2 is “L” and the remaining inverted signals XQ2 to XQn are “H”. Although the resistors R120 and R121 are connected, the remaining resistors RR120 and 122 to R12n are short-circuited, and the total resistance value is minimized. For this reason, the drive voltage VDRV supplied to the Nch driver becomes the lowest value, the gate-source voltage VGS of the NMOS power transistor is controlled to a small voltage, and the gate loss is reduced.

  10, 10A, 10B, 10C: switching power supply device, 11: input terminal, 12: output terminal, 13: ground terminal, 14: feedback terminal, 15: control circuit, 16: Pch driver, 17, 17A, 17B, 17C, 17D, 17E, 17F, 17G, 17H: Driver regulator, 18: Current detection circuit, 19, 19A, 19B: Current monitoring circuit, 20: Current detection terminal, 21: Drive terminal

Claims (2)

Current detecting means for detecting a load current flowing directly to a power transistor that is turned on so as to store energy from the power supply to the inductor; and the power transistor is controlled according to the value of the load current detected by the current detecting means. In the switching power supply device that sets the level of the drive voltage to be turned on,
Proportional current generating means for generating a current proportional to the current detected by the current detecting means, and reference voltage changing means for sample-holding a voltage corresponding to the current generated by the proportional current generating means immediately before the power transistor is turned off. And a level of the drive voltage is determined by changing the reference voltage corresponding to the voltage sampled and held by the reference voltage changing means.
The switching power supply device according to claim 1,
Said reference voltage changing means, switching characterized that you change the reference voltage by supplying a current corresponding to the sampled and held voltage to a transistor connected to a resistor element for generating the reference voltage Power supply.

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