JP6181983B2 - Switching regulator - Google Patents

Description

  The technology disclosed in the present application relates to a switching regulator.

  The switching regulator generates an output voltage to be supplied to a load circuit connected to the output terminal from the supplied input voltage. Some switching regulators control driving of a switch according to an output voltage output to a load circuit and a voltage between terminals of a sense resistor connected to a preceding stage of an output terminal (for example, Patent Documents 1 and 2) ). This switching regulator includes, for example, a plurality of switches having different current capacities in order to reduce the loss in the switch when driving the switch so that the output voltage is maintained at a desired potential, and according to the magnitude of the flowing current. Control to switch. For example, in the case of a heavy load in which the load of the load circuit increases and the load current flowing through the sense resistor increases, the switching regulator drives a switch having a large current capacity to reduce the loss in the switch.

JP-A-8-149804 JP 2006-238603 A

  In the switching regulator described above, a terminal voltage generated in the sense resistor due to a load current that increases or decreases with respect to a load change from a light load to a heavy load is detected by a detection circuit such as a comparator. The resistance value of the sense resistor is set as large as possible in order to switch a switch having a different current capacity by detecting a change in load current that decreases as the load decreases. However, when the resistance value of the sense resistor is increased, the power consumption generated by the sense resistor increases as the load becomes heavy and the load current increases.

  The technology disclosed in the present application has been proposed in view of the above-described problems, and an object thereof is to provide a switching regulator capable of reducing power consumption generated by a sense resistor regardless of a load variation.

  A switching regulator according to a technique disclosed in the present application detects a load current flowing in an external load connected to an output terminal and senses a sense resistor connected to an output terminal from which an output voltage is output based on the input voltage, and a sense A clamp circuit that is connected to the resistor and clamps a voltage between both terminals of the sense resistor that varies according to the load current.

  According to the switching regulator according to the technology disclosed in the present application, the voltage between the terminals of the sense resistor is clamped according to the fluctuation of the load. Therefore, while ensuring the sensing ability in the sense resistor at the light load, The power consumption at the sense resistor can be reduced.

The circuit diagram of the switching regulator of an embodiment. The timing chart which shows operation | movement of a regulator. The circuit diagram of the switching regulator of the 1st example of another. The timing chart which shows the operation | movement of the regulator of the 1st another example. The circuit diagram of the switching regulator of the 2nd example of another. The timing chart which shows the operation | movement of the regulator of a 2nd another example.

A configuration of a switching regulator (hereinafter referred to as “regulator”) 10 according to the present embodiment will be described with reference to FIG.
The regulator 10 shown in FIG. 1 includes a plurality of (two in this embodiment) switches 11 and 12, a control circuit 13 that drives each of the switches 11 and 12, a sense resistor Rs connected to the output terminal OUT, and a sense And a clamp circuit 20 connected to both ends of the resistor Rs. The regulator 10 is a step-down DC / DC converter, and generates an output voltage Vout supplied from an externally supplied input voltage Vin to a load circuit (not shown) connected to the output terminal OUT. Each of the switches 11 and 12 has a DC input voltage Vin connected to its input terminal. The switches 11 and 12 are, for example, pMOS transistors. The switch 12 is a pMOS transistor having a larger current capacity than that of the switch 11, for example. The switches 11 and 12 perform a switching operation when the gate voltage is input from the control circuit 13 to the gate terminals.

  A filter circuit including a diode 15, a coil 16, and a capacitor 17 is connected to the output side of the switches 11 and 12. The output terminals of the switches 11 and 12 are connected to the cathode terminal of the diode 15 and the input side of the coil 16, respectively. The anode terminal of the diode 15 is connected to the ground GND. The output side of the coil 16 is connected to the input side of the sense resistor Rs and is connected to the ground GND via the capacitor 17.

  The sense resistor Rs is for detecting a load current supplied to a load circuit connected to the output terminal OUT of the regulator 10, and the output side is connected to the output terminal OUT. The control circuit 13 receives the output voltage Vout of the output terminal OUT. The control circuit 13 is connected to the oscillation circuit 18, and a reference clock CLK that is a reference for circuit operation of the regulator 10 is input from the oscillation circuit 18. Based on the output voltage Vout, for example, the control circuit 13 performs control to maintain the output voltage Vout constant by changing the drive time (duty ratio) of the switches 11 and 12 by switching control.

  A comparator 19 is connected to both ends of the sense resistor Rs. The non-inverting input terminal of the comparator 19 is connected to the input side of the sense resistor Rs. Further, a voltage having a potential higher than the potential on the output side of the sense resistor Rs by the reference voltage Vref1 is input to the inverting input terminal of the comparator 19. The comparator 19 outputs the result of comparing the terminal voltage Vrs of the sense resistor Rs and the reference voltage Vref1 to the control circuit 13 as the output voltage V1. The control circuit 13 detects an increase / decrease in the load current Iout flowing through the sense resistor Rs based on the output voltage V1. The control circuit 13 switches the switches 11 and 12 to be driven based on the output voltage V1. For example, the control circuit 13 drives the switch 11 when the load current Iout is a light load. In addition, the control circuit 13 drives both the switches 11 and 12 when the load current Iout is a heavy load. Thereby, the loss in the switches 11 and 12 can be reduced by driving the switches 11 and 12 having different current capacities according to the load current Iout. In this case, the value of the reference voltage Vref1 is set by the potential of the inter-terminal voltage Vrs of the sense resistor Rs when shifting from the light load state driving the switch 11 to the heavy load state driving both the switches 11 and 12. Is done. The switches 11 and 12 may be pMOS transistors having the same current capacity, for example. Further, the control circuit 13 may be set so that only the switch 11 is driven when the load is light, and only the switch 12 is driven when the load is heavy.

  A clamp circuit 20 is connected to both ends of the sense resistor Rs. The clamp circuit 20 includes a pMOS transistor M1 and an amplifier circuit 22. The input end side of the sense resistor Rs is connected to the source terminal of the pMOS transistor M1 and the inverting input terminal of the amplifier circuit 22, respectively. The drain terminal of the pMOS transistor M1 is connected to the output side of the sense resistor Rs, and the pMOS transistor M1 is connected in parallel to the sense resistor Rs. In addition, a voltage having a potential higher than the potential on the output side of the sense resistor Rs by the reference potential Vclmp is input to the non-inverting input terminal of the amplifier circuit 22. The output voltage Vg of the amplifier circuit 22 is input to the gate terminal of the pMOS transistor M1.

  The amplifier circuit 22 amplifies a difference between a voltage that is higher than the potential on the output side of the sense resistor Rs by the reference potential Vclmp and a voltage on the input side of the sense resistor Rs. That is, the difference between the inter-terminal voltage Vrs and the reference potential Vclmp is amplified and output as the output voltage Vg to the gate terminal of the pMOS transistor M1. Therefore, the pMOS transistor M1 is driven when the potential of the voltage Vrs between the terminals of the sense resistor Rs is higher than the reference potential Vclmp. The pMOS transistor M1 is turned on according to the output voltage Vg of the amplifier circuit 22. As a result, the inter-terminal voltage Vrs is restricted from changing to a potential higher than the reference potential Vclmp.

  Next, the operation of the regulator 10 will be described with reference to the timing chart shown in FIG. For example, the output voltage V1 of the comparator 19 is set such that the signal level is switched when the load current Iout is 10 mA. If the reference voltage Vref1 in this case is 5 mV, the resistance value of the sense resistor Rs is 0.5Ω (= 5 mV / 10 mA). Further, the reference potential Vclmp is set to 10 mV.

  First, at time T1, the control circuit 13 drives the switch 11 (denoted as SW11 in the figure), and the load of the load circuit connected to the output terminal OUT increases from the state where the output voltage Vout is stable at a constant value. The load current Iout flowing through the sense resistor Rs increases. Next, at time T2, the load current Iout increases to 10 mA (terminal voltage Vrs is 5 mV). The control circuit 13 detects the transition of the signal level of the output voltage V1 of the comparator 19 to the high level and detects that the load current Iout has increased to 10 mA. The control circuit 13 drives a switch 12 (denoted as SW12 in the drawing) in addition to the switch 11.

  Further, the output voltage Vg of the amplifier circuit 22 decreases as the inter-terminal voltage Vrs increases. However, at this time, the pMOS transistor M1 is still maintained in a non-conductive state. When the load current Iout exceeds 20 mA at time T3, the terminal voltage Vrs exceeds the reference potential Vclmp (= 10 mV). As a result, the output voltage Vg of the amplifier circuit 22 further decreases to reduce the on-resistance of the pMOS transistor M1 and to turn on, and a part of the load current Iout is shunted. As a result, the current flowing through the sense resistor Rs is reduced and the inter-terminal voltage Vrs is reduced. As a result, the output voltage Vg is increased, the on-resistance of the pMOS transistor M1 is increased, and the flowing current is reduced. As a result, the current flowing through the sense resistor Rs again increases, the terminal voltage Vrs increases, the output voltage Vg decreases, the pMOS transistor M1 becomes conductive, and a part of the load current Iout is shunted. Thereafter, such feedback control is performed, and the inter-terminal voltage Vrs is clamped. While the terminal voltage Vrs is clamped to 10 mV, the current flowing through the sense resistor Rs is limited, while the remaining current of the load current Iout flows through the pMOS transistor. The amount of current that increases as the load increases flows through the pMOS transistor. Even in the case of a heavy load, the load current Iout can flow while the inter-terminal voltage Vrs of the sense resistor Rs is clamped. For example, when a memory is connected to the regulator 10 as a load circuit, the load current Iout increases from the time when access to the memory occurs, in this case from time T2 to time T4. During this time, the voltage Vrs between the terminals of the sense resistor Rs is clamped to 10 mV.

  At time T4, the load current Iout reaches its maximum value at 10A and then decreases. Here, for example, in a regulator not provided with the clamp circuit 20, the inter-terminal voltage Vrs increases to 5 V (= 10 A × 0.5Ω) as the load current Iout increases. Therefore, in a regulator not provided with the clamp circuit 20, the power consumption Prs generated in the sense resistor Rs at time T4 is 50 W (= 10 A × 5 V). On the other hand, when the resistance value of the sense resistor Rs is reduced in order to suppress the increase in the power consumption Prs in the heavy load, the inter-terminal voltage Vrs becomes relatively small, and a minute change in the load current Iout that occurs in the case of a light load is observed. It becomes difficult to detect by the comparator 19. As a result, it becomes difficult to switch the switches 11 and 12 having different current capacities with high accuracy due to load fluctuations, and loss in the switches 11 and 12 cannot be reduced, leading to a decrease in conversion efficiency.

  As another method, a method of short-circuiting the sense resistor Rs when the load current Iout increases in a heavy load is conceivable. However, in such a configuration, once the short-circuit is performed, the state of the load circuit is changed from a heavy load to a light load. Makes it difficult to detect a change in which the load current Iout decreases. As a result, it is difficult to automatically return to a state in which only the switch 11 is driven as the heavy load returns to the light load state.

  On the other hand, in the regulator 10 of this embodiment, by providing the clamp circuit 20, as shown in FIG. 2, the inter-terminal voltage Vrs is clamped to 10 mV in the case of a heavy load. Therefore, in the regulator 10 of the present embodiment, the power consumption Prs generated at the sense resistor Rs at time T4 is suppressed to 0.1 W (= 10 A × 10 mV). As a result, an increase in the power consumption Prs of the sense resistor Rs in a heavy load is suppressed, and the switches 11 and 12 can be appropriately switched with respect to load fluctuations, thereby improving the conversion efficiency.

  At time T5, the load current Iout decreases to 20 mA, and the terminal voltage Vrs that has been clamped to 10 mV starts to decrease. At time T6, the load current Iout decreases to 10 mA (terminal voltage Vrs is 5 mV). The control circuit 13 detects a low level transition of the signal level of the output voltage V1 of the comparator 19 and detects that the load current Iout has decreased to 10 mA. The control circuit 13 stops driving the switch 12. Accordingly, it is possible to automatically return to a state in which only the switch 11 having a small current capacity is driven in accordance with the state transition from the heavy load to the light load. That is, the conversion efficiency can be improved by switching the switches 11 and 12 with respect to the load fluctuation.

As described above, according to the present embodiment, the following effects can be obtained.
The regulator 10 has two switches 11 and 12 connected to the input voltage Vin. The regulator 10 includes a sense resistor Rs that detects a load current Iout of a load circuit connected to the output terminal OUT, and the control circuit 13 changes the switches 11 and 12 that are driven according to the voltage Vrs between the terminals of the sense resistor Rs. To do. The sense resistor Rs is connected to the clamp circuit 20, and the inter-terminal voltage Vrs is clamped to the reference potential Vclmp by the clamp circuit 20. As a result, the power consumption Prs generated in the sense resistor Rs is suppressed by the load current Iout that increases in the case of a heavy load, and a change in the load current Iout is detected in response to a load change, and the switches 11 and 12 are appropriately The conversion efficiency can be improved. That is, the power consumption Prs at the sense resistor Rs at the heavy load can be reduced while ensuring the sensing capability at the sense resistor Rs at the light load.

Needless to say, the technology disclosed in the present application is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the above embodiment, the control circuit 13 is configured to change the switches 11 and 12 that are driven based on the voltage Vrs between the terminals of the sense resistor Rs. However, the present invention is not limited to this. For example, as shown in FIG. 3, the control circuit 13 may be configured to change the switches 11 and 12 that are driven based on the output voltage Vg of the clamp circuit 20. In addition, in the regulator 10A shown in FIG. 3, about the same structure as the regulator 10 of the said embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably.

  As shown in FIG. 3, the regulator 10A includes a comparator 19A. The output voltage Vg of the amplifier circuit 22 of the clamp circuit 20 is input to the inverting input terminal of the comparator 19A. The reference voltage Vref2 is input to the non-inverting input terminal of the comparator 19A. The amplifier circuit 22 receives the output voltage Vout as a power supply voltage, and the inter-terminal voltage Vrs is lower than the reference potential Vclmp. That is, while the clamp circuit 20 is not driven, the output voltage Vg is a high voltage level equivalent to the output voltage Vout. It becomes. In this case, the reference voltage Vref2 input to the comparator 19A is set to a potential at which driving of the clamp circuit 20 (pMOS transistor M1) can be detected. For example, the threshold voltage Vth between the gate and the source of the pMOS transistor M1 is used and is set by the relational expression of reference voltage Vref2 = output voltage Vout−threshold voltage Vth. In this case, assuming that the voltage Vrs between the terminals of the sense resistor Rs is a small voltage, it is assumed that the voltage at the input side terminal of the sense resistor Rs (source terminal of the pMOS transistor) is substantially the output voltage Vout. Can do. Since the pMOS transistor M1 begins to conduct when a voltage lower than the source voltage by the threshold voltage Vth is applied to the gate terminal, the output voltage Vg is equal to this voltage if the voltage set by the above relational expression is the reference voltage Vref2. The pMOS transistor M1 becomes conductive when the value is lower than. The comparator 19A outputs the result of comparing the output voltage Vg and the reference voltage Vref2 to the control circuit 13 as the output voltage V2.

  Next, the operation of the regulator 10A will be described using the timing chart shown in FIG. For example, the output voltage V2 of the comparator 19A is set such that the signal level is switched when the load current Iout is 10 mA. Further, the resistance value of the sense resistor Rs is 0.5Ω, and the reference potential Vclmp is 5 mV.

  First, at time T21, the control circuit 13 increases the load current Iout from the state in which the switch 11 is driven. At time T22, the potential of the output voltage Vg is lower than that of the output voltage Vout as the inter-terminal voltage Vrs increases. When the load current lout increases to 10 mA (inter-terminal voltage Vrs is 5 mV) at time T23, the output voltage Vg of the amplifier circuit 22 further decreases, and the pMOS transistor M1 is turned on to bring the inter-terminal voltage Vrs into a clamped state. Since the pMOS transistor M1 becomes conductive, the output voltage Vg is lower than the reference voltage Vref2 = output voltage Vout−threshold voltage Vth. The control circuit 13 detects a high level transition of the signal level of the output voltage V2 of the comparator 19A. As a result, the switch 12 is driven in addition to the switch 11. While the terminal voltage Vrs is clamped at 5 mV, the load current Iout continues to increase as the load increases. The load current Iout has a maximum value at a current value of 10 A at time T24. Accordingly, even in such a configuration, an increase in the power consumption Prs in the sense resistor Rs is suppressed, and the switches 11 and 12 can be appropriately switched with respect to a load change, thereby improving the conversion efficiency.

  At time T25, the load current Iout decreases to 10 mA (inter-terminal voltage Vrs is 5 mV), and the control circuit 13 detects that the output voltage Vg has increased to the reference voltage Vref2 based on the output voltage V2, and switches 12 is stopped. Thereby, only the switch 11 having a small current capacity can be driven in accordance with the state transition from the heavy load to the light load.

  Moreover, in the said embodiment, although the regulator 10 was set as the structure which has the two switches 11 and 12, it is not limited to this, You may change to the structure which has a 3 or more several switch. For example, as shown in FIG. 5, the regulator 10B includes three switches 11, 12, 12A, and two comparators 19B, 19C that detect timings for driving the switches 12, 12A. The switch 12A is connected in parallel to the switches 11 and 12, and the switching operation is controlled by the gate voltage output from the control circuit 13. The switch 12A is a pMOS transistor having a larger current capacity than the switches 11 and 12, for example.

  In the comparator 19B, the output voltage Vg of the clamp circuit 20 is input to the inverting input terminal, and the reference voltage Vref3 is input to the non-inverting input terminal. The amplifier circuit 22 of the clamp circuit 20 receives the output voltage Vout as a power supply voltage. In this case, the reference voltage Vref3 input to the comparator 19B is set to a potential at which driving of the clamp circuit 20 (pMOS transistor M1) can be detected. For example, the threshold voltage Vth between the gate and the source of the pMOS transistor M1 is used to set the relational expression Vref3 = output voltage Vout−threshold voltage Vth. The comparator 19B outputs the result of comparing the output voltage Vg and the reference voltage Vref3 to the control circuit 13 as the output voltage V3. For example, the control circuit 13 drives the switch 12 based on the output voltage V3.

  In the comparator 19C, the output voltage Vg is input to the inverting input terminal, and the reference voltage Vref4 is input to the non-inverting input terminal. The comparator 19C detects the output voltage Vg that decreases with a predetermined value with respect to the load current Iout that further increases after driving the switches 11 and 12, and outputs the timing for driving the third switch 12A as the output voltage V4. Therefore, the reference voltage Vref4 is set to a lower level potential than the reference voltage Vref3. The relationship among the voltage levels of the output voltage Vout, the reference voltage Vref3, and the reference voltage Vref4 is Vout> Vref3> Vref4. For example, the reference voltage Vref4 is set by a relational expression of reference voltage Vref4 = output voltage Vout−gate / source voltage Vgs, using the gate-source voltage Vgs when the drain current of the pMOS transistor M1 is 100 mA. In general, in a MOS transistor, it is necessary to increase the gate-source voltage Vgs as the drain current increases, and the reference voltage Vref4 is a reference voltage for the load current Iout larger than that in the case of the reference voltage Vref3. The comparator 19C outputs the result of comparing the output voltage Vg and the reference voltage Vref4 to the control circuit 13 as the output voltage V4. The control circuit 13 drives the switch 12A based on the output voltage V4.

  Next, the operation of the regulator 10B will be described using the timing chart shown in FIG. For example, the output voltage V3 of the comparator 19B is set such that the signal level is switched when the load current Iout is 10 mA. The output voltage V4 of the comparator 19C is set so that the signal level is switched when the load current Iout is 100 mA. Further, the resistance value of the sense resistor Rs is 0.5Ω, and the reference potential Vclmp is 5 mV.

  First, at time T31, the control circuit 13 increases the load current Iout from the state in which the switch 11 is driven. At time T32, the output voltage Vg decreases in potential as compared to the output voltage Vout as the inter-terminal voltage Vrs increases. When the load current lout increases to 10 mA (inter-terminal voltage Vrs is 5 mV) at time T33, the output voltage Vg of the amplifier circuit 22 further decreases, and the pMOS transistor M1 is turned on to bring the inter-terminal voltage Vrs into a clamped state. Since the pMOS transistor M1 becomes conductive, the output voltage Vg is lower than the reference voltage Vref3 = output voltage Vout−threshold voltage Vth. The control circuit 13 drives the switch 12 in addition to the switch 11 based on the output voltage V3 of the comparator 19B. While the terminal voltage Vrs is clamped to 5 mV, the load current Iout continues to increase.

  At time T34, the load current Iout increases to 100 mA. The terminal voltage Vrs remains clamped at 5 mV. The control circuit 13 detects a high level transition of the signal level of the output voltage V4 of the comparator 19C. Thereby, in addition to the switches 11 and 12, the switch 12A is driven. The load current Iout becomes a maximum value at a current value of 10 A at time T35. Therefore, in such a configuration, an increase in the power consumption Prs in the sense resistor Rs is suppressed, and the switch 12A having a larger current capacity is driven at an appropriate timing in addition to the switches 11 and 12 with respect to a load variation. Thus, the conversion efficiency can be further improved. Further, the switches 12 and 12A are appropriately stopped in accordance with the decrease of the load current Iout. Therefore, the switches 11 and 12 having a small current capacity can be driven in accordance with the state transition from the heavy load to the light load.

  The switching regulators 10, 10A, and 10B are examples of switching regulators, the switches 11, 12, and 12A are examples of switches, the control circuit 13 is an example of control circuits, and the comparators 19, 19A to 19C are As an example of the comparator, the clamp circuit 20 is an example of the clamp circuit, the amplifier circuit 22 is an example of the amplifier, the output terminal OUT is an example of the output terminal, and the output voltage Vout is an example of the output voltage. The current Iout is an example of a load current, the pMOS transistor M1 is an example of a pMOS transistor, the inter-terminal voltage Vrs is an example of an inter-terminal voltage, the sense resistor Rs is an example of a sense resistor, and the reference voltage Vref1 is As an example of the first reference voltage, the output voltage V1 V4 as an example of the output signal, the output voltage Vg, as an example of the output voltage, the reference voltage Vref2~Vref4 are given as one example of a second reference voltage.

10, 10A, 10B Switching regulator 11, 12, 12A Switch 13 Control circuit 19, 19A-19C Comparator 20 Clamp circuit OUT Output terminal Vout Output voltage Iout Load current M1 pMOS transistor Rs Sense resistor Vrs Terminal voltage Vref1-Vref4 Reference voltage V1 ~ V4 Output voltage Vg Output voltage

Claims (3)

A sense resistor connected to the output terminal for detecting a load current flowing in an external load connected to the output terminal and outputting an output voltage based on the input voltage;
A clamp circuit connected to the sense resistor and clamping a voltage between both terminals of the sense resistor that varies according to the load current;
Characterized by comprising,
The clamp circuit is
An amplifier for inverting and amplifying the voltage difference between the terminals;
A switching regulator comprising a PMOS transistor connected in parallel to the sense resistor and controlled in conduction according to the output voltage of the amplifier . A plurality of switches that are supplied with the input voltage and controlled to output the output voltage;
A comparator for comparing the voltage between the terminals and the first reference voltage;
The switching regulator of claim 1, wherein, based on the comparator output signal, characterized by switching control of at least one switch of the plurality of switches. A plurality of switches that are supplied with the input voltage and controlled to output the output voltage;
A comparator for comparing the output voltage of the amplifier and a second reference voltage;
The switching regulator of claim 1, wherein, based on the comparator output signal, characterized by switching control of at least one switch of the plurality of switches.

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