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JP6189181B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP6189181B2
JP6189181B2 JP2013230650A JP2013230650A JP6189181B2 JP 6189181 B2 JP6189181 B2 JP 6189181B2 JP 2013230650 A JP2013230650 A JP 2013230650A JP 2013230650 A JP2013230650 A JP 2013230650A JP 6189181 B2 JP6189181 B2 JP 6189181B2
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Japan
Prior art keywords
semiconductor chip
bump electrode
semiconductor
bump
semiconductor device
Prior art date
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JP2013230650A
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English (en)
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JP2015090937A (ja
Inventor
慧至 築山
慧至 築山
福田　昌利
昌利 福田
幸史 尾山
幸史 尾山
真哉 深山
真哉 深山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
Original Assignee
Toshiba Memory Corp
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Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Priority to JP2013230650A priority Critical patent/JP6189181B2/ja
Priority to TW103123047A priority patent/TWI607514B/zh
Priority to US14/474,686 priority patent/US9570414B2/en
Priority to CN201410452983.2A priority patent/CN104637826B/zh
Publication of JP2015090937A publication Critical patent/JP2015090937A/ja
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Publication of JP6189181B2 publication Critical patent/JP6189181B2/ja
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Description

本発明の実施形態は、半導体装置の製造方法に関する。
半導体装置の小型化や高機能化を実現するために、１つのパッケージ内に複数の半導体チップを積層して封止したＳｉＰ（Ｓｙｓｔｅｍ ｉｎ Ｐａｃｋａｇｅ）構造の半導体装置が実用化されている。ＳｉＰ構造の半導体装置では、半導体チップ間の電気信号を高速に送受信することが求められる。このような場合、半導体チップ間の電気的な接続にはマイクロバンプが用いられる。マイクロバンプは、例えば５〜５０μｍ程度の直径を有し、１０〜１００μｍ程度のピッチで半導体チップの表面に半田で形成される。
このような半導体装置では、マイクロバンプの接合不良の抑制を図ることが望まれる。
特開２００３−１９７８５３号公報 米国特許出願公開第２０１０／０１３４５８３号明細書 米国特許出願公開第２０１３／０１３４５８３号明細書
本発明の一つの実施形態は、バンプの接合不良を抑制できる半導体装置の製造方法を提供することを目的とする。
本発明の一つの実施形態によれば、第１の半導体チップの第１面に第１のバンプ電極を形成し、第２の半導体チップの第２面に第２のバンプ電極と突起とを形成し、前記第１面と前記第２面とが対向する様に、前記第１の半導体チップと前記第２の半導体チップとを前記突起を用いて固定し、前記第１のバンプ電極と前記第２のバンプ電極に含まれる金属の少なくとも一部の金属の融点よりも高い温度環境下において前記第１の半導体チップと前記第２の半導体チップとを電気的に接続し、前記第１の半導体チップと前記第２の半導体チップとの電気的な接続の後に、前記第１のバンプ電極と前記第２のバンプ電極に含まれる金属の融点よりも低い温度環境下において前記突起を硬化させる。
図１は、第１の実施の形態にかかる半導体装置の断面図である。 図２は、図１に示すＡ−Ａ線に沿った矢視断面図である。 図３は、半導体装置の製造工程を示すフローチャートである。 図４は、半導体装置の製造工程を示す断面図である。 図５は、半導体装置の製造工程を示す断面図である。 図６は、図１に示す半導体装置の製造工程を示すフローチャートであって、比較例としての製造工程を示すフローチャートである。 図７は、第２の実施の形態にかかる半導体装置の断面図である。
以下に添付図面を参照して、実施形態にかかる半導体装置を詳細に説明する。なお、これらの実施形態により本発明が限定されるものではない。例えば、本実施形態に係る上下左右などの方向を示す説明は、図面上の上方向を上とした場合における相対的な方向を指す。すなわち、本実施形態において示す方向と、重力加速度方向を基準とした方向とは異なる場合がある。
（第１の実施形態）
まず、半導体装置の構成について説明する。図１は、第１の実施の形態にかかる半導体装置の断面図である。図２は、図１に示すＡ−Ａ線に沿った矢視断面図である。半導体装置１０は、第１の半導体チップ２と第２の半導体チップ３とを有する。第１の半導体チップ２の上面（第１面）２ａは第１の接続領域を有し、第１の接続領域内に第１のバンプ電極５ａが形成されている。第２の半導体チップ３の下面（第２面）３ａは、第１の接続領域と対向する第２の接続領域を有し、第２の接続領域内に第２のバンプ電極５ｂが形成されている。第１面２ａを有する第１の半導体チップ２と、第２面３ａを有する第２の半導体チップ３とが、第１面２ａと第２面３ａとを対向させるように積層されている。また、第２の半導体チップ３は、第２のバンプ電極５ｂを第１のバンプ電極５ａと接続しつつ、第１の半導体チップ２上に積層されている。すなわち、第１の半導体チップ２と第２の半導体チップ３とは、第１のバンプ電極５ａと第２のバンプ電極５ｂとの接続体（バンプ接続部）５を介して、電気的および機械的に接続されている。接続領域とは、半導体チップ２，３の表面２ａ，３ａにおける第１のバンプ電極５ａ、第２のバンプ電極５ｂの形成領域を意味するものである。第１のバンプ電極５ａ、第２のバンプ電極５ｂとは、第１の半導体チップ２と第２の半導体チップ３とを電気的および機械的に接続するバンプ接続部を形成する電極を意味するものである。
第１のバンプ電極５ａと第２のバンプ電極５ｂに用いられる材料には、半田、金（Ａｕ）等が例示される。第１のバンプ電極５ａと第２のバンプ電極５ｂの組合せとしては、半田／半田、金（Ａｕ）／半田、半田／金（Ａｕ）、金（Ａｕ）／金（Ａｕ）等の組合せが例示される。第１のバンプ電極５ａと第２のバンプ電極５ｂを形成する半田としては、錫（Ｓｎ）に銅（Ｃｕ）、銀（Ａｇ）、ビスマス（Ｂｉ）、インジウム（Ｉｎ）等を添加した錫（Ｓｎ）合金を用いた鉛（Ｐｂ）フリー半田が例示される。鉛（Ｐｂ）フリー半田の具体例としては、錫（Ｓｎ）−銅（Ｃｕ）合金、錫（Ｓｎ）−銀（Ａｇ）合金、錫（Ｓｎ）−銀（Ａｇ）−銅（Ｃｕ）合金等が挙げられる。第１のバンプ電極５ａと第２のバンプ電極５ｂを形成する金属は金（Ａｕ）に代えて、銅（Ｃｕ）、ニッケル（Ｎｉ）、錫（Ｓｎ）、パラジウム（Ｐｄ）、銀（Ａｇ）等を用いてもよい。これらの金属は単層膜に限らず、複数の金属の積層膜を用いてもよい。第１のバンプ電極５ａ，第２のバンプ電極５ｂの形状としては、半球状や柱状等の突起形状が挙げられるが、パッドのような平坦形状であってもよい。第１のバンプ電極５ａと第２のバンプ電極５ｂの組合せとしては、突起体同士の組合せ、突起体と平坦体との組合せ等が挙げられる。ここで、本実施の形態は、第１のバンプ電極５ａに第１の半導体チップ２側からニッケル（Ｎｉ）と金（Ａｕ）の積層膜、第２のバンプ電極５ｂに第２の半導体チップ３側からニッケル（Ｎｉ）と鉛（Ｐｂ）フリー半田の積層膜を用いた例をとって説明する。第１の半導体チップ２と第２の半導体チップ３とは、バンプ接続部５を介して電気的に接続される。バンプ接続部５を介して、第１の半導体チップ２と第２の半導体チップ３との間で電気信号の送受信が行われる。
第１の半導体チップ２の上面２ａにおける第１の接続領域を除く領域（第１の非接続領域）、および第２の半導体チップ３の下面３ａにおける第２の接続領域を除く領域（第２の非接続領域）の少なくとも一方の領域には、突起６が設けられている。突起６は、例えばエポキシ樹脂、ポリイミド樹脂、アクリル樹脂、フェノール樹脂等を用いた熱硬化性樹脂で形成される。突起６は、第１の半導体チップ２と第２の半導体チップ３との間の隙間（ギャップ）が、設定したバンプ電極５ａ，５ｂの接続高さ（バンプ接続部５の設定高さ）となるように設けられている。第１の半導体チップ２と第２の半導体チップ３とを圧着した際、それらの隙間（ギャップ）は突起６で規定されるため、バンプ接続部５の過度の潰れやバンプ電極５ａ，５ｂ間の接続不良（オープン不良）等の発生を抑制することができる。
突起６の先端は、第１の非接続領域および第２の非接続領域の他方の領域と接着されている。突起６は、第１のバンプ電極５ａと第２のバンプ電極５ｂとを接続した際に、第１の半導体チップ２と第２の半導体チップ３との接続状態を強化する。バンプ接続部５を介して接続された第１の半導体チップ２の第１面２ａと第２の半導体チップ３の第２面３ａとの隙間には、アンダーフィル樹脂７が充填されている。第１の半導体チップ２の第１の非接続領域と第２の半導体チップ３の第２の非接続領域との間に突起６を設けることによって、アンダーフィル樹脂７を充填する前の第１の半導体チップ２と第２の半導体チップ３との接続強度を高めることができる。すなわち、第１の半導体チップ２と第２の半導体チップ３とは、アンダーフィル樹脂７を充填する以前に、第１のバンプ電極５ａと第２のバンプ電極５ｂとのバンプ接続部５に加えて、突起６により接続されている。したがって、アンダーフィル樹脂７を充填する前の接続強度を高めることができる。
第１の半導体チップ２に設けられた第１のバンプ電極５ａと第２の半導体チップ３に設けられた第２のバンプ電極５ｂとは、例えば加熱しながら圧着することにより接続される。半導体チップ２，３の表面には、通常保護膜としてポリイミド樹脂膜のような図示しない有機絶縁膜（絶縁膜）が設けられている。半導体チップ２，３を構成するシリコン基板の熱膨張係数は３ｐｐｍ程度であるのに対し、ポリイミド樹脂の熱膨張係数は３５ｐｐｍ程度と大きい。このため、半導体チップ２，３に反りが生じやすく、特に半導体チップ２，３の厚さが薄くなるほど反り量が大きくなる傾向がある。ここで、突起６によって半導体チップ２，３との接続状態が強化され、バンプ電極５ａ，５ｂを接続する際に、あるいは接続した後に、半導体チップ２，３の反りでバンプ電極５ａ，５ｂのバンプ接続部５が破断することを抑制することができる。
突起６は半導体チップ２，３間に局所的に設けられている。このため、第１の半導体チップ２と第２の半導体チップ３との位置合わせ精度や第１のバンプ電極５ａと第２のバンプ電極５ｂとの接続性を高めることができる。例えばＮＣＦ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）のような接着機能と封止機能とを併せ持つ絶縁樹脂層を半導体チップ間の隙間全体に配置する方法では、第１の半導体チップ２と第２の半導体チップ３とを位置合わせする際に、アライメントマークの検出精度が低下する。バンプ電極５ａ，５ｂのピッチが狭くなるほど、位置合わせ精度をより一層高めることが求められる。突起６がアライメントマークを覆わない様、局所的に設けてアライメントマークの検出精度を高めることにより、半導体チップ２，３間の位置合わせ精度を向上させることが可能となる。
半導体チップ２，３間の隙間全体に配置された絶縁樹脂層は、第１のバンプ電極５ａと第２のバンプ電極５ｂとの間に噛み込まれて接続性が低下するおそれがあるのに対し、局所的に設けられた突起６はバンプ電極５ａ，５ｂ間に噛み込まれないため、バンプ電極５ａ，５ｂ間の接続性を低下させるおそれが少ない。したがって、第１のバンプ電極５ａと第２のバンプ電極５ｂとの接続性を向上させることができる。さらに、半導体チップ２，３間の隙間全体に配置される絶縁樹脂層がある場合には、半導体チップ２，３間の接続時や接着時に巻き込みボイドを発生しやすい。接続領域に発生したボイドは、バンプ接続部５が樹脂で覆われていない状態を生じさせることがあるため、電極間でショートが発生するおそれがある。本実施の形態では、突起６を用いて半導体チップ２，３間の接続強度を高めつつ、バンプ電極５ａ，５ｂ間を接続し、その上でアンダーフィル樹脂７を充填している。このため、バンプ接続部５を確実に覆った状態で封止することができ信頼性を高めることが可能となる。
次に、半導体装置１０の製造工程について説明する。図３は、半導体装置１０の製造工程を示すフローチャートである。図４は、半導体装置１０の製造工程を示す断面図である。図５は、半導体装置１０の製造工程を示す断面図である。
まず、第１の半導体チップ２の第１面２ａに第１のバンプ電極５ａ、第２の半導体チップ３の第２面３ａに第２のバンプ電極５ｂを形成する（ステップＳ１）。第１のバンプ電極５ａは、第１面２ａの表面に形成された表面電極８上に形成される。第２のバンプ電極５ｂは、第２面３ａの表面に形成された表面電極８上に形成される。表面電極８は、半導体チップに形成された貫通電極や内部配線に電気的に接続されている。表面電極８は、第１の半導体チップ２と第２の半導体チップ３とを積層させた際に互いに対向する位置に形成されている。表面電極８は、例えば銅（Ｃｕ）、アルミニウム（Ａｌ）、ニッケル（Ｎｉ）、金（Ａｕ）等を用いる。これらの金属は単層膜に限らず、複数の金属の積層膜を用いてもよい。第１のバンプ電極５ａ、第２のバンプ電極５ｂは、いずれか一方を省略してもよい。
次に、第２の半導体チップ３の第２面３ａに、突起６を形成する（ステップＳ２）。突起６は、第２の半導体チップ３の第２面３ａにおける第２の非接続領域に形成される。本実施の形態では、突起６を柱状体として第２面３ａの非接続領域全域に点在させている。なお、突起６は、第１の半導体チップ２の第１面２ａに形成してもよいし、第１面２ａと第２面３ａの両方に形成してもよい。突起６は、第１のバンプ電極５ａまたは第２のバンプ電極５ｂと離間する位置に設けることが好ましい。突起６は、例えばエポキシ樹脂、ポリイミド樹脂、アクリル樹脂、フェノール樹脂等を用いた熱硬化性樹脂で形成することが好ましい。突起６は、リソグラフィ技術やディスペンサまたはインクジェットによる塗布技術を適用して形成したり、フィルムの接着により形成したりすることができる。液状の熱硬化性樹脂組成物を塗布して突起６を形成する場合、半硬化状態としておくことが好ましい。あるいは、速硬化型の材料を用いて、半導体チップ２，３の接着、接続時の時間を短縮することが好ましい。
次に、第１の半導体チップ２と第２の半導体チップ３とを積層する積層工程を行う（ステップＳ３）。ここでは、第１面２ａと第２面３ａとを対向させつつ、第１の半導体チップ２と第２の半導体チップ３とを重ねた状態で仮固定される。図４，５に示すように、ボンディングヘッド１２に吸着保持された第２の半導体チップ３を、ステージ１１上に載置された第１の半導体チップ２に配置する。第１の半導体チップ２と第２の半導体チップ３との位置合わせは、例えば、図示を省略したカメラ等で第１および第２の半導体チップ２，３のアライメントマークを検出して行われる。なお、第１面２ａや第２面３ａの全体を覆わずに点在するように突起６を形成すればよいので、アライメントマークを避けた位置に突起６を形成することができる。アライメントマークを避けた位置に突起６が形成されれば、アライメントマークの検出が容易かつ確実に行われやすくなる。
また、第１のバンプ電極５ａまたは第２のバンプ電極５ｂに用いられた金属の融点以下であって、突起６に接着性を発現させることのできる温度環境下および時間で、ステップＳ３の工程を行うことで、第１の半導体チップ２と第２の半導体チップ３とが、突起６によって仮固定される。例えば、１５０℃の環境下で１秒間圧着することで、突起６によって第１の半導体チップ２と第２の半導体チップ３とを仮固定する。なお、以下の説明において、仮固定された第１の半導体チップ２と第２の半導体チップ３とを、まとめてチップ積層体ともいう。
次に、リフロー工程を行って、第１面２ａと第２面３ａとに形成された第１のバンプ電極５ａまたは第２のバンプ電極５ｂに含まれる金属の少なくとも一部を溶融させて、互いに接合させる（ステップＳ４）。例えば、リフロー炉内にチップ積層体を配置する。例えば、リフロー炉内では、第２のバンプ電極５ｂに用いられた鉛（Ｐｂ）フリー半田の融点以上である２５０℃がピーク温度とされる。そして、リフロー炉内でチップ積層体がピーク温度下に６０秒間配置される。ここで、第１のバンプ電極５ａおよび第２のバンプ電極５ｂの表面酸化膜を除去しつつ、第１のバンプ電極５ａと第２のバンプ電極５ｂとを接合させるために、例えばリフロー炉内を還元雰囲気とする。第１のバンプ電極５ａと第２のバンプ電極５ｂとがリフロー工程で接合されることで、バンプ接続部５を介して第１の半導体チップ２と第２の半導体チップ３とが電気的に接続される。
次に、熱硬化性樹脂を用いた突起６を硬化させるキュア工程を行う（ステップＳ５）。例えば、第１のバンプ電極５ａまたは第２のバンプ電極５ｂに含まれる金属の融点以下（本実施の形態の例では、第１のバンプ電極５ａまたは第２のバンプ電極５ｂに含まれる金属のうち、最も融点の低い鉛（Ｐｂ）フリー半田の融点以下）であり、熱硬化性樹脂の硬化が進行する１８０℃の環境下にチップ積層体を２時間配置する。突起６が硬化することで、第１の半導体チップ２と第２の半導体チップ３とが、仮固定の状態よりもより強固に固定される。
次に、第１の半導体チップ２の第１面２ａと第２の半導体チップ３の第２面３ａとの間にアンダーフィル樹脂７を充填する（ステップＳ６）。その後、充填されたアンダーフィル樹脂７を硬化させる（ステップＳ７）。以上の工程により、半導体装置１０が製造される。ここでは図示を省略したが、半導体装置１は外部接続端子を有する配線基板やリードフレーム等の回路基材上に搭載されてＳｉＰ構造の半導体装置等として使用される。半導体装置１と回路基材との接続は、フリップチップボンディングやワイヤボンディング等により実施される。
本実施の形態に係る半導体装置１０は、リフロー工程（Ｓ４）前の段階において、第１の半導体チップ２と第２の半導体チップ３とが突起６により仮固定されているため、リフロー後の半導体チップ２，３の反りを抑制することができる。したがって、半導体チップ２，３の反りによって、アンダーフィル樹脂７の充填前に第１のバンプ電極５ａと第２のバンプ電極５ｂとのバンプ接続部５が破断することを抑制することができる。
また、突起６は、半導体チップ２，３の第１面２ａや第２面３ａに点在するように設けられているので、第１面２ａや第２面３ａの全体に突起６を設けられた場合よりも、巻き込みボイドが発生しにくくなる。これにより、半導体装置１０の信頼性の向上を図ることができる。また、アンダーフィル樹脂７の充填工程（Ｓ６）とアンダーフィル樹脂７の硬化工程（Ｓ７）が、キュア工程（Ｓ５）よりも後なので、アンダーフィル樹脂７が突起６に浸透し、突起６が膨張してしまう可能性を低減できる。突起６の膨張は、バンプ接続部５の破断の原因となる。本実施の形態にかかる半導体装置１０によれば、突起６の膨張を抑制することで、バンプ接続部５の破断を抑制することができる。
なお、突起６を、感光性および熱硬化性を有する樹脂を用いて形成してもよい。感光性および熱硬化性樹脂の具体例としては、感光性接着剤樹脂のような感光剤を含有する熱硬化性樹脂が挙げられる。感光性および熱硬化性樹脂によれば、突起６の形成段階において、フォトリソグラフィ技術を用いて、突起６を柱状体として第２面３ａの非接続領域全域に点在させることができる。さらに、後の工程（Ｓ５）となる加熱時には熱硬化するため、第１の半導体チップ２と第２の半導体チップ３とをより強固に固定できる。
図６は、図１に示す半導体装置の製造工程を示すフローチャートであって、比較例としての製造工程を示すフローチャートである。比較例としての製造工程では、ステップＳ１４でキュア工程を行ってから、ステップＳ１５でリフロー工程を行っており、キュア工程とフロー工程の順番が、本実施の形態にかかる製造工程と逆になっている。それ以外の工程は、本実施の形態にかかる製造工程と同様である。比較例としての製造工程では、キュア工程において突起６を硬化させることで、半導体チップ２，３同士の固定を図ってから、リフロー工程において第１のパンプ電極５ａまたは第２のバンプ電極５ｂに含まれる金属の少なくとも一部を溶融させて、第１のバンプ電極５ａと第２のバンプ電極５ｂとの接合を図っている。
ここで、半導体チップ２，３の表面には、保護膜としてポリイミド樹脂膜のような有機絶縁膜（絶縁膜）が設けられることがある。半導体チップ２，３を構成するシリコン基板の熱膨張係数と、ポリイミド樹脂の熱膨張係数との違いによって、半導体チップ２，３には反りが生じやすくなっている。特に半導体チップ２，３の厚さが薄くなるほど反り量が大きくなる傾向がある。半導体チップ２，３の積層工程（Ｓ３）では、ステージ１１とボンディングヘッド１２とに挟み込まれることで、半導体チップ２，３の反りが矯正されるが、ステージ１１とボンディングヘッド１２との間からチップ積層体を取り出すと、半導体チップ２，３に再び反りが発生しやすくなる。比較例としての製造工程では、キュア工程（Ｓ１４）によって半導体チップ２，３同士の固定を図ることで、半導体チップ２，３に再び反りが発生するのを抑えている。
しかしながら、比較例としての製造工程では、第１のバンプ電極５ａと表面電極８との間に介在するニッケルや表面電極８を構成する銅が、第１のバンプ電極５ａに用いられる鉛（Ｐｂ）フリー半田内に拡散してしまう場合がある。ニッケルや銅等の異種金属が鉛（Ｐｂ）フリー半田内に拡散すると、鉛（Ｐｂ）フリー半田の融点が上昇してしまう。鉛（Ｐｂ）フリー半田の融点が上昇した場合、リフロー工程（Ｓ１５）の温度を高くしなければバンプ接続部５の接続不良が発生する可能性がある。一方で、リフロー工程（Ｓ１５）の温度を高くすると、その分残留応力が大きくなる可能性がある。
これに対し、本実施の形態にかかる製造工程では、図３に示すように、ステップＳ４でリフロー工程を行い、ステップＳ５でキュア工程を行っている。すなわち、キュア工程より前にリフロー工程を行っている。これにより、ニッケル（Ｎｉ）や銅（Ｃｕ）等の異種金属の拡散を抑制することができ、バンプ接続部５の接続不良の可能性の低減と残留応力の低減の両立を図ることができる。
また、本実施の形態にかかる製造工程では、積層工程において第１の半導体チップ２と第２の半導体チップ３とが突起６によって仮固定されているため、半導体チップ２，３に再び反りが発生しにくくなっている。そのため、キュア工程より前にリフロー工程を行っても、半導体チップ２，３の反りによって、バンプ接続部５が破断してしまうことを抑えることができる。
図７は、第２の実施の形態に係る半導体装置３０の断面図である。半導体装置３０は、第１の半導体チップ２１と、第２の半導体チップ２２と、第３の半導体チップ２３と、第４の半導体チップ３７とを備える。第１の半導体チップ２１と、第２の半導体チップ２２と、第３の半導体チップ２３には、例えばＮＡＮＤフラッシュメモリを用いる事ができる。また、第４の半導体チップ３７には、例えばＮＡＮＤコントローラを用いる事が出来る。第１の半導体チップ２１と第２の半導体チップ２２と第３の半導体チップ２３とは、第１の実施の形態と同様の方法を用いて積層されたチップ積層体２０の構成の一部となっている。半導体装置３０は外部接続端子３１と内部接続端子３２とを有する配線基板３３上に搭載されている。第３の半導体チップ２３は、第３のバンプ電極３８を介して、第４の半導体チップ３７と電気的に接続されている。配線基板３３の内部接続端子３２は、第４の半導体チップ３７に設けられた表面電極８と第４のバンプ電極３９とを介して、第４の半導体チップ３７と電気的に接続されている。配線基板３３上には、チップ積層体２０と第４の半導体チップ３７等とを共に封止する樹脂封止層３６が形成されている。
２、２１ 第１の半導体チップ、２ａ 第１面、３、２２ 第２の半導体チップ、３ａ 第２面、５ 接続体（バンプ接続部）、６ 突起、７ アンダーフィル樹脂、８ 表面電極、１０ 半導体装置、１１ ステージ、１２ ボンディングヘッド、２０ チップ積層体、２３ 第３の半導体チップ、３１ 外部接続端子、３２ 内部接続端子、３３ 配線基板、３７ 第４の半導体チップ

Claims (5)

  1. 第１の半導体チップの第１面に第１のバンプ電極を形成し、
    第２の半導体チップの第２面に第２のバンプ電極と熱硬化性樹脂を含む突起とを形成し、
    前記突起を熱圧着することにより、前記第１面と前記第２面とが対向する様に、前記第１の半導体チップと前記第２の半導体チップとを前記突起を用いて固定し、
    前記第１のバンプ電極と前記第２のバンプ電極に含まれる金属の少なくとも一部の金属の融点よりも高い温度環境下において前記第１の半導体チップと前記第２の半導体チップとを電気的に接続し、
    前記第１の半導体チップと前記第２の半導体チップとの電気的な接続の後に、前記第１のバンプ電極と前記第２のバンプ電極に含まれる金属の融点よりも低い温度環境下において前記突起に含まれる熱硬化性樹脂を硬化させる半導体装置の製造方法。
  2. 前記突起を硬化させた後に、前記第１面と前記第２面との間にアンダーフィル樹脂を充填し、その後前記アンダーフィル樹脂を硬化させる工程と、を備える請求項１に記載の半導体装置の製造方法。
  3. 前記突起は、前記第２面に対して、複数の柱状体として点在するように形成される請求項１または２記載の半導体装置の製造方法。
  4. 前記突起を熱圧着する工程は、前記第１のバンプ電極と前記第２のバンプ電極に含まれる金属の融点よりも低い温度環境下において行われる請求項１〜３のいずれか１つに記載の半導体装置の製造方法。
  5. 前記第１の半導体チップと前記第２の半導体チップとを圧着し、前記第１の半導体チップと前記第２の半導体チップとを固定する請求項１〜４のいずれか１つに記載の半導体装置の製造方法。
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