JP6154419B2 - Phase adjusting device and phase adjusting method - Google Patents

Description

  The present invention relates to a phase adjustment device and a phase adjustment method for adjusting the relative phases of a data signal and a clock signal, for example, in an ultrahigh frequency band of several GHz.

  Conventionally, a digital signal analyzer such as a code error measuring device or a logic analyzer removes a fluctuation component of an amplitude by shaping a waveform of a data signal input from the outside with a comparator, and the digital signal thus shaped is clocked with a discriminator. Are identified (that is, binary level code determination) and the phase fluctuation component is removed, and then analysis of the data signal, such as code error measurement and logic analysis, is performed.

  As described above, when the data signal is identified based on the clock signal, the data signal and the clock signal input to the identifier are identified so that the binary level of the data signal is identified at the most stable timing. It is necessary to adjust the relative phase (timing).

  As a circuit for performing this type of adjustment, a phase adjustment circuit described in Patent Document 1 is known. The conventional one described in Patent Document 1 adjusts the relative positions of the data signal and the clock signal by delaying the clock signal based on the output voltage of the data signal.

  Specifically, as shown in FIG. 6 (a), the conventional one obtains the position of the cross point a of the eye pattern based on the peak position of the output voltage of the data signal, and from this cross point a to the cross point c. The rising timing of the clock signal is adjusted so as to be positioned at the intermediate position b (the point where the phase margin is the largest) in one cycle T.

JP-A-8-88625

  However, in the prior art, for example, when a jitter component is added to the data signal in order to measure the bit error rate of the device under test, the peak position of the output voltage of the data signal as shown in FIG. Cannot be detected, the position corresponding to the intermediate position b shown in FIG. 6A cannot be obtained, and the optimum clock phase cannot be set.

  The present invention has been made to solve the conventional problems, and provides a phase adjustment apparatus and a phase adjustment method capable of setting an optimum clock phase even when a jitter component is added to a data signal. For the purpose.

A phase adjustment device according to claim 1 of the present invention is a phase adjustment device that adjusts the phase of a data signal and a clock signal, a delay unit that delays an input clock signal based on a set delay amount, and an input a code decision means for sign determination and outputs at the timing of the clock signal output of the data signal from said delay means, an output voltage detecting means for detecting the average DC voltage of the output signal output from the sign determination unit, wherein Storage means for sequentially storing the average DC voltage of the output signal in association with a time axis within a predetermined time range indicating a time range of one cycle time or more and less than two cycle times of the data signal ; and each of the storage means stored in the storage means Cross point position estimating means for estimating a temporal position of a cross point of the eye pattern of the data signal based on a voltage value, and the estimated temporal position of the cross point A delay amount setting means for setting a delay amount of the input clock signal to the delay means as a reference, normalized to a constant voltage value the voltage value of the above predetermined voltage of said stored voltage values in the storage means Voltage value normalizing means, and the cross-point position estimating means includes, among the voltage values normalized to the constant voltage value, an area continuously stored in the storage means for a predetermined number of times. On the condition that the voltage value continuous region shown is within the predetermined time range, the temporal position of the cross point is estimated based on the voltage value continuous region .

  With this configuration, in the phase adjusting apparatus according to claim 1 of the present invention, the cross point position estimating unit estimates the temporal position of the cross point of the eye pattern of the data signal based on each voltage value stored in the storage unit. However, since the delay amount setting means sets the delay amount of the input clock signal in the delay means with reference to the estimated time position of the cross point, even when a jitter component is added to the data signal, the optimum clock phase is set. Can be set.

Further, this configuration, the phase adjustment device according to claim 1 of the present invention, since the voltage value normalization means for normalizing the voltage values equal to or greater than a predetermined voltage at a constant voltage value, the temporal cross point of the eye pattern The position can be easily estimated.

In the phase adjusting device according to claim 2 of the present invention, the cross point position estimating means is preferably configured such that the voltage value distribution including one voltage value continuous region is one within the predetermined time range. It has the structure which estimates that the time position of a crossing point exists in the said voltage value continuous area | region.

With this configuration, the phase adjustment device according to claim 2 of the present invention is such that when there is one voltage value distribution including one voltage value continuous region within a predetermined time range, the temporal position of the cross point of the eye pattern Can be easily estimated.

In the phase adjustment device according to claim 3 of the present invention, the cross point position estimation means is preferably configured so that each of the voltage value distributions including a plurality of the voltage value continuous regions has one distribution within the predetermined time range. It has a configuration for estimating the temporal position of the cross point based on the voltage value continuous region.

With this configuration, the phase adjustment device according to claim 3 of the present invention is such that when there is one voltage value distribution including a plurality of voltage value continuous regions within the predetermined time range, the temporal position of the cross point of the eye pattern Can be easily estimated.

In the phase adjustment device according to claim 4 of the present invention, the cross point position estimating means includes a first voltage value and a second voltage value within which the distribution of the independent voltage values having the voltage value continuous region is within the predetermined time range. On the condition that there are two distributions, the temporal positions of the first and second cross points are estimated in the distributions of the first and second voltage values, respectively, and the temporal positions of the first cross points are estimated. It has the structure which estimates the time position of the said cross point between a position and the time position of the said 2nd cross point.

With this configuration, the phase adjustment device according to claim 4 of the present invention has two independent voltage value distributions having voltage value continuous regions as the first and second voltage value distributions within a predetermined time range. Even in this case, the temporal position of the cross point of the eye pattern can be easily estimated.

In the phase adjusting device according to claim 5 of the present invention, the voltage value continuous region included in at least one of the distributions of the first and second voltage values is a voltage value normalized to the constant voltage value. The storage means is a region that is continuously stored in the storage means one or more times.

With this configuration, the phase adjustment device according to claim 5 of the present invention has two independent voltage value distributions having voltage value continuous regions as the first and second voltage value distributions within a predetermined time range. Even in this case, the temporal position of the cross point of the eye pattern can be easily estimated.
In the phase adjusting apparatus according to claim 6 of the present invention, the cross point position estimating means includes a first voltage value and a second voltage value within which the distribution of the independent voltage values having the voltage value continuous region is within the predetermined time range. If the number of continuous voltage values between the distribution of the first voltage value and the distribution of the second voltage value is a predetermined number, the distribution of the first voltage value And the distribution of the second voltage value are continuous, and the temporal position of the cross point is estimated on the assumption that there is one voltage value continuous region.

According to a seventh aspect of the present invention, there is provided a phase adjustment method for adjusting a phase between a data signal and a clock signal using the phase adjustment device (10) according to the first aspect, wherein a set delay is set. A delay step (S12) for delaying the input clock signal based on the amount; a code determination step (S13) for determining and outputting the input data signal at the timing of the clock signal delayed in the delay step; An output voltage detection step (S14) for detecting an average DC voltage of the output signal output in the determination step; and a predetermined time range indicating a time range of one cycle time to less than two cycle times of the data signal. group a storage step of sequentially storing in association with the average DC voltage time axis (S15), the voltage values stored in said storing step And a cross point position estimating step (S20) for estimating a temporal position of the cross point of the eye pattern of the data signal, and setting a delay amount of the input clock signal based on the estimated temporal position of the cross point. A delay amount setting step (S17), and a voltage value normalizing step (S16) for normalizing a voltage value equal to or higher than a predetermined voltage among the voltage values stored in the storing step to a constant voltage value, In the cross point position estimating step, among the voltage values normalized to the constant voltage value, a voltage value continuous region indicating a region continuously stored in time for a predetermined number or more in the storing step is the predetermined time range. The temporal position of the crossing point is estimated based on the voltage value continuous region on the condition that it is within the range .

  With this configuration, in the phase adjustment method according to claim 7 of the present invention, in the cross point position estimation step, the time position of the cross point of the eye pattern of the data signal is estimated based on each voltage value, and the delay amount setting step Since the delay amount of the input clock signal is set based on the estimated time position of the cross point, the optimum clock phase can be set even when a jitter component is added to the data signal.

  The present invention can provide a phase adjustment device and a phase adjustment method having an effect that an optimum clock phase can be set even when a jitter component is added to a data signal.

It is a block block diagram in one Embodiment of the phase adjustment apparatus which concerns on this invention. It is explanatory drawing of the function of the control apparatus in one Embodiment of the phase adjustment apparatus which concerns on this invention. It is a figure which shows the specific example of the estimation process by the cross point position estimation part in one Embodiment of the phase adjustment apparatus which concerns on this invention. It is a flowchart in one Embodiment of the phase adjustment apparatus which concerns on this invention. It is a flowchart of the cross point estimation process in one Embodiment of the phase adjustment apparatus which concerns on this invention. It is explanatory drawing of the conventional phase adjustment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, the configuration of an embodiment of the phase adjustment device according to the present invention will be described. In the field of data communication and the like, the phase adjustment device according to the present embodiment is a digital signal analysis device such as a code error measurement device or a logic analyzer that analyzes a clock signal and a data signal input in synchronization therewith, or a data signal and a clock. It is used for a pattern generator or the like that must output a signal in synchronization.

  As shown in FIG. 1, the phase adjustment device 10 in this embodiment includes a variable delay device 11, a discriminator 12, a DC average value detector 13, and a control device 20.

  The variable delay device 11 delays the input clock signal in accordance with a control signal from the control device 20, and relatively changes the phase of the input clock signal with respect to the input data signal. As the variable delay device 11 for ultrahigh frequency, a variable length slabline structure is used in which the delay amount (delay time) is variable by varying the slag of the signal line length. The signal line length is slid by a driving device such as a servo motor. The variable delay device 11 is an example of a delay unit.

  The discriminator 12 is composed of, for example, a D-type flip-flop, and has a D terminal for inputting an input data signal, a CP terminal for inputting a clock signal delayed from the variable delay device 11, and a Q terminal for outputting an output signal. Have. The discriminator 12 determines the sign of the level of the data signal input to the D terminal at the rising (or falling) timing of the clock signal output from the variable delay unit 11 and input to the CP terminal. The output is output from the Q terminal to the DC average value detector 13. The discriminator 12 is an example of a code determination unit.

  The DC average value detector 13 includes an integrating circuit constituted by, for example, a resistor R1 and a capacitor C1, and detects an average DC voltage (DC average value) of the output signal of the discriminator 12 so as to output it to the control device 20. It has become. This DC average value detector 13 is an example of output voltage detection means.

  The control device 20 includes an AD converter (ADC) 21, a first memory 22, a normalization unit 23, a second memory 24, a cross point position estimation unit 25, a delay amount setting unit 26, and a DA converter (DAC) 27. . The control device 20 includes a CPU, a ROM, a RAM, and the like, for example, and operates according to a program stored in advance in the ROM.

  The ADC 21 converts the output signal of the DC average value detector 13 from an analog value to a digital value signal and outputs the signal to the first memory 22.

  The first memory 22 sequentially stores the voltage value of the output voltage of the ADC 21 in association with the time axis. The first memory 22 is an example of a storage unit.

  The normalizing unit 23 is configured to normalize a voltage value equal to or higher than a predetermined voltage among the voltage values stored in the first memory 22 to a constant voltage value. The normalizing unit 23 is an example of a voltage value normalizing unit.

  The second memory 24 stores data of each voltage value normalized by the normalizing unit 23 in association with the time axis.

  The cross point position estimation unit 25 estimates the temporal position of the cross point of the eye pattern of the data signal based on each voltage value stored in the second memory 24. The cross point position estimating unit 25 is an example of a cross point position estimating unit.

  The delay amount setting unit 26 is configured to set the delay amount of the variable delay device 11. The delay amount setting unit 26 is an example of a delay amount setting unit. Specifically, the delay amount setting unit 26 performs first and second processing shown below.

  In the first processing, the delay amount of the variable delay device 11 is set at a predetermined time interval over a time range of one cycle of the input clock signal, for example, at a time (T / 20) interval obtained by dividing one cycle of time (T) by 20 This is a process of outputting a signal for sequentially setting and generating and outputting an address value of the first memory 22 so as to correspond to the sequentially set delay amount. The first memory 22 receives the address value and sequentially stores the voltage value of the output voltage of the ADC 21 as described above.

  The second process receives information on the address value corresponding to the cross point of the eye pattern estimated by the cross point position estimating unit 25, and the variable delay device 11 corresponding to the cross point of the eye pattern is received from this address value information. A delay amount is specified, and a delay amount obtained by adding or subtracting the time (T / 2) for approximately half a cycle of the input clock signal to the delay amount is obtained, and a signal for setting the variable delay device 11 to the delay amount is obtained. It is a process to output. The delay amount setting unit 26 grasps and stores the relationship between the address value of the first memory 22 and the delay amount of the variable delay device 11 so that the above-described delay amount can be specified.

  The DAC 27 receives a signal for setting the delay amount of the variable delay device 11 output from the delay amount setting unit 26, and converts the signal from an analog value to a digital value. The converted signal is supplied as a control signal to a servo motor or the like that is a driving device of the variable delay device 11.

  Next, the function of the control device 20 will be specifically described with reference to FIGS.

  FIG. 2A shows an eye pattern data signal. One cycle time of the signal is indicated by 1 UI (Unit Interval).

  FIG. 2B shows each voltage value stored in the first memory 22 as a black dot. Each voltage value is measured and stored sequentially in step BmUI within a predetermined measurement range ± AmUI (milli UI). This measurement range is a range based on a predetermined measurement reference point indicated by 0. That is, the first memory 22 sequentially stores the voltage value of the output voltage of the DC average value detector 13 in association with the time axis within a predetermined measurement range (within a predetermined time range). As the measurement reference point, for example, the position of the cross point of the eye pattern can be obtained in advance using a data signal to which no jitter component is added, and the cross point can be used as a reference.

  The normalizing unit 23 performs normalization of voltage values with the minimum output voltage value being 0 and the maximum voltage value being 100 for each voltage value within the ± AmUI range stored in the first memory 22. It is. Then, as illustrated in FIG. 2C, the normalization unit 23 performs a process of setting a voltage value of 80 or more to 80 and a voltage value of 20 or less to 20, for example. The voltage value after the normalization process is stored in the second memory 24.

  Based on the voltage value stored in the second memory 24, the cross point position estimation unit 25 estimates the center position of the width W of the region having the voltage value of 80 as the cross point. Note that the center position of the width W does not have to be the cross point, and a point shifted by a desired amount from the center position of the width W may be estimated as the cross point.

  As shown in FIG. 2 (c), the delay amount setting unit 26 uses a cross point estimated by the cross point position estimation unit 25 as a reference, a position of a half cycle, that is, a position separated by ± 500 mUI (example shown in the figure). The delay amount is set in the variable delay device 11 so that the rising timing of the clock signal is positioned on the positive side.

  Next, a specific example of estimation processing by the cross point position estimation unit 25 will be described with reference to FIG.

  FIG. 3 shows various patterns of voltage values normalized by the normalization unit 23, the horizontal axis indicates UI, that is, time, and the vertical axis indicates voltage. Among these, FIGS. 3A to 3C show examples in which there is one voltage value distribution within the measurement range. Depending on the measurement conditions, two voltage value distributions may appear in the measurement range, and examples of such cases are shown in FIGS.

  FIG. 3A shows one area (hereinafter referred to as a “voltage value continuous area”) in which the voltage value normalized to 80 by the normalizing unit 23 is continuously stored over a predetermined number of times. An example is given. That is, the voltage value distribution 31 shown in FIG. 3A has one voltage value continuous region 31a. In this case, the cross point position estimating unit 25 estimates that the temporal position of the cross point is in the voltage value continuous region 31a, and is a position P1 that is temporally centered in the voltage value continuous region 31a. Is estimated as the cross point of the eye pattern. When the voltage value continuous region 31a includes one peak voltage value, the cross point position estimation unit 25 estimates the peak voltage value position P1 as the eye pattern cross point.

  FIG. 3B shows a voltage value distribution 32 having two voltage value continuous regions 32a and 32b. In this case, the cross point position estimation unit 25 determines the center position between the position P1 that is temporally central in the voltage value continuous region 32a and the position P2 that is temporally central in the voltage value continuous region 32b as the eye pattern. Estimated as the crossing point. When the number of continuous voltage values 32c between the voltage value continuous regions 32a and 32b is equal to or less than a predetermined number, the voltage value continuous regions 32a and 32b are continuous, and there is one voltage value continuous region. Processing may be performed assuming that there is.

  FIG. 3C shows a voltage value distribution 33 having one peak voltage value 33a and one voltage value continuous region 33b. In this case, the cross point position estimation unit 25 estimates the center position between the position P1 of the peak voltage value 33a and the position P2 that is temporally central in the voltage value continuous region 33b as the cross point of the eye pattern.

  FIG. 3D shows a case where there are voltage value distributions 34 and 35 that are independent of each other within the measurement range. In this case, the cross point position estimation unit 25 estimates the center position between the position P1 of the peak voltage value 34a and the position P2 of the peak voltage value 35a as the cross point of the eye pattern.

  FIG. 3E shows a case where there are independent voltage value distributions 36 and 37 within the measurement range. In this case, the cross point position estimation unit 25 estimates the center position between the position P1 of the peak voltage value 36a and the position P2 that is temporally central in the voltage value continuous region 37a as the cross point of the eye pattern.

  FIG. 3F shows a case where there are voltage value distributions 38 and 39 that are independent of each other within the measurement range. In this case, the cross point position estimation unit 25 determines the center position between the position P1 that is temporally central in the voltage value continuous region 38a and the position P2 that is temporally central in the voltage value continuous region 39a. Estimated as the crossing point.

  Next, the operation of the phase adjustment apparatus 10 in the present embodiment will be described with reference to FIGS. FIG. 4 is a flowchart showing the operation of the phase adjustment device 10. FIG. 5 is a flowchart showing the cross point estimation process.

  The discriminator 12 inputs an input data signal from the D terminal (step S11). The variable delay device 11 sequentially changes the delay amount of the input clock signal in accordance with the control signal from the control device 20, and outputs it to the CP terminal of the discriminator 12 (step S12).

  The discriminator 12 determines the sign of the input data signal at the rising (or falling) timing of the clock signal, and outputs the discrimination output from the Q terminal to the DC average value detector 13 (step S13).

  The DC average value detector 13 detects the output voltage of the data signal from the discriminator 12 (step S14) and outputs it to the control device 20.

  In the control device 20, the ADC 21 converts the output signal of the DC average value detector 13 from an analog value to a digital value signal and outputs the signal to the first memory 22.

  The first memory 22 sequentially stores the voltage value of the output signal of the DC average value detector 13 converted from the analog value into the digital value signal by the ADC 21 in association with the time axis (step S15).

  The normalizing unit 23 reads the voltage value of the output signal of the DC average value detector 13 from the first memory 22, and normalizes the read data (step S16). For example, as illustrated in FIG. 2C, the normalization unit 23 performs a process of setting a voltage value of 80 or more as 80 and a voltage value of 20 or less as 20. The voltage value after the normalization process is stored in the second memory 24.

  The cross point position estimation unit 25 performs a cross point estimation process shown in FIG. 5 (step S20).

  As shown in FIG. 5, the cross point position estimation unit 25 determines whether or not the voltage value of 80 is zero (step S <b> 21). Here, the cross point position estimation unit 25 ends the process when it is determined that the voltage value of 80 is 0, and the voltage value of 80 is 1 when it is not determined that the voltage value of 80 is 0. It is determined whether or not the number is individual (step S22).

  In step S22, when the cross point position estimating unit 25 determines that the voltage value of 80 is one, the position of the voltage value of 80 is set as P1 (step S23), and the position of P1 is set as the cross point of the eye pattern. Estimate (step S24) and return to the main routine (FIG. 4).

  On the other hand, when the cross point position estimation unit 25 does not determine that the voltage value of 80 is one in step S22, the cross point position estimation unit 25 determines whether or not there is one 80 voltage value region (step S25).

  In step S25, when the cross point position estimation unit 25 determines that there is one region of 80 voltage values, the center position which is the temporal center of the width of the voltage value region is set to P1 (step S26). The process proceeds to step S24 described above.

  On the other hand, when the cross point position estimation unit 25 does not determine that there is one region of 80 voltage values in step S25, it determines whether there are two regions of 80 voltage values (step S27).

  In step S27, when the cross point position estimation unit 25 determines that there are two 80 voltage value regions, it determines whether or not the 80 voltage value regions are continuous (step S28). In step S27, if the cross point position estimation unit 25 does not determine that there are two regions of 80 voltage values, that is, if there are three or more regions of 80 voltage values, the process ends.

  In step S28, when the cross point position estimation unit 25 does not determine that the 80 voltage value regions are continuous, the position of each 80 voltage value is set to P1 and P2, respectively (step S29). The center of P1 and P2 is estimated as the cross point of the eye pattern (step S30), and the process returns to the main routine (FIG. 4).

  In step S28, when the cross point position estimating unit 25 determines that the 80 voltage value region is continuous, the position of the 80 voltage value or the center of the region is set to P1 and P2 (step S31). The process proceeds to step S30 described above.

  In addition, when a process is complete | finished after step S21 (Yes) or step S27 (No), for example, the reference | standard of the voltage value which the normalization part 23 normalizes can be changed and each process can be performed again.

  Returning to FIG. 4, the delay amount setting unit 26 rises the clock signal at a position separated by, for example, 500 mUI with reference to P1 obtained in step S24 of the cross point estimation process or the center of P1 and P2 obtained in step S30. A delay amount for adjusting the timing of (or falling) is set (step S17). This delay amount is converted from a digital value to an analog value by the DAC 27 and set in the variable delay device 11.

  As described above, in the phase adjustment apparatus 10 according to the present embodiment, the cross point position estimation unit 25 estimates the temporal position of the cross point of the eye pattern of the data signal, and the delay amount setting unit 26 estimates the cross. Since the delay amount of the input clock signal is set in the variable delay device 11 with the temporal position of the point as a reference, an optimum clock phase can be set even when a jitter component is added to the data signal.

  As described above, the phase adjustment device according to the present invention has an effect that an optimum clock phase can be set even when a jitter component is added to a data signal. For example, in a very high frequency band of several GHz. It is useful as a phase adjustment device and a phase adjustment method for adjusting the relative phases of a data signal and a clock signal.

10 phase adjusting device 11 variable delay device (delay means)
12 Discriminator (code determination means)
13 DC average value detector (output voltage detection means)
20 control device 22 first memory (storage means)
23 normalization unit (voltage value normalization means)
24 second memory 25 cross point position estimating unit (cross point position estimating means)
26 Delay amount setting unit (delay amount setting means)

Claims (7)

A phase adjustment device (10) for adjusting a phase between a data signal and a clock signal,
Delay means (11) for delaying the input clock signal based on the set delay amount;
A code determination means (12) for determining the sign of the input data signal at the timing of the clock signal output from the delay means and outputting it;
Output voltage detection means (13) for detecting an average DC voltage of the output signal output from the sign determination means;
Storage means (22) for sequentially storing an average DC voltage of the output signal in association with a time axis within a predetermined time range indicating a time range of one cycle time or more and less than two cycle times of the data signal ;
Cross point position estimating means (25) for estimating a temporal position of a cross point of an eye pattern of the data signal based on each voltage value stored in the storage means;
A delay amount setting means (26) for setting the delay amount of the input clock signal in the delay means on the basis of the estimated temporal position of the cross point;
Voltage value normalizing means (23) for normalizing a voltage value equal to or higher than a predetermined voltage among the voltage values stored in the storage means to a constant voltage value;
With
The cross-point position estimating unit includes a voltage value continuous region indicating a region that is continuously stored in the storage unit for a predetermined number of times among the voltage values normalized to the constant voltage value. The time position of the cross point is estimated based on the voltage value continuous region on the condition that
A phase adjustment device characterized by the above. The cross point position estimation means is configured such that the temporal position of the cross point is within the voltage value continuous region on condition that there is one voltage value distribution including one voltage value continuous region within the predetermined time range. Is presumed to be in
The phase adjusting apparatus according to claim 1, wherein: The cross point position estimation means is configured to obtain a temporal distribution of the cross points based on each voltage value continuous region on condition that there is one voltage value distribution including a plurality of voltage value continuous regions within the predetermined time range. To estimate the position,
The phase adjusting apparatus according to claim 1 , wherein: The cross-point position estimating means is provided on the condition that there are two distributions of voltage values independent of each other having the voltage value continuous region as distributions of the first and second voltage values within the predetermined time range. Estimating the temporal positions of the first and second cross points in the distribution of the first and second voltage values, respectively, and determining the temporal position of the first cross point and the temporal position of the second cross point; The time position of the cross point is estimated during
The phase adjusting apparatus according to claim 1 , wherein: The voltage value continuous region included in at least one of the first voltage value distribution and the second voltage value distribution may be one or more than a predetermined number of time values in the storage unit among the voltage values normalized to the constant voltage value. Is an area continuously stored in
The phase adjusting apparatus according to claim 4 , wherein The cross-point position estimating means includes two distributions of voltage values independent of each other having the voltage value continuous region as distributions of the first voltage value and the second voltage value within the predetermined time range. When the number of continuous voltage values between the distribution of the first voltage value and the distribution of the second voltage value is a predetermined number, the distribution of the first voltage value and the distribution of the second voltage value are continuous. And the temporal position of the cross point is estimated as one voltage value continuous region.
The phase adjusting apparatus according to claim 1 , wherein: A phase adjustment method for adjusting the phases of a data signal and a clock signal using the phase adjustment device (10) according to claim 1,
A delay step (S12) for delaying the input clock signal based on the set delay amount;
A sign determination step (S13) for determining the sign of the input data signal at the timing of the clock signal delayed in the delay step and outputting it;
An output voltage detection step (S14) for detecting an average DC voltage of the output signal output in the sign determination step;
A storage step (S15) for sequentially storing the average DC voltage of the output signal in association with a time axis within a predetermined time range indicating a time range of one cycle time or more and less than two cycle times of the data signal ;
A cross point position estimating step (S20) for estimating a temporal position of a cross point of the eye pattern of the data signal based on each voltage value stored in the storing step;
A delay amount setting step (S17) for setting a delay amount of the input clock signal on the basis of the estimated temporal position of the cross point;
A voltage value normalizing step (S16) for normalizing a voltage value equal to or higher than a predetermined voltage among the voltage values stored in the storing step to a constant voltage value;
Including
In the cross point position estimating step, among the voltage values normalized to the constant voltage value, a voltage value continuous region indicating a region continuously stored in time for a predetermined number or more in the storing step is the predetermined time range. The phase adjustment method is characterized in that the temporal position of the crossing point is estimated based on the voltage value continuous region on the condition that it is within the range .

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