JP6041241B2 - Adaptive bias generation circuit and differential amplifier circuit for differential amplifier circuit - Google Patents

Description

  The present invention relates to an adaptive bias generation circuit for a differential amplifier circuit, and a differential amplifier circuit including the adaptive bias generation circuit.

  In recent years, the realization of a ubiquitous network society that improves the convenience of life using environmental sensors, biosensors, and the like is expected. Since many of these sensor devices are assumed to be installed in the environment or a living body, long-term continuous operation is required without battery replacement. Therefore, in order to realize such a next generation information society, a smart sensor LSI (Large Scale Integration) that operates with low power is required.

  The smart sensor LSI shapes an analog signal acquired from the environment or a living body with an amplifier or a filter, and then converts the analog signal into a digital signal with an AD converter. These systems use a number of operational amplifiers. Therefore, operating the operational amplifier with low power is an effective means for reducing the power consumption of the smart sensor LSI.

  A differential pair circuit is a basic component of an operational amplifier. The differential pair circuit is composed of an n-channel MOSFET or a p-channel MOSFET (hereinafter, the MOSFET is referred to as a MOS transistor, the n-channel MOS transistor is referred to as an nMOS transistor, and the p-channel MOS transistor is referred to as a pMOS transistor). The input voltage range is limited accordingly. When the input voltage range of the differential pair circuit is narrow, the dynamic range becomes narrow. As a differential amplifier (hereinafter referred to as an operational amplifier) that can ensure a wide input voltage range, there is a rail-to-rail operational amplifier in which an input differential pair circuit is a complementary configuration of an nMOS transistor and a pMOS transistor. . The rail-to-rail operational amplifier can substantially secure an input voltage range in the range from the ground potential to the power supply voltage.

  Patent Documents 1 and 2 disclose a technique for increasing the circuit operation speed by operating with low power during normal operation and feeding back an output current when the output changes with a MOS transistor configuration. .

JP 2001-255761 A JP 2011-182188 A

Y. Tsuruya et al., “A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs”, 38th IEEE European Solid-State Circuits Conference, pp. 69-72, September 2012. Chi-Hung Lin et al., “A Low-Voltage CMOS Rail-to-Rail Class-AB Input / Output OpAmp with Slew-Rate and Settling Enhancement”, IEEE International Symposium on Circuits and Systems, pp. 448-450, May 1998. Yuan Taur et al., “Fundamentals of Modern VLSI Devices”, Cambridge University Press, pp.125-129, 1998. S. Hatanaka et al., “CMOS Rail-to-Rail Opamp”, Technical Report of IEICE, pp. 169-175, July 1999. R. Jacob Baker et al., “CMOS Circuit Design, Layout, and Simulation”, Institute of Electrical and Electronics Engineers, pp.564-568, 1998. G. Ferri et al., “Integrated Rail-to-Rail Low-Voltage Low-Power Enhanced DC-Gain Fully Differential Operational Transconductance Amplifier”, ETRI Journal, Vol. 29, No. 6, pp. 785-793, December 2007 .

  However, since the rail-to-rail operational amplifier has a large circuit, there is a problem that power consumption becomes large. Since the power consumption of the operational amplifier is proportional to the bias current, low power operation can be realized by reducing the bias current. However, there is a problem that the operation speed is reduced by reducing the bias current.

  An operational amplifier using an adaptive bias technique has been reported as a technique for speeding up a low-power operational amplifier (see Non-Patent Document 1, for example). The adaptive bias technique is a circuit technique that operates with a small current during standby and generates a large current during operation. Thereby, reduction of power consumption and improvement of operation speed are realized at the same time. However, the existing adaptive bias technology is designed for simple op amps that do not consider rail-to-rail, and when used in rail-to-rail op amps, the operation becomes unstable, causing unintended large currents to be generated correctly. There was a problem that did not work. In addition, the amount of adaptive bias current generated cannot be controlled by design.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and in an adaptive bias generation circuit for a rail-to-rail operational amplifier, an adaptive bias generation circuit capable of improving stability and controlling an adaptive bias current amount, and a difference using the same. It is to provide a dynamic amplifier circuit.

An adaptive bias generation circuit according to a first invention is an adaptive bias generation circuit for a rail-to-rail differential amplifier circuit.
A bias current source for generating a constant bias current;
An adder for adding the bias current and a predetermined adaptive current and outputting the resulting current;
An input differential pair circuit that operates based on the current from the adder and differentially amplifies the differential input voltage to generate two corresponding currents;
A current comparison circuit that compares the two currents, selects a small current from the two currents, and outputs a current twice as large as the small current;
From a current obtained by adding the bias current, the adaptive current, and a current that is twice the small current, a current obtained by multiplying the current resulting from the addition of the two currents by K (0 <K <1). A current-voltage conversion circuit that subtracts, compares the current of the subtraction result with the bias current, and converts the current of the comparison result into a voltage;
And a current generation circuit that generates the adaptive current based on a voltage from the current-voltage conversion circuit.

  In the adaptive bias generation circuit, the current-voltage conversion circuit subtracts a current obtained by multiplying the current obtained by adding the two currents by K times (0 <K <1) from the current from the adder, and the subtraction result. And a current twice as large as the small current are added, the current resulting from the addition is compared with the bias current, and the current resulting from the comparison is converted into a voltage.

  Further, in the adaptive bias generation circuit, the current-voltage conversion circuit generates a current obtained by adding the bias current, the adaptive current, and a current twice the small current as a result of the addition of the two currents. A current obtained by multiplying the current by K (0 <K <1) and a current obtained by adding the bias current are compared, and the current of the comparison result is converted into a voltage.

Further, in the adaptive bias generation circuit, a circuit for converting the current of the comparison result into a voltage in the current-voltage conversion circuit is configured by a MOS transistor,
In the circuit to be compared, the adaptive current and a current that is twice the small current flow into the node connected to the gate of the MOS transistor, while the current resulting from the addition of the two currents from the node is multiplied by K times. (0 <K <1) configured to flow out current, or
In the circuit to be compared, a current obtained by multiplying the current resulting from the addition of the two currents by K times (0 <K <1) flows into a node connected to the gate of the MOS transistor. It is characterized in that it is configured such that a current twice as large as the small current flows out.

  In the adaptive bias generation circuit, the adaptive current to be added to a current that is twice the small current is replaced with a current that is n times the adaptive current (0 <n <K).

  Still further, in the current-voltage conversion circuit, the circuit that obtains a current obtained by multiplying the current resulting from the addition of the two currents by K times (0 <K <1) in the feedback circuit includes a pair of MOS transistors, It is a current mirror circuit formed by setting the aspect ratio of the pair of MOS transistors to 1: K.

  A rail-to-rail differential amplifier circuit according to a second aspect of the invention includes the adaptive bias generation circuit.

  According to the adaptive bias generation circuit of the present invention, the current obtained by adding the two currents is multiplied by K times from the current obtained by adding the bias current, the adaptive current, and the current that is twice the small current. (0 <K <1) is subtracted, the current of the subtraction result is compared with the bias current, and the current of the comparison result is converted to a voltage, so that it is suitable for a rail-to-rail operational amplifier. In the bias generation circuit, the stability can be improved and the adaptive bias current amount can be controlled.

(A) is a circuit diagram which shows the structure of a basic differential amplifier circuit, (b) is a figure which shows the input voltage range of the differential amplifier circuit of (a). (A) is a circuit diagram which shows the structure of a basic rail-to-rail operational amplifier, (b) is a figure which shows the input voltage range of the rail-to-rail operational amplifier of (a). (A) is a circuit diagram showing the configuration of a unity gain buffer using an operational amplifier, (b) is a voltage waveform diagram showing the step response of the unity gain buffer of (a). It is a block diagram which shows the structure of the adaptive bias generation circuit which concerns on a comparative example. It is a circuit diagram which shows the structure of the specific example of FIG. It is a circuit diagram which shows the structure of the differential pair circuit provided with the MOS transistor for electric current extraction. 7 is a graph showing a relationship between an input voltage difference ΔV _IN and currents I ₁ , I _2, and I _min in the differential pair circuit of FIG. 6. 4A is a circuit when the input differential pair circuit 1 is on in the adaptive bias generation circuit of FIG. 4, and FIG. 4B is a circuit when the input differential pair circuit 1 is off in the adaptive bias generation circuit of FIG. Circuit. 1 is a block diagram showing a configuration of an adaptive bias generation circuit according to a first embodiment of the present invention. It is a block diagram which shows the structure of the modification of the adaptive bias production | generation circuit of FIG. 9A. It is a circuit diagram which shows the structure of the specific example of the adaptive bias production | generation circuit of FIG. 9A. 10A is a circuit when the input differential pair circuit 1 is on in the adaptive bias generation circuit of FIG. 10, and FIG. 10B is a circuit when the input differential pair circuit 1 is off in the adaptive bias generation circuit of FIG. Circuit. It is a block diagram which shows the structure of the rail-to-rail differential amplifier circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the operational amplifier main body 21 among the rail-to-rail differential amplifier circuits of FIG. It is a circuit diagram which shows the structure of the adaptive bias production | generation circuit 22B among the rail-to-rail differential amplifier circuits of FIG. (A) It is a graph which shows the SPIE simulation result of the differential amplifier circuit based on Example 1, Comprising: The frequency characteristic of the gain, (b) It is the graph which shows the frequency characteristic of the phase. 5 is a graph showing the input / output characteristics of a SPIE simulation result of a unity gain buffer using the differential amplifier circuit according to the first embodiment. 6 is a graph showing the SPIE simulation result of the unity gain buffer using the differential amplifier circuit according to the first embodiment and showing the current consumption with respect to the input voltage. FIG. 9 is a graph showing an SPIE simulation result of the unity gain buffer using the differential amplifier circuit according to the first embodiment and showing an error voltage with respect to the input voltage. (A) is a SPIE simulation result of the input voltage of the unity gain buffer using the differential amplifier circuit according to the first embodiment, and is a voltage waveform diagram showing a step response characteristic at the time of rising; (b) These are figures which show the time passage of the consumption current. (A) is a SPIE simulation result of the unity gain buffer using the differential amplifier circuit according to the first embodiment, and is a voltage waveform diagram showing a step response characteristic when the input voltage falls, (b) ) Is a diagram showing the elapsed time of the current consumption. It is a table | surface which shows the summary of the SPIE simulation result of Example 1 and 2 and Comparative Example 1 and 2. FIG. It is a circuit diagram which shows the structure of the adaptive bias generation circuit which concerns on the 1st modification of this invention. It is a circuit diagram which shows the structure of the adaptive bias generation circuit which concerns on the 2nd modification of this invention. FIG. 24 is a circuit diagram showing a configuration of an n-fold current mirror circuit of FIG. 23.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  In the present invention, an adaptive bias technique that overcomes the problems of the conventional adaptive bias technique has been developed for the purpose of improving the performance of an operational amplifier for smart sensor LSI application. We also propose an ultra-low power, high-speed rail-to-rail differential amplifier circuit using this. The proposed adaptive bias generation circuit is characterized in that a current path is added to the existing circuit to improve the stability of the adaptive bias current generation circuit and to control the amount of adaptive bias current.

1. Basic Differential Amplifier Circuit FIG. 1A is a circuit diagram showing the configuration of a basic differential amplifier circuit, and FIG. 1B shows the input voltage range of the differential amplifier circuit of FIG. FIG. In FIG. 1A, the differential amplifier circuit includes an input differential pair circuit (MOS transistors M1 and M2), a current mirror circuit (MOS transistors M3 and M4), and a tail current source (MOS transistor M5). Configured. Here, the power supply voltage is V _DD , the gate-source voltage of the MOS transistor M1 is V _GS1 , the drain-source voltage is V _DS1 , the gate-source voltage of the MOS transistor M3 is V _GS3 , and the drain of the MOS transistor M5 The source voltage is V _DS5 , and the minimum saturation drain-source voltage necessary for operating the MOS transistor in the saturation region is V _Dsat .

Here, since V _DS5 = V _{IN +} −V _GS1 , the lower limit of the input voltage V _{IN +} is determined by the following equation based on conditions for the MOS transistor M5 to operate in the saturation region.

V _{IN +} -V _GS1 = V _DS5 > V _Dsat

Therefore, the lower limit of the input voltage _{VIN +} is expressed by the following equation.

V _{IN +} > V _GS1 + V _Dsat

In addition, since the sum of the drain-source voltages V _DS1 , V _DS3 , and V _DS5 of the MOS transistors M1, M3, and M5 must be lower than the power supply voltage, the upper limit of the input voltage V _{IN +} when V _DS1 = V _Dsat Is determined by the following equation.

V _DS1 + | V _GS3 | + V _DS5 = V _Dsat + | V _GS3 | + V _{IN +} −V _GS1 <V _DD

Therefore, the upper limit of the input voltage _{VIN +} is expressed by the following equation.

_{VIN +} <V _DD − (| V _GS3 | −V _GS1 + V _Dsat )

  From the above, the input voltage range of the input differential pair circuit composed of nMOS transistors is expressed by the following equation.

V _GS1 + V _Dsat <V _{IN +} <V _DD − (| V _GS3 | −V _GS1 + V _Dsat )

That is, the input voltage range of the basic differential amplifier circuit is smaller than the power supply voltage V _DD .

2. Rail-to-rail operational amplifier As a technique to solve the restrictions on the input voltage range of the input differential pair circuit, the input differential pair circuit is both an nMOS transistor input differential pair circuit and a pMOS transistor input differential pair circuit. There is a technique that enables rail-to-rail operation.

2A is a circuit diagram showing a configuration of a basic rail-to-rail operational amplifier, and FIG. 2B is a diagram showing an input voltage range of the rail-to-rail operational amplifier of FIG. 2A. is there. In FIG. 2A, a rail-to-rail operational amplifier includes an nMOS transistor input differential pair circuit (MOS transistors M1 and M2), a pMOS transistor input differential pair circuit (MOS transistors M3 and M4), and a tail. A current source (MOS transistors M5 and M6) and a cascode amplification stage (MOS transistors M7 to M14) are provided. As shown in FIG. 2B, when the input voltage V _{IN +} is higher than a predetermined voltage (V _GS1 + V _DSAT ), the input differential pair circuit of the nMOS transistor indicates that the input voltage V _{IN +} is equal to the predetermined voltage (V _DD − When it is lower than (V _GS3 + V _Dsat ), the input differential pair circuit of the pMOS transistor operates and corresponds to a wide input voltage range.

Next, the input voltage range of the input differential pair circuit of the nMOS transistor will be described. Here, the power supply voltage is V _DD , the gate-source voltage of the MOS transistor M1 is V _GS1 , the drain-source voltage is V _DS1 , the drain-source voltage of the MOS transistor M6 is V _DS6 , and the drain of the MOS transistor M7 - the source voltage _V DS7, the minimum saturation drain-source voltage required for the MOS transistor operates in the saturation region and _{V Dsat.} The lower limit of the input voltage _{VIN +} is determined by the following equation in the same manner as described above.

V _{IN +} -V _GS1 = V _DS6 > V _Dsat

Therefore, the lower limit of the input voltage _{VIN +} is expressed by the following equation.

V _{IN +} > V _GS1 + V _Dsat

Similarly, the upper limit of the input voltage _{VIN +} is determined by the following equation.

_{V DS1 + V DS6 + V DS7} = V Dsat + V IN + -V GS1 + V Dsat <V DD

Therefore, the upper limit of the input voltage _{VIN +} is expressed by the following equation.

_{VIN +} <V _DD − (2V _Dsat− V _GS1 )

Here, since 2V _Dsat −V _GS1 <0, the upper limit of the input voltage _{VIN +} is V _DD .

In the input voltage range of the input differential pair circuit of the pMOS transistor, the relationship between the upper limit and the lower limit of the nMOS transistor input stage is reversed. As described above, when the input voltage V _{IN +} is lower than the predetermined voltage (V _GS1 + V _DSAT ), the pMOS transistor input stage operates, and the input voltage V _{IN +} is higher than the predetermined voltage (V _DD − (V _GS3 + V _Dsat ). Sometimes the nMOS transistor input stage operates, both input stages operate simultaneously when the input voltage _{VIN +} is in the middle range between these two voltages, and compensates for the area where the two input stages cannot operate with each other. Input is possible in the range from the potential (GND) to the power supply voltage V _DD .

The rail-to-rail operational amplifier of FIG. 2 requires a tail current for each input stage of the nMOS transistor and the pMOS transistor. In addition, a bias circuit for generating the bias voltages V _B3 , V _B4 , and V _B5 of the cascode amplification stage is necessary. For this reason, compared with the basic differential amplifier circuit of FIG. 1, the circuit tends to be large and power consumption tends to increase (see, for example, Non-Patent Document 2).

3. Operational Amplifier Slew Rate and Power Consumption FIG. 3A is a circuit diagram showing a configuration of a unity gain buffer using an operational amplifier, and FIG. 3B is a step of the unity gain buffer of FIG. It is a voltage waveform diagram which shows a response. Here, the unity gain buffer includes an operational amplifier 10 having a non-inverting input terminal connected to the input voltage terminal and having a feedback circuit from the output terminal to the inverting input terminal, and the input voltage V _IN = the output voltage V. _Operates to be _OUT . When a steep pulse voltage is input to the unity gain buffer, it changes with a certain slope. This maximum inclination is called a slew rate SR and is expressed by the following equation (for example, see Non-Patent Document 3).

SR = ΔV / Δt (1)

Here, ΔV is a change amount of the output voltage per unit time Δt. A large slew rate SR means that the output voltage _VOUT can respond at high speed. Therefore, the slew rate SR can be regarded as a speed index of the operational amplifier 10. Further, the time Δt required to charge the output load capacitance C _L by a voltage ΔV can be expressed by the following equation using the bias current I _BIAS to drive the operational amplifier 10.

Δt = C _L × ΔV / I _BIAS (2)

  Substituting equation (2) into SR in equation (1), we obtain:

SR = ΔV / Δt = I _BIAS / C _L (3)

From equation (3), the slew rate SR is proportional to the bias current _{I BIAS,} seen to be inversely proportional to the output load capacitance _{C L.}

The power consumption Power of the operational amplifier 10 can be expressed by the product of the bias current I _BIAS and the power supply voltage V _{DD as shown in} the following equation.

Power = I _BIAS × V _DD (4)

Therefore, from the equation (4), the operational amplifier 10 can operate at low power by reducing the bias current I _BIAS . However, as described above, the slew rate SR is lowered by reducing the bias current I _BIAS . For this reason, there is a trade-off relationship between the operation speed of the operational amplifier 10 and the power consumption Power.

4). Adaptive bias technology and adaptive bias generation circuit There is adaptive bias technology as a method for solving the trade-off problem between power consumption and operation speed. From the equations (3) and (4), the slew rate SR and the power consumption Power of the operational amplifier 10 can be expressed by the following equations, respectively.

_{SR = ΔV / Δt = I BIAS} / C L
Power = I _BIAS × V _DD

Here, in order to realize the low power consumption operation of the operational amplifier 10, it is required to lower the bias current I _BIAS , which means that the operation speed is deteriorated. Therefore, consider using an adaptive bias technique. That is, the large current I _ADPmax is biased at the time of signal transition that requires a high slew rate SR, and the minute current I _ADPmin is biased at the time of standby when no signal is input. At this time, the slew rate SR and the power consumption Power are expressed by the following equations.

_{SR = ΔV / Δt = I ADPmax} / C L
Power = I _ADPmin × V _DD

  As a result, the circuit can operate at high speed while suppressing an increase in average power consumption.

FIG. 4 is a block diagram showing a configuration of an adaptive bias generation circuit according to a comparative example, and FIG. 5 is a circuit diagram showing a configuration of a specific example of FIG. 4 and 5 includes an input differential pair circuit 1 (MOS transistors Md1, Mb1, Md2, and Mb2), a current comparison circuit 2 (MOS transistors Mb3 to Mb6), and a current-voltage conversion circuit 3 ( A circuit including MOS transistors Mc3 and Mc4 and one fixed bias current source 5), an adaptive current I _ADP generation circuit 4 (circuit including the MOS transistor Ma2), and another fixed bias current source 5. Configured.

4 and 5, the adaptive bias generation circuit controls the adaptive current I _ADP according to the input voltage difference ΔV _IN = V _{IN +} −V _IN− between the terminals of the input differential pair circuit 1. Here, when the voltages V _{IN +} and V _{IN− of the} non-inverting input terminal and the inverting input terminal input to the input differential pair circuit 1 match (ΔV _IN = 0), the adaptive current I _ADP becomes the minimum value, When the voltages V _{IN +} and V _{IN− of the} non-inverting input terminal and the inverting input terminal are different (ΔV _IN ≠ 0), the adaptive current I _ADP changes according to the value of the input voltage difference ΔV _IN . The input voltage difference ΔV _IN is converted into currents I ₁ and I ₂ by the input differential pair circuit 1. The small current I _min of the two currents changes according to the absolute value | ΔV _IN | of the input voltage difference. For this reason, the adaptive current I _ADP can be controlled in accordance with the value of the input voltage difference ΔV _IN by using the minimum current I _min .

FIG. 6 is a circuit diagram showing a configuration of an input differential pair circuit including a current extracting MOS transistor. Here, the drain current _ID in the sub-threshold region of the MOS transistor is given by the following equation using the gate-source voltage V _GS , the threshold voltage V _TH , and the drain-source voltage V _DS (for example, non- (See Patent Document 3).

I _D = μC _OX (W / L) (ζ−1) V ² _T × exp ((V _GS −V _TH ) / ζ V _T )
X {1-exp (-V _DS / V _T )}

Where μ is the mobility, C _OX is the oxide film capacitance, W is the gate width, L is the gate length, and _VT is the thermal voltage. V _T = k _B T / q, k _B is Boltzmann's constant, T is absolute temperature, q is the elementary charge, ζ = 1 + C _d / C _OX , C _d is the depletion layer capacitance directly under the gate region is there. Here, when the drain-source voltage V _DS becomes larger than about 100 mV, the drain current _ID does not depend on the drain-source voltage V _DS and is expressed by the following equation.

I _D = μC _OX (W / L) (ζ−1) V ² _T × exp ((V _GS −V _TH ) / ζ V _T )

Here, when W / L = K and μC _OX (ζ−1) V _T ² = I ₀ , the following equation is obtained.

I _D = KI ₀ × exp ((V _GS −V _TH ) / ζV _T )

This equation is solved for the voltage V _GS between the gate and the source, the following expression is obtained.

V _GS = V _TH + ζV _T × ln (I _D / KI ₀ )

In FIG. 6, assuming that the gate-source voltages of the MOS transistors M1 and M2 are V _GS1 and V _GS2 and the currents flowing through the MOS transistors M1 and M2 are I ₁ and I ₂ , respectively, the gate-source voltages V _GS1 and V _GS2 can be expressed by the following equation using currents I ₁ and I ₂ , respectively.

V _GS1 = V _TH + ζV _T × ln (I ₁ / KI ₀ )
V _GS2 = V _TH + ζV _T × ln (I ₂ / KI ₀ )

_V IN _+, respectively the gate voltage of the MOS transistors M1 and _M2, when the _{V IN-,} than _{V IN + -V IN- = V GS1} -V GS2, the following expression is obtained.

V _{IN +} −V _IN− = V _GS1 −V _GS2
= {V _TH + ζV _T ln (I ₁ / KI ₀ )} − {V _TH + ζV _T ln (I ₂ / KI ₀ )}
= ΖV _T × ln (I ₁ / I ₂ )

  Therefore, the following equation is obtained.

I ₁ = I ₂ exp ((V _{IN +} −V _IN− ) / ζV _T )

Since the sum of the current I ₁ and the current I ₂ is equal to the tail current I _BIAS , assuming that I ₁ + I ₂ = I _BIAS and V _{IN +} −V _IN− = ΔV _IN , the current I ₁ and the current I ₂ are the input voltage difference as a function of [Delta] V _iN can be expressed by the following equation.

I ₁ = I _BIAS (exp (ΔV _IN / ζV _T ) / (1 + exp (ΔV _IN / ζV _T )))
I ₂ = I _BIAS (1 / (1 + exp (ΔV _IN / ζV _T )))

Here, since the current I ₁ and the current I ₂ are symmetric with respect to the input voltage difference ΔV _IN , the minimum current I _min = min (I ₁ , I ₂ ) can be expressed by the following equation.

I _min = α × I _BIAS

  However, the parameter α is expressed by the following equation.

α = 1 / (1 + exp (| ΔV _IN | / ζV _T )) (5)

FIG. 7 is a graph showing the relationship between the input voltage difference ΔV _IN and the currents I ₁ , I ₂ and I _min in the input differential pair circuit of FIG. As is apparent from FIG. 7, when the input voltage difference ΔV _IN = 0, the current I ₁ = I ₂ = I _min = I _BIAS / 2. Further, when the absolute value | ΔV _IN | of the input voltage difference increases, the minimum current I _min decreases, and when | ΔV _IN |> 0.2V, the minimum current I _min ≈0.

Circuit of Figure 5 showing a specific example of Figure 4, in accordance with the common mode voltage V _CM to be input to the input differential pair circuit 1, "the state input differential pair circuit 1 does not state or operation works", and wherein Hereinafter, each state is referred to as “the input differential pair circuit 1 is on or off”.

8A is a circuit when the input differential pair circuit 1 is on in the adaptive bias generation circuit of FIG. 4, and FIG. 8B is an input differential pair circuit 1 in the adaptive bias generation circuit of FIG. Is a circuit when is off. In Figures 8 (a) and 8 (b), V _AC is the AC voltage of the normal mode is input to the input differential pair circuit 1, V _CM is the common-mode input to the input differential pair circuit 1 The common-mode voltage. In FIG. 8B, a circuit portion that does not operate when the input differential pair circuit 1 is off is indicated by a dotted line.

  First, the case where the input differential pair circuit 1 is turned on will be described with reference to FIG.

When common-mode voltage _{V CM} is lower than a predetermined voltage, MOS transistor Md1, Mb1, Md2, Mb2 input differential pair circuit 1 constituted by the operating current through the input differential pair circuit 1, MOS transistors Mb3 It is detected by the current comparison circuit 2 constituted by ~ Mb6. Of MOS transistor Mb3 of the current comparison circuit 2 and MB5, MOS transistor towards the gate-source voltage _{V GS} is large, it operates in a linear region. As a result, the smaller current I _min of the current I ₁ and the current I ₂ flows through the MOS transistors Mb3 and Mb5. Since MOS transistors Mb4 and Mb6 operate similarly, 2I _min flows through MOS transistor Mc3.

When the MOS transistor Mb5 or Mb6 operates in the linear region, the gate-source voltage V _GS of the MOS transistors Mb3, Mb4 is compared with the gate-source voltage V _GS of the MOS transistors Mb1, Mb2, and the MOS transistors Mb5, Mb6 smaller by the drain-to-source voltage _{V DS.} Furthermore, since the source potential Vs of the MOS transistors Mb3 and Mb4 becomes higher than the substrate potential, the threshold voltage rises due to the substrate bias effect. Due to these factors, the amount of current flowing through the MOS transistors Mb3 and Mb4 is smaller than the amount of current to be monitored. Here, the amount of current decrease is assumed to be ΔI. The MOS transistors Mc3 and Mc4 have a current mirror configuration, and the MOS transistor Mc3 tries to pass the same current as itself to the MOS transistor Mc4. The current flowing through the MOS transistor Mc4 and _{I 4.} When the current I ₄ is larger than the bias current I _BIAS , the control voltage V _ADP increases and the adaptive current I _ADP decreases. Therefore, the minimum current _{I min} is decreased, the current _{I 4} also decreases. On the other hand, when the current I ₄ is smaller than the bias current I _BIAS , the control voltage V _ADP decreases and the adaptive current I _ADP increases. Therefore, the minimum current _{I min} increases, the current _{I 4} is also increased.

By the above operation, the following expression is established since the convergence finally occurs to I ₄ = I _BIAS .

2 (I _min −ΔI) = I _BIAS

Here, the following equation is obtained from I _min = α × I _BIAS .

2 (α × I _BIAS −ΔI) = I _BIAS

Since the tail currents of the MOS transistors Md1 and Md2 constituting the input differential pair circuit 1 are I _BIAS + I _ADP , the following equation is obtained.

2α × (I _BIAS + I _ADP ) −2ΔI = I _BIAS

Therefore, the following equation is obtained for the adaptive current I _ADP .

I _ADP = ((1-2α) / 2α) I _BIAS + (1 / α) ΔI

Here, alpha is because it is a function of the input voltage difference [Delta] V _IN, when the input voltage difference [Delta] V _IN changes, the control voltage V _ADP such that the adaptive current I _ADP as the above equation is satisfied changes. Since α = ½ when the input voltage difference ΔV _IN = 0, the following equation is established.

I _ADP = 2ΔI

Further, MOS transistors Mb3, Mb4 of aspect ratios each MOS transistor Mb2, is made larger than Mb1, can mitigate the decrease in the amount of current due to the decrease and the substrate bias effect of the gate-source voltage _{V GS,} the input voltage difference ΔV The value of the adaptive current I _ADP at _IN = 0 can be reduced, and power consumption during standby can be suppressed. When the input voltage difference ΔV _IN ≠ 0, according to the equation (5), α≈0 for a sufficiently large input voltage difference ΔV _IN , so that the adaptive current I _ADP increases and the operational amplifier can be driven at high speed.

  Further, problems of the adaptive bias generation circuit according to the comparative example will be described below.

  The adaptive bias generation circuit of FIG. 5 has a problem that when the input differential pair circuit 1 is turned off, the adaptive bias current generation circuit stops its operation and cannot operate stably. This will be described below with reference to FIG.

When common-mode voltage V _CM is higher than a predetermined voltage, the input differential pair circuit 1 stops operating. Since the input differential pair circuit 1 is off, the current I ₁ = I ₂ = 0. Here, since the current flowing through the MOS transistors Mb3, Mb4, Mb5, Mb6, and Mc3 is 0, the MOS transistor Mc4 is turned off. As a result, the control voltage V _ADP gradually approaches the ground potential. That is, when the input differential pair circuit 1 stops operating, the feedback loop of the adaptive bias loop is disconnected. For this reason, the control voltage V _ADP cannot be controlled, and stable operation becomes difficult. In particular, the change in common-mode voltage V _CM, the input differential pair circuit 1 when turned on again off, large distortion in the output uncontrollable large currents occur arises. This becomes a problem when the input range is from the ground potential to the power supply voltage V _DD . Therefore, the existing adaptive bias generation circuit cannot be applied to a rail-to-rail operational amplifier.

  As explained above, in the comparative example, the input range of the operational amplifier that does not consider rail-to-rail is narrower than the range from the ground potential to the power supply voltage, and the ratio of the input range to the power supply voltage width when the power supply voltage is lowered There is a problem that decreases. Rail-to-rail operational amplifiers can be input in the entire range from the ground potential to the power supply voltage, but there is a problem that the circuit scale is large and the power consumption increases compared to an operational amplifier that does not consider rail-to-rail. . In addition, it was clarified that there is a problem that the existing adaptive bias technology cannot be applied to the rail-to-rail operational amplifier.

5. FIG. 9A is a block diagram showing a configuration of an adaptive bias generation circuit according to the first embodiment of the present invention, and FIG. 10 shows a specific example of the adaptive bias generation circuit 22A in FIG. 9A. It is a circuit diagram which shows the structure of an example. As shown in FIG. 9A, the adaptive bias generation circuit according to the first embodiment has a feedback circuit constituted by a subtraction and addition circuit 11 to adjust the adaptive current I _ADP even when the input differential pair circuit 1 is turned off. A feedback loop is held to prevent the control voltage V _ADP from operating to the ground potential. Further, the addition and K multiplication circuit 12 in FIG. 9A is characterized in that the amount of feedback of the current is adjusted and the generation amount of the adaptive current I _ADP is controlled.

9A and 10, the adaptive bias generation circuit 22A according to the first embodiment includes:
(1) MOS transistor Md1, Md2, Mb1, is constituted by a circuit including a Mb2, the input voltage _V IN _+, the input voltage by performing a differential amplification with respect to _{V IN- V} IN _+, a current _{I 1} corresponding to _{V IN-} , I ₂ , an input differential pair circuit 1,
(2) is constituted by a circuit including a MOS transistor Mb3～Mb6, twice the current _{2I min} of the minimum current _{I min} is a small current ones of currents _I 1, _{I 2} compares the current _I 1, _{I 2} A current comparison circuit 2 for generating and outputting;
(3) it is constituted by MOS transistors Mc3, Mc4 and constant bias current _I circuit comprising fixed bias current source _{5 BIAS} the generated output, compared to the current flowing through the bias current _{I BIAS} to the MOS transistor Mc4, the comparison result A current-voltage conversion circuit 3 that converts a current corresponding to the voltage into a voltage and outputs the voltage;
(4) it is constituted by a circuit including a MOS transistor Ma2, and adaptive current _{I ADP} generation circuit 4 that generates and outputs an adaptive current _{I ADP} corresponding to the voltage from the current-voltage conversion circuit 3,
(5) a fixed bias current source 5 composed of two constant current sources and generating and outputting a constant bias current I _BIAS ;
(6) An adder 6 that is configured by a connection point connected to the gate of the MOS transistor Ma2, adds the adaptive current I _ADP and the bias current I _BIAS , and supplies a current resulting from the addition to the input differential pair circuit 1;
(7) Consists of a circuit including MOS transistors Mb7 and Mb8, and includes an adder 12a and a K multiplier 12b. The currents I ₁ and I ₂ are added and the resulting current is multiplied by K to obtain the resulting current Is added to the subtractor 11a of the subtraction and addition circuit 11, and the addition and K multiplication circuit 12;
(8) The circuit includes MOS transistors Mc1 and Mc2, and includes a subtractor 11a and an adder 11b. The current comparison circuit 2 subtracts the current from the adder 6 and the current from the K multiplier circuit 12b from the current from the adder 6. And a subtracting / adding circuit 11 for adding the current 2I _min from the current and outputting the resulting current to the current-voltage conversion circuit 3.

  11A is a circuit when the input differential pair is on in the adaptive bias generation circuit 22A of FIG. 10, and FIG. 11B is a circuit where the input differential pair is off in the adaptive bias generation circuit 22A of FIG. It is a circuit when. Hereinafter, the circuit operation of the adaptive bias generation circuit 22A of FIG. 10 will be described with reference to FIGS. 11 (a) and 11 (b).

In FIG. 11A showing when the input differential pair circuit 1 is on, the MOS transistors Mb1 to Mb6 operate in the same manner as in FIG. The MOS transistors Mb7 and Mb8 respectively extract the aspect ratio of the MOS transistors Mb7, Mb8, Mb1, and Mb2 (of the gate width W with respect to the gate length L) so as to extract a current K times (0 <K <1) that of the MOS transistors Mb1 and Mb2. Ratio). Specifically, the MOS transistors Mb1 and Mb7 form a current mirror circuit, the MOS transistors Mb2 and Mb8 form a current mirror circuit, and the aspect ratio of the MOS transistor Mb7 is K times the aspect ratio of the MOS transistor Mb1. The MOS transistors Mb7, Mb8, Mb1, and Mb2 are formed so that the aspect ratio of the MOS transistor Mb8 is K times the aspect ratio of the MOS transistor Mb2. At this time, a current K × I ₁ K times the current I ₁ flowing in the MOS transistor Mb1 flows in the MOS transistor Mb7, and a current K × I ₂ K times the current I ₂ flowing in the MOS transistor Mb2 flows in the MOS transistor Mb8. .

Since the adaptive current I _ADP flows through the MOS transistor Ma1, a current (I _BIAS + I _ADP −K (I ₁ + I ₂ )) flows through the MOS transistor Mc1. Since the current of the MOS transistor Mc1 is copied by the MOS transistor Mc2 by the current mirror circuit composed of the MOS transistors Mc1 and Mc2, the current of the following value flows through the MOS transistor Mc3.

I _BIAS + I _ADP −K (I ₁ + I ₂ ) + 2I _min (6)

The MOS transistors Mc3 and Mc4 constitute a current mirror circuit. The current of the above formula (6) flows through each MOS transistor Mc3 and Mc4, and the current of the above formula (6) flowing through the MOS transistor Mc4 is connected to the connection point. While flowing into 6C, the bias current I _BIAS flows out of the connection point 6C. The circuit operates so that these two currents are equal, and the operation is expressed by the following equation.

I _BIAS + I _ADP −K (I ₁ + I ₂ ) + 2I _min = I _BIAS

Here, since I ₁ + I ₂ = I _BIAS + I _ADP and I _min = α (I _BIAS + I _ADP ) −ΔI, the following equation is obtained.

I _BIAS + I _ADP −K (I _BIAS + I _ADP ) +2 (α (I _BIAS + I _ADP ) −ΔI) = I _BIAS

Accordingly, the adaptive current I _ADP is expressed by the following equation.

I _ADP = ((K-2α) I _BIAS + 2ΔI) / (1−K + 2α)

Since α = 1/2 when the input voltage difference ΔV _IN = 0, the following equation is obtained.

I _ADP = ((K-1) I _BIAS + 2ΔI) / (2-K)

Further, when the input voltage difference ΔV _IN ≠ 0, according to the equation (5), α≈0 is obtained for a sufficiently large ΔV _IN , so the following equation is obtained.

I _ADP = (KI _BIAS + 2ΔI) / (1-K)

From the above, regarding the aspect ratio of the MOS transistors Mb7, Mb8, Mb1, and Mb2, the aspect ratio of the MOS transistor Mb7 is K times the aspect ratio of the MOS transistor Mb1, and the aspect ratio of the MOS transistor Mb8 is K of the aspect ratio of the MOS transistor Mb2. The MOS transistors Mb7, Mb8, Mb1, and Mb2 are formed so as to be doubled, and the parameter K is adjusted to control the generation amount of the adaptive current I _ADP during standby and during operation. Note that the adaptive bias voltage V _ADPm corresponding to the adaptive current I _ADP is output from the gate voltage of the MOS transistor _Ma2 .

In FIG. 11B showing when the input differential pair circuit 1 is off, I ₁ = I ₂ = 0. At this time, since I _min = 0 and K (I ₁ + I ₂ ) = 0, the current flowing through the MOS transistor Mc3 is I _BIAS + I _ADP . As in the case where the input differential pair circuit 1 is on, the MOS transistors Mc3 and Mc4 constitute a current mirror circuit, and the same current flows in each circuit. In this circuit, the current flowing through the MOS transistor Mc4 and the bias current I _BIAS Are equal to each other, and the operation is expressed by the following equation.

I _BIAS + I _ADP = I _BIAS

As a result, the adaptive current I _ADP converges to 0. In the adaptive bias current generation circuit according to the comparative example illustrated in FIGS. 4 and 5, when the input differential pair circuit 1 is off, the control voltage V _ADP is 0 V and the feedback control is cut off. However, by using the adaptive bias generation circuit 22A according to the first embodiment of FIGS. 9A and 10, the control voltage V _ADP can be controlled, and a stable operation can be realized.

As described above, according to the adaptive bias generation circuit according to the present embodiment, the adaptive bias generation circuit according to the comparative example further includes the subtraction / addition circuit 11 and the addition / K multiplication circuit 12, thereby The adaptive current I _ADP can be controlled for all input voltages up to the power supply voltage V _DD . This solves the problem that a large current is generated at the moment when the input differential pair circuit 1 is switched from OFF to ON in the adaptive bias generation circuit according to the comparative example. Further, the generation amount of the adaptive current I _ADP can be controlled by adjusting the aspect ratio of the MOS transistors Mb7, Mb8, Mb1, and Mb2.

In the first embodiment described above, the adaptive current I _ADP may become negative when the input voltage difference ΔV _IN = 0, and the following relational expression will be described below.

nI _BIAS + I _ADP −K (I ₁ + I ₂ ) + 2I _min = I _BIAS

Here, since I ₁ + I ₂ = I _BIAS + I _ADP and I _min = α (I _BIAS + I _ADP ) −ΔI, the following equation is obtained.

nI _BIAS + I _ADP −K (I _BIAS + I _ADP ) +2 (α (I _BIAS + I _ADP ) −ΔI)
= I _BIAS

Accordingly, the adaptive current I _ADP is expressed by the following equation.

I _ADP = ((1-n + K-2α) I _BIAS + 2ΔI) / (1-K + 2α)

Here, when the input voltage difference ΔV _IN = 0, α = 1/2, so the following equation is obtained.

I _ADP = ((K−n) I _BIAS + 2ΔI) / (2-K)

When the input voltage difference ΔV _IN ≠ 0, according to the equation (5), α≈0 is obtained for a sufficiently large ΔV _IN , so the following equation is obtained.

I _ADP = ((1-n + K) I _BIAS + 2ΔI) / (1-K)

Accordingly, K is set in the range of 0 <K <1 as described above. However, in order to make the adaptive current I _ADP positive, 1−n + K> 0, and the condition of the following equation needs to be satisfied. .

0 <n <K <1

FIG. 9B is a block diagram showing a configuration of a modified example of the adaptive bias generation circuit of FIG. 9A. 9A, the subtraction and addition circuit 11 and the current-voltage conversion circuit 3 are configured separately. However, the present invention is not limited to this, and as shown in FIG. 9B, the operation of the addition circuit 11 and the current-voltage conversion circuit 3 May be integrated to form the current-voltage conversion circuit 3A. That is, the current-voltage conversion circuit 3A can change the circuit so that the current of I _BIAS + I _ADP + 2I _min is equal to the current of I _BIAS + K (I ₁ + I ₂ ). This configuration corresponds to the circuit configuration of FIG.

6). Rail-to-Rail Differential Amplifier Circuit According to Second Embodiment FIG. 12 is a block diagram showing a configuration of a rail-to-rail differential amplifier circuit according to the second embodiment of the present invention. 13 is a circuit diagram showing a configuration of the operational amplifier main body 21 in the rail-to-rail differential amplifier circuit of FIG. 12, and FIG. 14 is a circuit diagram of the rail-to-rail differential amplifier circuit in FIG. It is a circuit diagram which shows the structure of the adaptive bias generation circuit 22B. In FIG. 14, the same reference numerals are assigned to the corresponding circuits of the circuits 1 to 12 in FIG.

In FIG. 12, the rail-to-rail differential amplifier circuit according to the second embodiment is
(1) A rail-to-rail operational amplifier 21 disclosed in Non-Patent Document 4 and illustrated in FIG.
(2) The adaptive bias generation circuit 22 includes the adaptive bias generation circuit 22A of FIG. 10 and the adaptive bias generation circuit 22B of FIG.

Here, each adaptive bias generation circuit 22A has a pMOS transistor input differential pair circuit 1, and an adaptive bias voltage V for the pMOS transistor input differential pair circuit of the rail-to-rail operational amplifier 21 of FIG. _{Supply ADPm} . Each adaptive bias generation circuit 22B has an nMOS transistor input differential pair circuit 1, and an adaptive bias voltage V _ADPn for the nMOS transistor input differential pair circuit of the rail-to-rail operational amplifier 21 of FIG. Supply. Note that the adaptive bias voltage V _ADPm corresponding to the adaptive current I _ADP is output from the gate voltage of the MOS transistor _Ma2 .

The rail-to-rail operational amplifier 21 of FIG. 13 includes an operational amplifier unit 21a and a bias generation circuit 21b. Bias voltages V _B1 , V _B2 , V _B3 , and V _B4 are generated by supplying I _ADP generated by the bias current I _BAIS , I _ADP generated by the adaptive bias generation circuit 22 A, and I _ADP generated by the adaptive bias generation circuit 22 B as I _IN. Is done. (I _IN = I _BIAS + I _ADP (for pMOS differential pair circuit) + I _ADP (for nMOS differential pair circuit))

  Note that the current mirror circuit configured by the MOS transistors Me1 to Me6 in FIG. 13 prevents in-phase components of the current from flowing into the cascode output circuit configured by the MOS transistors Mc1 to Mc8 (for example, Non-Patent Document 4). reference).

According to the rail-to-rail operational amplifier according to the second embodiment configured as described above, the adaptive bias generation circuit 22A of FIG. 10 and the adaptive bias generation circuit of FIG. 22B is mounted, and an adaptive bias current and an adaptive bias voltage corresponding to the input voltage from the ground potential to the power supply voltage V _DD can be generated.

7). Evaluation by simulation
(1) In the case of the rail-to-rail operational amplifier 21 including the adaptive bias generation circuits 22A and 22B of FIGS. 10 and 14 and K = 15/16 (Example 1),
(2) In the rail-to-rail operational amplifier 21 including the adaptive bias generation circuits 22A and 22B shown in FIGS. 10 and 14, and K = 14/16 (Embodiment 2),
(3) a rail-to-rail operational amplifier 21 (Comparative Example 1) provided with the adaptive bias generation circuit shown in FIG.
(4) Simulation evaluation was performed by SPICE (Simulation Program with Integrated Circuit Emphasis) for the case where the adaptive bias generation circuits 22A and 22B were not used in the rail-to-rail operational amplifier 21 shown in FIG. 13 (Comparative Example 2). .

In the simulation, the process used was 0.18-μmCMOS process, the power supply voltage _{V DD} is 1.8 V, the output load capacitance _{C L} is set to 10 pF. Further, 106.5 nA in Comparative Example 2 to which only a fixed bias current was applied, 68 nA in Comparative Example 1, 65.5 nA in Example 1, 75.5 nA in Example 2, and the input voltage in the unity gain buffer configuration It was determined that the current consumption of the entire circuit when _VIN was 0.9 V was 1 μA.

  FIG. 15A is a SPICE simulation result of the differential amplifier circuit according to the first embodiment, and is a graph showing frequency characteristics of the gain. FIG. 15B is a graph showing frequency characteristics of the phase. 15 shows a Bode diagram of the first embodiment. Here, the DC gain is 83.4 dB, the unity gain frequency is 5.91 kHz, and the phase margin is 88.4 °. As is clear from FIG. 15, by ensuring a phase margin of 60 ° or more, the first embodiment operates stably even when negative feedback is applied.

  FIG. 16 is a SPICE simulation result of the unity gain buffer using the differential amplifier circuit according to the first embodiment, and is a graph showing its input / output characteristics. FIG. 17 is a graph showing the differential amplifier circuit according to the first embodiment. 5 is a SPICE simulation result of the unity gain buffer using the, and is a graph showing current consumption with respect to the input voltage. FIG. 18 is a SPICE simulation result of the unity gain buffer using the differential amplifier circuit according to the first embodiment, and is a graph showing an error voltage with respect to the input voltage.

  As can be seen from FIG. 18, Example 1 has high linearity in the range of input voltage from 100 mV to 1.7 V. The linearity is lost when the input voltage approaches the ground potential or the power supply voltage. The output voltage approaches the ground potential or the power supply voltage, and the MOS transistor at the output stage cannot secure a sufficient drain-source voltage. This is because it works. The current consumption depends on the input voltage because the differential pair is switched on / off by the input voltage. When the input voltage is low, the input differential pair circuit of the nMOS transistor is turned off and the input differential pair circuit of the pMOS transistor is turned on. When the input voltage is increased, the input differential pair circuit of the nMOS transistor is turned on and the input of the pMOS transistor is turned on. The differential pair circuit is turned off. Since both of the input differential pair circuits are turned on at an intermediate portion of the input voltage, the current consumption is maximized.

  FIG. 19A is a SPICE simulation result of the input voltage of the unity gain buffer using the differential amplifier circuit according to the first embodiment, and is a voltage waveform diagram showing a step response characteristic at the time of rising. 19 (b) is a diagram showing the elapsed time of the current consumption. FIG. 20A is a SPICE simulation result of the unity gain buffer using the differential amplifier circuit according to the first embodiment, and is a voltage waveform diagram showing step response characteristics at the time of falling of the input voltage. FIG. 20 (b) is a diagram showing the elapsed time of the current consumption.

  As is clear from FIGS. 19 and 20, in Comparative Examples 1 and 2, a large current is generated at the moment when the step wave is input, causing a large distortion. It can be confirmed that Example 1 and Example 2 are not distorted and respond faster than when no adaptive bias is used. Moreover, since the consumption current at the time of signal transition is larger in the first embodiment than in the second embodiment, it can be confirmed that the generation amount of the adaptive bias current can be controlled according to the value of K.

FIG. 21 is a table showing a summary of SPICE simulation results of Examples 1 and 2 and Comparative Examples 1 and 2. As is clear from FIG. 21, the power consumption when the input voltage _VIN is 0.9 V is the standby power (Static Power), and the average power consumption when the 1 kHz rectangular wave is input for 10 periods is the operating power (Dynamic). Power) was evaluated as _{P D.} Moreover, the performance index (figure of merit) FOM, the slew rate SR + and SR- of the mean SR ^±, output load capacitance _{C L,} and using a dynamic power _{P D} was evaluated defined by the following expression.

FOM = SR ^± C _L / P _D

Here, the average value SR ^± of the slew rates SR + and SR− is 9.2 times in the first embodiment and 6.5 times in the second embodiment, compared with the case where the adaptive bias generation circuit is not used. It was realized. Further, the figure of merit FOM was 6.9 times in Example 1 and 4.7 times in Example 2 compared to the case where the adaptive bias generation circuit was not used.

8). Advantageous Effects of Embodiment According to the embodiment of the present invention, adaptive bias generation circuits 22A and 22B capable of rail-to-rail operation, and an ultra-low power and high-speed rail-to-rail operational amplifier (FIG. 12) using the same. ) Was proposed. The adaptive bias generation circuit according to the first comparative example converts the terminal voltage of the input differential pair circuit into a current and monitors it, and generates an adaptive bias current according to a change in current. However, the adaptive bias generation circuit according to Comparative Example 1 has a problem that a large current is generated at the moment when the input differential pair circuit is switched from OFF to ON. This is because when the input differential pair circuit stops, the current flowing through the input differential pair circuit stops, so that the feedback loop in the adaptive bias generation circuit is cut, and the control voltage gradually approaches the ground potential or the power supply voltage. Is the cause. In addition, the amount of adaptive bias current generated cannot be controlled by design.

  Therefore, in the adaptive bias generation circuit according to the present embodiment, new current feedback circuits 11 and 12 are provided for the purpose of controlling the adaptive bias current and adjusting the generation amount of the adaptive bias current when the input differential pair circuit 1 is off. Added. As a result, the adaptive bias current can be converged with the input common mode voltage at which the input differential pair circuit 1 is stopped, and the problem that a large current is generated is solved. Further, the amount of adaptive bias current generated can be controlled by adjusting the aspect ratio of the MOS transistor of the adder / K multiplier circuit 12. Furthermore, by driving the rail-to-rail operational amplifier 21 using the adaptive bias generation circuits 22A and 22B according to the present embodiment, the rail-to-rail operational amplifier can be operated at extremely low power and at high speed. Further, in the SPICE simulation, the adaptive bias generation circuit according to the present embodiment confirms that the large current that has been a problem in the adaptive bias generation circuit according to Comparative Example 1 does not occur, and compares it with the case where the adaptive bias is not used. As a result, the speed was increased by 9.2 times under the same power consumption.

9. First Modified Example of Adaptive Bias Generation Circuit FIG. 22 is a circuit diagram showing a configuration of an adaptive bias generation circuit according to a first modified example of the present invention. The adaptive bias current I _ADP in the adaptive bias generation circuit according to the present embodiment in FIG. 10 is determined by the potential (control voltage V _M ) of the node 6C in FIG. Considering the current flowing into and out of the node 6C, the following equation is established.

I _BIAS + I _ADP −K (I ₁ + I ₂ ) + 2I _min = I _BIAS

  When this equation is transformed, the following equation is obtained.

I _BIAS + I _ADP + 2I _min = I _BIAS + K (I ₁ + I ₂ ) (7)

  From this equation (7), consider simplifying the adaptive bias current generating circuit. FIG. 22 shows an adaptive bias generation circuit according to a first modification that satisfies Equation (7). Unlike the adaptive bias generation circuit 22A according to the first embodiment of FIG. 10, the circuit configuration is such that necessary current addition / subtraction is performed at the node 6C. The circuit configuration corresponds to the adaptive bias generation circuit of FIG. 9B, and the subtraction and addition circuit 11 of FIG. 9A can be reduced. With the adaptive bias generation circuit according to the first modification, it is possible to reduce power and increase accuracy by simplifying the circuit configuration. The circuit operation will be described below.

As described above, when the current flowing through the MOS transistors Mb1, Mb2 of the input differential pair circuit 1, respectively, and _{I 1} and _{I 2,} the control voltage _{V M} so as to satisfy the relation of the equation (7) is determined .

I _BIAS + I _ADP + 2I _min = I _BIAS + K (I ₁ + I ₂ ) (8)

  The left side of the above equation (8) indicates the current flowing into the node 6C, while the right side of the above equation (8) indicates the current flowing out from the node 6C, and the control is performed so that the current flowing into the node 6C is equal to the flowing out current It shows that. This case is the case of the input differential pair circuit 1 of the pMOS transistor. However, in the case of the input differential pair circuit 1 of the nMOS transistor, the flowing current and the flowing current have an inverse relationship.

Here, I ₁ + I ₂ = I _BIAS + I _ADP , and the minimum current I _min is expressed by the following equation.

I _min = α (I _BIAS + I _ADP ) −ΔI

However, α (I _BIAS + I _ADP )> ΔI. Substituting and organizing these gives the following formula.

I _ADP = ((K−2α) / (1 + 2α−K)) I _BIAS + (2 / (1 + 2α−K)) ΔI
(9)

According to this equation (9), a control voltage _{V M} adaptively current _{I ADP} flows is controlled. Here, as a numerical example, when the absolute value of the input voltage difference | ΔV _IN | = 0, α is ½. At this time, the following equation is obtained.

I _ADP = ((K-1) / (2-K)) I _BIAS + (2 _// (2-K)) ΔI

Further, α is 0 when the absolute value of the input voltage difference | ΔV _IN | >> 0. At this time, the following equation is obtained.

I _ADP = (K / (1-K)) I _BIAS + (2 / (1-K)) ΔI

Further, when the input differential pair circuit 1 is off, since I _min = 0, I ₁ = 0, and I ₂ = 0, the following equation is obtained.

I _BIAS + I _ADP = I _BIAS (10)

Therefore, the adaptive current I _ADP flows so as to satisfy the equation (10). Since the adaptive current I _ADP = 0, the power consumption is zero.

10. Second Modified Example of Adaptive Bias Generation Circuit FIG. 23 is a circuit diagram showing a configuration of an adaptive bias generation circuit according to a second modification of the present invention. In the first modified example of FIG. 22, when the absolute value of the input voltage difference | ΔV _IN | = 0, the adaptive current I _ADP is I _ADP = ((K−1) / (2-K)) I _BIAS + ( 2 / (2-K)) ΔI, and depending on the values of ΔI and K, the adaptive current I _ADP may be a negative current. Further, when the input differential pair circuit 1 is off, the adaptive current I _ADP becomes 0, which may make controllability difficult. In order to solve these problems, a circuit configuration different from that of the first modification of FIG. 22 was considered. This is the adaptive bias generation circuit according to the second modification of FIG.

In FIG. 23, the bias current nI _BIAS is used instead of the bias current I _BIAS flowing into the node 6C. Thereby, the current flowing into and out of the node 6C is expressed by the following equation.

nI _BIAS + I _ADP + 2I _min = I _BIAS + K (I ₁ + I ₂ )

  The operation of this circuit will be described below.

In FIG. 23, when I _ADP is obtained by arranging the current related to the node 6C, the following equation is obtained.

I _ADP =
((1-n-2α + K) / (1 + 2α-K)) I _BIAS + (2 / (1 + 2α-K)) ΔI
(11)

According to this equation (11), a control voltage _{V M} adaptively current _{I ADP} flows is controlled. As a numerical example, when the absolute value of the input voltage difference | ΔV _IN | = 0, α is ½. Therefore, the following equation is obtained.

I _ADP = ((K−n) / (2-K)) I _BIAS + (2 / (2-K)) ΔI

Since K <1, it can be avoided that the adaptive current I _ADP becomes a negative current by setting n <K. Further, α is 0 when the absolute value of the input voltage difference | ΔV _IN | >> 0. Therefore, the following equation is obtained.

I _ADP = ((1-n + K) / (1-K)) I _BIAS + (2 / (1-K)) ΔI

Further, when the input differential pair circuit 1 is off, since I _min = 0, I ₁ = 0, and I ₂ = 0, the following equation is obtained.

I _ADP = (1-n) I _BIAS (12)

Therefore, the adaptive current I _ADP flows so as to satisfy the equation (12). Even in this case, the following equation must be satisfied.

0 <n <K <1

FIG. 24 is a circuit diagram showing a specific configuration of the n-fold current mirror circuit of FIG. In FIG. 24, when the size ratio of each MOS transistor is MN1: MN2: MN3: MN4 is 1: 1: 1: n, the currents flowing through the MOS transistors MN2, MN3, and MN4 are I _BIAS , I _BIAS , and nI _BIAS , respectively. Become. When the transistor size ratio of the pMOS transistors is MP1: MP2: MP3 = 1: 1: n, the bias current I _BIAS from the nMOS transistor MN2 is received, and the bias currents flowing through the pMOS transistors MP2 and MP3 are I _BIAS and nI _BIAS . Become. As described above, a bias current source of nI _BIAS can be configured.

11. Subtraction and addition circuit 11 and addition and K multiplication circuit 12
The adaptive bias generation circuit according to the first embodiment shown in FIG. 9A includes the subtraction / addition circuit 11 and the addition / K multiplication circuit 12. However, when only the subtraction / addition circuit 11 is provided, the adaptive bias generation circuit 11 The following considers whether the generation circuit performs a desired operation.

  The basic formula of the adaptive bias generation circuit including the subtraction / addition circuit 11 and the addition / K multiplication circuit 12 is as follows.

I _BIAS + I _ADP −K (I ₁ + I ₂ ) + 2I _min = I _BIAS

  Here, assuming the case of only the subtracting and adding circuit 11, the above expression is expressed by the following expression.

I _BIAS + I _ADP + 2I _min = I _BIAS

Here, when I _min = α (I _BIAS + I _ADP ) −ΔI is substituted, the following equation is obtained.

I _BIAS + I _ADP +2 (α (I _BIAS + I _ADP ) −ΔI) = I _BIAS

  In summary, the following equation is obtained.

I _ADP = (2 / (1 + 2α)) ΔI− (2α / (1 + 2α)) I _BIAS

Here, as a numerical example, when the absolute value of the input voltage difference | ΔV _IN | = 0 (α = 1/2), the adaptive bias current I _ADP is expressed by the following equation.

I _ADP = ΔI− (1/2) I _BIAS

In this case, since the adaptive current I _ADP is a negative current, the circuit configuration cannot be used.

When the absolute value of the input voltage difference | ΔV _IN | >> 0 (α = 0), the adaptive current I _ADP is expressed by the following equation.

I _ADP = 2ΔI

Here, when the absolute value of the input voltage difference | ΔV _IN | >> 0, only a very small current is generated in response to a request for generating a large current, so that the circuit configuration cannot be used.

When the input differential pair circuit 1 is off, since I _min = 0, the adaptive current I _ADP flows so as to satisfy the following equation.

I _BIAS + I _ADP = I _BIAS

  As described above, when only the subtraction and addition circuit 11 is provided in the adaptive bias generation circuit of FIG. 9A, the adaptive bias generation circuit cannot perform a desired operation. Therefore, the subtraction and addition circuit 11 and the addition and K It can be understood that the provision of the double circuit 12 is an essential requirement.

As described in detail above, according to the adaptive bias generation circuit of the present invention, the current-voltage conversion circuit is configured to add a current obtained by adding the bias current, the adaptive current, and a current that is twice the small current. The current obtained by adding the current of the two currents by K times (0 <K <1) is subtracted, the current of the subtraction result is compared with the bias current, and the current of the comparison result is converted into a voltage. Therefore, in the adaptive bias generation circuit for the rail-to-rail operational amplifier, the stability can be improved and the adaptive bias current amount can be controlled.

1 ... differential pair,
2 ... Current comparison circuit,
3, 3A ... current-voltage conversion circuit,
4 ... Adaptive current I _ADP generation circuit,
5 ... Fixed bias current source,
6 ... adder,
6C ... node,
10 ... operational amplifier,
11: Subtraction and addition circuit,
11a ... subtractor,
11b ... adder,
12: Addition and K-fold circuit,
12a ... adder,
12b ... K multiplier,
21 ... Rail-to-rail operational amplifier,
22A, 22B... Adaptive bias generation circuit.

Claims (7)

In an adaptive bias generation circuit for a rail-to-rail differential amplifier circuit,
A bias current source for generating a constant bias current;
An adder for adding the bias current and a predetermined adaptive current and outputting the resulting current;
An input differential pair circuit that operates based on the current from the adder and differentially amplifies the differential input voltage to generate two corresponding currents;
A current comparison circuit that compares the two currents, selects a small current from the two currents, and outputs a current twice as large as the small current;
From a current obtained by adding the bias current, the adaptive current, and a current that is twice the small current, a current obtained by multiplying the current resulting from the addition of the two currents by K (0 <K <1). A current-voltage conversion circuit that subtracts, compares the current of the subtraction result with the bias current, and converts the current of the comparison result into a voltage;
An adaptive bias generation circuit comprising: a current generation circuit that generates the adaptive current based on a voltage from the current-voltage conversion circuit.   The current-voltage conversion circuit subtracts a current obtained by multiplying the current resulting from the addition of the two currents by K times (0 <K <1) from the current from the adder, 2. The adaptive bias generation circuit according to claim 1, wherein a current doubled is added, a current resulting from the addition is compared with the bias current, and a current resulting from the comparison is converted into a voltage.   The current-voltage conversion circuit is configured to add a current obtained by adding the bias current, the adaptive current, and a current that is twice the small current, and a current obtained by adding the two currents to K times (0 <K < 2. The adaptive bias generation circuit according to claim 1, wherein the current obtained by 1) is compared with a current obtained by adding the bias current, and the current of the comparison result is converted into a voltage. In the current-voltage conversion circuit, a circuit for converting the current of the comparison result into a voltage is configured by a MOS transistor,
In the circuit to be compared, the adaptive current and a current that is twice the small current flow into the node connected to the gate of the MOS transistor, while the current resulting from the addition of the two currents from the node is multiplied by K times. (0 <K <1) configured to flow out current, or
In the circuit to be compared, a current obtained by multiplying the current resulting from the addition of the two currents by K times (0 <K <1) flows into a node connected to the gate of the MOS transistor. 4. The adaptive bias generation circuit according to claim 3, wherein a current twice as large as the small current flows out.   5. The adaptive current that is added to a current that is twice the small current is replaced with a current that is n times the adaptive current (0 <n <K). The adaptive bias generation circuit described in 1.   In the current-voltage conversion circuit, a circuit that obtains a current obtained by multiplying the current obtained by adding the two currents by K (0 <K <1) includes a pair of MOS transistors, and the aspect of the pair of MOS transistors. 6. The adaptive bias generation circuit according to claim 1, wherein the adaptive bias generation circuit is a current mirror circuit formed at a ratio of 1: K.   A rail-to-rail differential amplifier circuit comprising the adaptive bias generation circuit according to any one of claims 1 to 6.

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