JP6032415B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In order to increase the carrier mobility of a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) and an n-type MISFET formed in a semiconductor integrated circuit device, a structure is known in which stress is applied to the channel region of the MISFET. For example, an n-type MISFET has a known structure in which an insulating film that applies tensile strain to a channel region, such as an SOG film or an SiN film, is formed on the n-type MISFET. As for the p-type MISFET, it is known to form an insulating film that applies compressive strain to the channel region, for example, SiN on the p-type MISFET, or to embed a silicon germanium film in the source / drain regions. In addition, it is known that the tensile strain and the compressive strain are selected by changing the formation conditions of the SiN film.

  In a semiconductor integrated circuit device, since both an n-type MISFET and a p-type MISFET are formed, the insulating film for applying tensile strain and the insulating film for applying compressive strain are formed on the same semiconductor substrate. The insulating film covering the n-type MISFET on the semiconductor substrate is removed by etching in the p-type MISFET formation region. In the stress memorization technique (SMT) that stores strain in the channel region, the transistor region is covered with a stress application film, heat treatment is performed to store the strain in the channel region, and then the stress application film is removed. To do.

JP 2007-049092 A JP 2008-288606 A Japanese Patent Laid-Open No. 2003-068701 Japanese Patent Laid-Open No. 9-50968 JP 2007-134718 A

  By the way, depending on the pattern density on the semiconductor substrate, the etching time of the insulating film formed thereon may be partially increased or decreased.

  An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suppressing partial variations in etching end time of an insulating film covering a plurality of regions having different pattern densities.

According to one aspect of this embodiment, a first gate pattern and a second gate pattern are formed in a first region of a semiconductor substrate, and the first gate pattern and the second gate pattern are formed in a second region of the semiconductor substrate. Forming a third gate pattern and a fourth gate pattern that are adjacent to each other at a wider interval than the second gate pattern; the semiconductor substrate; the first gate pattern; the second gate pattern; A step of forming a first insulating film covering the third gate electrode and the fourth gate pattern; and covering a portion of the first insulating film on the first region and on the second region After the step of forming a first resist that exposes a portion, the step of implanting ions into the first insulating film using the first resist as a mask, and the step of performing ion implantation, the first resist Regis Removing the, after the step of removing the first resist, and a step of removing the first insulating film by etching, the first of the etching rate of the insulating film is the ion implantation the method of manufacturing a semiconductor device which is characterized that you drop by is provided.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention.

  According to the present embodiment, it is possible to suppress partial variations in the etching end time of the insulating film covering a plurality of regions having different pattern densities.

FIG. 1 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment. FIG. 8 is a diagram illustrating a difference in etching rate depending on presence / absence of ion implantation of elements into the insulating film in the manufacturing process of the semiconductor device according to the embodiment. FIG. 9 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment. FIG. 11 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment. FIG. 12 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment. FIG. 13 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment.

  Embodiments will be described below with reference to the drawings. In the drawings, similar components are given the same reference numerals.

(First embodiment)
1 to 7 are cross-sectional views illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

Next, steps required until a structure shown in FIG.
First, shallow trench isolation (STI) is formed as an element isolation insulating film 2 on a semiconductor substrate, for example, a silicon substrate 1, thereby partitioning an n-type MISFET formation region I and a p-type MISFET formation region II. The STI has a structure in which an insulating film is embedded in a groove formed in the upper part of the silicon substrate 1. Thereafter, p-type and n-type impurities are ion-implanted into the n-type MISFET formation region I and the p-type MISFET formation region II of the silicon substrate 1, thereby forming the P well 1p and the N well 1n. The ion implantation of p-type and n-type impurities is performed using a resist pattern.

  Subsequently, a gate insulating film 3, a polysilicon film 4, and a hard mask film 5 are sequentially formed on the silicon substrate 1. As the gate insulating film 3, silicon dioxide may be formed, or an insulating film having a higher dielectric constant may be formed. For example, a silicon nitride film is formed as the hard mask film 5.

  Thereafter, a resist pattern (not shown) having a gate electrode shape is formed on the hard mask film 5 above each of the P well 1p and the N well 1n. Thereafter, using the resist pattern as a mask, the hard mask film 5 to the gate insulating film 3 are etched. The polysilicon film 4 thus patterned is used as first to fourth gate patterns 4a to 4d having a gate electrode shape above the P well 1p. The simultaneously patterned polysilicon film 4 becomes the fifth to eighth gate patterns 4e to 4h having a gate electrode shape above the N well 1n. The first and second gate patterns 4a and 4b and the fifth and sixth gate patterns 4e and 4f are formed in different high-density regions IA and IIA with a small distance from each other. The gate patterns 4c and 4d and the seventh and eighth gate patterns 4g and 4h are formed in the low density regions IB and IIB, respectively. The interval between the gate patterns in the high density regions IA and IIA is narrower than the interval between the gate patterns in the low density regions IB and IIB.

  In the n-type MISFET formation region I, the distance between the second, third and fourth gate patterns 4b, 4c and 4d is formed wider than the distance between the first and second gate patterns 4a and 4b. ing. In the p-type MISFET formation region II, the distance between the sixth, seventh, and eighth gate patterns 4f, 4g, and 4h is larger than the distance between the fifth and sixth gate patterns 4e and 4f. Widely formed. Hard mask films 5a to 5h are stacked on the first to eighth gate patterns 4a to 4h, and gates are provided between the first to eighth gate patterns 4a to 4h and the silicon substrate 1, respectively. The insulating films 3a to 3h are sandwiched.

  Next, a silicon nitride film is formed on the silicon substrate 1 by a CVD method to cover the first to eighth gate patterns 4a to 4h. Thereafter, the silicon nitride film is etched back to leave the side surfaces of the first to eighth gate patterns 4a to 4h as shown in FIG. 1B and to use them as insulating offset spacers 6a to 6h. To do.

Next, steps required until a structure shown in FIG.
First, a silicon oxide film (not shown) is formed on the silicon substrate 1, and then the silicon oxide film in the n-type MISFET formation region I is covered with a resist pattern (not shown). Subsequently, the silicon oxide film exposed in the p-type MISFET formation region II is selectively removed by wet etching. Thereafter, the resist pattern is removed.

  Thereafter, the silicon oxide film (not shown) on the n-type MISFET formation region I, the fifth to eighth hard mask films 5e to 5h, and the offset spacers 6e to 6h are used as a mask, and the p-type MISFET formation region II is used. The exposed silicon substrate 1 is selectively etched. Thereby, grooves 1a to 1e are formed in regions on both sides of the fifth to eighth gate patterns 4e to 4h in the silicon substrate 1. Thereafter, first to fifth semiconductor layers 7a to 7e containing silicon germanium (SiGe) doped with boron (B) in the grooves 1a to 1e are selectively grown by a CVD method. The first to fifth semiconductor layers 7a to 7e are formed so as to protrude higher than the interface between the silicon substrate 1 and the gate insulating films 3e to 3h, and silicon below the fifth to eighth gate patterns 4e to 4h. A compressive strain is applied to the channel region of the substrate 1. Thereafter, the silicon oxide film (not shown) in the n-type MISFET formation region I is selectively removed by wet etching.

  Thereafter, using the hard mask films 5a to 5d and the offset spacers 6a to 6d as masks in the n-type MISFET formation region I, for example, arsenic or phosphorus is ionized as an n-type impurity in the silicon substrate 1 in the n-type MISFET formation region I. inject. Thus, n-type extension regions 8a to 8e are formed on both sides of the first to fourth gate patterns 4a to 4d in the P well 1p. Further, for example, boron is ion-implanted as a p-type impurity into the silicon substrate 1 in the p-type MISFET formation region II using the hard mask films 5e to 5h and the offset spacers 6e to 6h as masks in the p-type MISFET formation region II. Thus, p-type extension regions 10a to 10e are formed on both sides of the fifth to eighth gate patterns 4e to 4h in the N well 1n. The p-type impurity and the n-type impurity are separated by covering a region where ions are not implanted with a resist pattern (not shown). Thereby, the structure shown in FIG. 1C is formed.

  Next, a silicon nitride film is formed on the silicon substrate 1 by a CVD method to cover the first to eighth gate patterns 4 a to 4 h and the surface of the silicon substrate 1. Thereafter, the silicon nitride film is etched back so as to remain on the offset spacers 6a to 6h on the side surfaces of the first to eighth gate patterns 4a to 4h, and as shown in FIG. Used as sidewall spacers 12a to 12h.

  Thereafter, as shown in FIG. 2B, the silicon substrate 1, the side wall spacers 12 e to 12 h in the p-type MISFET formation region II are covered with a resist pattern 16. Subsequently, using the hard mask films 5a to 5d and the side wall spacers 12a to 12d as masks in the n-type MISFET formation region I, n-type impurities such as arsenic are ionized in the silicon substrate 1 in the n-type MISFET formation region I. inject. Thus, n-type source / drain regions 9a to 9e are formed on both sides of the first to fourth gate patterns 4a to 4d in the P well 1p. The first to fifth semiconductor layers 7a to 7e are used as p-type source / drain regions 11a to 11e.

  Next, as shown in FIG. 2C, a laminated structure is formed on the surface of the silicon substrate 1, the first to fifth semiconductor layers 7a to 7e, the sidewall spacers 12a to 12h, and the hard mask films 5a to 5h. As the SMT insulating film, a silicon oxide film 14 and a silicon nitride film 15 are formed by a CVD method. In this case, the silicon nitride film 15 is formed under a condition that causes tensile strain in the channel region below the first to fourth gate patterns 4a to 4d, and the thickness thereof is, for example, above the hard mask films 5a to 5h. The thickness is about several nm to several tens of nm, for example, about 30 nm. The silicon oxide film 14 is formed thinner than the silicon nitride film 15 so as not to attenuate the strain applied from the silicon nitride film 15 to the silicon substrate 1. The film thickness distribution of the silicon nitride film 15 is not uniform. For example, a silicon nitride film 15 is embedded in a narrow region between the first and second gate patterns 4a and 4b and a narrow region between the fifth and sixth gate patterns 4e and 4f. It is formed thicker than a wide region such as between the fourth gate patterns 4c and 4d and between the seventh and eighth gate patterns 4g and 4h.

  Next, as shown in FIG. 3A, impurities in n-type extension regions 8a to 8e, n-type source / drain regions 9a to 9e, p-type extension regions 10a to 10e, and p-type source / drain regions 11a to 11e. In order to activate the silicon substrate 1, activation annealing (heat treatment) is applied to the silicon substrate 1. As the activation annealing, for example, spike rapid annealing (RTA) or millisec annealing at 1000 ° C. or higher is employed. According to this annealing, the silicon nitride film 15 is heated and contracted simultaneously with the activation of impurities, and the stress of the silicon nitride film 15 is transferred to the n-type source / drain regions 9a to 9e in the n-type MISFET formation region I. The Thus, tensile strain is applied to the channel region below the first to fourth gate patterns 4a to 4d in the silicon substrate 1. In the p-type MISFET formation region II, since the surface of the p-type source / drain regions 11a to 11e is higher than the surface of the channel region, the application of tensile stress to the channel region is suppressed, and the first to fifth The p-type source / drain regions 11a to 11e made of the semiconductor layers 7a to 7e apply compressive strain to the channel regions below the fifth to eighth gate patterns 4e to 4h.

  Thereafter, the silicon nitride film 15 is removed. The silicon nitride film 15 annealed at a high temperature has a lower etching rate than the case where it is not annealed, and the silicon nitride film 15 formed by the CVD method is between the first and second gate patterns 4a and 4b. In such a narrow region, it is formed thicker than the region between the third and fourth gate patterns 4c and 4d, which are widely spaced. Therefore, if the entire silicon nitride film 15 is etched as it is after the annealing, the etching is completed earlier in the thin region of the silicon nitride film 15 than in the thick region, so that the thin silicon oxide film 14 thereunder is also excessive. It will be etched away. This is because the etchant of silicon nitride has a property of etching silicon oxide even though the etching rate for silicon oxide is smaller than the etching rate for silicon nitride. As a countermeasure against this, it is conceivable to form the silicon oxide film 14 thick, but the stress applied to the silicon substrate 1 from the silicon nitride film 15 is weakened by the thick silicon oxide film 14. Therefore, the silicon nitride film 15 is removed by the following method.

  First, a photoresist is applied on the silicon nitride film 15, and this is exposed, developed, etc., thereby forming a resist pattern 17 as shown in FIG. The resist pattern 17 is formed on the first and second gate patterns 4a and 4b and the region therebetween, and on the fifth and sixth gate patterns 4e and 4f and the region therebetween. It has a covering shape. In this case, the silicon nitride film 15 between the first and second gate patterns 4a and 4b, and between the gate patterns having a narrow interval such as the region between the fifth and sixth gate patterns 4e and 4f. It is good also as the shape of the resist pattern 17 which covers only.

Subsequently, using the resist pattern 17 as a mask, an etching rate adjusting impurity such as carbon is ion-implanted into the silicon nitride film 15. Carbon ion implantation conditions are set such that carbon is not substantially implanted into the underlying silicon oxide film 14 and silicon substrate 1. In this case, the acceleration energy and dose amount of the ion implantation are adjusted by the thickness of the silicon nitride film 15, for example, the center of the thickness of the silicon nitride film 15 on the n-type source / drain regions 9a to 9e or higher. It is adjusted so that a concentration peak exists at the position of. For example, when the thickness is about 30 nm, the acceleration energy is set to 1 to 5 keV, and the dose is set to 1 × 10 ¹⁴ cm ⁻² or more. Next, the resist pattern 17 is removed.

  Thereafter, the silicon nitride film 15 is removed by wet etching. For example, phosphoric acid is used as an etching solution. In this case, the etching rate of the silicon nitride film 15 annealed at a high temperature is lower than that in a state where it is not annealed. Further, comparing the state in which carbon is ion-implanted into the silicon nitride film 15 and the state in which carbon is not ion-implanted, as illustrated in FIG. I understand that. As a result, the etching end time in a narrow region between the first and second gate patterns 4a and 4b and between the fifth and sixth gate patterns 4e and 4f, and the second, third, and second patterns are reduced. Variation in etching end time in a wide region between the four gate patterns 4b, 4c, and 4d and between the sixth, seventh, and eighth gate patterns 4f, 4g, and 4h can be suppressed. .

  Therefore, as shown in FIG. 4A, in the n-type and p-type MISFET formation regions I and II, the silicon oxide on the side wall spacers 12a to 12h with the silicon nitride film 15 substantially removed. The film 14 will remain. In other words, the above carbon ion implantation conditions are adjusted so that the silicon oxide film 14 below the silicon nitride film 15 remains as much as possible. This is because when the etching proceeds to the silicon oxide film 14 and the side wall spacers 12a to 12h therebelow, the distances between the n-type and p-type source / drain regions 9a to 9e, 11a to 11e and the gate patterns 4a to 4h. This is because the current is shrunk and a leak current is generated between the silicide layers 19a to 19j formed in the subsequent process. Further, by positioning the concentration peak in the silicon nitride film 15 of the ion-implanted carbon as described above at the center or above it, the bottom of the silicon nitride film 15 can be easily etched, and the silicon nitride film 15 Etching residue is less likely to occur. Thereafter, as shown in FIG. 4B, the silicon oxide film 14 is removed by wet etching. In this case, for example, hydrofluoric acid is used as the etching solution.

  Next, a process for forming the structure shown in FIG. First, a metal film (not shown) such as a nickel film is formed on the n-type source / drain regions 9a to 9d, the p-type source / drain regions 11a to 11e, and the sidewall spacers 12a to 12h. Thereafter, silicide layers 19a to 19j are formed on the surfaces of the n-type source / drain regions 9a to 9e and the p-type source / drain regions 11a to 11e by annealing. Thereafter, the metal film is removed.

  Subsequently, as shown in FIG. 5B, a contact etch stop (CESL) layer 20 is formed thinly on the silicon substrate 1, thereby forming n-type and p-type source / drain regions 9 a to 9 e and 11 a to 11 e. Etc. As the CESL layer 20, for example, a silicon nitride film that applies tensile strain to the channel region between the n-type source / drain regions 9 a to 9 e is formed. Even if a silicon nitride film which gives such strain is formed on the semiconductor layers 7a to 7e containing SiGe which are the p-type source / drain regions 11a to 11e, the film thickness is small. The compressive strain applied to the channel region between them by 7e is hardly reduced. Thereafter, for example, a silicon oxide film, an impurity-doped silicon oxide film, or the like is formed on the CESL layer 20 as the first interlayer insulating film 21.

  Next, as shown in FIG. 6A, the upper surface of the first interlayer insulating film 21 is planarized by a chemical mechanical polishing (CMP) method, and further polished until the hard mask films 5a to 5h are removed. The top surfaces of the first to eighth gate patterns 4a to 4h are exposed.

  Subsequently, as shown in FIG. 6B, after a silicon nitride film, for example, is formed as the hard mask 22 on the first interlayer insulating film 21, the first to eighth gate patterns 4a to 4h, etc. This is patterned to be removed from the n-type MISFET formation region I and to remain in the p-type MISFET formation region II. Further, the first to fourth gate patterns 4a to 4d are selectively removed to form electrode spaces 23a to 23d.

Thereafter, a metal film for a gate electrode is formed in the electrode spaces 23a to 23d. Thereafter, the metal film and the hard mask film 22 on the first interlayer insulating film 21 are removed by a CMP method. Thereby, as shown in FIG. 6C, the metal film left in the electrode spaces 23a to 23d is used as the first to fourth n-side gate electrodes 24a to 24d. By this. The first to fourth n-type MISFETs (n-type MIS transistors) t _{n1 to} t _n4 are constituted by the first to fourth n-side gate electrodes 24a to 24d and the n-type source / drain regions 9a to 9e on both sides. A basic structure is formed. Note that adjacent transistors among the first to fourth n-type MISFETs t _{n1 to} t _n4 share the n-type source / drain regions 9a to 9e.

Subsequently, by the same method, as shown in FIG. 7A, the fifth to eighth gate patterns 4e to 4h in the p-type MISFET formation region II are removed to form recesses, and these recesses are formed. A metal is embedded in the first to fourth p-side gate electrodes 25a to 25d. By this. First to fourth p-type MISFET by p-type source / drain regions 11a~11e like on both sides of the first to fourth p-side gate electrode 25a~25d and each (p-type MIS _{transistor) t} p1 _{~t p4} is It is formed. Note that adjacent transistors among the first to fourth p-type MISFETs t _{p1 to} t _p4 share the p-type source / drain regions 11a to 11e.

Next, steps required until a structure shown in FIG.
First, the second interlayer insulating film 28 is formed by CVD on the first interlayer insulating film 21, the n-side gate electrodes 24a to 24d, the p-side gate electrodes 25a to 25d, and then the second interlayer insulating film 28 is formed. The upper surface is planarized by the CMP method. The second interlayer insulating film 28 is formed from the same material as the first interlayer insulating film 21.

Thereafter, the second interlayer insulating film 28 and the first interlayer insulating film 21 are patterned. As a result, the gate electrodes 24a and 24d of the first and fourth n-type MISFETs t _n1 and t _n4 and the silicide layers 19a, 19b, 19d and 19e on the surfaces of the n-type source / drain regions 9a, 9b, 9d and 9e are formed. A contact hole is formed. At the same time, first, the gate electrode 25a of the fourth p-type MISFETt _{p1, t p4,} 25d and p-type source / drain regions 11a, 11b, 11d, 11e surfaces of the silicide layer 19f, 19 g, 19i, contacts on the 19j A hole is formed. Further, conductive plugs 29a to 29l are formed by embedding a conductive material in the contact holes, and the gate electrodes 24a, 24d, 25a, 25d and the silicide layers 19a, 19b, 19d, 19e, 19f, 19g, 19i, 19j Connect to. The conductive material for the conductive plugs 29a to 29j formed on the second interlayer insulating film 28 is removed by CMP. Thereafter, a multilayer wiring structure is formed on the second interlayer insulating film 28 to form a semiconductor device.

  According to the above process, the thickness distribution of the silicon nitride film 15 formed on and between the plurality of gate patterns 4a to 4h and the sidewall spacers 12a to 12h is between the gate patterns 4a to 4h. In the case of non-uniformity due to the difference in the area of carbon, carbon is ion-implanted into a thin part. Since the etching rate of the silicon nitride film 15 changes so as to be reduced by carbon ion implantation, the time difference at the end of etching due to the difference in film thickness can be reduced or substantially eliminated. As a result, it is possible to prevent the film under the silicon nitride film 15 from being etched away by the etchant of the silicon nitride film 15 or to prevent deterioration.

  By the way, in the above description, carbon is ion-implanted into the thinly formed portion of the silicon nitride film 15 to reduce the etching rate. However, the ion implantation element is not limited to carbon. For example, Boron may be employed. However, if an element is implanted into the silicon nitride film 15 which is an insulating film, the etching rate is not necessarily slowed down. For example, as shown by the alternate long and short dash line in FIG. 8, when the nitrogen content of the silicon nitride film is increased, the etching rate increases as opposed to the case of carbon. Therefore, nitrogen may be ion-implanted into a thick region, but the difference in etching rate depending on whether or not ion implantation is performed is small.

(Second Embodiment)
9 to 13 are cross-sectional views illustrating manufacturing steps of the semiconductor device according to the second embodiment of the present invention. 9 to 13, the same reference numerals as those in FIGS. 1 to 7 denote the same elements.

Next, steps required until a structure shown in FIG.
First, similarly to the first embodiment, on the n-type MISFET formation region I and the p-type MISFET formation region II defined by the element isolation insulating film 2 in the silicon substrate 1, the gate insulating films 3a to 3h are interposed. First to eighth gate patterns 4a to 4h are formed. In this case, hard mask films 5a to 5h are stacked on each of the first to eighth gate patterns 4a to 4h, as in the first embodiment, and insulating offset spacers are formed on the side walls thereof. 6a-6h are formed.

  Subsequently, with the n-type MISFET formation region I of the silicon substrate 1 covered with a resist pattern (not shown), p-type impurities are ion-implanted into the p-type MISFET formation region II to form p-type extension regions 10a to 10e. . Thereafter, activation annealing is performed on the p-type extension regions 10a to 10e. Thereafter, the resist pattern (not shown) is removed.

  Subsequently, as shown in FIG. 9B, n-type impurities are ion-implanted into the n-type MISFET formation region I in a state where the p-type MISFET formation region II of the silicon substrate 1 is covered with the resist pattern 41. Regions 8a to 8e are formed. Thereafter, the resist pattern 41 is removed.

Next, a process for forming the structure shown in FIG.
First, sidewall spacers 12a to 12h are formed on the sides of the first to eighth gate patterns 4a to 4h on the silicon substrate 1 by the same method as in the first embodiment. Thereafter, n-type impurities are ion-implanted into the n-type MISFET formation region I with the p-type MISFET formation region II of the silicon substrate 1 covered with the resist pattern 42 to form n-type source / drain regions 9a to 9e. Thereafter, the resist pattern 42 is removed.

  Subsequently, as shown in FIG. 10A, the silicon oxide film 14 and the silicon nitride are formed on the silicon substrate 1 and the side wall spacers 12a to 12h as a stacked structure of the SMT insulating film as in the first embodiment. The film 15 is formed by the CVD method. In this case, the silicon nitride film 15 is formed under a condition that causes tensile strain in the channel region below the first to fourth gate patterns 4a to 4d in the silicon substrate 1, and the thickness thereof is, for example, a hard mask film The thickness is set to about several nm to several tens of nm, for example, about 30 nm on 5a to 5h. Further, the silicon oxide film 14 is formed thinner than the silicon nitride film 15 as in the first embodiment.

  Next, a photoresist 43 is applied on the silicon nitride film 15 and exposed and developed to leave it in the n-type MISFET formation region I and remove it from the p-type MISFET formation region II. Thereafter, as shown in FIG. 10B, the silicon nitride film 15 and the silicon oxide film 14 in the p-type MISFET formation region II are removed by etching using the photoresist 43 as a mask. Thereafter, the photoresist 43 is removed.

  Subsequently, as shown in FIG. 11A, the silicon nitride film 15 in the n-type MISFET formation region I, the hard mask films 5e to 5h in the p-type MISFET formation region II, and the side wall spacers 12e to 12h are used as masks. . Then, as in the first embodiment, the concave portions are formed by etching the portions of the silicon substrate 1 not covered with the hard mask films 5e to 5h and the side wall spacers 12e to 12h. After that, as in the first embodiment, semiconductor layers 7a to 7e containing SiGe doped with boron are formed in the recesses. Semiconductor layers 7a-7e are used as p-type source / drain regions 11a-11e.

  Next, as shown in FIG. 11B, in order to activate the impurities in the n-type extension regions 8a to 8e and the n-type source / drain regions 9a to 9e, the temperature is about 1000 ° C. as in the first embodiment. Annealing is performed. According to this annealing, strain of the silicon nitride film 15 in the n-type MISFET formation region I is applied to the underlying silicon substrate 1 to give tensile strain, and this state is maintained. Since the p-type MISFET formation region II is not covered with the silicon nitride film 15, no tensile strain is applied to the channel region. Further, the etching rate of the annealed silicon nitride film 15 is lower than that in the previous state. Therefore, as shown in FIG. 12A, a photoresist 45 is applied on the silicon substrate 1, and this is exposed and developed. As a result, in the n-type MISFET formation region I, the region between the narrow first and second gate patterns 4a and 4b and the regions on the hard mask films 5a and 5b on both sides thereof are covered with the photoresist 45. At the same time, the silicon substrate 1 and the side wall spacers 12e to 12h in the p-type MISFET formation region II are covered with the photoresist 45. A portion exposed from the photoresist 45 is a thin region of the silicon nitride film 15.

  Subsequently, for example, carbon or boron is ion-implanted as an etching rate adjusting element into the portion of the silicon nitride film 15 in the n-type MISFET formation region I exposed from the photoresist 45. For example, the carbon ion implantation conditions are set in the same manner as in the first embodiment. Thereafter, as shown in FIG. 12B, the photoresist 45 is removed.

Next, a silicon oxide film 18 is formed on the silicon substrate 1, and then the silicon oxide film 18 in the p-type MISFET formation region II is covered with a resist pattern (not shown). Subsequently, after the silicon oxide film 18 exposed in the n-type MISFET formation region I is selectively removed by wet etching, the resist pattern is removed. As a result, as shown in FIG. 13A, the silicon oxide film 18 is left on the p-type MISFET formation region II. The thickness of the silicon oxide film 18 is formed to be thicker than the thickness of the silicon oxide film 14 in the n-type MISFET formation region I.

  Next, as shown in FIG. 13B, the silicon nitride film 15 in the n-type MISFET formation region I is removed by wet etching. In this case, phosphoric acid is used as an etching solution. In this case, as in the first embodiment, the etching rate is slower in the ion implanted region of the silicon nitride film 15 than in the non-implanted region. Therefore, the partial excessive etching time of the silicon nitride film 15 due to the difference in film thickness is shortened, and the silicon oxide film 14 on the sidewall spacers 12a to 12d is almost left. On the other hand, the silicon oxide film 18 in the p-type MISFET formation region II remains in the p-type MISFET formation region II because the etching rate is slower than that of the silicon nitride film 15.

  Thereby, the thinning of the sidewall spacers 12a to 12h under the silicon oxide films 14 and 18 is suppressed, and the n-type and p-type source / drain regions 9a to 9e and 11a to 11e and the gate patterns 4a to 4h are formed. The distance between each other can be prevented from being reduced, and leakage current between silicide layers formed later can be prevented. In this case, it is possible to protect the sidewall spacers 12a to 12d by forming the silicon oxide film 14 thick, but the application of strain from the silicon nitride film 15 to the silicon substrate 1 is weakened to deteriorate the transistor characteristics.

  Subsequently, as shown in FIG. 13C, after the silicon oxide films 14 and 18 are removed in the same manner as in the first embodiment, the n-type source / drain regions 9a to 9e are formed by the same method as in the first embodiment. , Silicide layers 19a to 19j are formed on the surface layers of the p-type source / drain regions 11a to 11e, respectively.

  Thereafter, as shown in FIGS. 5B, 6 and 7 of the first embodiment, the first interlayer insulating film 21 is formed, and the first to fourth gate patterns 4a to 4d are made of metal. Instead of the film, first to fourth n-side gate electrodes 24a to 24d are formed. Further, the fifth to eighth gate patterns 4e to 4h are changed to metal films to form fifth to eighth p-type gate electrodes 25a to 25d. Further, the semiconductor device is completed through a process of forming a multilayer wiring structure such as forming the second interlayer insulating film 28 and further forming the conductive plugs 29a to 29l.

  In the process as described above, carbon is ion-implanted into an insulating film that adds strain to the n-type MISFET formation region I of the silicon substrate 1 by annealing, that is, a thinly formed region of the silicon nitride film 15. Therefore, as in the first embodiment, in the silicon nitride film 15, since the etching rate of the ion implanted portion is smaller than the etching rate of the non-implanted portion, the difference at the end of etching is reduced even if there is a difference in film thickness. Can be done or lost. For this reason, the etching of the silicon oxide film 14 formed under the silicon nitride film 15 is suppressed, and further, the lower sidewall spacers 12a to 12d are prevented from being thinned. This prevents the distance between the n-side gate electrodes 24a to 24d and the n-type source / drain regions 9a to 9e from being reduced.

  Since the p-type MISFET formation region II in the silicon nitride film 15 is removed before annealing, the entire etching rate is high even if there is a difference in film thickness distribution. Etching is suppressed. However, depending on the thickness of the silicon oxide film 14, the silicon oxide film 14 may be etched by an etchant for silicon nitride. In this case, carbon is used under the same conditions as in the first embodiment except for the portion of the silicon nitride film 15 embedded in the thick region between the fifth and sixth gate patterns 4e and 4f. Ion implantation may be performed.

  In the above description, carbon is ion-implanted into a partial region of the same silicon nitride film 15 to slow the etching rate. However, the ion implantation element is not limited to carbon. For example, boron may be employed as in the embodiment.

  In the first and second embodiments, after forming the gate patterns 4a to 4h and the sidewall spacers 12a to 12h on the silicon substrate 1, the gate patterns 4a to 4h are selectively removed to form the recesses. After that, a metal is buried in the recess, and the gate electrodes 24a to 24d and 25a to 25d are formed by the metal film. However, without using such a replacement gate process, the gate patterns 4a to 4h made of a polysilicon film may be used as they are as the gate electrodes. In this case, the formation of the hard mask films 5a to 5h on the gate patterns 4a to 4h is omitted, and a silicide layer is formed on the gate electrode. In the case of using the replacement gate process, a material that can be selectively etched with respect to the sidewall spacers 12a to 12h may be used as the gate pattern in addition to the polysilicon film. Further, ion implantation of carbon or the like into the silicon nitride film 15 which is an insulating film may be performed before annealing (heat treatment).

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, features of the embodiment of the present invention will be described.
(Supplementary Note 1) A first gate pattern and a second gate pattern are formed in a first region of a semiconductor substrate, and an interval between the first gate pattern and the second gate pattern is formed in a second region of the semiconductor substrate. Forming a third gate pattern and a fourth gate pattern adjacent to each other at a wider interval, the semiconductor substrate, the first gate pattern, the second gate pattern, the third gate electrode, and the A step of forming a first insulating film covering the fourth gate pattern; and a first portion of the first insulating film that covers a portion on the first region and exposes a portion on the second region. A step of forming a resist, a step of implanting ions into the first insulating film using the first resist as a mask, a step of removing the first resist after the step of performing ion implantation, Previous The method of manufacturing a semiconductor device, characterized in that it comprises after the step of removing the first resist and removing by etching said first insulating film.
(Supplementary Note 2) Before the step of forming the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern, the first region of the semiconductor substrate and The method of manufacturing a semiconductor device according to appendix 1, further comprising a step of implanting p-type ions into the second region.
(Supplementary Note 3) A step of implanting p-type ions into the first region and the second region of the semiconductor substrate, a step of implanting n-type ions into the third region and the fourth region of the semiconductor substrate, After the step of implanting p-type ions, a first gate pattern and a second gate pattern are formed in the first region, and the first gate pattern and the second gate pattern are formed in the second region. The fifth gate pattern and the sixth gate pattern are formed in the third region after the step of forming the third gate pattern and the fourth gate pattern that are adjacent to each other at a wider interval than the step of the step, and the step of implanting the n-type ions. Forming a gate pattern and forming, in the fourth region, a seventh gate pattern and an eighth gate pattern adjacent to each other at a wider interval than the fifth gate pattern and the sixth gate pattern; The first Using the 5 gate pattern, the 6th gate pattern, the 7th gate pattern, and the 8th gate pattern as a mask, the semiconductor substrate in the third region and the fourth region is etched to form grooves. Forming a semiconductor layer containing silicon and germanium in the trench, the semiconductor substrate, the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate use. Forming a pattern, the fifth gate pattern, the sixth gate pattern, the seventh gate pattern, the eighth gate pattern, and a first insulating film covering the semiconductor layer; The insulating film of 1 covers a portion on the first region and a portion on the third region, and a portion on the second region and a portion on the fourth region are exposed. A step of forming a first resist, a step of implanting ions into the first insulating film using the first resist as a mask, a step of removing the first resist, and the first resist And a step of removing the first insulating film by etching after the step of removing the semiconductor device.
(Supplementary Note 4) A step of implanting p-type ions into the first region and the second region of the semiconductor substrate, a step of implanting n-type ions into the third region of the semiconductor substrate, and the p-type ions. After the implantation step, a first gate pattern and a second gate pattern are formed in the first region, and an interval wider than an interval between the first gate pattern and the second gate pattern is formed in the second region. Forming a third gate pattern and a fourth gate pattern adjacent to each other, a step of forming a fifth gate pattern in the third region after the step of implanting the n-type ions, and the semiconductor Forming a first insulating film covering the substrate, the first gate pattern, the second gate pattern, the third gate pattern, the fourth gate pattern, and the fifth gate pattern; , Of the first insulating film, a step of forming a first resist covering the first region and the second region and opening the third region; and using the first resist as a mask, Etching the semiconductor substrate and etching the semiconductor substrate using the first insulating film and the fifth gate pattern as a mask. Forming a semiconductor layer containing silicon and germanium in the groove, and embedding the semiconductor layer, covering the first region and the third region, and opening the second region. Forming a second resist for exposing the first insulating film; performing ion implantation on the first insulating film using the second resist as a mask; and removing the second resist. Craft If, after said step of removing the second resist, a method of manufacturing a semiconductor device characterized by and a step of removing the first insulating film by etching.
(Supplementary Note 5) After the step of removing the second resist and before the step of removing the first insulating film by etching, the first insulating film, the semiconductor layer, and the fifth gate Forming a fourth insulating film covering the pattern with a material different from that of the first insulating film; covering a portion of the fourth insulating film on the third region; over the first region; Forming a third resist that exposes a portion on the second region; etching and removing the fourth insulating film using the third resist as a mask; and The method for manufacturing a semiconductor device according to appendix 4, further comprising a step of removing.
(Supplementary Note 6) Before forming the fifth gate pattern, the semiconductor substrate further includes a step of forming a gate insulating film on the semiconductor substrate, and the height of the surface of the semiconductor layer is determined between the semiconductor substrate and the gate insulating film The method for manufacturing a semiconductor device according to any one of appendix 3 to appendix 5, wherein the semiconductor layer is embedded so as to be higher than a height of the interface.
(Supplementary note 7) The method of manufacturing a semiconductor device according to any one of supplementary notes 1 to 6, further comprising a step of performing a first heat treatment on the first insulating film and the semiconductor substrate.
(Supplementary note 8) The method for manufacturing a semiconductor device according to supplementary note 7, wherein the first insulating film contracts by performing the first heat treatment.
(Supplementary Note 9) Before the step of forming the first insulating film, the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern are used as a mask. The method of manufacturing a semiconductor device according to any one of appendices 1 to 8, further comprising a step of implanting n-type ions into the first region and the second region of the semiconductor substrate.
(Appendix 10) Before the step of forming the first insulating film, the sidewalls of the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern are formed. The method for manufacturing a semiconductor device according to any one of appendices 1 to 9, further comprising a step of forming a sidewall spacer.
(Appendix 11) Before the step of forming the first insulating film, the semiconductor substrate, the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern 11. The method of manufacturing a semiconductor device according to any one of appendices 1 to 10, further comprising a step of forming a second insulating film covering the pattern with a material different from that of the first insulating film.
(Supplementary Note 12) After the step of removing the first insulating film, a step of forming a silicide layer on the semiconductor substrate, a step of forming a third insulating film covering the silicide layer, and the third insulation The method of manufacturing a semiconductor device according to any one of appendices 1 to 11, further comprising a step of forming a conductive plug in contact with the silicide layer in the film.
(Supplementary Note 13) Third insulation covering the semiconductor substrate, the first gate pattern, the second gate pattern, the third gate pattern, the fourth gate pattern, and the sidewall spacer Forming a film; and polishing the third insulating film to expose the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern. After the first polishing step and the first polishing step, the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern are removed to remove the first gate pattern. Forming the electrode space, the second electrode space, the third electrode space, and the fourth electrode space, the first electrode space, the second electrode space, the third electrode space, and Fourth electric Forming a metal film covering the space and the third insulating film; polishing the metal film to expose the third insulating film; and the first electrode space and the second electrode space The metal remaining in the third electrode space and the fourth electrode space is applied to the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode. The method for manufacturing a semiconductor device according to any one of appendices 1 to 12, further comprising: 2 polishing steps.
(Supplementary note 14) The first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern are gate electrodes formed of a silicon film. A method for manufacturing a semiconductor device according to any one of 1 to 13.
(Supplementary note 15) The method of manufacturing a semiconductor device according to any one of supplementary notes 1 to 14, wherein the first insulating film is a silicon nitride film.
(Additional remark 16) The said ion implantation to a said 1st insulating film implants carbon ion or boron ion, The manufacturing method of the semiconductor device as described in any one of additional remark 1 thru | or 15 characterized by the above-mentioned.
(Supplementary Note 17) The concentration peak of the element implanted by the ion implantation into the first insulating film is located in the center of the thickness of the first insulating film or above the center in the second region. 18. A method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 16, wherein:

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1n N well 1p P well 1a-1e Groove 2 Element isolation insulating films 3a-3h Gate insulating films 4a-4h Gate patterns 5a-5h Hard mask films 6a-6h Offset spacers 7a-7e Semiconductor layers 8a-8en Type extension regions 9a to 9e n type source / drain regions 10a to 10e p type extension regions 11a to 11e n type source / drain regions 12a to 12h side wall spacer 14 silicon oxide film 15 underground silicon film 16, 17 resist pattern 18 silicon oxide Films 19a to 19j Silicide layer 20 Silicon nitride film 21 First interlayer insulating film 22 Hard masks 23a to 23d Electrode spaces 24a to 24d Gate electrodes 25a to 35d Gate electrode 28 Second interlayer insulating films 29a to 29l Conductive plugs 41, 43, 45 resist pattern

Claims (9)

A first gate pattern and a second gate pattern are formed in the first region of the semiconductor substrate, and the second region of the semiconductor substrate is spaced at a wider interval than the interval between the first gate pattern and the second gate pattern. Forming adjacent third gate pattern and fourth gate pattern;
Forming a first insulating film covering the semiconductor substrate, the first gate pattern, the second gate pattern, the third gate electrode, and the fourth gate pattern;
Forming a first resist that covers a portion of the first insulating film on the first region and exposes a portion of the second region;
Performing ion implantation into the first insulating film using the first resist as a mask;
Removing the first resist after the ion implantation step;
After the step of removing the first resist, the step of removing the first insulating film by etching ,
The method of manufacturing a semiconductor device wherein an etching rate of the first insulating film, wherein that you drop by the ion implantation. Implanting p-type ions into the first region and the second region of the semiconductor substrate;
Implanting n-type ions into the third region and the fourth region of the semiconductor substrate;
After the step of implanting the p-type ions, a first gate pattern and a second gate pattern are formed in the first region, and the first gate pattern and the second gate pattern are formed in the second region. Forming a third gate pattern and a fourth gate pattern that are adjacent to each other at a wider interval than the pattern interval;
After the n-type ion implantation step, a fifth gate pattern and a sixth gate pattern are formed in the third region, and the fifth gate pattern and the sixth gate pattern are formed in the fourth region. Forming a seventh gate pattern and an eighth gate pattern adjacent to each other at an interval wider than the pattern interval;
Etching the semiconductor substrate in the third region and the fourth region using the fifth gate pattern, the sixth gate pattern, the seventh gate pattern, and the eighth gate pattern as a mask. Forming a groove;
Burying a semiconductor layer containing silicon and germanium in the groove;
The semiconductor substrate, the first gate pattern, the second gate pattern, the third gate pattern, the fourth gate pattern, the fifth gate pattern, the sixth gate pattern, and the seventh gate. Forming a first insulating film that covers the semiconductor layer, and the pattern for the eighth gate, the pattern for the eighth gate, and
Of the first insulating film, a first resist that covers a portion on the first region and a portion on the third region, and exposes a portion on the second region and a portion on the fourth region. Forming, and
Performing ion implantation into the first insulating film using the first resist as a mask;
Removing the first resist;
After the step of removing the first resist, the step of removing the first insulating film by etching ,
The method of manufacturing a semiconductor device wherein an etching rate of the first insulating film, wherein that you drop by the ion implantation. Implanting p-type ions into the first region and the second region of the semiconductor substrate;
Implanting n-type ions into the third region of the semiconductor substrate;
After the step of implanting the p-type ions, a first gate pattern and a second gate pattern are formed in the first region, and the first gate pattern and the second gate pattern are formed in the second region. Forming a third gate pattern and a fourth gate pattern that are adjacent to each other at a wider interval than the pattern interval;
A step of forming a fifth gate pattern in the third region after the step of implanting the n-type ions;
Forming a first insulating film covering the semiconductor substrate, the first gate pattern, the second gate pattern, the third gate pattern, the fourth gate pattern, and the fifth gate pattern; Process ,
Forming a first resist covering the first region and the second region of the first insulating film and opening the third region;
Etching and removing the first insulating film using the first resist as a mask;
Removing the first resist;
Etching the semiconductor substrate using the first insulating film and the fifth gate pattern as a mask to form a groove;
Burying a semiconductor layer containing silicon and germanium in the groove;
After the step of embedding the semiconductor layer, forming a second resist that covers the first region and the third region, opens the second region, and exposes the first insulating film;
Using the second resist as a mask, implanting ions into the first insulating film;
Removing the second resist;
A step of removing the first insulating film by etching after the step of removing the second resist ,
The method of manufacturing a semiconductor device wherein an etching rate of the first insulating film, wherein that you drop by the ion implantation.   4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a first heat treatment on the first insulating film and the semiconductor substrate. 5.   Before the step of forming the first insulating film, sidewall spacers are formed on sidewalls of the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming the semiconductor device.   Before the step of forming the first insulating film, the semiconductor substrate, the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern are covered. 6. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming the second insulating film with a material different from that of the first insulating film. A third insulating film is formed to cover the semiconductor substrate, the first gate pattern, the second gate pattern, the third gate pattern, the fourth gate pattern, and the sidewall spacer. Process,
A first polishing step of polishing the third insulating film to expose the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern;
After the first polishing step, the first gate pattern, the second gate pattern, the third gate pattern, and the fourth gate pattern are removed to remove the first electrode space, the second Forming the electrode space, the third electrode space, and the fourth electrode space;
The first electrode space and the second electrode space, said third electrode space, and the fourth electrode space, and a step of forming a metal film covering the third insulating film,
To expose the third insulating film by polishing the metal film, the first electrode space and the second electrode space, said third electrode space, and left in the fourth electrode space A second polishing step of applying the metal to the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode;
The method of manufacturing a semiconductor device according to claim 1, further comprising:   8. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation into the first insulating film is performed by implanting carbon ions or boron ions. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is silicon nitride.

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