JP5958317B2 - Overcurrent detection device and semiconductor drive device including the same - Google Patents

Description

  The present invention relates to an overcurrent detection device that detects an overcurrent flowing through a switching element such as an IGBT and a semiconductor drive device including the same.

  For example, Patent Document 1 discloses a technique for preventing an overcurrent from being erroneously detected due to a sense current temporarily jumping up when an IGBT is turned on or off. In the technique disclosed in Patent Document 1, erroneous detection of overcurrent is prevented by bypassing the sense current input to the overcurrent detection circuit to prevent input to the overcurrent detection circuit.

Japanese Patent Laid-Open No. 5-276761

  However, in the above-described prior art, the time for diverting the current input to the overcurrent detection circuit is determined in advance, and therefore the time for diverting may be too long or too short depending on the external environment such as temperature. There is. Therefore, the current input to the overcurrent detection circuit may not be controlled in an appropriate period.

An object of the present invention is to provide an overcurrent detection device and a semiconductor drive device including the same that can control the current input to the overcurrent detection unit only during a transition period until the turn-on or turn-off of the switching element is determined. .

In order to achieve the above object, the present invention provides:
An overcurrent detector connected to the sense terminal of the switching element;
An overcurrent detection device that detects an overcurrent flowing through the switching element when an input voltage that changes according to an input current input to the overcurrent detection unit is greater than a threshold voltage ,
A gate current detector for detecting a gate current of the switching element;
A control unit that controls the input current during a period in which the gate current is detected by the gate current detection unit so that the input voltage does not exceed the threshold voltage ;
The control unit adjusts the amount of decrease in the input voltage by controlling the magnitude of the input current according to the magnitude of the gate current, and has an overcurrent detection device and the same A semiconductor drive device is provided.
In order to achieve the above object, the present invention provides:
An overcurrent detector connected to the sense terminal of the switching element;
When the input voltage that changes according to the input current supplied from the sense terminal and input to the overcurrent detection unit is larger than the threshold voltage that changes according to the threshold correction current input to the overcurrent detection unit , An overcurrent detection device for detecting an overcurrent flowing through the switching element,
A gate current detector for detecting a gate current of the switching element;
A control unit that controls the threshold correction current during a period in which the gate current is detected by the gate current detection unit so that the input voltage does not exceed the threshold voltage;
The control unit adjusts the amount of increase in the threshold voltage by controlling the magnitude of the threshold correction current according to the magnitude of the gate current, and an overcurrent detection device, A semiconductor driving device is provided.

According to the present invention, only a transient period before the turn-on or turn-off of the switching element is determined, it is possible to control the current input to the overcurrent detection unit.

Circuit diagram of semiconductor drive device according to one embodiment Example of waveform when switching element is turned on Specific examples of semiconductor drive devices Specific examples of semiconductor drive devices Specific examples of semiconductor drive devices Specific examples of semiconductor drive devices Specific examples of semiconductor drive devices

<Configuration of Semiconductor Driving Device 1>
FIG. 1 is a circuit diagram showing a configuration of a semiconductor drive device 1 according to an embodiment. The semiconductor drive device 1 may be configured by an integrated circuit or may be configured by discrete components.

  The semiconductor drive device 1 includes a switching element 10, a drive circuit 30, and an overcurrent detection device 60, and is a semiconductor circuit that protects the switching element 10 from driving and overcurrent. The switching element 10 may be a semiconductor element on the same substrate as the overcurrent detection device 60 and / or the drive circuit 30, or may be a semiconductor element on a different substrate from the overcurrent detection device 60 and / or the drive circuit 30. .

  The switching element 10 is an insulated gate voltage control semiconductor element with a current sense function, and performs an on / off operation. Specific examples thereof include power transistor elements such as IGBTs and MOSFETs. FIG. 1 illustrates an IGBT that is an example of the switching element 10. Hereinafter, for convenience of explanation, the switching element 10 will be described as an IGBT. In the case of a MOSFET, it is better to read “collector” as “drain” and “emitter” as “source”.

  The gate terminal G of the switching element 10 is a control terminal connected to the drive circuit 30 via, for example, a gate resistor Rg connected in series to the gate terminal G. The collector terminal C of the switching element 10 is connected to, for example, a first power supply potential section (for example, a high potential power supply section such as a positive electrode of a power supply) via another semiconductor switching element or load (not shown) or directly. A first main terminal. The emitter terminal E of the switching element 10 is, for example, a low-potential power supply unit such as another semiconductor switching element (not shown), a load, or a second power supply potential unit (for example, a negative electrode of a power supply connected to the ground (GND)) ) Is connected to the second main terminal. The sense emitter terminal ES of the switching element 10 is a sense terminal connected to the same low potential power supply unit as the emitter terminal E, for example, via a sense resistor Rs1 for current detection. The sense resistor Rs1 is inserted between the emitter terminal E and the sense emitter terminal ES.

  The switching element 10 includes a main element 11 and a sense element 12. The main element 11 and the sense element 12 are switching elements made of IGBT. The gate electrodes of the main element 11 and the sense element 12 are control electrodes commonly connected to the gate terminal G of the switching element 10. Each collector electrode of the main element 11 and the sense element 12 is a first main electrode commonly connected to the collector terminal C of the switching element 10. The emitter electrode of the main element 11 is a second main electrode connected to the emitter terminal E of the switching element 10. The emitter electrode of the sense element 12 is a sense electrode connected to the sense emitter terminal ES of the switching element 10.

  Between the collector terminal C and the emitter terminal E of the switching element 10, a diode D1 is formed. The diode D1 may be a diode additionally connected in parallel to the switching element 10, or a body diode that is a parasitic element formed between the collector electrode and the emitter electrode of the main element 11. It is also possible to use the diode part of the reverse conducting IGBT as the diode D1.

  The switching element 10 has a parasitic capacitance between the electrodes. Each of the main element 11 and the sense element 12 includes an input capacitance that is parasitic between the gate electrode and the emitter electrode, a feedback capacitance that is parasitic between the gate electrode and the collector electrode, and between the collector electrode and the emitter electrode. There is an output capacitance that is parasitic. The diode D1 also has a parasitic diode capacitance Cdi between the anode and the cathode.

  FIG. 1 shows some of the parasitic capacitances of the main element 11 and the sense element 12. An output capacitance Cm_oes parasitic between the collector electrode and the emitter electrode of the main element 11 and an output capacitance Cs_oes parasitic between the collector electrode and the emitter electrode of the sense element 12 are illustrated. Further, a feedback capacitance Cres parasitic between the gate terminal G and the collector terminal C of the switching element 10 is illustrated. The feedback capacitance Cres of the switching element 10 is the sum of the feedback capacitance parasitic between the gate electrode and the collector electrode of the main element 11 and the feedback capacitance parasitic between the gate electrode and the collector electrode of the sense element 12. .

  The drive circuit 30 is a drive unit that controls the gate voltage Vg of the gate terminal G of the switching element 10 to a voltage for turning on or off the switching element 10 via the gate resistor Rg in accordance with a drive signal supplied from the outside. . The gate voltage Vg is applied to the gate electrodes of the main element 11 and the sense element 12 via the gate terminal G. The main element 11 and the sense element 12 are turned on or off according to the value of the gate voltage Vg applied to the gate electrode. Further, the drive circuit 30 detects when an overcurrent is detected by the overcurrent detection device 60 (for example, when a stop signal (abnormal signal) indicating that the overcurrent is detected is output from the overcurrent detection device 60). The gate voltage Vg is controlled to a voltage that turns off the switching element 10.

  A specific example of the drive circuit 30 is a microcomputer including a CPU. The drive circuit 30 may be a circuit that controls the gate voltage Vg in accordance with a signal supplied from the microcomputer.

  The overcurrent detection device 60 is a circuit including an overcurrent detection circuit 20, a gate current monitor circuit 40, and a sense current adjustment circuit 50.

  The overcurrent detection circuit 20 has a sense resistor Rs1 as an overcurrent detection unit connected to the sense emitter terminal ES of the switching element 10. The overcurrent detection circuit 20 detects an overcurrent flowing through the switching element 10 based on the input current Ir input to the sense resistor Rs1.

  The overcurrent detection circuit 20 compares, for example, the sense voltage Vs obtained by the sense element 12 with the threshold voltage Vth2 of the threshold voltage generation node 23, and the overcurrent flowing between the collector electrode and the emitter electrode of the main element 11 is detected. Detect current. The overcurrent detection circuit 20 includes a sense resistor Rs1 as an overcurrent detection unit and an overcurrent determination circuit 21.

  One end of the sense resistor Rs1 is connected to the sense emitter terminal ES, and the other end of the sense resistor Rs1 is connected to a second power supply potential unit such as ground. The sense voltage Vs is a potential difference generated at both ends of the sense resistor Rs1 when the sense current Is supplied from the sense emitter terminal ES of the sense element 12 flows as the input current Ir to the sense resistor Rs1.

  The overcurrent determination circuit 21 includes a sense-side input unit connected to the sense emitter terminal ES and a threshold-side input unit connected to the threshold voltage generation node 23, and the overcurrent is detected by the collector electrode and the emitter electrode of the main element 11. It is an overcurrent determination part which determines that it flowed between. The overcurrent determination circuit 21 includes, for example, a reference voltage source 25 and a comparator 22.

  The reference voltage source 25 is a circuit that is connected to the threshold voltage generation node 23 and generates and outputs a constant reference voltage Vth1. The reference voltage source 25 may have, for example, a resistance voltage dividing circuit that generates the reference voltage Vth1, may have a secondary battery, or may have a voltage regulator circuit.

  The comparator 22 is a circuit that compares the sense voltage Vs generated at the sense emitter terminal ES with the threshold voltage Vth2 generated at the threshold voltage generation node 23 (Vth2 = Vth1 in the case of FIG. 1). The comparator 22 is a comparison circuit including a non-inverting input terminal as a sense side input unit connected to the sense emitter terminal ES and an inverting input terminal as a threshold side input unit connected to the threshold voltage generation node 23. .

  When the sense voltage Vs is smaller than the threshold voltage Vth2, the overcurrent determination circuit 21 determines that no overcurrent flows through the main element 11, and outputs a normal signal indicating that no overcurrent is detected. On the other hand, when the sense voltage Vs is larger than the threshold voltage Vth2, the overcurrent determination circuit 21 determines that an overcurrent flows through the main element 11, and an overcurrent detection signal (stop) indicating that an overcurrent is detected. Signal).

  For example, when the sense voltage Vs is smaller than the threshold voltage Vth2, the comparator 22 outputs a low-level normal signal, and when the sense voltage Vs is larger than the threshold voltage Vth2, the comparator 22 outputs a high-level overcurrent detection signal (stop signal). Is output.

  When an overcurrent detection signal (stop signal) is output from the overcurrent determination circuit 21, the drive circuit 30 forcibly controls the gate voltage Vg to a voltage that turns off the main element 11 and the sense element 12. Thereby, the switching element 10 can be protected from overcurrent.

  The gate current monitor circuit 40 is a gate current detection unit that detects a gate current Ig flowing through the gate terminal G of the switching element 10. The gate current monitor circuit 40 monitors, for example, a charging current supplied to the gate electrodes of the main element 11 and the sense element 12 via the gate resistance Rg and the gate terminal G as the gate current Ig, and the gate current Ig flows. Detect whether or not. For example, the gate current monitor circuit 40 outputs a gate current detection signal during a period in which it is detected that a gate current Ig having a predetermined current value greater than zero is flowing. Further, the gate current monitor circuit 40 stops the output of the gate current detection signal during a period in which it is detected that the gate current Ig is not flowing (a period in which it is not detected that the gate current Ig is flowing).

  The sense current adjustment circuit 50 controls the input current Ir input to the sense resistor Rs1 during the period when the gate current Ig is detected by the gate current monitor circuit 40 so that the overcurrent is not detected by the overcurrent detection circuit 20. It is a control unit.

  As described above, the overcurrent detection device 60 monitors the flow of the gate current Ig and controls the input current Ir input to the sense resistor Rs1. It can be limited to the period in which Ig is detected. The period during which the gate current Ig is detected is included in a transient period until the switching element 10 is turned on or turned off. Therefore, the overcurrent detection device 60 is configured so that the input current Ir input to the sense resistor Rs1 is only input during a transient period until the turn-on or turn-off of the switching element 10 is determined so that the overcurrent is not detected by the overcurrent detection circuit 20. Can be controlled. Therefore, even if the sense current Is fluctuates temporarily during such a transient period, it is possible to reliably prevent the overcurrent from being erroneously detected by the overcurrent detection unit 20.

  The sense current adjustment circuit 50 controls, for example, the input current Ir input to the sense resistor Rs1 so that the overcurrent is not detected by the overcurrent detection circuit 20. As a result, the overcurrent detection device 60 receives the input current that is input to the sense resistor Rs1 only during the transient period until the turn-on or turn-off of the switching element 10 is determined so that the overcurrent is not detected by the overcurrent detection circuit 20. The size of Ir can be controlled. The magnitude of the sense voltage Vs can be adjusted by controlling the magnitude of the input current Ir.

  For example, the sense current adjustment circuit 50 generates an adjustment current for adjusting the magnitude of the input current Ir input to the sense resistor Rs1 during the detection period in which the gate current Ig is detected by the gate current monitor circuit 40. In the case of FIG. 1, the sense current adjustment circuit 50 generates an adjustment current Is ′ as an adjustment current for adjusting the magnitude of the input current Ir input to the sense resistor Rs1.

  When the switching element 10 is turned on, the main element 11 of the switching element 10 and the gate electrode of the sense element 12 are charged. At this time, since the gate current Ig flows, the gate current monitor circuit 40 can monitor the gate current Ig. For example, the sense current adjustment circuit 50 has an adjustment current Is having a magnitude determined according to the magnitude of the gate current Ig detected by the gate current monitor circuit 40 so that the overcurrent is not detected by the overcurrent detection circuit 20. Pull 'from the sense emitter terminal ES. The sense current adjustment circuit 50 extracts the adjustment current Is ′ from the sense emitter terminal ES only during the period when the gate current Ig is detected. Since Is≈Ir + Is ′, the magnitude of the input current Ir can be reduced and the voltage value of the sense voltage Vs can be reduced by increasing the extraction amount of the adjustment current Is ′ from the sense emitter terminal ES.

  The gate current Ig is not detected by the gate current monitor circuit 40 in the stable period of the gate voltage Vg or the collector voltage Vc (the state where there is no temporal voltage change) when the switching element 10 is turned on or off. Therefore, the sense current adjustment circuit 50 can stop the adjustment of the input current Ir by the adjustment current Is ′ during a period when the gate current Ig is not detected by the gate current monitor circuit 40. Thereby, in the stable period in which the turn-on or turn-off is determined, overcurrent detection monitoring can be performed based on the normal input current Ir or the sense voltage Vs that is not corrected by the adjustment current Is ′.

  Therefore, as shown in FIG. 2, for example, when the sense current Is temporarily jumps at the time of turn-on (see period t2-t6), if there is no adjustment by the adjustment current Is ′, the sense current has a magnitude proportional to the sense current Is. The voltage Vs jumps up temporarily (see waveform a in the period t2-t6). As a result, when the sense voltage Vs exceeds the threshold voltage Vth2, erroneous detection of overcurrent occurs.

  On the other hand, for example, by performing adjustment for extracting the correction current Is ′ from the sense emitter terminal ES, the sense voltage Vs is temporarily increased to a magnitude proportional to the difference obtained by subtracting the correction current Is ′ from the sense current Is. Decrease (see waveform b of period t2-t6). This difference corresponds to the input current Ir. Thereby, even if the sense current Is temporarily rises at the time of turn-on, the sense voltage Vs does not exceed the threshold voltage Vth2, and thus it is possible to prevent an overcurrent from being erroneously detected. In addition, the sense voltage Vs decreases only during the turn-on transient period, and the sense voltage Vs does not decrease during the stable period after the turn-on or turn-off transient period. Therefore, it is possible to prevent an overcurrent detection delay in the stable period.

<Magnitude of correction current Is'>
FIG. 2 is a waveform of a process in which the switching element 10 is turned on by the drive circuit 30. In the mirror period when the switching element 10 is turned on (a state in which the gate voltage Vg is temporarily flat), the gate current Ig flows from the gate terminal G to the collector terminal C and becomes an increase current of the collector current Ic. Further, the collector voltage Vc decreases when the switching element 10 is turned on. As a result, discharge of the output capacitance Cres of the switching element 10 and the diode capacitance Cdi of the diode D1 connected in parallel to the switching element 10 also occurs, and the discharge current becomes an increase current of the collector current Ic.

  Therefore, the collector current Ic at turn-on is larger than the load current IL. The sense voltage Vs also has an increase due to the increased current due to these parasitic capacitances.

  Therefore, the overcurrent detection device 60 prevents erroneous detection of overcurrent by temporarily reducing the sense voltage Vs when the switching element 10 is turned on, as shown in FIG. The amount of decrease in the sense voltage Vs can be determined by adjusting the magnitude of the adjustment current Is ′.

here,
Im_oes: Output capacity current flowing in the output capacity Cm_oes of the main element 11
Is_oes: Output capacitance current flowing in the output capacitance Cs_oes of the sense element 12
Idi: Diode capacitance current flowing in the diode capacitance Cdi of the diode D1
Ig: Gate current
n: Sense ratio (the sense ratio during the transition period is smaller than the stable period)
And The sense ratio n corresponds to the size ratio between the main element 11 and the sense element 12.

  For example, when adjusting to Is ′ = (Im_oes + Is_oes + Idi + Ig) / n, the magnitude of the adjustment current Is ′ can be made substantially equal to the temporary increase amount of the sense current Is. By adjusting the magnitude of the adjustment current Is ′ in this way, it is possible to prevent erroneous detection of an overcurrent even if the sense current Is jumps temporarily.

  Further, for example, when adjusting to Is ′> (Im_oes + Is_oes + Idi + Ig) / n, the magnitude of the adjustment current Is ′ can be made larger than the temporary increase amount of the sense current Is. By adjusting the magnitude of the adjustment current Is ′ in this way, it is possible to prevent erroneous detection of an overcurrent even if the sense current Is jumps temporarily. In particular, in this case, since the difference between the magnitude of the adjustment current Is ′ and the magnitude of the sense current Is can be further increased, it is possible to more effectively prevent the overcurrent from being erroneously detected.

  That is, the adjustment current Is ′ is the sum of the magnitude of the current flowing through the output capacitance Cm_oes, the magnitude of the current flowing through the output capacitance Cs_oes, the magnitude of the current Idi flowing through the diode capacitance Cdi, and the magnitude of the gate current Ig. It is good that it is more than the size obtained by dividing. As a result, even if the sense current Is jumps temporarily, it is possible to effectively prevent the overcurrent from being detected.

  Further, for example, if the magnitude of the adjustment current Is ′ is a value that makes the sense voltage Vs lower than the threshold voltage Vth2, it may be adjusted to Is ′ <(Im_oes + Is_oes + Idi + Ig) / n. By adjusting the magnitude of the adjustment current Is ′ in this way, it is possible to prevent an erroneous detection of an overcurrent even if the sense current Is jumps temporarily.

  For convenience of expression, the magnitude of the adjustment current Is ′ is Is ′, the magnitude of the output capacitance current Im_oes is Im_oes, the magnitude of the output capacitance current Is_oes is Is_oes, and the magnitude of the diode capacitance current Idi is Let Idi be the magnitude of the gate current Ig.

  As described above, since the sense voltage Vs is temporarily lowered by the adjustment current Is ′ at the time of turn-on, it is possible to prevent erroneous detection due to a temporary jump of the sense voltage Vs.

<Example of operation at turn-on>
Next, an example of an operation at turn-on will be described with reference to FIGS.

  In the switching element 10, both the main element 11 and the sense element 12 have a feedback capacity and an output capacity. The diode D1 also has a capacitance. Due to these capacitances, the sense voltage Vs temporarily increases in a transition period at turn-on. Therefore, in this operation example, by pulling out the current equal to or more than the sense current Is temporarily increased from the sense emitter terminal ES, the jump of the sense voltage Vs is suppressed at the time of turn-on, and the overcurrent is erroneously detected. To prevent this.

  (1) The drive circuit 30 outputs a high level signal, and charging of the gate electrodes of the main element 11 and the sense element 12 of the switching element 10 starts. As a result, the gate voltage Vg of the switching element 10 increases (period t1-t2 in FIG. 2). Further, the gate current Ig when charging of the gate electrode is started flows from the gate terminal G to the collector terminal C through the feedback capacitor Cres. The gate current Ig can be expressed as “Ig = dVgc / dt × Cres”. The dVgc / dt at this time is mainly due to the rise of the gate voltage Vg.

  (2) When the gate voltage Vg exceeds the gate threshold voltage of the switching element 10, the switching element 10 is turned on (the main element 11 and the sense element 12 are turned on). As a result, the load current IL and the collector current Ic start to flow, and the collector voltage Vc starts to decrease.

(3) At this time, the load current IL flowing through the collector terminal C of the switching element 10 temporarily rises due to the recovery current of the diode between the collector and the emitter of the opposing arm (switching element) of the switching element 10 (FIG. 2). Period t2-t3). Is during period t2-t3 is
Is = (IL (including recovery current) + Ig (constant)) / n
It can be expressed as.

  (4) The gate voltage Vg is constant until the collector voltage Vc is sufficiently lowered and charging of the feedback capacitance Cres of the switching element 10 (feedback capacitance Cm_res of the main element 11 + feedback capacitance Cs_res of the sense element 12) is finished (FIG. 2). Period t2-t5 (mirror period)).

(5) During the mirror period, a current flows from the gate terminal G to the collector terminal C through the feedback capacitor Cres. The gate current Ig is
Ig = dVgc / dt × Cres
It can be expressed as. The dVgc / dt at this time is mainly due to a decrease in the collector voltage Vc.

(6) During the first half period t3-t4 during the mirror period, the collector voltage Vc greatly decreases. At this time, the charge accumulated in the output capacitance Cm_oes of the main element 11, the output capacitance Cs_oes of the sense element 12, and the diode capacitance Cdi of the diode D1 is discharged.
Im_oes = dVce / dt × Cm_oes
Is_oes = dVcs / dt x Cs_oes
Idi = dVce / dt × Cdi
A discharge current represented by flows. Is during period t3-t4 is
Is = (IL + Ig (constant) + Im_oes (constant) + Is_oes (constant) + Idi (constant)) / n
It can be expressed as.

(7) In the latter half period t4-t5 of the mirror period, the collector voltage Vc is sufficiently lowered and the voltage change is small. At this time, almost no charge is accumulated in the output capacitance Cm_oes, the output capacitance Cs_oes, and the diode capacitance Cdi, and the discharge current is small. Is during period t4-t5 is
Is = (IL + Ig (constant) + Im_oes (decreasing) + Is_oes (decreasing) + Idi (decreasing)) / n
It can be expressed as.

(8) As described above, the collector current Ic during the mirror period includes the output capacity current Im_oes, the output capacity current Is_oes, the diode capacity current Idi, and the gate current Ig in addition to the load current IL. Therefore, the total collector current Ic flowing through the switching element 10 is
Ic = (IL + Ig + Im_oes + Is_oes + Idi)
It becomes. If the sense current ratio of the sense element 12 to the main element 11 is n, the sense current Is is
Is = (IL + Ig + Im_oes + Is_oes + Idi) / n
It becomes. Therefore, the increment ΔIs of the sense current Is during the mirror period is
ΔIs = (Ig + Im_oes + Is_oes + Idi) / n
It becomes. That is, by pulling out this ΔIs from the sense emitter terminal ES, a temporary increase in the sense voltage Vs can be suppressed. The gate current Ig always flows during the mirror period. Im_oes, Is_oes, and Idi flow a lot in the first half of the mirror period. Since the collector voltage Vc is small in the latter half of the mirror period, the influence of the output capacitance Coes and the diode capacitance Cdi is small, but when the collector voltage Vc is small, the feedback capacitance Cres is large. As the feedback capacitance Cres increases, the mirror period is extended.

  (9) The gate current monitor circuit 40 can detect the magnitude of the gate current Ig.

(10) The sense current adjustment circuit 50 extracts the adjustment current Is ′ from the sense emitter terminal ES. This adjustment current Is ′ is, for example, proportional to the gate current Is ′. Also, it is equal to or greater than ΔIs. If the proportionality constant used for this adjustment is m, it can be defined as Is ′ = m × Ig. Therefore, the value of m is
m × Ig ≧ ΔIs = (Ig + Im_oes + Is_oes + Idi) / n
By determining so as to satisfy the condition, the input current Ir can be suppressed. Thereby, erroneous detection of overcurrent can be prevented. Since the sense ratio n changes transiently, adapting (adjusting) m according to the time in the transient period further increases the effect of preventing erroneous detection of overcurrent.

(11) When the mirror period ends, the discharge of the output capacitor Coes and the diode capacitor Cdi ends (see period t5-t6). Is during period t5-t6 is
Is = (IL + Ig (decreasing)) / n
It can be expressed as. When the gate current finally disappears, Is ′ = 0 (stable period after period t6). Is in the stable period after period t6 is
Is = IL / n
It can be expressed as.

  FIG. 3 is a circuit diagram of a semiconductor drive device 100 which is a first specific example of the semiconductor drive device 1 of FIG. The semiconductor drive device 100 includes a drive circuit 31, an overcurrent detection circuit 20, a gate current monitor circuit 41, and a sense current adjustment circuit 50.

  The drive circuit 31 is a drive unit that drives the switching element 10. The drive circuit 31 controls the period during which the gate current Ig flows by voltage feedback of the gate voltage Vg. The drive circuit 31 includes an operational amplifier 32 having an output terminal that outputs a control signal for controlling a period during which the gate current Ig flows, and a P-channel output MOS transistor M1 having a gate connected to the output terminal of the operational amplifier 32. ing. The output MOS transistor M1 has a source connected to a power supply potential section such as a positive electrode of the power supply, a drain connected to the non-inverting input terminal of the operational amplifier 32, and to the gate terminal G via the gate resistor Rg.

  The overcurrent detection circuit 20 compares the sense voltage Vs, which is an input voltage that changes according to the input current Ir input to the sense resistor Rs1, and the threshold voltage Vth2, and detects an overcurrent. have.

  The gate current monitor circuit 41 is a gate current detection unit that detects the gate current Ig of the switching element 10 based on a control signal that controls a period during which the gate current Ig flows. The gate current monitor circuit 41 has a P-channel type MOS transistor M2 whose gate and source are commonly connected to the output MOS transistor M1. The gate of the output MOS transistor M2 is connected to the output terminal of the operational amplifier 32.

  The sense current adjustment circuit 50 controls the input current Ir input to the sense resistor Rs1 during the period when the gate current Ig is detected by the gate current monitor circuit 41 so that the overcurrent is not detected by the overcurrent detection circuit 20. It is a control unit. The sense current adjustment circuit 50 adjusts the magnitude of the sense voltage Vs by controlling the magnitude of the input current Ir by adjusting the adjustment current Ir.

  The sense current adjustment circuit 50 includes a sense current extraction adjustment circuit 51 and a sense current extraction circuit 52. The sense current extraction adjusting circuit 51 has a MOS transistor M3 whose drain is connected to the drain of the MOS transistor M2 of the gate current monitor circuit 41. The sense current extraction circuit 52 includes a MOS transistor M4 that is current-mirror connected to the MOS transistor M3. The drain of the MOS transistor M4 is connected to the sense emitter terminal ES.

  Next, the operation of the semiconductor drive device 100 will be described.

  The drive circuit 31 turns on the output MOS transistor M1 based on a high-level drive signal input to the inverting input terminal of the operational amplifier 32. When the output MOS transistor M1 is turned on, the gate voltage Vg rises and the switching element 10 is turned on. At this time, the sense voltage Vs tends to rise as the sense current Is rises.

  On the other hand, the MOS transistor M2 is also turned on simultaneously with the output MOS transistor M1 being turned on. During the period when the monitor current I (M2) flows through the MOS transistor M2, the MOS transistors M3 and M4 are also turned on. The adjustment current Is ′ is sucked from the sense emitter terminal ES only during the period when the MOS transistor M4 is on. The current mirror formed by the MOS transistors M3 and M4 and the mirror ratio correspond to the proportional constant m. As a result, the sense voltage Vs can be stabilized so that the sense voltage Vs does not exceed the threshold voltage Vth2 during the turn-on transition period.

  When the mirror period ends, the gate voltage Vg starts increasing again. When the drain voltage of the output MOS transistor M1 (the gate voltage Vg of the switching element 10) is stabilized, the gate current Ig does not flow. Then, the ON state of the switching element 10 is maintained by the imaginary short of the operational amplifier 32, and the output terminal of the operational amplifier 32 becomes high level, so that the output MOS transistor M1 and the MOS transistor M2 are turned off. When the MOS transistor M2 is turned off, the MOS transistors M3 and M4 are also turned off.

  In this way, the MOS transistor M4 functions only during the turn-on transition period, and the sense voltage Vs at the time of turn-on can be stabilized.

  FIG. 4 is a circuit diagram of a semiconductor drive device 200 which is a second specific example of the semiconductor drive device 1 of FIG. The semiconductor drive device 200 is obtained by replacing the IGBT of the semiconductor drive device 100 of FIG. 3 with an N-channel MOSFET. The switching element 70 includes a main element 71 and a sense element 72. The main element 71 has an output capacity Cm_oes and a feedback capacity Cm_rss, and the sense element 72 has an output capacity Cs_oes and a feedback capacity Cs_rss. The description of the operation of the semiconductor drive device 200 is omitted because it is the same as that of the semiconductor drive device 100.

  FIG. 5 is a circuit diagram of a semiconductor drive device 300 which is a third specific example of the semiconductor drive device 1 of FIG. The semiconductor drive device 300 is obtained by adding a monitor current adjustment circuit 53 to the semiconductor drive device 100 of FIG. The monitor current adjustment circuit 53 is a circuit that adjusts the monitor current flowing through the MOS transistor M2 of the gate current monitor circuit 41.

  The description of the operation of the semiconductor driving device 300 up to the mirror period is the same as that of the semiconductor driving device 100, and is omitted.

  When the mirror period ends, the gate voltage Vg starts to rise again. When the drain voltage of the output MOS transistor M1 (the gate voltage Vg of the switching element 10) is stabilized, the gate current Ig is almost eliminated. However, at this time, the operational amplifier 32 of the gate drive circuit 31 is turned on so that a certain amount of current flows through the output MOS transistor M1 in order to stabilize the constant voltage control of the gate voltage Vg. Accordingly, the MOS transistor M2 of the gate current monitor circuit 41 is also turned on, and the monitor current I (M2) continues to flow.

  The monitor current adjustment circuit 53 monitors the monitor current I flowing through the MOS transistor M2 so that the MOS transistors M3 and M4 are not turned on by the monitor current I (M2) of the MOS transistor M2 during the ON stable period of the switching element 10 after the mirror period. Pull in (M2). The monitor current adjustment circuit 53 includes, for example, a current source 54 as such a pull-in circuit.

  In the turn-on transition period, the current flowing through the MOS transistor M2 is larger than the current drawn by the monitor current adjusting circuit 53, so that the MOS transistors M3 and M4 can be turned on. Thereby, the MOS transistors M3 and M4 can be turned off in the stable period after the end of the mirror period.

  In this way, the MOS transistor M4 functions only during the turn-on transition period, and the sense voltage Vs at the time of turn-on can be stabilized.

  FIG. 6 is a circuit diagram of a semiconductor drive device 400 which is a fourth specific example of the semiconductor drive device 1 of FIG. The semiconductor drive device 400 is obtained by replacing the drive circuit 31 and the gate current monitor circuit 41 of the semiconductor drive device 100 of FIG. 3 with a drive circuit 33 and a gate current monitor circuit 42.

  The drive circuit 33 is an on / off circuit that turns on the output MOS transistor M1 based on a high level drive signal and turns off the output MOS transistor M1 based on a low level drive signal. The gate current monitor circuit 42 includes MOS transistors M2-1 and M2-2 that constitute a current mirror to which the drain of the output MOS transistor M1 is connected.

  When the output MOS transistor M1 is turned on, the drain voltage of the output MOS transistor M1 (the source voltage of the MOS transistors M2-1 and M2-2) increases, and the MOS transistors M2-1 and M2-2 are turned on. When the MOS transistor M2-1 is turned on, the gate voltage Vg rises and the switching element 10 is turned on. At this time, the sense voltage Vs tends to rise as the sense current Is rises. On the other hand, the MOS transistor M2-2 is turned on simultaneously with the turning on of the MOS transistor M2-1. During the period when the monitor current I (M2) flows through the MOS transistor M2-2, the MOS transistors M3 and M4 are also turned on. Since the subsequent operation description is the same as the above-described operation description, the description thereof will be omitted.

  FIG. 7 is a circuit diagram of a semiconductor drive device 500 according to an embodiment. A description of the same configuration as that of the above-described embodiment is omitted. The semiconductor drive device 500 includes the switching element 10, the drive circuit 31, and the overcurrent detection device 61. The overcurrent detection device 61 is a circuit having an overcurrent detection circuit 26 and a gate current monitor circuit 41.

  The overcurrent detection circuit 26 is an overcurrent detection unit connected to the sense emitter terminal ES of the switching element 10. The overcurrent detection circuit 26 detects an overcurrent flowing through the switching element 10 based on a sense current Is that is an input current input to the overcurrent detection circuit 26.

  The overcurrent detection circuit 26 has an overcurrent determination circuit 27 that detects an overcurrent by comparing the sense voltage Vs and the threshold voltage Vth2. The sense voltage Vs is a voltage that changes according to the sense current Is supplied from the sense emitter terminal ES and input to the overcurrent detection circuit 20. In this case, the sense current Is is substantially equal to the input current Ir flowing through the sense resistor Rs1. The threshold voltage Vth2 is a voltage that changes according to the threshold correction current It input to the overcurrent detection circuit 26.

  The gate current monitor circuit 41 is a gate current detection unit that detects the gate current Ig of the switching element 10 based on a control signal that controls a period during which the gate current Ig flows. Further, the gate current monitor circuit 41 is configured so that the input current that is input to the overcurrent detection circuit 26 during the period when the gate current Ig is detected by the gate current monitor circuit 41 so that the overcurrent is not detected by the overcurrent detection circuit 26. This is a control unit for controlling the threshold correction current It. The gate current monitor circuit 41 adjusts the magnitude of the threshold voltage Vth2 by controlling the magnitude of the threshold correction current It input to the overcurrent determination circuit 27. The drain of the MOS transistor M 2 is connected to the threshold voltage generation node 23.

  Next, the operation of the semiconductor drive device 500 will be described.

  The drive circuit 31 turns on the output MOS transistor M1 based on a high-level drive signal input to the inverting input terminal of the operational amplifier 32. When the output MOS transistor M1 is turned on, the gate voltage Vg rises and the switching element 10 is turned on. At this time, the sense voltage Vs tends to rise as the sense current Is rises.

  On the other hand, the MOS transistor M2 is also turned on simultaneously with the output MOS transistor M1 being turned on. If the size ratio between the output MOS transistor M1 and the MOS transistor M2 is p: 1, the sense current I (M2) of the MOS transistor M2 is Ig / p. Since the sense current I (M2) flows through the MOS transistor M2, a current also flows through the resistor Rs2. The sense current I (M2) corresponds to the threshold correction current It (I (M2) = It = Ig / p).

  As a result, the threshold voltage Vth2 generated at the threshold voltage generation node 23 can be increased from the reference voltage “Vth1” of the reference voltage source 25 to “Vth1 + Rs2 × Ig / p”. On the other hand, the sense current Is flowing during the transition period until the turn-on is determined includes a current increase of “(Is_oes + Ig) / n”. Note that Is_oes is an output capacitance current flowing in the output capacitance Cs_oes of the sense element 12, and Ig is a gate current.

  Therefore, for example, “Rs2” so that the voltage increase “Rs2 × Ig / p” due to the threshold correction current It is included in the sense current Is and is equal to or greater than the voltage increase “Rs1 × (Is_oes + Ig) / n” in the transient period. And “p” should be adjusted. As a result, the gate current monitor circuit 41 can control the threshold correction current It to a magnitude at which no overcurrent is detected during the transition period until the turn-on is determined, and the overcurrent is erroneously detected during the transition period. Can be reliably prevented.

  When the mirror period ends, the gate voltage Vg starts increasing again. When the drain voltage of the output MOS transistor M1 (the gate voltage Vg of the switching element 10) is stabilized, the gate current Ig does not flow. Then, the switching element 10 is kept on by the imaginary short of the operational amplifier 32, and the output terminal of the operational amplifier 32 becomes high level, so that the output MOS transistor M1 and the MOS transistor M2 are turned off. When the MOS transistor M2 is turned off, the value of the threshold voltage Vth2 for detecting overcurrent returns to Vth1 (Vth2 = Vth1).

  In this way, the MOS transistor M4 functions only during the turn-on transition period, and the sense voltage Vs at the time of turn-on can be stabilized.

  As described above, the overcurrent detection device and the semiconductor drive device including the same have been described by way of the embodiment. However, the present invention is not limited to the above embodiment. Various modifications and improvements, such as combinations and substitutions with part or all of other example embodiments, are possible within the scope of the present invention.

  For example, the detection of the gate current Ig may be performed by measuring the voltage across the gate resistance Rg. Further, the switching element 10 may be a P-channel type MOSFET having a current sense like the sense element 12.

1, 100, 200, 300, 400, 500 Semiconductor driving device 10, 70 Switching element 11, 71 Main element 12, 72 Sense element 20, 26 Overcurrent detection circuit 21, 27 Overcurrent determination circuit 22, Comparator 23 Threshold voltage generation node 25 Reference voltage source 30, 31, 33 Drive circuit (an example of drive unit)
40, 41, 42 Gate current monitor circuit (an example of a gate current detector)
50 sense current adjustment circuit (an example of a control unit)
60, 61 Overcurrent detection device

Claims (3)

An overcurrent detector connected to the sense terminal of the switching element;
An overcurrent detection device that detects an overcurrent flowing through the switching element when an input voltage that changes according to an input current input to the overcurrent detection unit is greater than a threshold voltage ,
A gate current detector for detecting a gate current of the switching element;
A control unit that controls the input current during a period in which the gate current is detected by the gate current detection unit so that the input voltage does not exceed the threshold voltage ;
The overcurrent detection device, wherein the control unit adjusts the amount of decrease in the input voltage by controlling the magnitude of the input current according to the magnitude of the gate current . An overcurrent detector connected to the sense terminal of the switching element;
When the input voltage that changes according to the input current supplied from the sense terminal and input to the overcurrent detection unit is larger than the threshold voltage that changes according to the threshold correction current input to the overcurrent detection unit , An overcurrent detection device for detecting an overcurrent flowing through the switching element,
A gate current detector for detecting a gate current of the switching element;
A control unit that controls the threshold correction current during a period in which the gate current is detected by the gate current detection unit so that the input voltage does not exceed the threshold voltage ;
The overcurrent detection apparatus, wherein the control unit adjusts an increase amount of the threshold voltage by controlling a magnitude of the threshold correction current according to a magnitude of the gate current . The overcurrent detection device according to claim 1 or 2 ,
A semiconductor drive device comprising: a drive unit that drives the switching element.

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