JP5840019B2 - amplifier - Google Patents

Description

  The present invention relates to an amplifier.

  Patent Document 1 discloses a differential amplifier circuit that suppresses overshoot of the output voltage by generating an auxiliary bias voltage when the output voltage rises from a steady state to a predetermined voltage. The overshoot is a phenomenon that instantaneously exceeds the intended voltage value at the output end.

  However, the technique described in Patent Document 1 requires a plurality of elements for generating an auxiliary bias voltage to be inserted into the differential amplifier circuit, which increases the size of the differential amplifier circuit and outputs the output level. There was a problem that the load current dependency also increased.

  On the other hand, the differential amplifier circuit described in Patent Document 2 is configured such that the size of the circuit does not increase due to the insertion of an element for generating an auxiliary bias voltage. That is, in order to stabilize the output voltage, a part of the output voltage is divided and fed back by a variable resistor connected in parallel to the capacitive load connected to the output terminal, thereby adjusting the output voltage.

JP 2009-53783 A JP 2005-157523 A

  However, when a part of the output voltage is simply fed back, there is a problem that the overshoot may not be eliminated depending on the switching speed of the resistance value of the variable resistor and the amount of change in the resistance value due to switching. For example, FIG. 9 shows an example of overshoot when the intended voltage value (desired voltage value) is 1.8 V as the voltage value of the output terminal of the differential amplifier circuit. By suddenly changing the resistance value of the resistor, the intended voltage value of 1.8V is instantaneously overshooted by about 0.05V. In addition, although overshoot was mentioned as an example so far, it is not restricted to this, The same problem exists also about undershoot. Here, “undershoot” refers to a phenomenon that instantaneously falls below the intended voltage value at the output end.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide an amplifier that can accurately reach an output level to a predetermined level when the output level is switched.

  In order to achieve the above object, the amplifier according to claim 1 is connected to the output terminal of the reference voltage supplied to one terminal of the pair of terminals and to the other terminal of the pair of terminals. A differential amplifier circuit that outputs a voltage having a magnitude corresponding to a difference between a voltage divided by a voltage divider connected in parallel to the capacitive load and the output terminal; And a control means for controlling the voltage divider so as to reach the predetermined level by switching the output level a plurality of times when the output level reaches the predetermined level.

  According to the present invention, when the output level is switched, it is possible to obtain an effect that the output level can reach the predetermined level with high accuracy.

It is a block diagram which shows an example of a structure of the amplifier which concerns on embodiment. It is a block diagram which shows an example of a structure of the voltage divider contained in the amplifier which concerns on embodiment. It is a graph which shows an example (the 1) of the time change of the voltage value in the output terminal of the amplifier which concerns on embodiment. It is a graph which shows an example (the 2) of the time change of the voltage value in the output terminal of the amplifier which concerns on embodiment. It is a graph which shows an example (the 3) of the time change of the voltage value in the output terminal of the amplifier which concerns on embodiment. It is a graph which shows an example (the 1) of the relationship between the voltage (supply voltage) divided | segmented by the voltage divider contained in the amplifier which concerns on embodiment, and supply time. It is a graph which shows an example (the 2) of the relationship between the voltage (supply voltage) divided | segmented by the voltage divider contained in the amplifier which concerns on embodiment, and supply time. It is a graph which shows an example (the 3) of the relationship between the voltage (supply voltage) divided | segmented by the voltage divider contained in the amplifier which concerns on embodiment, and supply time. It is a graph with which the conventional problem is demonstrated, Comprising: It is a graph which shows an example of the time change of the voltage value in the output terminal of an amplifier.

  Embodiments for carrying out the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a configuration diagram illustrating an example of a configuration of an amplifier 10 according to the present embodiment. As shown in FIG. 1, the amplifier 10 includes a differential amplifier circuit 12 and a control unit 14, which are a semiconductor device formed as a single chip. The differential amplifier 12 includes a driving voltage terminal VDD to which a driving voltage is supplied and a ground voltage terminal GND to which a voltage smaller than the driving voltage (for example, a ground voltage) is supplied. The differential amplifier circuit 12 includes P-channel field effect transistors (hereinafter referred to as “PMOS transistors”) 12A, 12B, 12C, and 12D, N-channel field effect transistors (hereinafter referred to as “NMOS transistors”) 12E. , 12F, 12G, a constant current circuit 12H, a resistor 12J, a voltage divider 12K, a capacitor 12L as an example of a capacitive load, and an output terminal 12M.

  The PMOS transistor 12A includes a source to which the drive voltage terminal VDD is connected, and a diode-connected drain and gate. The NMOS transistor 12E includes a gate to which a fixed voltage having a fixed size is supplied, a drain to which the drain of the PMOS transistor 12A is connected, a source connected to the ground voltage terminal GND through the constant current circuit 12H, It has. The PMOS transistor 12B includes a source to which the driving voltage terminal VDD is connected, a gate to which the gate of the PMOS transistor 12A is connected, and a drain that can drain the current flowing into the source. The NMOS transistor 12F includes a gate to which the voltage divided by the voltage divider 12K is supplied, a drain to which the drain of the PMOS transistor 12B is connected, and a source to which the source of the NMOS transistor 12E is connected.

  The PMOS transistor 12C includes a gate to which the drain of the PMOS transistor 12B is connected, a source to which the driving voltage terminal VDD is connected, and a drain from which a current flowing into the source can flow out. The NMOS transistor 12G includes a gate to which a predetermined voltage is supplied, a drain to which the drain of the PMOS transistor 12C is connected, and a source to which the ground voltage terminal GND is connected.

  The PMOS transistor 12D includes a source connected to the reference voltage terminal VDD, a gate connected to the drain of the PMOS transistor 12C, and a drain connected to the output terminal 12M.

  The resistor 12J is connected in series to the PMOS transistor 12D. That is, one end of the resistor 12J is connected to the output end 12M, and the other end of the resistor 12J is connected to the ground voltage terminal GND.

  The capacitor 12L is connected to the output terminal 12M. That is, one electrode of the capacitor 12L is connected to the output terminal 12M, and the other electrode of the capacitor 12L is connected to the ground voltage terminal GND.

  The voltage divider 12K is connected in parallel to the capacitor 12L and divides the output terminal 12M. That is, one end of the voltage divider 12K is connected to the output terminal 12M, and the other end of the voltage divider 12K is connected to the ground voltage terminal GND.

  The control unit 14 controls the operation of the voltage divider 12K. That is, it controls the magnitude of the voltage that is divided and extracted by the voltage divider 12K.

  FIG. 2 is a configuration diagram showing an example of the configuration of the voltage divider 12K according to the present embodiment. As shown in FIG. 2, the voltage divider 12 includes a resistor unit 16 and a switch group 18. The resistor unit 16 includes a resistor 16A, which is an example of a reference resistor, and resistors 16B, 16C, 16D, 16E, which are examples of a plurality of voltage dividing resistors, and the resistor 16A. -16E are connected in series. One end of the resistor unit 16 configured in this way is connected to the output end 12M, and the other end of the resistor unit 16 is connected to the ground voltage terminal GND.

  The switch group 18 includes switches 18A, 18B, 18C, and 18D. The switches 18A, 18B, 18C, and 18D are connected in parallel across the resistors 16B, 16C, and 16D. That is, one end of the switch 18A is a connection point between the resistors 16A and 16B, one end of the switch 18B is a connection point between the resistors 16B and 16C, and one end of the switch 18C is a resistor 16C and a resistor 16D. One end of the switch 18D is connected to the connection point between the resistor 16D and the resistor 16E, and the other end of the switches 18A, 18B, 18C, 18D is connected to the gate of the NMOS transistor 12F. Each of the switches 18A, 18B, 18C, and 18D performs a switching operation under the control of the control unit 14. Accordingly, each of the switches 18A, 18B, 18C, and 18D is switching-controlled by the control unit 14, whereby the voltage between the resistors 16A to 16E can be selectively extracted and supplied to the gate of the NMOS transistor 12F.

  Next, the operation of the amplifier 10 according to the present embodiment will be described with reference to FIGS. FIG. 3 is a graph showing an example of the time displacement of the voltage value at the output end 12M, which is a physical quantity corresponding to the output level of the output end 12M. Further, here, in order to avoid complication, when the voltage value at the output terminal 12M is set to 1.2V, only the switch 18A among the switches included in the switch group 18 is turned on, and the voltage at the output terminal 12M is turned on. When the value is set to 1.8 V, among the switches included in the switch group 18, the switches 18A, 18B, 18C, and 18D are turned on. Here, a case will be described in which the voltage value at the output end 12M is increased from 1.2V to 1.8V in order to avoid complications.

  As shown in FIG. 3, the control unit 14 controls the switch group 18 so that the switches 18A, 18B, and 18C are turned on for a predetermined time in a state where the voltage value at the output terminal 12M is 1.2V. The “predetermined time” is a predetermined time as a time when the voltage value at the output terminal 12M reaches a predetermined voltage value of less than 1.8 V when the switches 18A, 18B, and 18C are turned on. The “predetermined voltage value” mentioned here is 1.39 V as shown in FIG. 3, for example. However, the present invention is not limited to this, and even if the switches 18A, 18B, and 18C are suddenly turned on, 1. Any voltage value determined in advance as a voltage value that does not exceed 8V may be used.

  When the predetermined time elapses, the control unit 14 determines that all of the switches 18A, 18B, 18C, and 18D are temporarily turned off after the switches 18B, 18C, and 18D are temporarily turned off. The switch group 18 is controlled so that both are turned on. The time when only the switches 18B, 18C, 18D are temporarily turned off is sufficiently shorter than the discharge time of the capacitor 12L. This is because if the time for which the power is turned off is too long, the charging / discharging of the capacitor 12L is simply repeated, and the charging of the capacitor 12L does not proceed at all.

  As described above, in the amplifier 10 according to the present embodiment, when the control unit 14 increases the voltage value at the output end 12M from 1.2V to 1.8V, the capacitor 12L is gradually charged at the output end 12M. Since the voltage divider 12K is controlled so as to increase the voltage value in multiple steps (in small increments), the voltage value at the output terminal 12M exceeds the intended voltage value compared to the case where such control is not performed. Occurrence of a situation of shooting can be suppressed.

  In addition, by increasing the number of switches that are turned on from the switch 18A to the switches 18A, 18B, and 18C and further increasing to the switches 18A, 18B, 18C, and 18D, the amount of increase in the voltage value at the output terminal 12M is multistage. Since the voltage is increased, the voltage value at the output end 12M can be quickly increased to the intended voltage value without overshooting with a simple configuration. In order to increase the increase amount in multiple steps, for example, the switching time may be the same and the resistance value to be changed may be different.

  In the example shown in FIG. 3, the voltage value of the output terminal 12M is increased to 1.8V in two stages. However, the present invention is not limited to this, and the voltage value of the output terminal 12M is increased to 1.8V in three or more stages. May be. For example, as shown in FIG. 4, when the voltage value of the output terminal 12M is increased to 1.8V in three stages, the number of switches to be turned on is increased from the switch 18A to the switches 18A and 18B, and then the switches 18A, 18B and 18C. And then further increasing the switches 18A, 18B, 18C, 18D, the amount of increase in the voltage value at the output terminal 12M can be increased in three stages. In this way, when the magnitude of the voltage supplied from the voltage divider 12K to the gate of the NMOS transistor 12F is increased for each step, the voltage value at the output terminal 12M is changed to an intended voltage by increasing the number of steps. Occurrence of the situation of overshooting the value can be more reliably suppressed.

Further, in addition to increasing the increase amount of the voltage value of the output terminal 12M in a stepwise manner, for example, as shown in FIG. Good (The changing resistance value remains constant, and the voltage value is increased stepwise by gradually extending the time of the resistance value corresponding to 1.8 V. As described in the above embodiment mode. Unlike the case, this modification can be realized even if the resistance value has only a resistance value corresponding to 1.2 V and a resistance value corresponding to 1.8 V). As shown in FIG. 6, as an example, increasing the voltage value rising time of the output terminal 12M every time the step is performed, the voltage from the voltage divider 12K to the gate of the NMOS transistor 12F (smaller than the output level of the output terminal 12M). This is realized by increasing the time during which the voltage of the magnitude) is supplied for each step. That is, the control unit 14 performs switching control of the switch group 18 so that the time during which the switch to be turned on among the switches included in the switch group 18 is turned on is increased each time the step is performed, Increasing the voltage value rise time of the output terminal 12M is realized each time the step is followed. Accordingly, the configuration in which the rising time of the voltage value of the output terminal 12M is increased every time the step is followed, the voltage value at the output terminal 12M can be quickly set to the intended voltage value without overshooting compared to the case without this configuration. Furthermore, the voltage value at the output terminal 12M exceeds the intended voltage value compared to the case without this configuration due to the configuration in which the rising time of the voltage value at the output terminal 12M is lengthened every time a step is followed. Occurrence of a situation of shooting can be further reliably suppressed.

  Further, as described above, the magnitude of the voltage supplied from the voltage divider 12K to the gate of the NMOS transistor 12F is increased every step, and the voltage is supplied from the voltage divider 12K to the gate of the NMOS transistor 12F. For example, as shown in FIG. 7, a voltage (a voltage smaller than the output level of the output terminal 12M) is applied from the voltage divider 12K to the NMOS transistor. The control unit 14 may perform switching control of the switch group 18 so that the time supplied to the gate of 12F is divided at equal time intervals and equally divided than the case shown in FIG. Also in this case, it is possible to suppress the occurrence of a situation in which the voltage value at the output terminal 12M overshoots the intended voltage value.

  Further, in the example shown in FIG. 7, the case where the time during which the voltage is supplied from the voltage divider 12K to the gate of the NMOS transistor 12F is equally divided is shown, but the present invention is not limited to this. For example, as shown in FIG. The controller 14 supplies the voltage (voltage having a magnitude smaller than the output level of the output terminal 12M) from the voltage divider 12K to the gate of the NMOS transistor 12F so that the time is gradually increased (longer with each step). However, the same effect can be expected even when switching control of the switch group 18 is performed. In this case, the control unit 14 switches the switch group 18 so that the total area of the pulse waveform shown in FIG. 7 until the voltage value at the output terminal 12M reaches 1.8 V coincides with the total area of the pulse waveform shown in FIG. It is preferable to control switching.

  In the present embodiment, the voltage value of the output terminal 12M is described as an example of the case where the voltage value of the output terminal 12M is increased to an intended voltage value (when the output level is increased to a predetermined level). When the voltage is lowered to the intended voltage value (when the output level is lowered to a predetermined level), it may be the same as the case where it is raised. That is, the control unit 14 controls the voltage divider 12K so as to lower the voltage value at the output end 12M in multiple steps (in small increments), so that the voltage value at the output end 12M undershoots the intended voltage value. The occurrence of the situation can be suppressed. For example, when the voltage value of 1.8V at the output end 12M is lowered to 1.2V, the control unit 14 turns off only the switch 18D among the switches 18A, 18B, 18C, and 18D that are turned on for a predetermined time. The switch group 18 is controlled so that the switches 18A, 18B, 18C, 18D are temporarily turned on after the predetermined time has elapsed, and then the switches 18B, 18C, 18D are turned off. To do.

  Further, the number of switches to be turned on is reduced from the switches 18A, 18B, 18C, and 18D to the switches 18A, 18B, and 18C and then further reduced to the switch 18A, so that the amount of decrease in the voltage value at the output terminal 12M is multistage. Since the voltage can be increased, the voltage value at the output end 12M can be quickly lowered to the intended voltage value without undershooting with a simple configuration. Further, the voltage value may be lowered to the intended voltage value over three stages. In this case, the occurrence of a situation in which the voltage value at the output terminal 12M undershoots the intended voltage value can be further reliably suppressed.

  As described above in detail, according to the amplifier 10 according to the present embodiment, the signal is supplied to one terminal (for example, the gate of the NMOS transistor 12E) of the pair of terminals (for example, the gates of the NMOS transistors 12E and 12F). To a capacitive load (capacitor 12L as an example) that is supplied to the other terminal (gate of the NMOS transistor 12F as an example) and connected to the output terminal 12M. The differential amplifier circuit 12 outputs a voltage having a magnitude corresponding to the difference between the voltage divided by the voltage divider 12K connected in parallel from the output terminal 12M, and the output level of the output terminal 12M (an example) As a voltage value) to reach a predetermined level (1.8V as an example), the output level is determined in multiple steps. And the controller 14 that controls the voltage divider 12K to reach the bell, so that when the output level is switched, the output level can reach the predetermined level without straddling the predetermined level. it can.

DESCRIPTION OF SYMBOLS 10 Amplifier 12 Differential amplifier circuit 12K Voltage divider 12L Capacitor 12M Output terminal 14 Control part 18A, 18B, 8C, 18D Switch 16A, 16B, 16C, 16D, 16E Resistor

Claims (11)

A reference voltage supplied to one terminal of the pair of terminals and a voltage divider connected in parallel to the capacitive load supplied to the other terminal of the pair of terminals and connected to the output terminal. A differential amplifier circuit that outputs a voltage of a magnitude according to a difference between the magnitude of the pressed voltage from the output terminal;
Control means for controlling the voltage divider so as to reach the predetermined level by switching the output level a plurality of times when the output level of the output terminal reaches a predetermined level;
Including amplifier.   2. The amplifier according to claim 1, wherein when the output level of the output terminal is increased to a predetermined level, the control unit controls the voltage divider so as to increase the output level to the predetermined level in multiple steps.   The control means controls the voltage divider so as to increase the output level of the output end to the predetermined level in a multi-step manner when increasing the output level of the output end to a predetermined level. The amplifier according to claim 2, wherein the voltage divider is controlled to increase an increase amount of the output level.   The control means controls the voltage divider so as to increase the output level of the output end to the predetermined level in a multi-step manner when increasing the output level of the output end to a predetermined level. 4. The amplifier according to claim 2, wherein the voltage divider is controlled so as to lengthen a time during which the voltage divided by the voltage divider is supplied to the other terminal.   2. The amplifier according to claim 1, wherein when the output level of the output terminal is lowered to a predetermined level, the control unit controls the voltage divider so as to lower the output level to the predetermined level in multiple steps.   The control means controls the voltage divider so as to lower the output level of the output end to the predetermined level in a multi-step manner when lowering the output level of the output end to a predetermined level. The amplifier according to claim 5, wherein the voltage divider is controlled so as to increase a decrease amount of the output level.   The control means controls the voltage divider so as to lower the output level of the output end to the predetermined level in a multi-step manner when lowering the output level of the output end to a predetermined level. The amplifier according to claim 5 or 6, wherein the voltage divider is controlled so as to lengthen a time during which the voltage divided by the voltage divider is supplied to the other terminal.   The control means controls the voltage divider so as to increase the output level to the predetermined level in a multi-step manner when increasing the output level of the output end to a predetermined level, and sets the output level of the output end to a predetermined level. 2. The amplifier according to claim 1, wherein when the voltage level is lowered to the level, the voltage divider is controlled so that the output level is lowered to the predetermined level in multiple steps.   The control means controls the voltage divider so as to increase the output level of the output end to the predetermined level in a multi-step manner when increasing the output level of the output end to a predetermined level. When the voltage divider is controlled so as to increase the amount of increase in the output level and the output level at the output end is lowered to a predetermined level, the output level at the output end is lowered to the predetermined level in multiple steps. The amplifier according to claim 8, wherein the amplifier is controlled in such a manner that the voltage divider is controlled to increase a decrease amount of the output level every time a step is performed.   The control means controls the voltage divider so as to increase the output level of the output end to the predetermined level in a multi-step manner when increasing the output level of the output end to a predetermined level. When the voltage divider is controlled to increase the time during which the voltage divided by the voltage divider is supplied to the other terminal and the output level of the output terminal is lowered to a predetermined level, the output terminal The voltage divider is controlled so as to lower the output level of the output voltage to the predetermined level in a multi-step manner, and a time during which the voltage divided by the voltage divider is supplied to the other terminal each time a step is followed. The amplifier according to claim 8 or 9, wherein the voltage divider is controlled to be lengthened.   The voltage divider is a plurality of resistors connected in parallel to the capacitive load, between a plurality of resistors connected in series and an adjacent resistor of the plurality of resistors. A plurality of switches each connected to a connection point and connected in parallel;
  The control means selectively controls the plurality of switches so as to reach the predetermined level by switching the output level a plurality of times when the output level of the output terminal reaches the predetermined level.
  The time during which the switch that is turned off according to the control of the plurality of switches is turned off is shorter than the discharge time of the capacitive load, and according to the control of the control means, The amplifier according to any one of claims 1 to 10, which is a predetermined time as a time during which charging can proceed.

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