JP5767721B2 - Inverter control circuit and grid-connected inverter system provided with this inverter control circuit - Google Patents

Description

  The present invention provides an inverter control circuit for PWM control of an inverter circuit that converts DC power to AC power, a grid-connected inverter system provided with the inverter control circuit, a program for realizing the inverter control circuit, and The present invention relates to a recording medium on which this program is recorded.

  In recent years, distributed power sources using natural energy such as sunlight have been in widespread use. A grid-connected inverter system that includes an inverter circuit that converts DC power generated by a distributed power source into AC power and supplies the converted AC power to a connected load or power system has also been developed. The grid-connected inverter system is provided with a function for detecting an overcurrent and stopping the inverter circuit in order to prevent damage to the inverter circuit due to an excessively large current (overcurrent) flowing.

  FIG. 12 is a block diagram for explaining a conventional grid-connected inverter system A ′ for supplying power to a three-phase power system B (hereinafter abbreviated as “system B”).

  In the grid-connected inverter system A ′, the inverter circuit 2 performs a power conversion operation based on the PWM signal input from the inverter control circuit 10 ′. The inverter control circuit 10 ′ receives the system voltage signal Vs (Vsu, Vsv, Vsw) and the alternating current signal I (Iu, Iv, Iw) from the system voltage sensor 9 and the current sensor 7, respectively. A PWM signal is generated. That is, the alternating current signal I input from the current sensor 7 is converted into each component of the rotating coordinate system. Hereinafter, the conversion is referred to as “dq conversion”, and the converted components are referred to as “d-axis component” and “q-axis component”. Correction values ΔXd and ΔXq for calculating the deviation amounts between the d-axis component Id and the q-axis component Iq after the dq conversion and the target values Id ′ and Iq ′ to “0” are calculated. Further, the system voltage signal Vs input from the system voltage sensor 9 is also dq converted to calculate the d-axis component Vsd and the q-axis component Vsq. Correction values ΔXd and ΔXq are added to the components Vsd and Vsq, respectively, and inversely transformed to a stationary coordinate system to calculate command values Xu, Xv, and Xw. Hereinafter, the inverse transformation is referred to as “inverse dq transformation”. A PWM signal is generated based on the command values Xu, Xv, and Xw subjected to inverse dq conversion.

  Each dq conversion and inverse dq conversion is performed based on the phase θ of the U-phase system voltage detected from the system voltage signal Vs input from the system voltage sensor 9. At this time, the phase θ is a state in which the system voltage signals Vsu, Vsv, and Vsw of each phase are in an equilibrium state (a state in which the amplitude of the voltage of each phase is common and the phase difference of the voltage of each phase is 2π / 3, respectively). That is, it is detected on the assumption that the voltage of each phase of the system B is in an equilibrium state. That is, the voltage phase of each phase of the system B is not reflected in the d-axis component Vsd and the q-axis component Vsq obtained by the dq conversion of the system voltage signal Vs, and the command value Xu, calculated based on Vsd and Vsq It is not reflected in Xv and Xw.

  Therefore, when the voltages of the respective phases of the system B are in an unbalanced state, the command values Xu, Xv, and Xw have the voltage phases of the respective phases even though the actual voltage phases of the respective phases of the system B are unbalanced. Calculated at equilibrium. Thereby, the control accuracy of the output current of the inverter circuit 2 is deteriorated, and the imbalance of the output current is increased. At this time, when an overcurrent is detected, the inverter circuit 2 is stopped, and the grid-connected inverter system A ′ is disconnected from the grid B. When the scale of the grid interconnection inverter system A ′ is larger than that of the grid B, the grid interconnection inverter system A ′ is disconnected from the grid B, thereby further expanding the voltage unbalanced state of the grid B or instantaneous voltage drop. May occur. In this case, there is a possibility that other grid-connected inverter systems connected to the grid B may be disconnected at once.

  The inventor has invented an inverter control circuit that generates a PWM signal so that the inverter circuit 2 can continue to operate stably even when the system B is in an unbalanced state.

  FIG. 13 is a block diagram for explaining an inverter control circuit that generates a PWM signal so that the inverter circuit 2 can stably operate even when the system B is in an unbalanced state.

  As shown in the figure, the inverter control circuit 10 ″ includes system command value signals Ku, Kv, Kw generated by the system command value generation unit 12 ′ and correction value signals ΔXu, ΔXv, generated by the correction value generation unit 11 ′. ΔXw is added by the adding unit 13 ′, and the PWM signal generating unit 14 ′ generates a PWM signal based on the calculated command value signals Xu, Xv, Xw.

  System command value signals Ku, Kv, and Kw serving as references for the command value signals Xu, Xv, and Xw are generated for each phase based on the voltages of the respective phases of the system B by the system command value generation unit 12 '. Therefore, even when the voltage of each phase of the system B is in an unbalanced state, a command value signal for each phase corresponding to the voltage of each phase in the unbalanced state is generated, so the output voltage from the inverter circuit 2 is also The unbalanced state is the same as the voltage of each phase of the system B. Thereby, since the control accuracy of the output current of the inverter circuit 2 is not deteriorated, it is possible to suppress an increase in the imbalance of the output current, and thus it is possible to suppress the detection of an overcurrent. Therefore, even when the connected system B is in a voltage unbalanced state, the inverter circuit 2 can be stably operated.

On the other hand, the present inventor reduces power conversion by reducing the number of on / off operations of a switching element (not shown) built in the inverter circuit 2 in the grid-connected inverter system A ′ shown in FIG. Invented to reduce loss (generally called “switching loss”). This invention is a period in which the switching of each phase is fixed to zero by changing the neutral point potential of the three phases every 1/3 period and fixing the potential of each phase to zero by 1/3 period. The control of stopping is performed. This control method is characterized in that the neutral point potential is shifted, and is hereinafter referred to as “NVS (Neutral Voltage Shift) control”. The NVS control generates a command value signal (hereinafter referred to as an “NVS command value signal”) having a special waveform whose 1/3 period is zero, and a PWM signal generated based on the NVS command value signal. This is done by controlling the inverter circuit 2. Since the PWM signal continues to be at a low level while the NVS command value signal is zero, the on / off operation of the switching element during this period is stopped. Therefore, since the number of on / off operations of the switching element is reduced to 2/3, switching loss can be reduced.

  FIG. 14 is a block diagram for explaining an internal configuration of an NVS control PWM signal generation unit 14 ″ that generates an NVS command value signal and generates a PWM signal based on the NVS command value signal. The NVS control PWM signal generation unit 14 ″ corresponds to the PWM signal generation unit of FIG.

  The NVS control PWM signal generator 14 ″ includes a line voltage command value signal generator 14a ″, an NVS command value signal generator 14b ″, and a pulse signal generator 14c ″.

The line voltage command value signal generation unit 14a ″ includes an inverse conversion unit (inverter control circuit 10 ′ in FIG. 12).
The line voltage command value signals Xuv, Xvw, and Xwu are generated from the command value signals Xu, Xv, and Xw that are input from (see). Since the system voltage sensor 9 detects the phase voltage of each phase of the system B, the command value signals Xu, Xv, Xw input from the inverse conversion unit are command value signals for commanding the phase voltage of each phase. . The line voltage command value signal generation unit 14a ″ is configured to command line voltage command value signals Xuv, Xvw, Xvw for commanding line voltages from command value signals Xu, Xv, Xw for commanding phase voltages of respective phases. Xwu is generated and output to the NVS command value signal generation unit 14b ″. The line voltage command value signal generation unit 14a ″ generates a difference signal between Xu and Xv as Xuv, a difference signal between Xv and Xw as Xvw, and a difference signal between Xw and Xu as Xwu.

The NVS command value signal generation unit 14b ″ is based on the phase θ of the U-phase system voltage and the line voltage command value signals Xuv, Xvw, Xwu input from the line voltage command value signal generation unit 14a ″. The value signals Xu ′, Xv ′, and Xw ′ are generated and output to the pulse signal generation unit 14c ″. The NVS command value signal generation unit 14b ″ generates a line voltage command value every 1/3 period. By switching the signals Xuv, Xvw, Xwu, the zero signal whose value is zero, and the signals Xvu, Xwv, Xuw obtained by inverting the polarities of the line voltage command value signals Xuv, Xvw, Xwu, the NVS command value signal Xu ', Xv', Xw 'are generated.

  FIG. 15 is a diagram for explaining the waveforms of the NVS command value signals Xu ′, Xv ′, and Xw ′ generated by the NVS command value signal generator 14b ″.

Waveforms Xuv, Xvw, and Xwu shown in FIG. 6A are the waveforms of the line voltage command value signals Xuv, Xvw, and Xwu, respectively, and are the target line intervals of the U, V, and W phases of the system voltage, respectively. It matches the waveform of the voltage signal. FIG. 4B is a diagram for explaining the waveform of the NVS command value signal Xu ′. A waveform Xuv shown in FIG. 6B is a waveform of the line voltage command value signal Xuv, and is the same as the waveform Xuv shown in FIG. A waveform Xuw shown in FIG. 5B is a waveform of the signal Xuw obtained by inverting the polarity of the line voltage command value signal Xwu. A waveform Xu ′ shown in FIG. 5B is a waveform of the NVS command value signal Xu ′.

As shown in FIG. 5B, the waveform of the NVS command value signal Xu ′ is 3π / 6 ≦ θ ≦ 7π / 6.
During this period, the waveform of the line voltage command value signal Xuv is obtained, the period of 7π / 6 ≦ θ ≦ 11π / 6 is zero, and the period of 11π / 6 ≦ θ ≦ 15π / 6 is the waveform of the signal Xuw. Similarly, the waveform of the NVS command value signal Xv ′ is zero during the period of 3π / 6 ≦ θ ≦ 7π / 6 and the period of 7π / 6 ≦ θ ≦ 11π / 6 as shown in FIG. The waveform of the signal Xvu is obtained by inverting the polarity of the line voltage command value signal Xuv, and the waveform of the line voltage command value signal Xvw is obtained during the period of 11π / 6 ≦ θ ≦ 15π / 6. The waveform of the NVS command value signal Xw ′ is not shown, but 3
During the period of π / 6 ≦ θ ≦ 7π / 6, the waveform of the signal Xwv is obtained by inverting the polarity of the line voltage command value signal Xvw, and during the period of 7π / 6 ≦ θ ≦ 11π / 6, the line voltage command value signal Xwu is A waveform is obtained, and the period of 11π / 6 ≦ θ ≦ 15π / 6 is zero.

The pulse signal generation unit 14c ″ includes a carrier signal (for example, a triangular wave signal) generated therein and NVS command value signals Xu ′, Xv ′, and Xw ′ input from the NVS command value signal generation unit 14b ″. Each phase generates a PWM signal and outputs it to the inverter circuit 2.

FIG. 16 is a diagram for explaining a method of generating a PWM signal from the NVS command value signal Xu ′ and the carrier signal. In the figure, the NVS command value signal Xu ′ is indicated by a waveform X, the carrier signal is indicated by a waveform C, and the PWM signal is indicated by a waveform P. The pulse signal generation unit 14c ″ generates, as a PWM signal, a pulse signal that becomes high level when the NVS command value signal Xu ′ is larger than the carrier signal and becomes low level when the NVS command value signal Xu ′ is equal to or lower than the carrier signal. Accordingly, in the same figure, the waveform P is at a high level during a period when the waveform X is greater than the waveform C, and the waveform P is at a low level during a period when the waveform X is equal to or less than the waveform C. NVS The carrier signal is a triangular wave signal whose lower limit value is zero so that the minimum value of the NVS command value signal Xu ′ changes within the range of 0 level or higher so that the minimum value of the command value signal Xu ′ matches the minimum value of the carrier signal. Note that the carrier signal is not limited to a triangular wave signal, and may be, for example, a sawtooth wave having a lower limit value of zero.

As shown by the waveform P in the figure, the PWM signal output from the pulse signal generation unit 14c ″ continues to be at a low level in a period in which the NVS command value signal Xu ′ (waveform X) is zero. The on / off operation of the switching element is stopped, so that the number of on / off operations of the switching element is reduced to 2/3, so that the switching loss can be reduced, as shown in FIG. As described above, the difference signal Xuv ′ between the NVS command value signals Xu ′ and Xv ′ coincides with the line voltage command value signal Xuv (see (a) of the figure). A line voltage signal having the same waveform as that of the value signal Xuv can be output.

JP 2004-153957 A JP 2010-068630 A

Masayuki Hattori, Noriyuki Moromi, Ikuo Nakaoka, "High-efficiency three-phase inverter by neutral point potential shift control", 2009 IEEJ Industrial Application Conference (JIASC09), lecture number R1-7-7 (2009) / 8/31)

However, when the NVS control PWM signal generation unit 14 ″ shown in FIG. 14 is applied to the inverter control circuit 10 ″ shown in FIG. 13, when the system B is in an unbalanced state, the inverter circuit 2 continues to operate stably. There is a problem that can not be.

FIG. 17 is a diagram for explaining the waveform of the output line voltage signal of the inverter circuit 2 when the NVS control PWM signal generation unit 14 ″ shown in FIG. 14 is applied to the inverter control circuit 10 ″ shown in FIG. It is. This figure shows a case of an unbalanced state in which only the W-phase voltage is reduced by 60%.

  FIG. 5A shows the waveform of the line voltage of the system voltage at the time of the unbalance (hereinafter referred to as “system line voltage”). Since the phase voltage of the W phase has decreased, the V-phase line voltage with respect to the W phase and the W-phase line voltage with respect to the U phase have decreased.

FIG. 6B shows the NVS command value signal Xu ′, generated by the NVS command value signal generator 14b ″.
The waveforms of Xv ′ and Xw ′ are shown. Since the phase voltage of the W phase has decreased and the system command value signals Ku, Kv, Kw are generated for each phase based on the voltage of each phase of the system B by the system command value generation unit 12 ′, the command value signal Xu, Xv, and Xw are in an unbalanced state. Since the NVS command value signals Xu ′, Xv ′, and Xw ′ are generated from the line voltage command value signals Xuv, Xvw, and Xwu which are differential signals of the unbalanced command value signals Xu, Xv, and Xw, As shown in (b), the waveform has a distorted shape.

FIG. 2C shows the waveform of the line voltage signal output from the inverter circuit 2. As shown in FIG. 6B, the NVS command value signals Xu ′, Xv ′, and Xw ′ have a distorted waveform, and the phase voltage signal output from the inverter circuit 2 has the same shape. Therefore, the waveform of the line voltage signal output from the inverter circuit 2 has the same waveform as the difference signal of the NVS command value signals Xu ′, Xv ′, and Xw ′, and the waveform of the shape shown in FIG. Become.

  As shown in FIGS. 5A and 5C, the waveform of the line voltage signal output from the inverter circuit 2 has a shape that is significantly different from the waveform of the system line voltage, and the output line voltage and the system line voltage And the current increases due to the generated potential difference. When an overcurrent is detected due to the increased current, the inverter circuit 2 is stopped, so that the operation cannot be stably continued.

  The present invention has been conceived under the above circumstances, and even when the connected three-phase power system is in a voltage unbalanced state, the inverter circuit can be stably operated. And it aims at providing the inverter control circuit which produces | generates a PWM signal so that switching loss can be reduced.

  In order to solve the above problems, the present invention takes the following technical means.

An inverter control circuit provided by the first aspect of the present invention is an inverter control circuit for PWM control of an inverter circuit that converts DC power into AC power and outputs the AC power to a three-phase power system. Command value signal generating means for generating a command value signal of each phase for commanding a voltage of each phase to be output from the inverter circuit from each of the voltage signals of each phase of the three-phase power system detected by Correction value signal generating means for generating a correction value signal for each phase for controlling a measured value relating to input / output of the inverter circuit measured by a predetermined measuring means to a predetermined target value; and a command value for each phase A command value signal correcting unit that corrects the signal based on the correction value signal of each corresponding phase and outputs a corrected command value signal of each phase; and based on the corrected command value signal of each phase. And a first PWM signal generating means for generating a first PWM signal for each phase for PWM control of the inverter circuit, and a difference signal between the corrected command value signals for each phase. A second PWM signal generating means for generating a second PWM signal for each phase based on an NVS command value signal for each phase that becomes zero in a period of 1/3 period; and each phase of the three-phase power system An unbalance detection means for detecting that the voltage signal is in an unbalanced state; and when the unbalanced state is detected by the unbalance detection means, the first PWM signal is output to the inverter circuit. and an output means if said unbalanced state is not detected that outputs the second PWM signal to the inverter circuit by said imbalance detection means, is detected by the DC voltage detection unit, before DC voltage acquisition means for acquiring a DC voltage input to the inverter circuit, the command value signal generation means, the effective value calculation means for calculating the voltage effective value of the voltage signal of each phase, From the phase difference detection means for detecting the phase difference between the phase of the voltage signal of the phase and the phase at the time of three-phase equilibrium, the ratio of the effective voltage value of each phase to the DC voltage, and the phase difference of each phase, Command value calculating means for calculating a command value for each phase, and outputting the command value for each phase calculated by the command value calculating means as a command value signal for each phase .

  In a preferred embodiment of the present invention, the command value signal correcting means corrects by adding the correction value signals of the phases respectively corresponding to the command value signals of the phases.

In a preferred embodiment of the present invention, the command value calculation means calculates each of the phase effective values Veu, Vev, Vew of the phases and the phase differences φu, φv, φw of the phases according to the following formulas. The phase command values Ku (t), Kv (t), Kw (t) are calculated. Ω is an angular frequency of the three-phase power system, ωt is a current phase of the U-phase system voltage, and Cm is a command value signal Ku (t), Kv (t), Kw at the three-phase equilibrium. (T) is an amplitude, Vin is a direct current voltage input to the inverter circuit, and Kt is a transformation ratio of a transformation means for transforming the output voltage of the inverter circuit.

  In a preferred embodiment of the present invention, the correction value signal generating means converts the output current signal of each phase of the inverter circuit detected by the current detecting means into each component of a rotating coordinate system; From a first correction value calculating means for calculating a first correction value for feedback control based on a deviation amount from the target value with respect to a measured value, and the first correction value for any one of the components And a second correction value calculating means for calculating a second correction value for feedback control based on the deviation amount, and reversely converting the second correction value into a correction value for each phase of the stationary coordinate system. Conversion means for outputting a correction value for each phase as a correction value signal for each phase.

  In a preferred embodiment of the present invention, the second PWM signal generation means, from the difference signal of the corrected command value signal of each phase, the waveform of one cycle becomes zero in the period of 1/3 cycle, In the following 1/3 period period, a sine wave waveform having a phase of 0 to 2π / 3 is obtained, and in the remaining 1/3 period, the sine wave has a waveform having a phase of π / 3 to π. The first NVS command value signal, the second NVS command value signal whose phase is advanced by 2π / 3 with respect to the first NVS command value signal, and the phase with respect to the first NVS command value signal A third NVS command value signal delayed by 2π / 3 is generated, and the second PWM signal is generated based on each NVS command value signal and a carrier signal having a lower limit value of zero.

  In a preferred embodiment of the present invention, the second PWM signal generation means sets the NVS command value signal of each phase to zero for a period of 1/3 period, and continues for a period of 1/3 period of the phase. The difference signal is obtained by subtracting the corrected command value signal whose phase order is one previous from that phase from the corrected command value signal, and the remaining 1/3 period is calculated from the corrected command value signal of the phase. It is generated as a differential signal obtained by subtracting the corrected command value signal whose phase order is one more later.

  In a preferred embodiment of the present invention, the first PWM signal generation means generates the first PWM signal from a comparison result between the corrected command value signal and a first triangular wave signal having a predetermined frequency. The second PWM signal generating means generates the second PWM signal from a comparison result between the NVS command value signal and the second triangular wave signal having the predetermined frequency.

  In a preferred embodiment of the present invention, after the unbalance detection unit detects the unbalanced state, the timing when the first triangular wave signal or the second triangular wave signal becomes a minimum value, After the PWM signal to be output to the inverter circuit is switched from the second PWM signal to the first PWM signal and the unbalanced state is not detected by the unbalanced detecting means, the first triangular wave is detected. At the timing when the signal or the second triangular wave signal becomes the minimum value, the PWM signal output to the inverter circuit is switched from the first PWM signal to the second PWM signal.

  In a preferred embodiment of the present invention, the unbalance detection means has a predetermined difference between a voltage effective value of a voltage signal of any phase of the three-phase power system and a voltage effective value of a voltage signal of another phase. Or when the phase difference between the phase of the voltage signal of any phase of the three-phase power system and the phase at the three-phase equilibrium is equal to or greater than a predetermined phase difference. Detect that.

  In a preferred embodiment of the present invention, the unbalance detection means extracts a q-axis component and a d-axis component, which are vector components of a rotating coordinate system, from the voltage signal of each phase, and the q-axis component is predetermined. If the value is greater than or equal to the value or if the d-axis component is greater than or equal to a predetermined value, the unbalanced state is detected.

  The grid interconnection inverter system provided by the second aspect of the present invention includes the inverter circuit and the inverter control circuit provided by the first aspect of the present invention.

A program provided by the third aspect of the present invention is a program for causing a computer to function as an inverter control circuit for PWM control of an inverter circuit that converts DC power into AC power and outputs the AC power to a three-phase power system. Each phase command for commanding a voltage of each phase to be output from the inverter circuit from each phase voltage signal of the three-phase power system detected by the voltage detection means. A command value signal generating means for generating a value signal, and a correction value for generating a correction value signal for each phase for controlling a measured value relating to input / output of the inverter circuit measured by the predetermined measuring means to a predetermined target value And correcting the command value signal of each phase based on the correction value signal of the corresponding phase, and generating the corrected command value signal of each phase. Command value signal correcting means for outputting, and first PWM signal generating means for generating a first PWM signal of each phase for PWM control of the inverter circuit based on the corrected command value signal of each phase The second PWM signal of each phase is generated based on the NVS command value signal of each phase that becomes zero in the period of 1/3 period, which is generated based on the difference signal of the corrected command value signal of each phase. Second PWM signal generation means to be generated, unbalance detection means for detecting that the voltage signal of each phase of the three-phase power system is in an unbalanced state, and the unbalanced state by the unbalance detection means. Is detected, the first PWM signal is output to the inverter circuit. If the unbalance detection unit does not detect the unbalanced state, the second PWM signal is output to the inverter circuit. Inverter circuit And output means for outputting, is detected by the DC voltage detection means, to function as a DC voltage acquiring means for acquiring a DC voltage input to the inverter circuit, the command value signal generating means, the phase of the voltage signal An effective value calculating means for calculating an effective voltage value, a phase difference detecting means for detecting a phase difference between the phase of the voltage signal of each phase and a phase at the time of three-phase equilibrium, and the direct current of the effective voltage value of each phase Command value calculating means for calculating a command value of each phase from a ratio to the voltage and a phase difference of each phase, and the command value of each phase calculated by the command value calculating means It outputs as a value signal .

  The recording medium provided by the fourth aspect of the present invention is a computer-readable recording medium that records the program provided by the third aspect of the present invention.

  According to the present invention, when the voltage signal of each phase of the three-phase power system is unbalanced, the first PWM signal is output to the inverter circuit, and the voltage signal of each phase of the three-phase power system is unbalanced. If not, the second PWM signal is output to the inverter circuit. Since the first PWM signal of each phase is generated based on the corrected command value signal of each phase corresponding to the voltage of each phase in an unbalanced state, the output voltage from the inverter circuit is also the value of each of the three-phase power systems. The unbalanced state is the same as the phase voltage. Thereby, the control accuracy of the output current of the inverter circuit is not deteriorated, and it is possible to suppress an increase in the imbalance of the output current, and thus it is possible to suppress the detection of an overcurrent. Therefore, even when the voltage signal of each phase of the three-phase power system is in an unbalanced state, the inverter circuit can continue to operate stably.

  On the other hand, since the second PWM signal of each phase is generated based on the NVS command value signal of each phase that becomes zero in the period of 1/3 cycle, the number of switching of the switching element of the inverter circuit can be reduced. it can. Therefore, when the voltage signal of each phase of the three-phase power system is not in an unbalanced state, switching loss can be reduced.

  As a result, the inverter circuit can reduce switching loss when the three-phase power system is in an equilibrium state, and can continue to operate stably even when the three-phase power system is in an unbalanced state.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a block diagram for demonstrating the grid connection inverter system provided with the inverter control circuit which concerns on this invention. It is a block diagram for demonstrating the internal structure of the correction value production | generation part of the inverter control circuit which concerns on this invention. It is a block diagram for demonstrating the internal structure of the system | strain command value generation part of the inverter control circuit which concerns on this invention. It is a figure for demonstrating the phase difference detection method. It is a figure for demonstrating a triangular wave comparison method. It is a figure for demonstrating an example of the internal structure of an unbalanced voltage difference detection part. It is a figure for demonstrating an example of the internal structure of an unbalanced phase difference detection part. It is a figure for demonstrating an example of the internal structure of the PWM signal generation part for NVS control. It is a timing chart for demonstrating the timing of the switching of the PWM signal in a switching part. It is a figure for demonstrating the waveform of the output line voltage signal of an inverter circuit in the simulation when the connected system | system | group will be in a voltage imbalance state. It is a block diagram for demonstrating the internal structure of the other Example of an unbalanced state detection part. It is a block diagram for demonstrating the conventional grid connection inverter system. It is a block diagram for demonstrating the conventional inverter control circuit. It is a block diagram for demonstrating the internal structure of the PWM signal generation part for NVS control. It is a figure for demonstrating NVS control. It is a figure for demonstrating the method to produce | generate a PWM signal from a NVS command value signal and a carrier signal. It is a figure for demonstrating the waveform of the output line voltage signal of an inverter circuit.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, taking as an example a case where the inverter control circuit according to the present invention is used in a grid-connected inverter system.

  FIG. 1 is a block diagram for explaining a grid-connected inverter system including an inverter control circuit according to the present invention.

  As shown in the figure, the grid-connected inverter system A includes a DC power source 1, an inverter circuit 2, a filter circuit 3, a transformer circuit 4, a switch 5, a DC voltage sensor 6, current sensors 7 and 8, and a system voltage sensor 9. , And an inverter control circuit 10.

  The DC power source 1 is connected to the inverter circuit 2. The inverter circuit 2, the filter circuit 3, and the transformer circuit 4 are connected in series to the output lines of the U-phase, V-phase, and W-phase output voltages in this order. It is connected to the power system B (system B). The DC voltage sensor 6 is installed on a connection line between the DC power source 1 and the inverter circuit 2, and the current sensor 7 is installed on a connection line between the inverter circuit 2 and the filter circuit 3. The current sensor 8 is installed on a connection line between the transformer circuit 4 and the switch 5, and the system voltage sensor 9 is installed on a connection line between the switch 5 and the system B. The inverter control circuit 10 is connected to the inverter circuit 2. The grid interconnection inverter system A is linked to the grid B by the switch 5, converts the DC power output from the DC power supply 1 into AC power, and supplies the AC power to the grid B. In addition, the structure of the grid connection inverter system A is not restricted to this. For example, a sensor that is not necessary for controlling the inverter circuit 2 may not be provided, or a so-called transformerless system in which a DC / DC converter circuit is provided between the DC power source 1 and the inverter circuit 2 instead of the transformer circuit 4. It may be.

  The DC power source 1 outputs DC power and includes, for example, a solar battery. A solar cell generates direct-current power by converting solar energy into electrical energy. The DC power source 1 outputs the generated DC power to the inverter circuit 2. Note that the DC power source 1 is not limited to one that generates DC power from a solar cell. For example, the DC power source 1 may be a fuel cell, a storage battery, an electric double layer capacitor, a lithium ion battery, or AC power generated by a diesel engine generator, a micro gas turbine generator, a wind turbine generator, or the like. It may be a device that converts to DC power and outputs it.

  The inverter circuit 2 converts a DC voltage input from the DC power source 1 into an AC voltage and outputs the AC voltage to the filter circuit 3. The inverter circuit 2 is a three-phase inverter, and is a PWM control type inverter circuit including three sets of six switching elements (not shown). The inverter circuit 2 converts the DC voltage input from the DC power source 1 into an AC voltage by switching each switching element on and off based on the PWM signal input from the inverter control circuit 10.

  The filter circuit 3 removes high frequency components due to switching from the AC voltage input from the inverter circuit 2. The filter circuit 3 includes a low pass filter including a reactor and a capacitor. The AC voltage from which the high frequency component has been removed by the filter circuit 3 is output to the transformer circuit 4. The configuration of the filter circuit 3 is not limited to this, and any known filter circuit for removing high frequency components may be used. The transformer circuit 4 boosts or steps down the AC voltage output from the filter circuit 3 to a level substantially the same as the system voltage of the system B.

  The switch 5 connects the system interconnection inverter system A and the system B or disconnects the connection. The switch 5 connects the grid-connected inverter system A and the system B when the grid-connected inverter system A can supply power to the system B. The switch 5 disconnects the connection between the grid-connected inverter system A and the system B when an abnormality such as a system fault occurs in the system B. Actually, when an abnormality occurs in the system B, the system interconnection inverter system A is disconnected from the system B by a circuit breaker (not shown). At this time, in order to prevent the grid-connected inverter system A from being in a single operation state, the switch 5 is used to disconnect a load (not shown) connected between the grid-connected inverter system A and the circuit breaker. Is released.

The DC voltage sensor 6 detects a DC voltage output from the DC power supply 1. The detected DC voltage signal Vin is input to the inverter control circuit 10. The current sensor 7 detects the alternating current of each phase output from the inverter circuit 2. The detected alternating current signal I ₁ (I ₁ u, I ₁ v, I ₁ w) is input to the inverter control circuit 10. The current sensor 8 detects an alternating current of each phase output from the transformer circuit 4 (that is, an output current of the grid interconnection inverter system A). The detected alternating current signal I ₂ (I ₂ u, I ₂
v, I ₂ w) is input to the inverter control circuit 10. The system voltage sensor 9 detects the system voltage of each phase of the system B. The detected system voltage signal Vs (Vsu, Vsv, Vsw) is input to the inverter control circuit 10. Note that the output voltage output by the grid interconnection inverter system A substantially matches the grid voltage.

The inverter control circuit 10 controls the inverter circuit 2. The inverter control circuit 10 includes a DC voltage signal Vin input from the DC voltage sensor 6, an AC current signal I ₁ input from the current sensor 7, an AC current signal I ₂ input from the current sensor 8, and a system voltage sensor. A PWM signal is generated based on the system voltage signal Vs input from 9 and output to the inverter circuit 2. The inverter control circuit 10 generates a command value signal for commanding the waveform of the output voltage output from the inverter circuit 2 based on a detection signal input from each sensor, and a pulse generated based on the command value signal The signal is output as a PWM signal. The inverter circuit 2 outputs an alternating voltage having a waveform corresponding to the command value signal by switching each switching element on and off based on the input PWM signal. The inverter control circuit 10 controls the output current by changing the waveform of the output voltage of the inverter circuit 2 by changing the waveform of the command value signal. Thereby, the inverter control circuit 10 performs various feedback controls.

  In the present embodiment, the inverter control circuit 10 includes DC voltage control (feedback control performed so that the input DC voltage becomes a preset voltage target value), reactive power control (target value for which output reactive power is preset). Feedback control performed so as to be “0”), and output current control (feedback control performed by dq-converting the output current of the inverter circuit 2 so that the d-axis component becomes a correction value for reactive power control, and q-axis Feedback control is performed so that the component becomes a correction value for DC voltage control. The control method performed by the inverter control circuit 10 is not limited to this. For example, output voltage control or active power control may be performed.

  The inverter control circuit 10 includes a correction value generation unit 11, a system command value generation unit 12, an addition unit 13, and a PWM signal generation unit 14.

The correction value generation unit 11 generates a correction value signal for correcting the system command value signal output from the system command value generation unit 12 described later. The correction value generator 11 receives the DC voltage signal Vin from the DC voltage sensor 6 and the AC current signal I ₁ from the current sensor 7.
The AC current signal I ₂ is input from the current sensor 8, and the system voltage signal Vs is received from the system voltage sensor 9.
And an unbalanced state detection signal is input from the system command value generation unit 12 to generate correction value signals ΔXu, ΔXv, ΔXw and output them to the addition unit 13. The correction value signals ΔXu, ΔXv, ΔXw are correction value signals for setting the deviation between the detection value of each sensor and the target value to “0”.

  FIG. 2 is a block diagram for explaining the internal configuration of the correction value generation unit 11.

  The correction value generator 11 includes a phase detector 111, a PI controller 112, a reactive power calculator 113, a PI controller 114, a dq converter 115, a PI controller 116, a PI controller 117, an inverse dq converter 118, and An unbalanced current compensator 119 is provided.

The phase detector 111 detects the phase θ of the U-phase system voltage from the system voltage signal Vs input from the system voltage sensor 9, and is, for example, a PLL (Phase-Locked Loop) circuit. The detected phase θ is output to the dq converter 115 and the inverse dq converter 118.

The PI control unit 112 performs PI control based on a deviation between the DC voltage signal Vin input from the DC voltage sensor 6 and a preset target DC voltage Vin ^*, and outputs a correction value. The reactive power calculation unit 113 calculates and outputs the output reactive power Q from the AC current signal I ₂ input from the current sensor 8 and the system voltage signal Vs input from the system voltage sensor 9. The PI control unit 114 performs PI control based on a deviation between the output reactive power Q output from the reactive power calculation unit 113 and a preset target reactive power Q ^*, and outputs a correction value.

The dq conversion unit 115 performs dq conversion on the alternating current signal I ₁ input from the current sensor 7. The dq converter 115 receives the alternating current signal I ₁ from the current sensor 7 and the phase θ from the phase detector 111. The dq converter 115 converts the three-phase alternating current signal I ₁ to 2
The signal is converted into a phase signal, converted into a d-axis component Id that is a phase difference component with respect to the phase θ, and a q-axis component Iq that is an in-phase component and output.

  The PI control unit 116 performs PI control based on the deviation between the correction value output from the PI control unit 112 and the d-axis component Id output from the dq conversion unit 115, and outputs a correction value ΔXd. The PI control unit 117 performs PI control based on the deviation between the correction value output from the PI control unit 114 and the q-axis component Iq output from the dq conversion unit 115, and outputs a correction value ΔXq. The inverse dq conversion unit 118 performs inverse dq conversion between the correction value ΔXd input from the PI control unit 116 and the correction value ΔXq input from the PI control unit 117. The inverse dq conversion unit 118 receives the correction value ΔXd from the PI control unit 116, the correction value ΔXq from the PI control unit 117, and the phase θ from the phase detection unit 111. The inverse dq conversion unit 118 converts the d-axis component correction value ΔXd and the q-axis component correction value ΔXq into a two-phase correction value by inverse dq conversion, and then converts the correction value into a three-phase correction value. Output as value signals ΔXu, ΔXv, ΔXw.

The unbalanced current compensator 119 is for compensating for the unbalanced current. The unbalanced current compensator 119 calculates and outputs a correction value for setting the negative phase component of the alternating current signal I ₁ input from the current sensor 7 to “0”. The correction value output from the unbalanced current compensator 119 is added to the correction value signals ΔXu, ΔXv, ΔXw. Since the unbalanced current compensator 119 controls the negative phase component of the alternating current signal I ₁ to be “0”, the unbalanced current is instantaneously suppressed. The unbalanced current compensator 119 receives an unbalanced state detection signal from the system command value generator 12 and the unbalanced state detection signal is “ON” (that is, when an unbalanced state is detected). However, when the unbalanced state detection signal is “OFF” (that is, when the unbalanced state is not detected), the compensating operation is not performed.

  Returning to FIG. 1, the system command value generation unit 12 receives the DC voltage signal Vin from the DC voltage sensor 6 and the system voltage signal Vs from the system voltage sensor 9, and receives the system command value signals Ku, Kv, Kw. Is output to the adder 13. The system command value signals Ku, Kv, Kw serve as a reference for the command value signal for commanding the waveform of the output voltage output from the inverter circuit 2, and the system command value signals Ku, Kv, Kw are the correction value signal ΔXu. , ΔXv, ΔXw, the command value signal is generated.

  FIG. 3 is a block diagram for explaining the internal configuration of the system command value generation unit 12.

The system command value generation unit 12 is an effective value calculation unit 121u, 121v, 121w, filter unit 122u, 122v, 122w, phase difference detection unit 123u, 123v, 123w, filter unit 124u, 124v, 124w, U phase system command value calculation. Unit 125u, V phase system command value calculation unit 125v, W phase system command value calculation unit 125w, and unbalanced state detection unit 129.

  The effective value calculation units 121u, 121v, and 121w calculate respective effective values of the system voltage signal Vs (Vsu, Vsv, Vsw). The effective value calculation unit 121u calculates the effective value Veu of the U-phase system voltage signal Vsu and outputs it to the filter unit 122u, and the effective value calculation unit 121v calculates the effective value Vev of the V-phase system voltage signal Vsv and filters it. The effective value calculation unit 121w calculates the effective value Vew of the W-phase system voltage signal Vsw and outputs it to the filter unit 122w.

なお、Ｖｓｕ（ωｔ）はＵ相の系統電圧の現在の瞬時値であり、Ｖｓｕ（ωｔ−π／２）はＵ相の系統電圧のπ／２前の瞬時値である。Ｖ相、Ｗ相についても同様である。なお、実効値は他の方法で算出するようにしても構わない。 The effective values Veu, Vev, and Vew are calculated from the system voltage signals Vsu, Vsv, and Vsw by the following equations (1), (2), and (3).

Vsu (ωt) is the current instantaneous value of the U-phase system voltage, and Vsu (ωt−π / 2) is the instantaneous value π / 2 before the U-phase system voltage. The same applies to the V phase and the W phase. Note that the effective value may be calculated by another method.

  The filter units 122u, 122v, and 122w are low-pass filters that remove high-frequency components from the effective values Veu, Vev, and Vew calculated by the effective value calculation units 121u, 121v, and 121w, respectively. The effective values Veu, Vev, Vew from which the high frequency components have been removed by the filter units 122u, 122v, 122w are the U-phase system command value calculation unit 125u, the V-phase system command value calculation unit 125v, and the W-phase system command value calculation unit, respectively. It is output to 125w. Note that the configuration of the filter units 122u, 122v, and 122w is not limited to this, and any known filter for removing high-frequency components may be used.

  The phase difference detectors 123u, 123v, 123w detect the phase difference between the phase of the system voltage signal Vs (Vsu, Vsv, Vsw) and the phase at equilibrium. The control system of the inverter control circuit 10 is processed in synchronization with the U-phase phase θ of the system voltage. The phase θ is detected by the phase detector 111 (see FIG. 2). If the system B is in a voltage balanced state, the phases of the system voltage signals Vsu, Vsv, and Vsw are θ, (θ-2π / 3), and (θ + 2π / 3), respectively. The phase difference detectors 123u, 123v, 123w correspond to the phases θ, (θ-2π / 3), (θ + 2π / 3) in the equilibrium state of the phase of the actually detected system voltage signals Vsu, Vsv, Vsw. The phase differences φu, φv, and φw are detected. The phase difference detection unit 123u detects the phase difference φu of the U-phase system voltage signal Vsu and outputs it to the filter unit 124u. The phase difference detection unit 123v detects the phase difference φv of the V-phase system voltage signal Vsv and filters it. The phase difference detector 123w detects the phase difference φw of the W-phase system voltage signal Vsw and outputs it to the filter unit 124w.

  FIG. 4 is a diagram for explaining a method of detecting a phase difference.

  FIG. 5A shows the waveforms of the system voltage signals Vsu, Vsv, Vsw in a voltage balanced state. The thick line waveform is the waveform of the system voltage signal Vsu, the thin line waveform is the waveform of the system voltage signal Vsv, and the broken line waveform is the waveform of the system voltage signal Vsw. The arrow on the right side is a vector diagram showing the relationship between the system voltage signals Vsu, Vsv, and Vsw. The system voltage signal Vsu is synchronized with the synchronizing pulse based on the phase θ of the system voltage, and the rising edge of the synchronizing pulse coincides with the rising zero cross of the system voltage signal Vsu (timing when the voltage passes zero changing from minus to plus). ing. The system voltage signal Vsv is delayed in phase by 2π / 3 from the system voltage signal Vsu, and the rising zero cross of the system voltage signal Vsv is delayed by 2π / 3 from the rising edge of the synchronization pulse. The phase of the system voltage signal Vsw is advanced by 2π / 3 from the system voltage signal Vsu, and the rising zero cross of the system voltage signal Vsw is advanced by 2π / 3 from the rising edge of the synchronization pulse.

  FIG. 5B shows the waveforms of the system voltage signals Vsu, Vsv, Vsw in a voltage unbalanced state. The voltage unbalanced state in FIG. 6B shows a voltage unbalanced state when, for example, the V phase and the W phase are grounded, and the phase and amplitude of the system voltage signals Vsv and Vsw vary. The system voltage signal Vsv is delayed in phase by 2π / 9 from the equilibrium state (see the waveform Vsv in FIG. 9A), and the rising zero cross of the system voltage signal Vsv is 8π / 9 (= 2π / 3 + 2π / from the rising edge of the synchronization pulse. 9) It is late. The phase of the system voltage signal Vsw is advanced by 2π / 9 from the equilibrium state (see the waveform Vsw in FIG. 9A), and the rising zero cross of the system voltage signal Vsw is 8π / 9 (= 2π / 3 + 2π / from the rising edge of the synchronization pulse. 9) Go ahead. That is, the phase differences φu, φv, and φw can be calculated by comparing the rising zero crosses of the system voltage signals Vsu, Vsv, and Vsw with the rising zero crosses at the respective equilibrium times with reference to the rising edge of the synchronization pulse.

  For example, the phase difference φv is measured by, for example, counting the reference clock from the rising edge of the synchronizing pulse to the rising zero cross of the system voltage signal Vsv, and the reference clock is counted from the rising edge of the synchronizing pulse to the rising zero cross at equilibrium. For example, it is calculated by subtracting the phase difference measured in advance. In the case of the example in FIG. 5B, the phase difference φv is the phase difference between the rising zero cross of the system voltage signal Vsv and the rising edge of the synchronizing pulse −8π / 9 (the rising zero cross of the system voltage signal Vsv is the rising edge of the synchronizing pulse. Subtract the phase difference of −2π / 3 between the rising zero cross at the equilibrium and the rising edge of the sync pulse, and φv = −8π / 9 − (− 2π / 3) = − 2π / 9 Is calculated.

  Further, the phase difference φw is measured by, for example, counting the reference clock from the rising zero cross of the system voltage signal Vsw to the rising of the synchronization pulse, and counting the reference clock from the rising zero cross at the equilibrium to the rising of the synchronizing pulse. For example, it is calculated by subtracting the phase difference measured in advance. In the case of the example shown in FIG. 5B, the phase difference φw is obtained from the phase difference 8π / 9 between the rising zero cross of the system voltage signal Vsw and the rising edge of the synchronizing pulse, and the phase difference between the rising zero cross at equilibrium and the rising edge of the synchronizing pulse. By subtracting 2π / 3, φw = 8π / 9−2π / 3 = 2π / 9 is calculated.

The filter units 124u, 124v, and 124w are low-pass filters that remove high-frequency components from the phase differences φu, φv, and φw detected by the phase difference detection units 123u, 123v, and 123w, respectively. The phase differences φu, φv, φw from which the high frequency components have been removed by the filter units 124u, 124v, 124w are respectively the U-phase system command value calculation unit 125u, the V-phase system command value calculation unit 125v, and the W-phase system command value calculation unit. It is output to 125w. The configuration of the filter units 124u, 124v, and 124w is not limited to this, and any known filter for removing high-frequency components may be used.

  The U-phase system command value calculation unit 125u, the V-phase system command value calculation unit 125v, and the W-phase system command value calculation unit 125w calculate system command values. The U-phase system command value calculation unit 125u calculates the U-phase from the effective value Veu input from the filter unit 122u, the phase difference φu input from the filter unit 124u, and the DC voltage signal Vin input from the DC voltage sensor 6. The system command value Ku is calculated. The V-phase system command value calculation unit 125v calculates the V-phase from the effective value Vev input from the filter unit 122v, the phase difference φv input from the filter unit 124v, and the DC voltage signal Vin input from the DC voltage sensor 6. System command value Kv is calculated. The W-phase system command value calculation unit 125w calculates the W phase from the effective value Vew input from the filter unit 122w, the phase difference φw input from the filter unit 124w, and the DC voltage signal Vin input from the DC voltage sensor 6. The system command value Kw is calculated. The calculated system command values Ku, Kv, Kw are output to the adder 13 as system command value signals.

System command values Ku (t), Kv (t), and Kw (t) are calculated by the following equations (4), (5), and (6).

Ω is the angular frequency of the system B, and ωt is the current phase of the U-phase system voltage. Cm is the amplitude of the system command value signals Ku (t), Kv (t), Kw (t) when the system B is in a voltage balanced state. φu, φv, and φw are the phase differences φu, φv, and φw input from the phase difference detectors 123u, 123v, and 123w, respectively, and Veu, Vev, and Vew are input from the effective value calculators 121u, 121v, and 121w, respectively. Are the effective values Veu, Vev, and Vew of the system voltage signal. Kt is the transformation ratio of the transformer circuit 4, if the number of primary winding of the line B side and N ₁ and the secondary winding speed of the inverter circuit 2 side and N _2, the Kt = N ₁ / N _2. Vin is a DC voltage signal Vin input from the DC voltage sensor 6.

  Below, the method of calculating said (4), (5), (6) Formula is demonstrated.

  As will be described later, the unbalanced PWM signal generation unit 142 compares the command value signal generated from the system command value signals Ku, Kv, and Kw with a predetermined carrier signal (for example, a triangular wave signal) to generate a PWM signal. Generate. As shown in FIG. 5, in order to compare the command value signal X and the carrier signal C, it is desirable to match the amplitude of the command value signal X with the amplitude Cm of the carrier signal C. Therefore, the amplitude of the system command value signals Ku, Kv, Kw when the system B is in a voltage balanced state is set as the amplitude Cm of the carrier signal C.

In the present embodiment, the comparison processing in the PWM signal generation unit 14 is performed by digital processing. Therefore, Cm × 2 which is the peak-to-peak value of the amplitude of the carrier signal C is a resolution in digital processing (for example, when the bit width is 12 bits, the resolution is 2 ¹² = 4096 [number of bits]). Then, the output voltage change width ΔV of the grid interconnection inverter system A per bit number is
ΔV = Vin · Kt / (2 · Cm) [V] (7)
It becomes. Here, when the output gain of the system command value signal Ku is Gu, the effective value Vinv of the output voltage of the system interconnection inverter system A generated by the system command value signal Ku is
Vinv = (ΔV · 2 · Cm · Gu / 2) / √2
= ΔV · Cm · Gu / √2 [Vrms] (8)
It becomes. From this, in order to make the voltage levels of the grid-connected inverter system A and the grid B coincide with each other, an output gain Gu that satisfies Vinv = Veu may be calculated.

From the above equations (8) and (7),
Veu = Vinv = ΔV · Cm · Gu / √2
= {Vin · Kt / (2 · Cm)} · Cm · Gu / √2
Gu = Veu · 2√2 / (Vin · Kt)
= (2√2 / Kt) · (Veu / Vin)

Therefore, using the output gain Gu, the amplitude Cm, and the phase difference φu, the system command value signal Ku is
Ku = Gu · Cm · SIN (ωt + φu)
It is represented by Similarly, the output gain Gv of the system command value signal Kv and the output gain Gw of the system command value signal Kw are:
Gv = (2√2 / Kt) · (Vev / Vin)
Gw = (2√2 / Kt) · (Vew / Vin)
The system command value signal Kv and the system command value signal Kw are
Kv = Gv · Cm · SIN (ωt-2π / 3 + φv)
Kw = Gw · Cm · SIN (ωt + 2π / 3 + φw)
It is represented by

  Returning to FIG. 3, the unbalanced state detection unit 129 detects the unbalanced state of the system B. The unbalanced state detection unit 129 receives effective values Veu, Vev, and Vew from the filter units 122u, 122v, and 122w, and receives phase differences φu, φv, and φw from the filter units 124u, 124v, and 124w, respectively. It is determined whether B is in an unbalanced state, and an unbalanced state detection signal is output to an unbalanced current compensation unit 119 of the correction value generation unit 11 and a switching unit 143 (described later) of the PWM signal generation unit 14. In this embodiment, the unbalanced state detection signal is “ON” when an unbalanced state is detected, and the unbalanced state detection signal is “OFF” when no unbalanced state is detected. The unbalanced state detection unit 129 includes an unbalanced voltage difference detection unit 126, an unbalanced phase difference detection unit 127, and an OR operation unit 128.

  The unbalanced voltage difference detection unit 126 detects the unbalanced state of the system B from the effective values Veu, Vev, and Vew input from the filter units 122u, 122v, and 122w, and sends the unbalanced voltage difference detection signal to the OR operation unit 128. Output. The unbalanced voltage difference detection unit 126 determines that the system B is in an unbalanced state when any of the differences between the effective values Veu, Vev, and Vew is equal to or higher than the unbalanced voltage difference detection level that is a predetermined threshold value. The unbalanced voltage difference detection signal is turned “ON”. On the other hand, if any of the differences between the effective values Veu, Vev, and Vew is less than the unbalanced voltage difference detection level, the unbalanced voltage difference detection signal is set to “OFF”.

  FIG. 6 is a diagram for explaining an example of the internal configuration of the unbalanced voltage difference detection unit 126.

  As shown in the figure, the unbalanced voltage difference detection unit 126 includes subtraction units 126a, 126b, and 126c, absolute value conversion units 126d, 126e, and 126f, hysteresis comparators 126g, 126h, and 126i, an OR operation unit 126j, and a delay filter 126k. It has.

  First, the subtraction units 126a, 126b, and 126c and the absolute value conversion units 126d, 126e, and 126f perform the difference between the effective value Veu and the effective value Vev, the difference between the effective value Vev and the effective value Vew, and the effective value Vew and the effective value. The difference from the value Veu is calculated. Next, the hysteresis comparators 126g, 126h, 126i respectively compare the calculated differences with the unbalanced voltage difference detection level, and output an “ON” signal when each difference is equal to or greater than the unbalanced voltage difference detection level. . A hysteresis is provided to suppress chattering. The OR operation unit 126j calculates and outputs a logical sum of the outputs of the hysteresis comparators 126g, 126h, and 126i. Therefore, when any of the differences is equal to or higher than the unbalanced voltage difference detection level, the unbalanced voltage difference detection signal is output as “ON”. The delay filter 126k delays the falling time of the unbalanced voltage difference detection signal and is provided to suppress chattering. That is, chattering at the time of transition is suppressed by determining that the state is an equilibrium state when a state in which an unbalance state is not detected continues for a predetermined time.

  Note that the internal configuration of the unbalanced voltage difference detection unit 126 is not limited to this. For example, the delay filter 126k may not be provided, or the delay filter 126k may delay the rise time of the unbalanced voltage difference detection signal. In place of the hysteresis comparators 126g, 126h, and 126i, a comparator that does not provide hysteresis may be used.

  Returning to FIG. 3, the unbalanced phase difference detection unit 127 detects the unbalanced state of the system B from the phase differences φu, φv, and φw input from the filter units 124u, 124v, and 124w, and outputs an unbalanced phase difference detection signal. Is output to the OR operation unit 128. The unbalanced phase difference detection unit 127 determines that the system B is in an unbalanced state when any of the absolute values of the phase differences φu, φv, and φw is greater than or equal to a predetermined threshold unbalanced phase difference detection level. The unbalanced phase difference detection signal is turned “ON”. On the other hand, when all of the absolute values of the phase differences φu, φv, and φw are less than the unbalanced phase difference detection level, the unbalanced phase difference detection signal is set to “OFF”.

  FIG. 7 is a diagram for explaining an example of the internal configuration of the unbalanced phase difference detection unit 127.

  As shown in the figure, the unbalanced phase difference detection unit 127 includes absolute value conversion units 127d, 127e, 127f, hysteresis comparators 127g, 127h, 127i, an OR operation unit 127j, and a delay filter 127k.

  First, the absolute value converters 127d, 127e, and 127f calculate absolute values of the phase differences φu, φv, and φw. Next, the hysteresis comparators 127g, 127h, 127i compare the calculated absolute values of the respective phase differences with the unbalanced phase difference detection levels, respectively, and when the absolute values of the respective phase differences are equal to or greater than the unbalanced phase difference detection level, ON "signal is output. A hysteresis is provided to suppress chattering. The OR operation unit 127j calculates and outputs a logical sum of the outputs of the hysteresis comparators 127g, 127h, and 127i. Therefore, when any of the absolute values of the phase differences is equal to or higher than the unbalanced phase difference detection level, the unbalanced phase difference detection signal is output as “ON”. Note that the delay filter 127k delays the falling time of the unbalanced phase difference detection signal, and is provided to suppress chattering. That is, chattering at the time of transition is suppressed by determining that the state is an equilibrium state when a state in which an unbalance state is not detected continues for a predetermined time.

  The internal configuration of the unbalanced phase difference detection unit 127 is not limited to this. For example, the delay filter 127k may not be provided, or the delay filter 127k may delay the rise time of the unbalanced phase difference detection signal. In place of the hysteresis comparators 127g, 127h, and 127i, a comparator that does not provide hysteresis may be used.

  Returning to FIG. 3, the OR operation unit 128 calculates the logic between the unbalanced voltage difference detection signal input from the unbalanced voltage difference detection unit 126 and the unbalanced phase difference detection signal input from the unbalanced phase difference detection unit 127. The sum is calculated and output as an unbalanced state detection signal. That is, the OR operation unit 128 sets the unbalanced state detection signal to “ON” when at least one of the unbalanced voltage difference detection signal and the unbalanced phase difference detection signal is “ON”, and both are “OFF”. The unbalanced state detection signal is set to “OFF”.

  Returning to FIG. 1, the adding unit 13 adds the correction value signals ΔXu, ΔXv, ΔXw input from the correction value generating unit 11 to the system command value signals Ku, Kv, Kw input from the system command value generating unit 12. Addition and output to the PWM signal generation unit 14 as command value signals Xu, Xv, Xw.

  The PWM signal generation unit 14 generates PWM signals Pu, Pv, Pw based on the command value signals Xu, Xv, Xw input from the addition unit 13 and outputs them to the inverter circuit 2.

  The PWM signal generation unit 14 includes an NVS control PWM signal generation unit 141, an unbalanced PWM signal generation unit 142, and a switching unit 143. The PWM signal generation unit 14 outputs the PWM signal generated by the NVS control PWM signal generation unit 141 when the system B is in an equilibrium state, and is generated by the unbalanced PWM signal generation unit 142 when the system B is in an unbalanced state. The PWM signal thus output is output.

  The NVS control PWM signal generation unit 141 generates an NVS control PWM signal from the command value signals Xu, Xv, and Xw input from the addition unit 13 and outputs the NVS control PWM signal to the switching unit 143.

  FIG. 8 is a block diagram for explaining an example of the internal configuration of the NVS control PWM signal generation unit 141.

  The NVS control PWM signal generation unit 141 includes a line voltage command value signal generation unit 141a, an NVS command value signal generation unit 141b, and a pulse signal generation unit 141c.

  The line voltage command value signal generation unit 141a generates line voltage command value signals Xuv, Xvw, Xwu from input command value signals Xu, Xv, Xw. Since the system voltage sensor 9 detects the phase voltage of each phase of the system B, the command value signals Xu, Xv, and Xw generated based on the system voltage signal Vs input from the system voltage sensor 9 are for each phase. It is a command value signal for commanding a phase voltage. The line voltage command value signal generation unit 141a uses line voltage command value signals Xuv, Xvw, Xwu for commanding line voltages from command value signals Xu, Xv, Xw for commanding phase voltages of the respective phases. Is output to the NVS command value signal generation unit 141b. The line voltage command value signal generation unit 141a generates a difference signal between Xu and Xv as Xuv, a difference signal between Xv and Xw as Xvw, and a difference signal between Xw and Xu as Xwu.

The NVS command value signal generation unit 141b receives the phase θ of the U-phase system voltage input from the phase detection unit 111 and the line voltage command value signals Xuv, Xvw, Xwu input from the line voltage command value signal generation unit 141a. Based on the above, NVS command value signals Xu ′, Xv ′, Xw ′ are generated and output to the pulse signal generation unit 141c. The NVS command value signal generation unit 141b generates a line voltage command value signal Xuv, Xvw, Xwu, a zero signal whose value is zero, and a line voltage command value signal Xuv, Xvw, Xwu every 1/3 period. The NVS command value signals Xu ′, Xv ′, and Xw ′ are generated by switching the signals Xvu, Xwv, and Xuw whose polarities are inverted (
FIG. 15).

Note that the method of generating the NVS command value signals Xu ′, Xv ′, and Xw ′ is not limited to this. For example, instead of using the line voltage command value signals Xuv, Xvw, Xwu and the signals Xvu, Xwv, Xuw whose polarities are inverted, the full-wave rectified signals of the line voltage command value signals Xuv, Xvw, Xwu are used. May be generated.

The pulse signal generation unit 141c includes a carrier signal (for example, a triangular wave signal) generated therein and NVS command value signals Xu ′, Xv ′, and Xw ′ input from the NVS command value signal generation unit 141b, respectively. A PWM signal for each phase is generated. Pulse signal generator 1
41c generates a carrier signal that changes in a range of 0 level or higher of the NVS command value signals Xu ′, Xv ′, and Xw ′, and compares the carrier signal with the NVS command value signals Xu ′, Xv ′, and Xw ′. Thus, a PWM signal is generated. The pulse signal generation unit 141c outputs a pulse signal that becomes a high level when the NVS command value signal Xu ′ is larger than the carrier signal and becomes a low level when the NVS command value signal Xu ′ is equal to or lower than the carrier signal, as a U-phase PWM signal. (See FIG. 16). Similarly, by comparing the NVS command value signals Xv ′ and Xw ′ with the carrier signal, V-phase and W-phase PWM signals are generated, respectively. The generated PWM signal is output to the switching unit 143.

The PWM signal may be generated by a method other than the method based on the comparison between the NVS command value signals Xu ′, Xv ′, and Xw ′ and the carrier signal. For example, the pulse width is calculated from the line voltage command value signals Xuv, Xvw, Xwu using the PWM hold method, and the PWM signal is calculated based on the pulse width for the phase voltage converted from the pulse width for the calculated line voltage. It can also be generated.

  The unbalanced PWM signal generation unit 142 performs a triangular wave comparison based on the command value signals Xu, Xv, Xw input from the addition unit 13 and a carrier signal generated as a triangular wave signal having a predetermined frequency (for example, 4 kHz). A PWM signal is generated by the method. In the triangular wave comparison method, as shown in FIG. 5, the command value signal X and the carrier signal C are compared. For example, when the command value signal X is larger than the carrier signal C, the command value signal X becomes high level. When it is smaller than C, a pulse signal P that is at a low level is generated as a PWM signal. The generated PWM signal is output to the switching unit 143.

  The switching unit 143 receives the PWM signals generated by the NVS control PWM signal generation unit 141 and the unbalanced PWM signal generation unit 142, respectively, and is input from the unbalanced state detection unit 129 of the system command value generation unit 12. The PWM signal to be output is switched according to the equilibrium state detection signal. When the unbalanced state detection signal is “ON”, that is, when it is determined that the system B is in an unbalanced state, the switching unit 143 receives a PWM signal (hereinafter, referred to as an unbalanced PWM signal generation unit 142). The “unbalanced PWM signal” is output to the inverter circuit 2 as PWM signals Pu, Pv, Pw. On the other hand, when the unbalanced state detection signal is “OFF”, that is, when it is determined that the system B is in the balanced state, the PWM signal input from the NVS control PWM signal generation unit 141 (hereinafter referred to as “NVS PWM”). Signal ") is output to the inverter circuit 2 as PWM signals Pu, Pv, Pw.

  FIG. 9 is a timing chart for explaining the switching timing of the PWM signal in the switching unit 143. The upper waveform in the figure shows the carrier signal, the middle waveform shows the unbalanced state detection signal, and the lower waveform shows the switching timing of the PWM signal.

  As shown in the figure, the switching unit 143 does not switch the PWM signal at the ON / OFF switching timing of the unbalanced state detection signal, but the carrier after switching the ON / OFF state of the unbalanced state detection signal. The PWM signal is switched at the timing when the signal becomes the minimum value. That is, in the case of the figure, after the unbalanced state detection signal is switched from OFF to ON, the output PWM signal is switched from the NVS PWM signal to the unbalanced PWM signal at the timing when the carrier signal becomes the minimum value. After the unbalanced state detection signal is switched from ON to OFF, the output PWM signal is switched from the unbalanced PWM signal to the NVS PWM signal at the timing when the carrier signal becomes the minimum value. The carrier signal generated by the pulse signal generation unit 141c of the NVS control PWM signal generation unit 141 and the carrier signal generated by the unbalanced PWM signal generation unit 142 have different amplitudes but the same clock. Since it is generated based on the signal, the frequency and phase are common. Therefore, the timing at which the carrier signal becomes the minimum value is common.

  The reason why the switching unit 143 switches the PWM signal to the above timing is to suppress the output current from jumping up or down and causing a vertical short circuit, and to perform the switching smoothly. Note that the PWM signal may be switched at the timing when the carrier signal becomes the maximum value instead of the timing when the carrier signal becomes the minimum value.

  The U-phase, V-phase, and W-phase switching elements of the inverter circuit 2 are turned on / off based on U-phase, V-phase, and W-phase PWM signals Pu, Pv, and Pw, respectively. Note that the NVS control PWM signal generation unit 141 and the unbalanced PWM signal generation unit 142 also generate pulse signals obtained by inverting the U-phase, V-phase, and W-phase PWM signals, respectively, and the switching unit 143 The pulse signal is output to the inverter circuit 2 as a reverse phase PWM signal. The switching elements connected in series to the U-phase, V-phase, and W-phase switching elements of the inverter circuit 2 are respectively referred to as the U-phase, V-phase, and W-phase switching elements based on the reverse-phase PWM signals. On the other hand, it operates on and off.

  The inverter control circuit 10 may be realized as an analog circuit or a digital circuit. Further, the processing performed by each unit may be designed by a program, and the computer may function as the inverter control circuit 10 by executing the program. The program may be recorded on a recording medium and read by a computer.

  In the present embodiment, the unbalanced state detection unit 129 determines whether the system B is in an unbalanced state, and uses the unbalanced state detection signal as the unbalanced current compensation unit 119 of the correction value generation unit 11 and the PWM signal generation. To the switching unit 143 of the unit 14.

  In the unbalanced state, the unbalanced current compensator 119 performs an operation for compensating the unbalanced current, and the PWM signal generator 14 converts the PWM signal generated by the unbalanced PWM signal generator 142 into the PWM signals Pu, Pv, Pw. Is output to the inverter circuit 2 as follows. In this case, since the PWM signals Pu, Pv, Pw are generated based on the command value signals Xu, Xv, Xw of each phase corresponding to the voltages of the respective phases in an unbalanced state, the output voltage from the inverter circuit 2 is also The unbalanced state is the same as the voltage of each phase of the system B. Thereby, since the control accuracy of the output current of the inverter circuit 2 is not deteriorated, it is possible to suppress an increase in the imbalance of the output current, and thus it is possible to suppress the detection of an overcurrent. Therefore, the inverter circuit 2 can continue operation stably.

On the other hand, in the balanced state (when the unbalanced state is not detected), the unbalanced current compensator 119 does not perform the operation of compensating the unbalanced current, and the PWM signal generator 14 is generated by the NVS control PWM signal generator 141. The PWM signal thus output is output to the inverter circuit 2 as PWM signals Pu, Pv, Pw. In this case, since the PWM signals Pu, Pv, Pw are generated based on the NVS command value signals Xu ′, Xv ′, Xw ′ in which one-third of the period is zero, the switching elements of the inverter circuit 2 The number of times of switching can be reduced. Therefore, switching loss can be reduced.

  Thereby, the inverter circuit 2 can reduce the switching loss when the system B is in an equilibrium state, and can continue the operation stably even when the system B is in an unbalanced state.

  FIG. 10 is a diagram for explaining the waveform of the output line voltage signal of the inverter circuit 2 in the simulation when the connected system is in a voltage unbalanced state.

  FIG. 4A shows the case where the system B is in an equilibrium state, the upper waveform diagram shows each waveform of the system line voltage, and the lower waveform diagram is between the output lines of the inverter circuit 2. The waveform of the voltage signal is shown. Since the system B is in an equilibrium state, the inverter circuit 2 is controlled by the PWM signal generated by the NVS control PWM signal generation unit 141, and the output line voltage signal is also in an equilibrium state.

  FIG. 7B shows the case where the system B is in an unbalanced state (the same as in FIG. 17, the unbalanced state in which only the phase voltage of the W phase is reduced by 60%), and the upper waveform diagram is between the system lines. Each waveform of the voltage is shown, and the lower waveform diagram shows the waveform of the output line voltage signal of the inverter circuit 2. Since the system B is in an unbalanced state, the inverter circuit 2 is controlled by the PWM signal generated by the unbalanced PWM signal generation unit 142, and the output line voltage signal is also in the same unbalanced state as the system line voltage.

  As shown in the upper and lower waveform diagrams of FIG. 5B, even when the system B is in an unbalanced state, the waveform of the output line voltage signal of the inverter circuit 2 matches the waveform of the system line voltage. Therefore, there is no difference between the output line voltage and the system line voltage. Therefore, since an overcurrent caused by a potential difference between the output line voltage and the system line voltage is not detected, the inverter circuit 2 can continue to operate stably.

In the above embodiment, even when the system B is in an equilibrium state, the system command value generation unit 12 generates the system command value signals Ku, Kv, Kw for each phase based on the voltage of each phase of the system B. It is not limited to this. When the system B is in an equilibrium state, the system command value generation unit 12 may generate and output system command value signals Ku, Kv, and Kw in an equilibrium state based on the U-phase voltage of the system B. Further, the NVS control PWM signal generation unit 141 generates only the U-phase NVS command value signal Xu ′, and generates Xv ′ and Xw ′ by shifting the phase by 2π / 3 from the Xu ′. Also good. Alternatively, only the U-phase PWM signal may be generated, and the V-phase and W-phase PWM signals may be generated by shifting the U-phase PWM signal.

  In the above-described embodiment, the unbalanced state detection unit 129 includes the unbalanced voltage difference detection unit 126 and the unbalanced phase difference detection unit 127, and at least one of the unbalanced state detection units 129 detects the unbalanced state of the system B. Although the state is detected, the configuration of the unbalanced state detection unit 129 is not limited to this. Hereinafter, an example of an unbalanced state detection unit having another configuration will be described.

  FIG. 11 is a block diagram for explaining an internal configuration of another embodiment of the unbalanced state detection unit.

The unbalanced state detection unit 129 ′ detects the unbalanced state of the system B. The unbalanced state detection unit 129 ′ receives the system voltage signal Vs (Vsu, Vsv, Vsw) from the system voltage sensor 9.
Is input to determine whether or not the system B is in an unbalanced state, and an unbalanced state detection signal is output to the unbalanced current compensation unit 119 of the correction value generation unit 11 and the switching unit 143 of the PWM signal generation unit 14. To do. In this embodiment, the unbalanced state detection signal is “ON” when an unbalanced state is detected, and the unbalanced state detection signal is “OFF” when no unbalanced state is detected. The unbalanced state detection unit 129 ′ includes a dq conversion unit 129a ′, filter units 129b ′ and 129c ′, hysteresis comparators 129d ′ and 129e ′, and an OR operation unit 129f ′.

  The dq converter 129a 'converts the input system voltage signal Vs (Vsu, Vsv, Vsw) into a two-phase signal, performs reverse-phase dq conversion, and outputs a d-axis component and a q-axis component. The filter unit 129b 'removes components other than the fundamental wave component (50 Hz or 60 Hz) from the d-axis component input from the dq conversion unit 129a', and outputs the result as a system voltage level difference. The filter unit 129c 'removes components other than the fundamental wave component (50 Hz or 60 Hz) from the q-axis component input from the dq conversion unit 129a', and outputs the result as a system voltage phase difference.

  The hysteresis comparator 129d ′ compares the system voltage level difference input from the filter unit 129b ′ with a preset unbalanced voltage difference detection level, and when the system voltage level difference is greater than or equal to the unbalanced voltage difference detection level, Outputs “ON” signal. The hysteresis comparator 129e ′ compares the system voltage phase difference input from the filter unit 129c ′ with a preset unbalanced phase difference detection level, and when the system voltage phase difference is greater than or equal to the unbalanced phase difference detection level, Outputs “ON” signal. In order to suppress chattering, hysteresis comparators 129d 'and 129e' are provided with hysteresis.

  The OR operation unit 129f 'calculates the logical sum of the outputs of the hysteresis comparators 129d' and 129e 'and outputs the result as an unbalanced state detection signal. That is, the OR operation unit 129f ′ sets the unbalanced state detection signal “ON” when the system voltage level difference is equal to or higher than the unbalanced voltage difference detection level or when the system voltage phase difference is equal to or higher than the unbalanced phase difference detection level. When the system voltage level difference is less than the unbalanced voltage difference detection level and the system voltage phase difference is less than the unbalanced phase difference detection level, the unbalanced state detection signal is set to “OFF”.

  In addition, although the said embodiment demonstrated the case where the inverter control circuit of this invention was used for the grid connection inverter system, it is not restricted to this. The inverter control circuit of the present invention is realized by reading a program that causes a conventional inverter control circuit to perform PWM control by the above-described method from a recording medium such as a ROM that is recorded in a computer-readable manner and executing the program. May be.

  The inverter control circuit according to the present invention and the grid-connected inverter system including the inverter control circuit are not limited to the above-described embodiments. The specific configuration of each part of the inverter control circuit according to the present invention and the grid-connected inverter system including the inverter control circuit can be varied in design in various ways.

A Grid-connected inverter system 1 DC power supply 2 Inverter circuit 3 Filter circuit 4 Transformer circuit 5 Switch 6 DC voltage sensor 7, 8 Current sensor 9 System voltage sensor 10 Inverter control circuit 11 Correction value generation unit (correction value signal generation means)
111 phase detector 112 PI controller (first correction value calculation means)
113 reactive power calculation unit 114 PI control unit (first correction value calculation means)
115 dq converter (converter)
116 PI control unit (second correction value calculation means)
117 PI control unit (second correction value calculating means)
118 Inverse dq conversion unit (inverse conversion means)
119 Unbalanced current compensation unit 12 System command value generation unit (command value signal generation means)
121u, 121v, 121w Effective value calculation unit (effective value calculation means)
122u, 122v, 122w Filter unit 123u, 123v, 123w Phase difference detection unit (phase difference detection means)
124u, 124v, 124w Filter unit 125u U-phase system command value calculation unit (command value calculation means)
125v V-phase system command value calculation unit (command value calculation means)
125w W-phase system command value calculation unit (command value calculation means)
126 Unbalanced voltage difference detector 126a, 126b, 126c Subtractor 126d, 126e, 126f Absolute value converter 126g, 126h, 126i Hysteresis comparator 126j OR operation unit 126k Delay filter 127 Unbalanced phase difference detector 127d, 127e, 127f Absolute Value conversion unit 127g, 127h, 127i Hysteresis comparator 127j OR operation unit 127k Delay filter 128 OR operation unit 129, 129 ′ Unbalance state detection unit (unbalance detection means)
129a ′ dq conversion unit 129b ′, 129c ′ filter unit 129d ′, 129e ′ hysteresis comparator 129f ′ OR operation unit 13 addition unit (command value signal correction means)
14 PWM signal generator 141 PWM signal generator for NVS control (second PWM signal generator)
141a Line Voltage Command Value Signal Generation Unit 141b NVS Command Value Signal Generation Unit 141c Pulse Signal Generation Unit 142 Unbalanced PWM Signal Generation Unit (First PWM Signal Generation Unit)
143 switching unit (output means)
B Three-phase power system

Claims (12)

An inverter control circuit for PWM control of an inverter circuit that converts DC power to AC power and outputs it to a three-phase power system,
A command value signal for generating a command value signal of each phase for commanding a voltage of each phase to be output from the inverter circuit from each of the voltage signals of each phase of the three-phase power system detected by the voltage detection means Generating means;
Correction value signal generating means for generating a correction value signal for each phase for controlling a measured value related to input / output of the inverter circuit measured by a predetermined measuring means to a predetermined target value;
Command value signal correcting means for correcting the command value signal of each phase based on the correction value signal of the corresponding phase, and outputting a corrected command value signal of each phase;
First PWM signal generating means for generating a first PWM signal of each phase for PWM control of the inverter circuit based on the corrected command value signal of each phase;
Generates a second PWM signal for each phase based on the NVS command value signal for each phase that is zero based on the difference signal of the corrected command value signal for each phase. Second PWM signal generating means for
Unbalance detection means for detecting that the voltage signal of each phase of the three-phase power system is in an unbalanced state;
When it is detected that the unbalanced state is detected by the unbalance detecting means, the first PWM signal is output to the inverter circuit, and the unbalanced detecting means detects that the unbalanced state is detected. If not, output means for outputting the second PWM signal to the inverter circuit;
DC voltage acquisition means for acquiring a DC voltage input to the inverter circuit, detected by the DC voltage detection means;
Equipped with a,
The command value signal generating means is
Effective value calculating means for calculating a voltage effective value of the voltage signal of each phase;
Phase difference detection means for detecting a phase difference between the phase of the voltage signal of each phase and the phase at the time of three-phase equilibrium;
Command value calculation means for calculating a command value for each phase from the ratio of the effective voltage value of each phase to the DC voltage and the phase difference of each phase;
With
Outputting the command value of each phase calculated by the command value calculating means as the command value signal of each phase;
An inverter control circuit characterized by that. The command value signal correcting means corrects by adding the correction value signals of phases corresponding to the command value signals of the phases,
The inverter control circuit according to claim 1. The command value calculation means calculates the command values Ku (t), Kv of the respective phases from the effective voltage values Veu, Vev, Vew of the respective phases and the phase differences φu, φv, φw of the respective phases according to the following equations. (t), calculates the Kw (t), the inverter control circuit according to claim 1 or 2.
Ω is an angular frequency of the three-phase power system, ωt is a current phase of the U-phase system voltage, and Cm is a command value signal Ku (t), Kv (t), Kw at the three-phase equilibrium. (T) is an amplitude, Vin is a direct current voltage input to the inverter circuit, and Kt is a transformation ratio of a transformation means for transforming the output voltage of the inverter circuit.

The correction value signal generation means includes
Conversion means for converting the output current signal of each phase of the inverter circuit detected by the current detection means into each component of the rotating coordinate system;
First correction value calculating means for calculating a first correction value for feedback control based on an amount of deviation from the target value with respect to the measured value;
Second correction value calculating means for calculating a second correction value for feedback control based on a deviation amount from the first correction value for any of the components;
Inverse conversion means for inversely converting the second correction value into a correction value for each phase of the stationary coordinate system;
With
Outputting the correction value of each phase as the correction value signal of each phase;
Inverter control circuit according to any one of claims 1 to 3. The second PWM signal generation means, from the difference signal of the corrected command value signal of each phase, the waveform of one cycle becomes zero in the period of 1/3 period, and the phase in the period of the subsequent 1/3 period. A first NVS command value signal having a waveform of a sine wave in the interval of 0 to 2π / 3, and a phase of the sine wave in the interval of π / 3 to π in the remaining 1/3 period; A second NVS command value signal whose phase is advanced by 2π / 3 with respect to the first NVS command value signal, and a third NVS whose phase is delayed by 2π / 3 with respect to the first NVS command value signal The inverter control according to any one of claims 1 to 4 , wherein a command value signal is generated, and the second PWM signal is generated based on each NVS command value signal and a carrier signal having a lower limit value of zero. circuit. The second PWM signal generation means sets the NVS command value signal of each phase to zero for a period of 1/3 cycle, and continues the period of 1/3 cycle from the corrected command value signal for the phase from the phase. The difference signal is obtained by subtracting the corrected command value signal of the previous order, and the remaining 1/3 period is corrected from the corrected command value signal of the relevant phase by one phase after the relevant phase. The inverter control circuit according to claim 5 , wherein the inverter control circuit is generated as a difference signal obtained by subtracting the command value signal. The first PWM signal generating means generates the first PWM signal from a comparison result between the corrected command value signal and a first triangular wave signal having a predetermined frequency,
The second PWM signal generation means generates the second PWM signal from a comparison result between the NVS command value signal and the second triangular wave signal having the predetermined frequency.
The inverter control circuit according to claim 5 or 6 . The unbalance detection means is configured to detect a difference between a voltage effective value of a voltage signal of any phase of the three-phase power system and a voltage effective value of a voltage signal of another phase being a predetermined value or more, or when the phase difference between the phase and three-phase equilibrium in the phase of either phase of the voltage signal of the phase power system is greater than or equal to a predetermined phase difference, it detects that the unbalanced state, claims 1 7 The inverter control circuit in any one of. The unbalance detection means extracts a q-axis component and a d-axis component, which are vector components of a rotating coordinate system, from the voltage signal of each phase, and when the q-axis component is a predetermined value or more, or the d If the shaft component is equal to or larger than a predetermined value, detects that the unbalanced state, the inverter control circuit according to any one of claims 1 to 7. The inverter circuit and the inverter control circuit according to any one of claims 1 to 9 ,
A grid-connected inverter system. A program for causing a computer to function as an inverter control circuit for PWM control of an inverter circuit that converts DC power into AC power and outputs it to a three-phase power system,
The computer,
A command value signal for generating a command value signal of each phase for commanding a voltage of each phase to be output from the inverter circuit from each of the voltage signals of each phase of the three-phase power system detected by the voltage detection means Generating means;
Correction value signal generating means for generating a correction value signal for each phase for controlling a measured value related to input / output of the inverter circuit measured by a predetermined measuring means to a predetermined target value;
Command value signal correcting means for correcting the command value signal of each phase based on the correction value signal of the corresponding phase, and outputting a corrected command value signal of each phase;
First PWM signal generating means for generating a first PWM signal of each phase for PWM control of the inverter circuit based on the corrected command value signal of each phase;
Generates a second PWM signal for each phase based on the NVS command value signal for each phase that is zero based on the difference signal of the corrected command value signal for each phase. Second PWM signal generating means for
Unbalance detection means for detecting that the voltage signal of each phase of the three-phase power system is in an unbalanced state;
When it is detected that the unbalanced state is detected by the unbalance detecting means, the first PWM signal is output to the inverter circuit, and the unbalanced detecting means detects that the unbalanced state is detected. If not, output means for outputting the second PWM signal to the inverter circuit;
DC voltage acquisition means for acquiring a DC voltage input to the inverter circuit, detected by the DC voltage detection means;
To function ,
The command value signal generating means is
Effective value calculating means for calculating a voltage effective value of the voltage signal of each phase;
Phase difference detection means for detecting a phase difference between the phase of the voltage signal of each phase and the phase at the time of three-phase equilibrium;
Command value calculation means for calculating a command value for each phase from the ratio of the effective voltage value of each phase to the DC voltage and the phase difference of each phase;
With
Outputting the command value of each phase calculated by the command value calculating means as the command value signal of each phase;
A program characterized by that . The computer-readable recording medium which recorded the program of Claim 11 .

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