JP5719182B2 - Insulated gate bipolar transistor inspection method, manufacturing method, and test circuit - Google Patents

Description

  The present invention relates to an inspection technique for inspecting the performance of an insulated gate bipolar transistor (hereinafter referred to as IGBT).

An IGBT is known as one of power transistors that drive and control large power. The IGBT has a structure in which a P collector layer is provided on the drain side of an N-channel power MOSFET, and the N-channel power MOSFET and a PNP-type BJT (BJT: bipolar transistor) are configured in one semiconductor element.
Among the performance index values of the IGBT, the saturation voltage (also referred to as “on voltage”) characteristic between the collector and the emitter and the turn-off loss characteristic are assumed to depend on the hole density from the P collector layer to the N base layer. Are known.
Specifically, the saturation voltage characteristic is dominated by conductivity modulation due to the density of holes injected from the P collector layer into the N base layer (n-epitaxial layer of the N-channel power MOSFET). The characteristics improve as the hole density from the P collector layer to the N base layer increases.
The turn-off loss is dominated by the residual hole density injected from the P collector layer to the N base layer, and the turn-off loss characteristic becomes worse as the residual hole density from the P collector layer to the N base layer increases.
As described above, it is known that the saturation voltage characteristic and the turn-off loss characteristic have a trade-off relationship with respect to the hole density. Since the hole density is proportional to the carrier concentration of the P collector layer, when manufacturing the IGBT, the carrier concentration of the P collector layer that improves both the saturation voltage characteristic and the turn-off loss characteristic is obtained in advance. An IGBT is to be manufactured.

  A performance test is performed after the IGBT is manufactured. As a technology for performance inspection, for example, a technology is known in which a TEG (test element group) is formed in a partial region of a semiconductor wafer for manufacturing an IGBT, and the performance of the IGBT is inspected by measuring the characteristics of the TEG. (For example, refer to Patent Document 1).

Japanese Patent No. 3101364

By the way, since the IGBT is a power transistor used with high power, it is necessary to conduct a performance test of the saturation voltage characteristic and the turn-off loss characteristic by passing a large current. Therefore, conventionally, these performance inspections are performed in a state where a collector electrode and an emitter electrode are formed in order to pass a large current to each of the collector and emitter of the IGBT, and the power module is mounted.
However, since the performance inspection is performed after the power module is mounted, even if a saturation voltage characteristic and a turn-off loss characteristic defect are found, the carrier concentration of the P collector layer that affects these characteristics cannot be adjusted. There was no choice but to discard it. As a result, the manufacturing cost of the IGBT, the members of the power module, and the mounting cost are wasted.

  The present invention has been made in view of the above-described circumstances, and provides an inspection method, a manufacturing method, and a test circuit for an insulated gate bipolar transistor capable of inspecting a saturation voltage characteristic and a turn-off loss characteristic without passing a large current. For the purpose.

In order to achieve the above object, the present invention provides a second conductivity type base region, a first conductivity type emitter region formed in the base region, and the emitter on the main surface of the first conductivity type semiconductor layer. In an inspection method of an insulated gate bipolar transistor in which an insulated gate adjacent to each region is provided and a second conductivity type collector layer is provided on the other main surface side of the semiconductor layer, a gate voltage is applied to the insulated gate. The electron current and the hole current due to holes injected from the collector layer into the semiconductor layer are measured, the ratio of the hole current to the collector current obtained by adding the hole current to the electron current, the saturation voltage characteristic, and the turn-off characteristic of it obtained in advance based on the correlation between each of the non-defective determination range where the saturation voltage characteristic and the turn-off characteristic is good, the collector It determines whether the measured value of the ratio of the hole current enters for flow, characterized by inspecting the quality of the saturation voltage characteristics and turn-off characteristics.

According to the present invention, the electron current when a gate voltage is applied to the insulated gate and the hole current due to carriers injected from the collector layer into the semiconductor layer are measured, and the hole with respect to the collector current obtained by adding the hole current to the electron current is measured. Based on the correlation between the current ratio and the saturation voltage characteristics and turn-off characteristics, the saturation voltage characteristics and turn-off characteristics are inspected. Therefore, the saturation voltage characteristics and turn-off characteristics can be inspected without actually passing a large current. .
Thereby, the quality of the saturation voltage characteristic and the turn-off characteristic can be inspected in an unmounted state before mounting a power module or the like for flowing a large current.

In order to achieve the above object, the present invention provides a second conductivity type base region, a first conductivity type emitter region formed in the base region, and a main surface of the first conductivity type semiconductor wafer, In the method of manufacturing an insulated gate bipolar transistor, in which an insulated gate is provided adjacent to the emitter region, and a second conductivity type collector layer is formed by diffusing impurities on the other main surface side of the semiconductor wafer, a gate voltage is applied to the insulated gate. Measures the electron current when the voltage is applied and the hole current due to the holes injected from the collector layer into the semiconductor wafer, the ratio of the hole current to the collector current obtained by adding the hole current to the electron current, and saturation is predetermined based on the correlation between the respective voltage characteristics and turn-off characteristics, the saturation voltage characteristic and the turn-off characteristics and good The non-defective determination range that determines whether the measured value of the ratio of the hole current to the collector current enters, checks the quality of the saturation voltage characteristics and turn-off characteristics, measurements of the ratio to the non-defective determination range If not, the number of carriers in the collector layer is increased or decreased based on the measured value of the ratio and the size of the non-defective product determination range .

According to the present invention, the electron current when the gate voltage is applied to the insulated gate and the hole current due to the carriers injected from the collector layer into the semiconductor wafer are measured, and the hole with respect to the collector current obtained by adding the hole current to the electron current is measured. Based on the correlation between the current ratio and the saturation voltage characteristics and turn-off characteristics, the saturation voltage characteristics and turn-off characteristics are inspected. Therefore, the saturation voltage characteristics and turn-off characteristics can be inspected without actually passing a large current. .
If the result of the inspection is negative, by adjusting the number of carriers in the collector layer, performance inspection and adjustment according to the result can be performed in the manufacturing process of the insulated gate bipolar transistor, Yield can be improved.

In order to achieve the above object, the present invention provides a test circuit used for measuring the electron current and the hall current in the method for inspecting the insulated gate bipolar transistor or the method for producing the insulated gate bipolar transistor. The same structure having the same structure as that of the insulated gate bipolar transistor and the emitter region of the same structure when a gate voltage is applied to the insulated gate of the same structure. An electron current probe electrode for detecting an electron current flowing through the electrode, and a hole current probe electrode for detecting a hole current flowing outside the emitter region of the same structure in the base region of the same structure , wherein the electron current probe electrode, and the hole current probe Through use electrodes, characterized in that said electron current, and the said hole current is measured.

According to the present invention, by applying a gate voltage to the insulated gate, detecting the electron current from the electron current probe electrode, and detecting the hole current from the hole current probe electrode, the hole current is added to the electron current. The quality of the saturation voltage characteristic and the turn-off characteristic can be inspected based on the correlation between the ratio of the hall current to the added collector current and the saturation voltage characteristic and the turn-off characteristic.

According to the present invention, the electron current when a gate voltage is applied to the insulated gate and the hole current due to carriers injected from the collector layer into the semiconductor layer are measured, and the hole with respect to the collector current obtained by adding the hole current to the electron current is measured. Based on the correlation between the current ratio and the saturation voltage characteristics and turn-off characteristics, the saturation voltage characteristics and turn-off characteristics are inspected. Therefore, the saturation voltage characteristics and turn-off characteristics can be inspected without actually passing a large current. . As a result, it is possible to check whether the saturation voltage characteristic and the turn-off characteristic are good or not in an unmounted state before mounting a power module or the like for flowing a large current.
Further, if the result of the inspection is negative, by adjusting the number of carriers of the collector layer, in the manufacturing process of the insulated gate bipolar transistor, performance inspection and adjustment according to the result can be performed, Yield can be improved.
Also, an insulated gate bipolar transistor, an electrode for an electron current probe for detecting an electron current flowing in the emitter region when a gate voltage is applied to the insulated gate, and a hole current in the base region that flows outside the emitter region are detected. A test circuit having a hole current probe electrode for detecting the electron current, applying a gate voltage to the insulated gate, detecting the electron current from the electron current probe electrode, and generating the hole current from the hole current probe electrode. The quality of the saturation voltage characteristic and the turn-off characteristic can be inspected based on the correlation between the ratio of the hole current to the collector current obtained by adding the hole current to the electron current and the saturation voltage characteristic and the turn-off characteristic.

1 is a partially cut perspective view schematically showing a structure of a power semiconductor device including an IGBT to be a target of performance inspection according to an embodiment of the present invention. It is a figure which shows typically the silicon wafer in which IGBT and TEG were formed. It is a figure which shows the manufacturing process of the power semiconductor device 1 containing thin IGBT. It is a figure which shows the relationship between the number of injection | pouring holes from a P + collector layer to a N- base layer, and a saturation voltage. It is a figure which shows an example of the turn-off current at the time of turn-off, and the collector-emitter voltage. It is a figure which shows the relationship between the number of injection | pouring holes from a P + collector layer to an N- base layer, and a turn-off loss. It is a figure which shows the relationship between (alpha) PNP, saturation voltage, and turn-off loss. It is a figure which shows typically the structure of TEG which is a test pattern of a performance test.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a partially cut perspective view schematically showing the structure of the power semiconductor device 1.
The power semiconductor device 1 includes an IGBT 2 that is a target of performance inspection of the present embodiment, an emitter electrode 21 and a collector electrode 22 that are mounted on the IGBT 2 after the performance inspection.
In the IGBT 2, a p-type P− base region 11 as a second conductivity type base region is selectively striped on the main surface 10 </ b> A side of the n-type N− layer 10 as a first conductivity type semiconductor substrate. An n type N + emitter region 12 of the first conductivity type is selectively formed in the region of the P− base region 11 so as to extend in the same direction as the stripe direction of the P− base region 11. An insulated gate 15 provided with a gate 14 is formed adjacent to the region 12 through an insulating layer 13, and a p-type p-type collector layer of the second conductivity type is formed on the other main surface 10 </ b> B side of the N− layer 10. A P + collector layer 16 is formed. With this configuration, the P + collector layer 16, the N− layer 10, and the P− base region 11 become one PNP type BJT that forms a parasitic thyristor.

A contact opening 18 exposing the N + emitter region 12 is provided in the insulating layer 13 of the IGBT 2 so as to extend in a stripe shape in parallel with the N + emitter region 12.
The emitter electrode 21 is provided so as to cover the main surface 10A side of the IGBT 2 and is in contact with the N + emitter region 12 through the contact opening 18. The collector electrode 22 is provided on the other main surface 10B side (back surface side) of the N− layer 10 (semiconductor substrate) so as to cover the P + collector layer 16.
FIG. 1 shows a state where the contact opening 18 covered with the emitter electrode 21 is exposed so as to be exposed.

  In FIG. 1, one IGBT2 cell is formed on each side of the contact opening 18, and an IGBT2 as a semiconductor chip is configured by a large number of these cells. At the time of manufacturing the IGBT 2, as shown in FIG. 2, a large number of IGBTs 2 are simultaneously formed on the silicon wafer 30 that is a semiconductor substrate (corresponding to the N− layer 10). Further, when manufacturing the IGBT 2, a TEG 40, which is a test circuit for performance inspection of the IGBT 2, is provided on the silicon wafer 30 for each IGBT 2. The TEG 40 is a circuit pattern for measuring αPNP, which will be described later, and the configuration thereof will be described later together with the description of the performance inspection.

By the way, the IGBT is classified into a conventional type and a thin layer type according to the thickness of the P + collector layer 16. In the conventional IGBT, the P + collector layer 16 has a thickness of about 200 μm, whereas the IGBT is a thin layer type IGBT. Then, the P + collector layer 16 has a thickness of about 0.5 μm and is very thin.
These conventional type and thin layer type IGBTs are also different in the manufacturing process. In the conventional type IGBT, an N− base layer or N + layer is formed on the surface of a sub-wafer (thickness of 200 μm or more) having a P + collector layer formed on the back surface. The layer and the N− base layer are epitaxially grown to form a wafer comprising a P + collector layer and an N− base layer. On the other hand, in a thin layer type IGBT, a wafer including a P + collector layer and an N− base layer is formed by ion implantation and heat treatment on the back surface of an N− wafer (thickness of 400 μm or more).
In the present embodiment, since the carrier concentration of the P + collector layer 16 can be easily adjusted according to the result of the performance inspection, a thin layer type IGBT is used as the IGBT 2.

FIG. 3 is a diagram illustrating a manufacturing process of the power semiconductor device 1 including the thin IGBT 2.
First, in manufacturing the IGBT 2, an n-type silicon wafer 30 that is a first conductivity type is used as the silicon wafer 30. Then, on the main surface (front surface) side of the silicon wafer 30, surface structures such as the P-base region 11, the N + emitter region 12, the insulating gate 15, and the emitter electrode 21 shown in FIG. 1 are formed (step S1).
Next, the back surface side of the silicon wafer 30 is ground (back grind) to reduce the thickness of the silicon wafer 30 (step S2). For example, a silicon wafer 30 having a thickness of 400 μm or more is ground to about 100 μm. Then, the back side of the silicon wafer 30 is removed by etching in order to remove a layer in which damage such as strain caused by grinding has occurred (step S3).

Next, the P + collector layer 16 is formed on the back side of the clean silicon wafer 30 after the etching is completed (step S4). The P + collector layer 16 is formed, for example, by ion-implanting ions at a predetermined concentration on the back side of the silicon wafer 30 (step S4A) and then by heat treatment by laser annealing for activation (step S4B).
Then, a performance inspection is performed on the TEG 40 of the silicon wafer 30 (step S5), and a non-defective product determination is performed (step S6). In this performance inspection, the saturation voltage characteristic and the turn-off loss characteristic are inspected in a state where the collector electrode 22 is not provided. The details will be described later.

As a result of the performance inspection, if it is a non-defective product (step S6: Yes), for example, metal is deposited on the back surface of the silicon wafer 30 (that is, the surface of the P + collector layer 16) by vapor deposition or sputtering, and the collector electrode 22 is formed. Form (step S7).
Then, each IGBT 2 is separated by chip dicing of the silicon wafer 30 (step S8), each IGBT 2 is mounted on a tray, and wires and the like are bonded to manufacture the power semiconductor device 1.

  On the other hand, if the result of the performance inspection is not good (step S6: No), since the saturation voltage characteristic and the turn-off loss characteristic depend on the carrier concentration of the P + collector layer 16, ion implantation into the P + collector layer 16 ( By performing step S4A) and heat treatment (step S4B), the carrier concentration of the P + collector layer 16 is increased to adjust the saturation voltage characteristic and the turn-off loss characteristic, and then the performance inspection is performed again in step S5. It will be.

The relationship between the saturation voltage characteristic, the turn-off loss characteristic, and the carrier concentration of the P + collector layer 16 will be described in detail.
The saturation voltage Vce (sat) is proportional to the drift voltage V _Ndrift of the N− layer 10 that is the drift layer when turned on, and this drift voltage V _Ndrift is expressed by the following equation (1).

ただし、式（１）において、Ｄは拡散定数、τはライフタイム、Ｊｃは電流密度、Ｗ_Nはオン状態のＰＮ接合（Ｐ−ベース領域１１とＮ−層１０との接合部）の空乏層幅、ｑは電子の電荷量、ｐ０はＰ＋コレクタ層１６からＮ−層１０への注入ホール数、μ_nは電子移動度、μ_pはホール移動度、ｆ１（τ）、ｆ２（τ）はそれぞれライフタイムの多項式である。

In Equation (1), D is a diffusion constant, τ is a lifetime, Jc is a current density, and W _N is a depletion layer of an on-state PN junction (a junction between the P-base region 11 and the N-layer 10). width, q is the electron charge quantity, p0 is injection hole number into N- layer 10 from the P + collector layer 16, mu _n is the electron mobility, mu _p is the hole mobility, f1 (τ), f2 ( τ) is Each is a lifetime polynomial.

According to equation (1), it can be seen that the drift voltage V _Ndrift is inversely proportional to the number of injected holes p0. Therefore, as shown in FIG. 4, as the number of injection holes p0 increases, the saturation voltage Vce (sat) also decreases. If the number of injection holes p0 is measured, the saturation voltage Vce (sat) is derived (or predicted). It will be possible.
Since the number of injected holes p0 is proportional to the number of carriers in the P + collector layer 16, it can be seen that the saturation voltage characteristic depends on the carrier concentration in the P + collector layer 16. That is, when the saturation voltage characteristic is bad, it can be improved by increasing the carrier concentration of the P + collector layer 16 and increasing the number of carriers.

On the other hand, the turn-off loss Eoff will be described. As shown in FIG. 5, at the time of turn-off, a turn-off current I _off that decays with time flows and a collector-emitter voltage Vce is generated. The turn-off loss Eoff is obtained by time-integrating the product of the turn-off current I _off and the collector-emitter voltage Vce in the turn-off period (from the turn-off until the turn-off current I _off becomes zero). _off is expressed by the following equation (2).

ただし、τ’はＰ＋コレクタ層１６からホールが引き抜かれる時定数、Ｉａ_offはターンオフ電流Ｉ_offの初期値である。

However, τ ′ is a time constant for extracting holes from the P + collector layer 16, and Ia _off is an initial value of the turn-off current I _off .

The initial value Ia _off of the turn-off current is expressed by the following equation (3).

ただし、Ａは定数、αＰＮＰはホール電流／コレクタ電流である。なお、ホール電流はＰ＋コレクタ層１６からＮ−層１０に注入されるキャリアであるホールによる電流であって、Ｎ−層１０からＰ＋コレクタ層１６に移動するキャリアである電子による電子電流と等しく、これらホール電流及び電子電流の和がコレクタ電流となる。

However, A is a constant, and αPNP is a Hall current / collector current. The hole current is a current due to holes that are carriers injected from the P + collector layer 16 to the N− layer 10, and is equal to an electron current due to electrons that are carriers moving from the N− layer 10 to the P + collector layer 16. The sum of the Hall current and the electron current becomes the collector current.

According to these equations (2) and (3), it can be seen that the turn-off current I _off is proportional to the number of injected holes p0. Therefore, as shown in FIG. 6, as the number of injection holes p0 increases, the turn-off loss Eoff also increases. If the number of injection holes p0 is measured, the turn-off loss Eoff can be derived (or predicted).
As described above, since the number of injected holes p0 is proportional to the number of carriers in the P + collector layer 16, it can be seen that the turn-off loss characteristic depends on the carrier concentration in the P + collector layer 16, and when the turn-off loss characteristic is poor, This can be improved by cutting the P + collector layer 16 to reduce the volume and the number of carriers.

  As described above, it can be seen that the saturation voltage Vce (sat) and the turn-off loss Eoff are derived (or predicted) if the number of injected holes p0 is measured. Since the number of injected holes p0 can be obtained indirectly as αPNP indicating the ratio of the hole current Ih to the collector current Ic, by measuring this αPNP, these currents can be obtained without actually passing a large current through the IGBT 2. Performance inspection can be performed.

That is, the saturation voltage Vce (sat) and the turn-off loss Eoff are in a trade-off relationship with each other, and the relationship between these and αPNP is as shown in FIG. Accordingly, since the range of αPNP in which the saturation voltage Vce (sat) and the turn-off loss Eoff are respectively in the non-defective region (hereinafter referred to as the non-defective product determination range K) is uniquely obtained, In the performance test of the IGBT 2, as shown in FIG. 3, the αPNP is measured (step S5A), and it is determined whether or not the product is in the non-defective product determination range K (step S6). A good product can be judged.
As a result of the determination, if αPNP deviates from the non-defective product determination range K, that is, if the saturation voltage characteristic is poor, the process returns to step S4 in FIG. By adjusting the number of carriers by heat treatment, αPNP is adjusted to be within the non-defective product determination range K.
When αPNP deviates from the non-defective product determination range K, that is, when the turn-off loss characteristic is poor, the number of carriers is reduced by reducing the thickness of the P + collector layer 16 by etching or the like, and αPNP is non-defective. Adjustment can be made so as to be within the determination range K.

FIG. 8 is a diagram schematically showing the structure of the TEG 40, which is a test pattern for performance inspection.
The measurement of αPNP at the time of performance inspection is performed on the TEG 40 provided on the silicon wafer 30. As shown in FIG. 8, the TEG 40 has the same structure as the IGBT 2. However, since the electron current Ie and the hole current Ih are measured during the measurement of αPNP, an electron current probe electrode 41 and a hole current probe electrode are used on the surface of the P-base region 11 instead of the emitter electrode 21. An electrode 42 is provided.
The electron current probe electrode 41 is an electrode for detecting the electron current Ie when the gate voltage Vg is applied, and is provided immediately above the N + emitter region 12. The hole current probe electrode 42 is an electrode for detecting a hole current when the gate voltage Vg is applied, and is provided outside the N + emitter region 12 in the P− base region 11. However, a P + semiconductor layer 43 having a high concentration is formed immediately below the Hall current probe electrode 42. In this P + semiconductor layer 43, since the hole carrier density is high, holes easily flow when the Fermi level approaches the valence band, and the hole current probe electrode 42 can detect the hole current Ih.

In the measurement of αPNP at the time of performance inspection (step S5 in FIG. 3), the current probes 50 and 51 are brought into contact with the electron current probe electrode 41 and the hole current probe electrode 42, respectively, and the silicon wafer A collector voltage application probe 52 for applying a collector voltage Vc of a predetermined voltage is brought into contact with the P + collector layer 16 on the back surface of 30.
Then, with the gate voltage Vg of a predetermined volt applied, the collector voltage Vc is changed stepwise between, for example, 0 to 10, and an emitter current is generated in the TEG 40. At this time, the collector electrode 22 is not formed on the surface of the P + collector layer 16, but since the ion implantation and the heat treatment have already been performed, sufficient ohmic contact can be made even with a small current.

  The emitter current is detected by the electron current probe electrode 41 and the hole current probe electrode 42 separately from the electron current Ie and the hole current Ih, and is obtained by adding the electron current Ie and the hole current Ih. Based on the ratio of the current Ic and the hall current Ih, αPNP is calculated for each collector voltage Vc by αPNP = hall current Ih / collector current Ic. The calculation of αPNP is performed by changing the gate voltage Vg stepwise between, for example, 7 to 17 volts. Then, the non-defective product determination is performed based on the average value of αPNPs in each case or whether all αPNPs are included in the non-defective product determination range K.

  As described above, according to the present embodiment, the quality of the saturation voltage characteristic and the turn-off characteristic is inspected based on the correlation between αPNP, which is the ratio of the hole current Ih to the collector current Ic, and the saturation voltage characteristic and the turn-off characteristic. The quality of the saturation voltage characteristic and the turn-off characteristic can be inspected without actually passing a large current through the IGBT 2. As a result, it is possible to inspect whether the saturation voltage characteristic and the turn-off characteristic are good or not in an unmounted state before mounting a power module or the like for flowing a large current to the IGBT 2, and the power module mounting amount when the inspection is defective is wasted. There is nothing.

  In particular, according to the present embodiment, when the result of the performance inspection is negative, the number of carriers in the P + collector layer 16 is adjusted by ion implantation or cutting, so that the performance inspection can be performed in the manufacturing process of the IGBT 2. Since the adjustment according to the inspection result is performed, the defective product can be made non-defective and the yield can be improved.

Further, according to the present embodiment, when manufacturing the IGBT 2, the TEG 40 as a test circuit including the IGBT 2, the structure of the IGBT 2, the electron current probe electrode 41, and the hole current probe electrode 42 is provided on the silicon wafer 30. Configured.
Thus, the gate voltage Vg is applied to the insulated gate 15 of the TEG 40, the electron current Ie is detected from the electron current probe electrode 41, the hole current Ih is detected from the hole current probe electrode 42, and the electron current Ie is detected. The quality of the saturation voltage characteristic and the turn-off characteristic can be inspected based on the correlation between αPNP, which is the ratio of the hole current Ih to the collector current Ic to which the hole current Ih is added, the saturation voltage characteristic and the turn-off characteristic.

  The above-described embodiments are merely examples of the present invention, and can be arbitrarily modified and applied without departing from the spirit of the present invention.

For example, in the above-described embodiment, the case where the saturation voltage characteristic and the turn-off loss characteristic are inspected for the thin-layer IGBT 2 has been described. Similarly, the saturation voltage characteristic and the turn-off loss characteristic for the conventional IGBT 2 are also described. Can be inspected.
For example, in the above-described embodiment, the IGBT 2 has been described as having the first conductivity type n-type and the second conductivity type p-type. However, the present invention is not limited to this, and the first conductivity type is p-type and the second conductivity type. The type may be n-type.
For example, in the above-described embodiment, the non-punch through type (NPT) IGBT has been described. However, the present invention is not limited to this, and the present invention can also be applied to a punch through type (PT).

1 Power Semiconductor Device 2 IGBT (Insulated Gate Bipolar Transistor)
10 N-layer (first conductivity type semiconductor layer, first conductivity type semiconductor wafer)
11 P-base region 12 N + emitter region 13 Insulating layer 14 Gate 15 Insulating gate 16 P + collector layer 21 Emitter electrode 22 Collector electrode 30 Silicon wafer (first conductivity type semiconductor wafer)
40 TEG (test circuit)
41 Electron current probe electrode 42 Hall current probe electrode 43 P + base layer Eoff Turn-off loss Ic Collector current Ie Electron current Ih Hall current K Non-defective product judgment range p0 Number of injected holes Vce (sat) Saturation voltage

Claims (3)

A main surface of the first conductivity type semiconductor layer is provided with a second conductivity type base region, a first conductivity type emitter region formed in the base region, and an insulated gate adjacent to the emitter region, respectively. In an inspection method for an insulated gate bipolar transistor in which a collector layer of a second conductivity type is provided on the other main surface side of the layer,
Measuring an electron current when a gate voltage is applied to the insulated gate, and a hole current due to holes injected from the collector layer into the semiconductor layer;
The saturation voltage characteristic and the turn-off characteristic obtained in advance based on the correlation between the ratio of the hole current to the collector current obtained by adding the hole current to the electron current and the saturation voltage characteristic and the turn- off characteristic are non-defective products. A method for inspecting an insulated gate bipolar transistor, comprising: determining whether a measured value of the ratio of the Hall current to the collector current is in a non-defective product determination range, and inspecting whether the saturation voltage characteristic and the turn-off characteristic are good . A main surface of a first conductivity type semiconductor wafer is provided with a second conductivity type base region, a first conductivity type emitter region formed in the base region, and an insulated gate adjacent to the emitter region, respectively. In the method of manufacturing an insulated gate bipolar transistor in which impurities are diffused on the other main surface side of the wafer to provide a collector layer of the second conductivity type,
Measuring an electron current when a gate voltage is applied to the insulated gate, and a hole current caused by holes injected from the collector layer into the semiconductor wafer;
The saturation voltage characteristic and the turn-off characteristic determined in advance based on the correlation between the ratio of the hole current to the collector current obtained by adding the hole current to the electron current and the saturation voltage characteristic and the turn- off characteristic are non-defective products. To determine whether or not the measured value of the ratio of the Hall current to the collector current enters the non-defective product determination range, inspecting the quality of the saturation voltage characteristics and the turn-off characteristics
Insulated gate bipolar, wherein the number of carriers in the collector layer is increased or decreased based on the measured value of the ratio and the size of the non-defective product determination range when the measured value of the ratio is not within the non-defective product determination range A method for manufacturing a transistor. A test circuit used for measuring the electron current and the hall current in the method for inspecting an insulated gate bipolar transistor according to claim 1 or the method for producing an insulated gate bipolar transistor according to claim 2,
The same structure that is arranged in parallel with the insulated gate bipolar transistor and has the same structure as the insulated gate bipolar transistor,
The same said same structure electronic current probe electrode for detecting the electron current flowing to the emitter region, and said a base region of the same structure when a gate voltage is applied to the insulated gate of the same structure A hole current probe electrode for detecting a hole current flowing outside the emitter region of the structure;
With
The test circuit , wherein the electron current and the hole current are measured through the electron current probe electrode and the hole current probe electrode .

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