JP2025015178A - Manufacturing method of semiconductor device - Google Patents

Abstract

To provide a manufacturing method of semiconductor devices capable of improving the yield by suppressing overdetection while reducing the rejection of defective products to be commercialized by executing more appropriate quality judgment.SOLUTION: After preparing a semiconductor wafer, a device formation process is carried out to form semiconductor elements (S100). Subsequently, the electrical characteristics of each semiconductor device that is to be chipped from the semiconductor wafer are measured (S110). Subsequently, at least one of the areas of any region on the graph of the electrical characteristic waveform obtained by measuring the electrical characteristics and the slope of a line connecting any two points on the graph of the electrical characteristic waveform is defined as a feature, and the feature is calculated (S120). Based on the features and the discriminant, a pass/fail determination is made for each semiconductor device (S130).SELECTED DRAWING: Figure 8

Description

This disclosure relates to a method for manufacturing a semiconductor device, and is particularly suitable for a method for manufacturing a compound semiconductor device using semiconductor materials such as silicon carbide (hereinafter referred to as SiC) and gallium nitride (hereinafter referred to as GaN).

Patent Document 1 discloses a method for manufacturing a semiconductor device in which a crystal defect inspection is performed before an electrical characteristic inspection is performed after a semiconductor element is formed by a semiconductor process. Specifically, an appearance inspection using a laser, that is, a crystal defect inspection by image detection, is performed at the stage where an epitaxial film is grown in advance on a SiC substrate, and crystal defects present in the epitaxial film are detected using a crystal defect inspection device. After the crystal defect inspection, an element structure is formed on the semiconductor wafer and then the wafer is diced into individual semiconductor chips. Semiconductor chips for which no crystal defects were detected in the crystal defect inspection are selected as candidates for good products.

JP 2022-176696 A

Semiconductors, especially compound semiconductors such as SiC and GaN, have a high density of crystal defects and can contain crystal defects known as killer defects that have a negative impact on downstream processes and quality. Such crystal defects must be properly detected and rejected before shipment to prevent them from being used in products.

However, even if crystal defects exist, some crystal defects do not cause problems in practical use, while other crystal defects, even if small, can expand and become killer defects when the product is used, and so image detection based crystal defect inspection is not accurate enough. This can lead to problems such as products that should be rejected being made into products, or overdetection resulting in the rejection of products that do not need to be rejected.

The present disclosure aims to provide a method for manufacturing semiconductor devices that can perform more appropriate quality/failure judgments, reduce the rejection of defective products and commercialization, and reduce overdetection, thereby improving yields.

In one aspect of the present disclosure, a method for manufacturing a semiconductor device includes:
After preparing a semiconductor wafer, a device formation process is performed to form a semiconductor element (S100);
Measuring electrical characteristics of individual semiconductor devices to be chipped from the semiconductor wafer (S110);
calculating at least one of an area of an arbitrary region of a graph of an electrical characteristic waveform obtained by measuring the electrical characteristics and a slope of a line connecting any two points of the graph as a characteristic quantity (S120);
and determining whether each of the semiconductor devices is good or bad based on the characteristic amounts obtained by calculating the characteristic amounts and a discriminant (S130).

In this way, at least one of the area of an arbitrary region of the graph of the electrical characteristic waveform obtained by measuring the electrical characteristics and the slope of the graph of the electrical characteristic waveform is used as a feature, and a pass/fail judgment is made based on the feature and the discriminant. This makes it possible to increase the detection rate of defective products while reducing the overdetection rate. This makes it possible to provide a manufacturing method for semiconductor devices that can more appropriately detect crystal defects that could become killer defects, prevent products from being rejected and commercialized, and reduce overdetection, thereby improving yields.

The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below.

FIG. 1 is a perspective cross-sectional view of a SiC semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is an explanatory diagram of a current path in a SiC semiconductor device. FIG. 4 is an explanatory diagram showing the state of holes and electrons in the vicinity of a built-in diode. FIG. 1 is an explanatory diagram of defect growth caused by BPD near a built-in diode. 1 is a graph showing experimental results of investigating electrical characteristics of drain current Id versus source-drain voltage Vds. 1 is a graph showing the Gini coefficient. FIG. 13 is a diagram showing a case where three nodes are extracted from a graph of an electrical characteristic waveform. FIG. 6B is a graph showing the Gini coefficients normalized for the three nodes extracted as in FIG. 6A. FIG. 13 is a diagram showing an example of a case in which measured feature quantities of each SiC semiconductor device are plotted on a two-axis coordinate system with the two feature quantities being on the x-axis and y-axis, and a discriminant equation for determining whether a product is good or bad is set. 1 is a flowchart of a manufacturing process of a SiC semiconductor device. 13 is a graph showing regions defined by equal straight lines and Lorentz curves described in another embodiment.

Embodiments of the present disclosure will be described below with reference to the drawings. Note that in each embodiment, including the other embodiments described below, parts that are identical or equivalent to each other will be described with the same reference numerals.

First Embodiment
A first embodiment of the present disclosure will be described. In the present embodiment, a SiC semiconductor device using SiC as a semiconductor material will be described as an example of a semiconductor device.

[Configuration of SiC semiconductor device]
The SiC semiconductor device according to this embodiment is formed with an inverted vertical MOSFET having a trench gate structure as shown in FIG. 1 as a semiconductor element. The vertical MOSFET shown in these figures is formed in a cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming a peripheral breakdown voltage structure so as to surround the cell region, but only the vertical MOSFET is shown here. In the following, directions perpendicular to each other as shown in FIG. 1 will be described as the X direction, the Y direction, and the Z direction. Specifically, the width direction of the vertical MOSFET is the X direction, the depth direction of the vertical MOSFET intersecting the X direction is the Y direction, and the thickness direction or depth direction of the vertical MOSFET, i.e., the normal direction to the XY plane, is the Z direction.

1, the SiC semiconductor device uses an n ⁺ type SiC substrate 11 doped with n-type impurities. The SiC substrate 11 constitutes the drain region of a vertical MOSFET. The SiC substrate 11 has an off angle of, for example, 0 to 8° with respect to the (0001) Si-plane, and is doped with a high concentration of n-type impurities such as N (nitrogen) and P (phosphorus).

An n ^- type buffer layer 12 made of SiC constituting a part of the drift layer is formed on the main surface of the SiC substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the SiC substrate 11, and has an n-type impurity concentration between that of the SiC substrate 11 and a low concentration layer 13 described below. In addition, an n ^- type low concentration layer 13 made of SiC constituting a part of the drift layer having a lower concentration than the SiC substrate 11 is formed on the buffer layer 12.

In the cell region, an n-type JFET section 14 that constitutes part of a drift layer made of SiC is formed on the low-concentration layer 13. The low-concentration layer 13 is connected to the JFET section 14 on the side opposite the SiC substrate 11. Furthermore, a p-type deep layer 15 doped with p-type impurities such as Al (aluminum) in addition to the JFET section 14 is formed on the low-concentration layer 13.

The JFET section 14 and the deep layer 15 constitute a saturation current suppression layer, and are both extended in the X direction as the longitudinal direction, and are arranged alternately and repeatedly in the Y direction. In other words, when viewed from the normal direction to the main surface of the SiC substrate 11, at least a portion of the JFET section 14 and the deep layer 15 are each arranged in a multiple line shape, in other words, stripe shape, and are arranged alternately.

Each line-shaped portion of the striped deep layer 15 has a constant width and is spaced at equal intervals, so the p-type impurity concentration is constant in the depth direction.

Furthermore, an n-type current spreading layer 16 that constitutes part of the drift layer made of SiC is formed on the JFET portion 14 and the deep layer 15. The current spreading layer 16 is a layer that allows the current flowing through the channel of the vertical MOSFET to be diffused in the Y direction. It is formed in contact with the tip side of the gate trench 21 in the depth direction, which will be described later, and has a higher n-type impurity concentration than the low concentration layer 13, for example.

In this embodiment, the drift layer is composed of the buffer layer 12, the low concentration layer 13, the JFET section 14, and the current spreading layer 16, but the configuration of the drift layer is arbitrary, and for example, it may be a structure without a buffer layer.

A p-type base region 17 made of SiC is formed on the current spreading layer 16. An n ⁺ type source region 18 made of SiC is formed on the base region 17. The base region 17 has a lower p-type impurity concentration than the deep layer 15. The source region 18 has a higher n-type impurity concentration than the current spreading layer 16.

In addition, a p ⁺ type contact region 19 having a higher p-type impurity concentration than the base region 17 is formed so as to extend from the surface of the source region 18 to the base region 17. In this embodiment, the contact region 19 is configured in a line shape with the Y direction as the longitudinal direction. Furthermore, a p-type coupling layer 20 that connects the base region 17 and the deep layer 15 is formed below the contact region 19. The coupling layer 20 is formed in a line shape with the Y direction as the longitudinal direction together with the contact region 19, and is disposed on both sides of the current spreading layer 16.

The contact region 19 and the coupling layer 20 serve to connect the deep layer 15 and the base region 17 to the source electrode 25 described later in order to fix the deep layer 15 and the base region 17 to the source potential.

The spacing between the contact regions 19 and the coupling layers 20 is arbitrary, but in this embodiment, they are formed on both sides of the trench gate structure described below. The width of the contact regions 19 and the coupling layers 20 is arbitrary, but here they are set to be equal to or less than the spacing between adjacent trench gate structures.

Furthermore, a gate trench 21 is formed with a predetermined width and depth so as to penetrate the source region 18 and the base region 17 and reach the current spreading layer 16. The above-mentioned base region 17 and source region 18 are formed so as to contact the side of this gate trench 21, and the contact region 19 is arranged away from the gate trench 21. The gate trench 21 is formed in a line-shaped layout with the X direction as the width direction, the direction intersecting the longitudinal direction of the JFET section 14 and the deep layer 15, the Y direction as the length direction here, and the Z direction as the depth direction. As shown in FIG. 1, the gate trench 21 is formed in a stripe shape with multiple gate trenches 21 arranged at equal intervals in the X direction, and the base region 17, source region 18, contact region 19, and coupling layer 20 are arranged between each of them.

The portion of the base region 17 located on the side of the gate trench 21 is used as a channel region that connects the source region 18 and the current spreading layer 16 when the vertical MOSFET is in operation, and the inner wall surface of the gate trench 21 including the channel region is covered with a gate insulating film 22. A gate electrode 23 made of doped Poly-Si is formed on the surface of the gate insulating film 22, and the gate insulating film 22 and gate electrode 23 are disposed within the gate trench 21 to form a trench gate structure. In addition, an interlayer insulating film 24 is formed to cover the gate electrode 23.

As shown in FIG. 1, a source electrode 25 and the like are formed on the surface of the source region 18 and the surface of the gate electrode 23 via an interlayer insulating film 24. The source electrode 25 is made of a plurality of metals, for example, Ni/Al. At least the n-type SiC, specifically the part that contacts the source region 18 and the gate electrode 23 in the case of n-type doping, is made of a metal that can make ohmic contact with n-type SiC among the plurality of metals. At least the p-type SiC, specifically the part that contacts the contact region 19 is made of a metal that can make ohmic contact with p-type SiC among the plurality of metals. The source electrode 25 is electrically insulated from the SiC part by being formed on the interlayer insulating film 24, but is electrically in contact with the source region 18 and the contact region 19 through a contact hole 24a formed in the interlayer insulating film 24.

On the other hand, a drain electrode 26 electrically connected to the SiC substrate 11 is formed on the back side of the SiC substrate 11. With this structure, an n-channel type inverted trench gate structure vertical MOSFET is formed. A cell region is formed by arranging multiple such vertical MOSFETs. Then, although not shown, a peripheral breakdown voltage structure such as a guard ring is formed to surround the periphery of the cell region, thereby forming a SiC semiconductor device.

In a SiC semiconductor device with such a configuration, a built-in diode is formed in the vertical MOSFET by a pn junction between the low concentration layer 13, the JFET portion 14, etc. and the deep layer 15, the coupling layer 20, etc.

The above is an example of the basic configuration of the SiC semiconductor device according to this embodiment. This SiC semiconductor device is used, for example, in an inverter circuit for driving a three-phase motor that uses a vertical MOSFET as a switching element.

As described above, the SiC semiconductor device has a structure in which a vertical MOSFET with a trench gate structure and an internal diode composed of a pn junction are provided in the cell region. The drift layer including the SiC substrate 11 and the buffer layer 12 contains wavy dislocations having dislocation lines on the (0001) plane, called basal plane dislocations (hereinafter referred to as BPDs). Defects caused by these BPDs can occur in the SiC semiconductor device.

2, an equivalent circuit of the SiC semiconductor device is shown as a circuit configuration having a vertical MOSFET 30 and a built-in diode 40, and when the vertical MOSFET 30 is on, an on-current I _ON is generated from the drain electrode 26 to the source electrode 25. Note that "S", "D", and "G" in FIG. 2 correspond to the source electrode 25, the drain electrode 26, and the gate electrode 23, respectively. Specifically, when a predetermined voltage, for example, 20 V, is applied to the gate electrode 23, a channel region is formed on the surface of the base region 17 that is in contact with the gate trench 21, and the on-current I _ON flows as a drain current Id flowing between the source electrode 25 and the drain electrode 26.

Thereafter, when the SiC semiconductor device is turned off, a reverse bias is applied to the SiC semiconductor device, and the built-in diode 40 functions as a freewheeling diode, and a freewheeling current I _OFF flows through the built-in diode 40 as a drain current Id. At this time, as shown in FIG. 3A, holes diffused from the p-type layer side to the n-type layer side of the pn junction constituting the built-in diode 40 recombine with electrons in the n-type layer. Since the recombination energy between the holes and electrons is large, the BPD 50 expands and the SSF 60 is generated, as shown in FIG. 3B. The SSF 60 expands as the current stress on the built-in diode 40 accumulates. Since the SSF 60 occupies a larger area than the BPD 50, it hinders the on-current I _ON and the freewheeling current I _OFF . Since the SSF 60 expands in response to the current stress on the built-in diode 40, the electrical characteristics after operation are degraded compared to the electrical characteristics immediately after manufacture, that is, before the SSF 60 is generated.

Therefore, it is desirable to be able to reject SiC semiconductor devices that contain BPD50 that can be expanded to SSF60, which would prevent the product from achieving the desired electrical characteristics, during quality determination.

However, as mentioned above, the accuracy of crystal defect inspection using image detection is insufficient, and problems can arise such as products that should be rejected being manufactured into products, or overdetection resulting in the rejection of products that do not need to be rejected.

Therefore, we investigated the detection of crystal defects by electrical property testing, but the standard judgment that a value such as leakage current, which is generally performed in an electrical property test, is compared with a threshold value, and if the value does not exceed the threshold value, the product is good, and if it does exceed the threshold value, the product is defective, was insufficient. In other words, each value such as leakage current obtained by an electrical property test is obtained as an absolute value, but the magnitude of the absolute value does not necessarily match the presence of a killer defect that adversely affects the subsequent process or quality when the SiC semiconductor device is actually used. For example, even if the leakage current exceeds the threshold value during an electrical property test, the leakage current may not increase much when the SiC semiconductor device is actually used, and the SiC semiconductor device may be durable for practical use. In addition, even if BPD50 exists, it may not expand to SSF60 to the extent that it has an adverse effect. In such cases, it is difficult to accurately detect a SiC semiconductor device having a killer defect by simply comparing the absolute value of the leakage current during an electrical property test with a threshold value, and accurate judgment of good or bad could not be performed.

As a result of further intensive research, it was found that the electrical characteristics of a SiC semiconductor device having a killer defect may be characterized by a specific waveform shape, and that if this specific waveform can be detected with high accuracy, it is possible to accurately detect a SiC semiconductor device having a killer defect. It was confirmed that there are various specific waveform shapes, but here, as an example, the electrical characteristics of the drain current Id that flows as a leakage current relative to the source-drain voltage Vds under reverse bias will be described.

In an experiment, the electrical characteristics of the drain current Id versus the source-drain voltage Vds and the electrical characteristics of a SiC semiconductor device that had a killer defect after practical use were investigated. In order to obtain a large number of actual device data, a large number of SiC semiconductor devices manufactured using multiple SiC wafers were prepared, and the desired source-drain voltage Vds was applied with a gate voltage Vg = 0 V and a source voltage Vs = 0 V, and the drain current Id was measured. The source-drain voltage Vds was applied instantaneously, creating an instantaneous reverse bias state, and the drain current Id that flowed at that time was measured with a tester. The source-drain voltage Vds can be set arbitrarily, but here it was set to six levels: 100 V, 400 V, 600 V, 900 V, 1100 V, and 1200 V. Figure 4 shows the results. In the following explanation, each point that divides the graph of the electrical characteristics waveform shown in Figure 4 into multiple regions, here the relationship between the value of the drain current Id and each source-drain voltage Vds, is called a node. Additionally, the nodes are called nodes 1 to 6 in ascending order of the applied source-drain voltage Vds.

Furthermore, after this experiment, a durability test was performed on the SiC semiconductor device used in the experiment, in which a source-drain voltage Vds of 1000V was applied for a long time, for example, a test under conditions under which BPD50 can expand to SSF60. Then, after the durability test, an electrical characteristic test was performed again to check whether the electrical characteristics of the SiC semiconductor device had deteriorated compared to immediately after manufacture, thereby determining whether a killer defect existed. For example, if the on-current I _ON flowing as the drain current I d when the vertical MOSFET 30 is turned on is less than a threshold, it is considered that the BPD50 has expanded to SSF60 and the electrical characteristics have deteriorated. For this reason, if the electrical characteristics of the SiC semiconductor device have deteriorated compared to immediately after manufacture, it was determined that a killer defect existed.

As shown in Figure 4, a large amount of actual device data was obtained, and the electrical characteristics showed that the drain current Id gradually increased as the source-drain voltage Vds increased. However, the change in the drain current Id between each node was not constant, and the slope also varied.

On the other hand, when the electrical characteristics of the SiC semiconductor device in which the killer defect was present were examined before the durability test, the characteristics were as shown by the line L _kill in Fig. 4. In the following description, the electrical characteristic waveform of the SiC semiconductor device in which it was determined that the killer defect was present is referred to as an NG waveform. In Fig. 4, the line L _kill is the NG waveform. Moreover, the electrical characteristic waveform of the SiC semiconductor device in which it was not determined that the killer defect was present is referred to as a pass-quality waveform. In Fig. 4, waveforms other than the line L _kill are pass-quality waveforms.

When comparing the NG waveform with the good waveform, there was no clear relationship between the magnitude of the drain current Id at each node, and it was not possible to distinguish between the NG waveform and the good waveform based only on the magnitude of the drain current Id. This means that it is difficult to accurately detect SiC semiconductor devices that have killer defects simply by comparing the absolute value of the leakage current during electrical characteristics testing with a threshold value, and it is not possible to accurately determine whether the device is good or bad.

For example, when only the magnitude of the drain current Id is considered for node 2, the drain current Id of a SiC semiconductor device that has not been determined to have a killer defect may be greater than that of a SiC semiconductor device that has been determined to have a killer defect. For this reason, simply comparing the absolute value of the leakage current with a threshold value may result in overdetection, in which a killer defect is determined to exist when it does not. Conversely, a killer defect may be determined to not exist when it does exist.

Therefore, in this embodiment, a discriminant equation obtained from the NG waveform is calculated based on the actual device data, and when an electrical characteristic test is performed on the manufactured SiC semiconductor device, the good/bad judgment is made based on the discriminant equation. The method for calculating this discriminant equation is described below.

As described above, the electrical characteristic waveform is obtained as the relationship between the source-drain voltage Vds and the drain current Id. The electrical characteristic waveform can be selected by capturing the electrical characteristic waveform as the area and the slope of the line and quantifying the area. Here, the Gini coefficient, which has been widely used in statistics, is applied to quantifying the waveform shape by interpreting it geometrically. The Gini coefficient in the following explanation is not a statistical measure, but a unique measure that uses the above-mentioned geometric interpretation to quantify the waveform shape. Furthermore, the electrical characteristic waveform graph is divided into regions, and the "Gini coefficient" is calculated for each region, and the "slope" of the line connecting any two points on the graph is calculated, and a specific electrical characteristic waveform is accurately selected by applying this to linear discrimination on two axes.

The "Gini coefficient" is generally a feature that numerically expresses "bias" or "unevenness," but here we use the Gini coefficient to quantify the shape information of the electrical characteristic waveform. As shown in Figure 5, the Gini coefficient is defined as S1/(S1+S2), the ratio of area S1 to the sum S1+S2 of the area S1 surrounded by the Lorentz curve and the uniform straight line drawn using two cumulative relative frequencies and the area S2 of the area below the uniform straight line. The smaller the difference between the Lorentz curve and the uniform straight line and the closer the Gini coefficient is to 0, the smaller the "bias" or "unevenness." Also, the larger the difference between the Lorentz curve and the uniform straight line and the closer the Gini coefficient is to 1, the greater the "bias" or "unevenness."

In this embodiment, the electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id is a Lorentz curve. In addition, the line y=x when the source-drain voltage Vds on the x-axis (horizontal axis) and the drain current Id on the y-axis (vertical axis) are normalized to 1 for the maximum value and 0 for the minimum value, respectively, is the equal line. When the Lorentz curve is used as the electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id, the Lorentz curve is a curve whose y coordinate value is always lower than the equal line, that is, a curve that satisfies the relationship y<x. In order to quantify the waveform information of the electrical characteristic waveform, the area S1 of the crescent-shaped portion between the Lorentz curve and the equal line is calculated. When normalized, the area of the right-angled triangle formed by the equal line and the y-axis is 1/2, so the area S1 is 1/2 the ratio S1/(S1+S2). The area S1 is doubled to 2×S1, which represents the Gini coefficient.

The Gini coefficient is calculated by selecting at least three consecutive nodes from among the multiple nodes. Specifically, the node with the smallest absolute value of the electrical characteristics among the at least three consecutive nodes, in this case the node with the smallest source-drain voltage Vds and drain current Id, is taken as the MIN node, and the node with the largest values is taken as the MAX node. Then, the source-drain voltage Vds and drain current Id of the MIN node are normalized to 0, and the source-drain voltage Vds and drain current Id of the MAX node are normalized to 1. This results in a Gini coefficient graph that depicts a Lorentz curve represented by the three or more consecutive selected nodes, and an equal straight line where y = x.

For example, a case where the Gini coefficient is calculated using all six nodes will be described. In this case, as shown in FIG. 4, the source-drain voltage Vds of the MAX node was 1200V, and the drain current Id at that time was 5×10 ⁻⁴ A. Also, the source-drain voltage Vds of the MIN node was 100V, and the drain current Id at that time was 1.5×10 ⁻⁹ A. In this case, the source-drain voltage Vds of each node is subtracted by 100, and then multiplied by 1/(1200-100) to obtain the standardized source-drain voltage Vds. Similarly, the drain current Id of each node is subtracted by 1.5×10 ⁻⁹ , and then multiplied by 1/(5×10 ⁻⁴ -1.5×10 ⁻⁹ ) to obtain the standardized drain current Id. The above conversion is performed when evaluating the waveform shape on a linear axis, and when evaluating the waveform shape on a logarithmic axis, a logarithmic function is applied before performing the normalization calculation. For example, when evaluating the drain current Id axis as a logarithmic axis, normalization is performed after setting the drain current of the MAX node to -3.3 and the drain current of the MIN node to -8.8.

The same applies when calculating the Gini coefficient by selecting a smaller number of nodes rather than all six nodes. For example, FIG. 6A shows the case where three consecutive nodes, node 2 to node 4, are selected. In this case, node 2 is the MIN node, and node 4 is the MAX node. Then, normalization is performed by setting the source-drain voltage Vds and drain current Id of node 2, which is the MIN node, to 0, and the source-drain voltage Vds and drain current Id of node 4, which is the MAX node, to 1. This results in a graph of the Gini coefficient, as shown in FIG. 6B, which shows a Lorentz curve represented by nodes 2 to 4 and an equal straight line where y = x.

When three or more nodes are selected from the six nodes from node 1 to node 6, the number of combinations is four when there are three nodes, three when there are four, two when there are five, and one when there are six, for a total of ten combinations. In addition, while FIG. 4 above shows an electrical characteristic waveform in which the drain current Id on the vertical axis is represented on a logarithmic scale, it is also possible to use an electrical characteristic waveform represented on a linear scale in which the drain current Id on the vertical axis is shown as a linear value. Since the Gini coefficient can be calculated for each of the two patterns, the logarithmic scale and the linear scale, the Gini coefficient can be calculated for a total of 20 combinations, ten for each pattern.

"Slope" is also used to quantify the shape information of the electrical characteristic waveform. "Slope" here refers to the gradient of the line connecting any two points on the electrical characteristic waveform graph, two nodes in this case, and is expressed as the change in drain current Id on the vertical axis (x-axis) relative to the change in source-drain voltage Vds on the horizontal axis (y-axis).

When any two nodes are selected from the six nodes, node 1 to node 6, the number of combinations is ₆ C ₂ = 15. In addition, while the electrical characteristic waveform shown in Fig. 4 has the drain current Id on the vertical axis represented on a logarithmic scale, it is also possible to use an electrical characteristic waveform represented on a linear scale showing the drain current Id on the vertical axis as a linear value. Since the slope can be calculated for each of the two patterns, the logarithmic scale and the linear scale, the slope can be calculated for 15 patterns for each pattern, for a total of 30 combinations.

In this way, by calculating the "Gini coefficient" and "slope," a total of 50 feature quantities can be created, with 30 and 20 for each. From these 50 feature quantities, two feature quantities that can accurately determine whether a product is good or bad are selected, and these two feature quantities are set on the vertical and horizontal axes to perform linear discrimination. The standard for accurate quality/bad judgment is a high detection rate for NG products and a low overdetection rate, where good products are mistakenly detected as NG products. A discriminant equation used for linear discrimination is calculated to satisfy this. More specifically, it is preferable to set the discriminant equation so that a profit can be made by considering the expected expenses such as repair costs when NG products are mistakenly shipped and the loss when products are not shipped due to overdetection, and looking at the difference between the expenses and losses.

Specifically, for all the SiC semiconductor devices used in the experiment, 50 types of feature quantities, here the Gini coefficient and the slope, and data on whether the product was a good product or a bad product are stored in an electronic computer as learning data. As the electronic computer, for example, a microcomputer equipped with a CPU, ROM, RAM, I/O, etc. can be applied. Next, any two of the 50 types of feature quantities are selected, and a two-axis coordinate system is set with one being the x-axis and the other being the y-axis. Then, from all the feature quantities of each stored SiC semiconductor device, feature quantities identical to the two previously selected feature quantities are extracted, and points corresponding to the values of each feature quantity are plotted in the two-axis coordinate system. In the case of selecting any two of the 50 types of feature quantities, a two-axis coordinate system of 1225 combinations of ₅₀ C ₂ is set, and feature quantities corresponding to the two axes are extracted and plotted from all the feature quantities of each stored SiC semiconductor device. At this time, it is made possible to determine whether each plot was a good product or a bad product.

Figure 7 shows an example of this. Here, the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 on the logarithmic scale and the slope of the line connecting the two selected nodes 3 and node 5 on the linear scale are selected as two feature quantities. The former is set as the horizontal axis and the latter as the vertical axis. In this two-axis coordinate system, points corresponding to the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 in each SiC semiconductor device and the slope of the line connecting the two selected nodes 3 and node 5 on the linear scale are plotted. Based on this, a straight line L1 is drawn in the two-axis coordinate system, which indicates a high detection rate of NG products and a low overdetection rate of good products, and the following discriminant is calculated based on the equation y = -ax + b that indicates the straight line L1.

(Equation 1)
y ≧ −ax + b
In Equation 1, "-a" indicates the slope of line L1, and "b" indicates the intercept of line L1.

In other words, the feature on the horizontal axis, here the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 on a logarithmic scale, is denoted as x, and the feature on the vertical axis, here the slope of the line connecting the two selected nodes 3 and node 5 on a linear scale, is denoted as y. Then, when each feature is substituted for x and y in the discriminant, if y≧-ax+b is satisfied, the product is determined to be good, and y<-ax+b, and if the discriminant is not satisfied, the product is determined to be NG.

The discriminant set in this way can be calculated using only arithmetic operations and logarithmic operations based on the actual device data. Therefore, compared to the case of performing good/bad judgment by machine learning, it is possible to calculate the discriminant by simple calculations and can be easily implemented. Of course, the discriminant used for linear discrimination may be a formula showing a nonlinear curve, etc., instead of a formula showing the straight line L1. However, by using a formula showing the straight line L1, it is possible to make it simpler. And, by the good/bad judgment based on the discriminant, it is possible to increase the detection rate of NG products while reducing the overdetection rate. Therefore, it is possible to more appropriately detect crystal defects caused by killer defects, suppress rejection and commercialization, and manufacture highly reliable SiC semiconductor devices. It is also possible to suppress overdetection and improve yield.

As described above, a discriminant equation can be obtained, which can be used to determine whether a SiC semiconductor device is good or bad. Next, a method for manufacturing a SiC semiconductor device that includes such a good or bad determination will be described.

The SiC semiconductor device shown in FIG. 1 is manufactured according to the manufacturing process flowchart shown in FIG. 8.

First, in step S100, a device formation process is performed to form a semiconductor element. Specifically, after preparing a SiC wafer that constitutes the SiC substrate 11, the buffer layer 12 and the low concentration layer 13 are formed in sequence by epitaxial growth. Then, a mask (not shown) that opens the area where the JFET section 14 is to be formed is formed on the surface of the low concentration layer 13, and n-type impurities are ion-implanted to form the JFET section 14. Then, a mask that opens the area where the deep layer 15 is to be formed is formed on the surfaces of the JFET section 14 and the low concentration layer 13, and p-type impurities are ion-implanted to form the deep layer 15.

Next, a current spreading layer 16 made of SiC is epitaxially grown on the low concentration layer 13, the JFET section 14, and the deep layer 15. This forms a drift layer consisting of the buffer layer 12, the low concentration layer 13, the JFET section 14, and the current spreading layer 16. In addition, a mask that opens up the area where the coupling layer 20 is to be formed is placed, and then p-type impurities are ion-implanted to form the coupling layer 20.

Furthermore, a p-type impurity layer is epitaxially grown on the current spreading layer 16 and the coupling layer 20 to form the base region 17, and then an n-type impurity layer is epitaxially grown on the base region 17 to form the source region 18. Next, a mask that opens the area where the contact region 19 is to be formed is placed, and then the contact region 19 is formed by ion implantation of p-type impurities. In this manner, each impurity layer is formed.

After this, a trench gate structure is constructed by performing a process of forming a gate trench 21 by anisotropic etching, a process of forming a gate insulating film 22, and a process of forming a gate electrode 23. In addition, a process of depositing an interlayer insulating film 24, a process of forming a contact hole 24a, a process of forming a source electrode 25 and gate wiring, and a process of forming a drain electrode 26 on the back side of the SiC substrate 11 are performed, and then the substrate is divided into individual chips by dicing. In this way, the chips of the SiC semiconductor device of this embodiment are manufactured.

Next, in step S110, the electrical characteristics of each chip of the SiC semiconductor device are measured. The electrical characteristics are measured using a tester or the like. In the case of this embodiment, the electrical characteristics of the drain current Id versus the source-drain voltage Vds are measured by changing the source-drain voltage Vds in multiple steps. For example, as described above, the source-drain voltage Vds is changed in six steps of 100V, 400V, 600V, 900V, 1100V, and 1200V, and the drain current Id is measured.

Furthermore, in step S120, data on the measurement results of the electrical characteristics is input to an inspection device (not shown). Then, in the inspection device, feature quantities of the electrical characteristics are calculated based on the measurement results of the electrical characteristics. At this time, it is sufficient to calculate only the feature quantities used for determining whether the product is good or bad, that is, the feature quantities used for linear discrimination.

As described above, a discriminant equation that has a high detection rate for defective products and a low overdetection rate for non-defective products is calculated based on a combination of various feature quantities obtained in advance from data on a large number of actual products. This discriminant equation is also stored in the inspection device. For this reason, the feature quantities used for linear discrimination are also known by the inspection device, and are calculated from the measurement results of electrical characteristics.

For example, if the Gini coefficient calculated by selecting five consecutive nodes, node 2 to node 6, on the logarithmic scale shown in Figure 7 and the slope of the line connecting the two selected nodes, node 3 and node 5, on the linear scale, are the features used in the discriminant, then they are calculated. Of course, it is possible to calculate all 50 feature amounts described above and extract the feature amount to be used in the discriminant from among them, but since the feature amounts to be used in the discriminant are known in advance on the inspection device side, the calculation load can be reduced by calculating only the necessary feature amounts.

In the next step S130, a pass/fail judgment is performed. Specifically, for each SiC semiconductor device, the two calculated feature quantities are substituted for x and y in the discriminant y≧-ax+b as the x-axis and y-axis values in a two-axis coordinate system. If the discriminant satisfies the equation, the device is judged as a pass/fail product, and if y<-ax+b and the discriminant is not satisfied, the device is judged as a fail/fail product. SiC semiconductor devices judged as fail/fail products by this pass/fail judgment are rejected and disposed of, while SiC semiconductor devices judged as pass/fail products are moved to a process for shipping as products.

By using this type of quality judgment based on a discriminant, it is possible to increase the detection rate of defective products while reducing the overdetection rate. Therefore, more appropriate quality judgment can be performed and defective products can be rejected, preventing products that should be rejected from being commercialized, and enabling the manufacture of highly reliable SiC semiconductor devices. It is also possible to improve yield by suppressing overdetection.

Other Embodiments
Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

For example, in the above embodiment, an electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id when a reverse bias is applied while the vertical MOSFET is off is used to extract the feature amount, but other electrical characteristic waveforms may be used. As one example, an electrical characteristic waveform showing the relationship between the gate voltage Vg and the drain current Id when the vertical MOSFET 30 is turned on by applying a gate voltage Vg may be used. Also, an electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id when the vertical MOSFET 30 is turned on may be used.

Furthermore, in the above embodiment, six points were used to measure the electrical characteristics, but three or more points may be sufficient. Also, the Gini coefficient and the slope were used as the feature quantities, but only one of them may be used, or other parameters may be used. For example, the Gini coefficient is an example of a case in which the graph of the electrical characteristics waveform is divided into regions partitioned by node, and the area of each divided region is used as the feature quantity, but other areas divided in this way can also be used as feature quantities.

Specifically, the Gini coefficient is the area S1 of the crescent-shaped portion between the equal straight line and the Lorentz curve, i.e., the graph of the electrical characteristic waveform, between the nodes, and corresponds to the sum of the areas of the regions obtained by dividing the crescent-shaped portion into individual nodes. In other words, the area S1 is calculated as the sum of the differences between the areas Sa1 to Sa5 shown by solid line hatching in FIG. 9 and the areas Sb1 to Sb5 shown by dashed line hatching. In other words, the area S1 is the sum of the difference between the area Sa1 of the right-angled isosceles triangle between node 1 and node 2 and the area Sb1 of the right-angled triangle, and the difference between the areas Sa2 to Sa5 of the trapezoids between adjacent nodes among nodes 2 to 6 and the areas Sb2 to Sb5 of the trapezoids.

In contrast to this, instead of the sum of the divided areas, the area of the divided regions themselves, for example the area obtained by dividing the crescent-shaped portion for each node, for example the difference between area Sa1 and area Sb1, can be used as the feature. Also, the areas Sb1 to Sb5 of the portions other than the crescent-shaped portion for each node can be used as the feature.

In the above embodiment, two of the multiple feature amounts are selected, one is set as the x-axis and the other as the y-axis, and a discriminant equation for linear discrimination between the two selected axes is set to determine whether the feature amount is good or bad. In contrast, instead of a two-axis coordinate, three of the multiple feature amounts may be selected, one as the x-axis, the other as the y-axis, and the remaining one as the z-axis, and a discriminant equation for the three selected axes may be set to determine whether the feature amount is good or bad. In that case, points corresponding to the three feature amounts are plotted on the three-axis coordinate, and the discriminant equation in the three-axis coordinate may be calculated.

In the above embodiment, a SiC semiconductor device in which a semiconductor element is formed using SiC as a semiconductor material has been described as an example, but the present disclosure can also be applied to semiconductor devices made of other semiconductor materials such as GaN and Si, not limited to SiC. However, since compound semiconductors such as SiC and GaN have a particularly high density of crystal defects, and crystal defects can become killer defects, it is particularly suitable to apply the present disclosure to semiconductor devices that use compound semiconductors as semiconductor materials.

In addition, in the above embodiment, a vertical MOSFET 30 is used as an example of a semiconductor element formed in a semiconductor device, but the present disclosure can also be applied to semiconductor devices in which other semiconductor elements, such as IGBTs, are formed.

11...SiC substrate, 12...buffer layer, 13...low concentration layer, 14...JFET section, 15...deep layer, 16...current spreading layer, 17...base region, 18...source region, 19...contact region, 20...connection layer, 21...gate trench, 22...gate insulating film, 23...gate electrode, 24...interlayer insulating film, 24a...contact hole, 25...source electrode, 26...drain electrode, 30...vertical MOSFET, 40...built-in diode

Claims (5)

After preparing a semiconductor wafer, a device formation process is performed to form a semiconductor element (S100);
Measuring electrical characteristics of individual semiconductor devices to be chipped from the semiconductor wafer (S110);
calculating at least one of an area of an arbitrary region of a graph of an electrical characteristic waveform obtained by measuring the electrical characteristics and a slope of a line connecting any two points of the graph as a characteristic quantity (S120);
and determining whether each of the semiconductor devices is good or bad based on the characteristic amount obtained by calculating the characteristic amount and a discriminant (S130). In the calculation of the feature amount, the graph is divided into a plurality of regions, and at least one of an area of each divided region and a slope of a line connecting any two points on the graph is calculated as the feature amount;
2. The method of claim 1, wherein, in the pass/fail judgment, two of the feature amounts calculated in each of the regions are selected, and a formula for linearly discriminating the two selected feature amounts with respect to two axes is set as the discriminant, and the pass/fail judgment is made based on the two selected feature amounts and the discriminant. The method for manufacturing a semiconductor device according to claim 2, wherein the feature amount is calculated by dividing the graph into a plurality of regions and calculating the area of each region as the feature amount, and the area is calculated as the Gini coefficient. The method for manufacturing a semiconductor device according to claim 3, wherein each point that divides the graph into a plurality of regions is taken as a node, three or more nodes are selected from the plurality of nodes, the node with the smallest absolute value of the electrical characteristic among the selected three or more nodes is taken as the MIN node, the node with the largest absolute value of the electrical characteristic is taken as the MAX node, and the electrical characteristic at the MIN node is normalized to 0 and the electrical characteristic at the MAX node is normalized to 1, and a value twice the area enclosed by an equal straight line on the two axes where y = x and a Lorentz curve that connects the selected three or more nodes is calculated as the characteristic amount of the area of each region. The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the discriminant is calculated as a formula for discriminating between a good product and a bad product from actual device data obtained by calculating the feature amount for a plurality of the semiconductor devices manufactured in advance and inspecting the semiconductor devices to determine whether the semiconductor devices are good products or bad products.

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