JP5708550B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a SiC semiconductor device capable of realizing an ohmic junction of electrodes formed in a semiconductor element composed of silicon carbide (hereinafter referred to as SiC) and a method for manufacturing the same.

  Conventionally, when a vertical power device is formed on an SiC substrate, an ohmic that reduces the contact resistance between the SiC substrate and the drain electrode when forming an electrode for connecting the device to an electric circuit or the like, particularly a drain electrode. It is desired to form an electrode.

  On the other hand, Patent Document 1 proposes a method of obtaining an ohmic electrode by irradiating a SiC substrate with laser light. The process of forming the back electrode when this method is used is performed as follows. First, after forming an electrode on the surface side of the SiC substrate on which the vertical element is formed, the surface of the SiC substrate is protected by a resin film, and the back surface of the SiC substrate is thinned. Then, ion implantation of impurities is performed on the back surface of the SiC substrate, and laser light irradiation is performed on the back surface of the SiC substrate. Thereafter, an electrode is formed by forming a metal thin film on the back surface of the SiC substrate. Thereby, it becomes possible to make ohmic contact between the impurity layer activated by laser light irradiation and the electrode.

  However, there is a problem that ion implantation of impurities must be performed on the back surface of the SiC substrate, and the ion implantation process itself is expensive in addition to the expensive ion implantation apparatus. Therefore, it is desirable to obtain an ohmic electrode without performing an ion implantation process.

  As this method, Patent Document 2 proposes a method of irradiating a laser beam after forming a metal layer on a SiC substrate. The process of forming the back electrode using this method is performed as follows. First, an electrode is formed on the surface side of a SiC substrate on which a vertical element is formed. Next, the surface of the SiC substrate is protected by the resin film, and the back surface of the SiC substrate is thinned. Then, a metal layer is formed on the back surface of the SiC substrate, and the metal contained in the metal layer and the Si contained in the SiC layer are silicidated to form a metal silicide by irradiating the metal layer with laser light. Thus, ohmic contact can be achieved.

JP 2002-289550 A JP 2008-135611 A

  However, it is difficult to obtain a sufficiently low resistance ohmic junction simply by forming a metal silicide without performing impurity ion implantation, and it is desirable to obtain a further low resistance ohmic junction.

  In view of the above, an object of the present invention is to provide a method of manufacturing a SiC semiconductor device capable of obtaining a further low-resistance ohmic junction without performing impurity ion implantation. It is another object of the present invention to provide a SiC semiconductor device capable of further ohmic contact.

In order to achieve the above object, in the first aspect of the present invention, a semiconductor substrate (1) having a main surface (1a) and a back surface (1b) opposite to the main surface and made of single crystal SiC is prepared. A step of forming a metal thin film (12) made of an electrode material containing impurities at a mass concentration of 10 ppm to 2% in a portion of the semiconductor substrate where the first electrode is to be formed; Thereafter, by irradiating the metal thin film with laser light (50), the metal atoms constituting the metal thin film and impurities contained in the metal thin film are simultaneously diffused, and the metal atoms and carbon and silicon constituting the semiconductor substrate are diffused. An electrode forming step of forming a first electrode (11) including a metal reaction layer in which impurities are incorporated by forming a metal reaction layer obtained by reacting at least one of them. It is.

  Through such a process, impurities contained in the metal thin film are diffused, and a first electrode having a metal reaction layer made of metal silicide or metal carbide by reaction between metal atoms constituting the metal thin film and SiC is formed. it can. Such a first electrode can obtain an ohmic junction having a structure in which impurities are taken into the metal reaction layer in the junction with the semiconductor substrate. This makes it possible to obtain a low-resistance ohmic junction without performing impurity ion implantation.

As in the invention described in claim 2, an impurity layer (14) and an electrode made of SiC containing impurities at a mass concentration of 10 ppm to 2% in a portion of the semiconductor substrate where the first electrode is formed Even if laser annealing is performed by laminating a metal layer (15) made of a material and irradiating the impurity layer and the metal layer with laser light (50), the same effect as in claim 1 is obtained. be able to.

  According to the fourth aspect of the present invention, the impurity contained in the first electrode is taken into the bonding portion of the first electrode with the semiconductor substrate, and the metal atoms constituting the first electrode are the semiconductor substrate. The metal reaction layer is formed by reacting with at least one of carbon and silicon constituting the metal, and the diffusion depth of impurities and the diffusion depth of metal atoms in the metal reaction layer are the same. It is characterized by that.

  As described above, since the impurities are incorporated into the metal reaction layer included in the first electrode, not only the resistance is reduced by metal silicide or metal carbide, but also the resistance is reduced by impurity diffusion. it can. Since the depth of impurity diffusion is equal to the depth of diffusion of metal atoms in the metal silicide or metal carbide constituting the metal reaction layer, impurity diffusion is uniformly performed in the metal reaction layer. It will be in the state. For this reason, the resistance of the metal reaction layer can be further reduced. Therefore, a further low resistance ohmic junction can be obtained.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

It is sectional drawing of the SiC semiconductor device provided with the vertical power MOSFET concerning 1st Embodiment of this invention. It is sectional drawing which showed the formation process of the drain electrode in the manufacturing process of the SiC semiconductor device shown by FIG. It is the figure which showed the mode of the target in a sputtering device. It is a figure showing distribution of impurity diffusion and diffusion of metal atoms, (a) is a figure showing the distribution of this embodiment, (b) is when forming a metal thin film after ion implantation and activation of impurities FIG. It is a comparison figure of contact resistance. It is the figure which showed the mode of the target in the sputtering device demonstrated in the modification of 1st Embodiment. It is sectional drawing which showed a part of formation process of the drain electrode in the manufacturing process of the SiC semiconductor device concerning 2nd Embodiment of this invention. It is sectional drawing which showed a part of formation process of the drain electrode demonstrated in the modification of 2nd Embodiment. It is sectional drawing which showed a part of formation process of the drain electrode demonstrated in the modification of 2nd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. In the present embodiment, an SiC semiconductor device provided with a planar MOSFET (vertical power MOSFET) as a semiconductor element will be described as an example. This device is suitable when applied to, for example, an inverter.

As shown in FIG. 1, an n ⁺ type semiconductor substrate (hereinafter referred to as an n ⁺ type substrate) 1 has an upper surface as a main surface 1a and a lower surface opposite to the main surface 1a as a back surface 1b. It will be. The thickness of the n ⁺ type substrate 1 is 350 μm, for example. The n type impurity concentration of the n ⁺ type substrate 1 is, for example, 1 × 10 ¹⁷ to 1 × 10 ¹⁸ cm ⁻³ . On the main surface 1a of the n ⁺ -type substrate 1, n ⁺ -type substrate 1 n is constituted by SiC having a lower dopant concentration than ^- -type epitaxial layer (hereinafter, n ^- referred -type epitaxial layer) 2 is stacked Has been.

A p ⁻ type base region 3 a and a p ⁻ type base region 3 b having a predetermined depth are formed in a predetermined region in the surface layer portion of the n ⁻ type epi layer 2 so as to be separated from each other. Further, deep base layers 30a and 30b having a partially increased thickness are formed in the p ⁻ type base regions 3a and 3b. The deep base layers 30a and 30b are formed in portions that do not overlap with the n ⁺ type source regions 4a and 4b, and the deep base layers 30a and 30b are formed thick in the p ⁻ type base regions 3a and 3b. The formed portion has a higher impurity concentration than the thin portion where the deep base layer 30a is not formed.

Such deep base layers 30a and 30b reduce the thickness of the n ⁻ type epi layer 2 below the deep base layers 30a and 30b (the n ⁺ type semiconductor n ⁺ type substrate 1 and the deep base layers 30a and 30b The electric field strength can be increased and the avalanche breakdown can be facilitated.

Further, p ^- is a predetermined region in the surface layer of type base region 3a, the p ^- type base region shallower n ⁺ -type source region 4a than 3a is formed, p ^- in a predetermined region in the surface layer of type base region 3b An n ⁺ type source region 4b shallower than the p ⁻ type base region 3b is formed.

Further, n ⁻ -type layer 5a and n ⁺ -type layer 5b are formed on the surface of n ⁻ -type epi layer 2 and p ⁻ -type base regions 3a and 3b between n ⁺ -type source region 4a and n ⁺ -type source region 4b. An n ⁻ -type SiC layer 5 made of is extended. That is, the n ⁻ type SiC layer 5 is arranged so as to connect the source regions 4a and 4b and the n ⁻ type epi layer 2 at the surface portions of the p ⁻ type base regions 3a and 3b. This n ⁻ -type SiC layer 5 functions as a channel forming layer on the device surface during device operation. Hereinafter, the n ⁻ -type SiC layer 5 is referred to as a surface channel layer.

The dopant concentration of the n ⁻ type layer 5a disposed on the p ⁻ type base regions 3a and 3b in the surface channel layer 5 is as low as about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ^−3. And the concentration is lower than the dopant concentration of the n ⁻ -type epi layer 2 and the p ⁻ -type base regions 3a and 3b. Thereby, low on-resistance is achieved.

Further, contact recesses 6a and 6b are formed on the surface portions of the p ⁻ type base regions 3a and 3b and the n ⁺ type source regions 4a and 4b.

A gate insulating film (silicon oxide film) 7 is formed on the upper surface of the surface channel layer 5 and the upper surfaces of the n ⁺ -type source regions 4a and 4b. Further, a gate electrode 8 is formed on the gate insulating film 7. The gate electrode 8 is covered with an insulating film 9. A silicon oxide film is used as the insulating film 9. A source electrode 10 is formed thereon, and the source electrode 10 is in contact with the n ⁺ type source regions 4a and 4b and in contact with the p ⁻ type base regions 3a and 3b through the recesses 6a and 6b. A drain electrode 11 is formed on the back surface 1 b of the n ⁺ type substrate 1. The drain electrode 11 is in ohmic contact with the back surface 1 b of the n ⁺ type substrate 1.

In the case of this embodiment, the drain electrode 11 corresponds to the first electrode of the present invention, and the portion of the n ⁺ type substrate 1 where the drain electrode 11 is formed is the first electrode of the semiconductor substrate. It becomes a part.

  Next, a method for manufacturing the vertical power MOSFET shown in FIG. 1 will be described with reference to FIGS. However, since the basic manufacturing method of the vertical power MOSFET according to the present embodiment is the same as the conventional method, only the method for forming the drain electrode 11 different from the conventional method will be described. In FIG. 2, the device structure of the vertical power MOSFET is not shown for simplification.

First, in the step shown in FIG. 2A, a device in which the device shown in FIG. 1 is formed on the surface side of the n ⁺ type substrate 1, that is, a device in which the source electrode 10 excluding the drain electrode 11 is formed is prepared. Then, the n ⁺ type substrate 1 is thinned, and the thickness of the n ⁺ type substrate 1 is set to 350 μm, for example.

Next, in the step shown in FIG. 2B, a metal thin film 12 containing impurities is formed on the back surface 1 b of the n ⁺ type substrate 1. The metal thin film 12 is configured by using one or both of electrode materials for forming metal silicide or metal carbide with SiC such as nickel (Ni) or molybdenum (Mo). When both electrode materials are used, a mixed material of each electrode material can be used, or a thin film made of each electrode material can be used as a laminated film. The content rate of the contained impurities is set to, for example, 10 ppm to 2% so as to achieve an impurity concentration level that can be expected by ion implantation. In the present embodiment, an n-channel vertical power MOSFET is taken as an example of the semiconductor element, so that the drain electrode 11 is ohmic-bonded to the n ⁺ -type substrate 1, that is, n-type SiC. For this reason, the metal thin film 12 is made to contain phosphorus (P) which becomes an n-type impurity.

For example, as shown in FIG. 3, an electrode material containing impurities is arranged as a target 13 in a sputtering apparatus and sputtering is performed using the target 13, so that impurities are formed on the back surface 1 b of the n ⁺ -type substrate 1. A metal thin film 12 containing can be formed. When the metal thin film 12 is composed of only one of electrode materials for forming metal silicide and metal carbide, the target 13 may be prepared by mixing impurities into the electrode material. Further, in the case of using both of them, the target 13 may be a mixture of impurities mixed with each electrode material or a laminate of layers mixed with impurities in each electrode material.

  Although the case where the metal thin film 12 containing impurities is formed by sputtering has been described here, the metal thin film 12 containing impurities may be formed by any method such as vapor deposition, plating, or CVD. I do not care. In the case of sputtering, the content ratio of impurities in the target 13 and the content ratio of the formed metal thin film 12 are equivalent, so the content ratio of impurities in the target 13 may be 10 ppm to 2%.

2C, laser annealing is performed by irradiating the metal thin film 12 with laser light (electrode formation process). Specifically, the laser beam 50 is scanned on the back surface 1b of the n ⁺ -type substrate 1, and the laser beam 50 is preferably irradiated only on the portion where the metal thin film 12 is formed by scanning or masking. As a result, a metal atom (for example, Ni or Mo) constituting the metal thin film 12 is reacted with Si or C constituting the n ⁺ type substrate 1 to form a metal silicide or metal carbide as shown in FIG. A drain electrode 11 having a metal reaction layer configured in (1) can be formed. At the same time, the impurities contained in the metal thin film 12 are also diffused and taken into the metal reaction layer. The depth of impurity diffusion and the depth of diffusion of metal atoms when the metal reaction layer is formed are substantially the same. Further, the distribution of these diffusions is similar, and as shown in FIG. 4A, impurities and metal atoms are diffused up to, for example, about 200 to 300 nm, and the concentration after diffusion is similarly diffused. The peak positions of are almost identical. As a reference, as shown in FIG. 4B, an impurity is ion-implanted into the back surface 1b of the n ⁺ -type substrate 1, a metal thin film not containing the impurity is formed, and laser irradiation is performed to obtain an ohmic junction. In this case, however, the impurity diffusion depth and the metal atom diffusion depth are different, and the distribution is also different.

When only one electrode material that forms silicide or carbide with SiC as the metal thin film 12 is used, the metal reaction layer included in the drain electrode 11 is either a metal silicide or a metal carbide layer. It consists of only one. When both electrode materials are used, the drain electrode 11 becomes a metal reaction layer containing both metal silicide and metal carbide. When both electrode materials are used, as described above, a mixed material of each electrode material can be used, or a thin film made of each electrode material can be used as a laminated film. In any case, the metal atoms constituting the metal thin film 12 and the impurities contained in the metal thin film 12 are simultaneously diffused to the back surface 1b side of the n ⁺ type substrate 1 by laser light irradiation, and the impurity diffusion and the metal atoms The diffusion depth is almost the same, and the distribution is almost the same.

As described above, the vertical power MOSFET shown in FIG. 1 is completed. Then, by such a process, the impurity contained in the metal thin film 12 is diffused, and the drain electrode has a metal reaction layer made of metal silicide or metal carbide by the reaction between the metal atoms constituting the metal thin film 12 and SiC. 11 can be formed. Such a drain electrode 11 can obtain an ohmic junction having a structure in which impurities are taken into the metal reaction layer in the junction with the back surface 1b of the n ⁺ type substrate 1. This makes it possible to obtain a low-resistance ohmic junction without performing impurity ion implantation.

Further, when the drain electrode 11 is formed by the manufacturing method as in the present embodiment, impurities are taken into the metal reaction layer included in the drain electrode 11. For this reason, not only resistance reduction by metal silicide or metal carbide but also resistance reduction by impurity diffusion can be realized. The depth of impurity diffusion is equal to the depth of diffusion of metal atoms in the metal silicide or metal carbide constituting the metal reaction layer, and the impurity diffusion is uniformly performed in the metal reaction layer. It becomes a state. For this reason, the resistance of the metal reaction layer can be further reduced. Therefore, a further low resistance ohmic junction can be obtained. In particular, the diffusion of impurities and the diffusion of metal atoms in the metal reaction layer have the same distribution at the junction between the drain electrode 11 of this embodiment and the back surface 1b of the n ⁺ -type substrate 1, and the metal reaction layer The resistance can be further reduced.

Through experiments, the contact resistance at the junction between the drain electrode 11 formed by the manufacturing method of the present embodiment and the back surface 1b of the n + type substrate 1 was examined. In addition, for comparison, the case where there is no ion implantation or laser annealing (case 1), the case where activation is performed by ion implantation and laser annealing (case 2), and the case where silicidation is performed by laser annealing. For (Case 3), the contact resistance was similarly examined. As a result, as shown in FIG. 5, the contact resistance decreased in both cases 2 and 3 as compared with case 1, but in case 2 it was 4.56 ± 1.58 × 10 ^−4. Omega · cm ² or so, it was the case 3, ^{4.11 ± 1.01 × 10 -4 Ω ·} cm 2 or so. On the other hand, according to the manufacturing method of this embodiment, the contact resistance was reduced to about 2.35 ± 1.30 × 10 ⁻⁴ Ω · cm ² . This also shows that the drain electrode 11 manufactured by the manufacturing method as in the present embodiment can be made to have a low resistance ohmic junction.

(Modification of the first embodiment)
In contrast to the first embodiment, dual sputtering may be performed in which two targets 13 of an electrode material containing impurities are provided for sputtering. For example, as shown in FIG. 6, if sputtering is performed with one target 13a as Ni containing impurities and the other target 13b as Mo containing impurities, two kinds of electrode materials are mixed. A metal thin film 12 containing impurities can be formed.

(Second Embodiment)
A second embodiment of the present invention will be described. In this embodiment, the laser annealing method is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment. Therefore, only the parts different from the first embodiment will be described.

As shown in FIG. 7, in this embodiment, instead of the metal thin film 12 containing the impurity described in the first embodiment, an impurity layer 14 in which impurities are mixed in the SiC layer and a metal layer 15 that is an electrode material. A structure in which and are stacked is applied. The impurity layer 14 is formed, for example, by growing a SiC layer in an atmosphere containing an impurity serving as a dopant. The metal layer 15 is formed on the surface of the impurity layer 14 by sputtering, vapor deposition, plating, CVD, or the like. Even if laser annealing is performed by irradiating laser light on such a laminated structure of the impurity layer 14 and the metal layer 15, impurities in the impurity layer 14 and metal atoms constituting the metal layer 15 Can be simultaneously diffused to the back surface 1b side of the n ⁺ type substrate 1. For this reason, when metal atoms constituting the metal layer 15 react with Si or C constituting the n ⁺ type substrate 1 or the impurity layer 12 to form a metal reaction layer constituted by metal silicide or metal carbide, Impurities are taken into the metal reaction layer.

Therefore, the junction location between the drain electrode 11 and the back surface 1b of the n ⁺ type substrate 1 can have the same structure as in the first embodiment. For this reason, even if laser annealing is performed using a laminated structure of the impurity layer 14 and the metal layer 15 as in the present embodiment, the same effect as in the first embodiment can be obtained.

  When the impurity layer 14 is formed separately from the metal layer 15 as in the present embodiment, the impurity diffusion distribution and the metal atom distribution are shifted, but the depth after diffusion is substantially the same. Impurities are uniformly taken into the reaction layer. Therefore, the same effect as that of the first embodiment can be obtained.

(Modification of the second embodiment)
In the second embodiment, the impurity layer 14 is formed on the back surface 1b of the n ⁺ -type substrate 1, but as shown in FIG. 8, the impurity layer 14 is formed so as to be sandwiched between the metal layers 15. Also good. Alternatively, the impurity layer 14 may be formed on a part of the back surface 1b of the n ⁺ type substrate 1 and the back surface 1b of the n ⁺ type substrate 1 and the metal layer 15 may be in contact with each other. For example, as shown in FIG. 9, the impurity layer 14 can be formed in a stripe shape. In this manner, the region in which the impurity layer 14 is formed has a structure in which impurities are taken into the metal reaction layer formed of metal silicide or metal carbide, and the region in which the impurity layer 14 is not formed has metal silicide. Or a metal reaction layer consisting of only metal carbide. Thereby, the ohmic characteristics can be adjusted as appropriate.

(Other embodiments)
In each of the above embodiments, the vertical power MOSFET has been described as an example. However, this is merely an example, and the present invention can also be applied to a SiC semiconductor device including other semiconductor elements such as a diode and an IGBT. Is possible. That is, the present invention can be applied to any SiC semiconductor device provided with a first electrode that performs ohmic contact with a semiconductor element formed on a semiconductor substrate. . Also in this case, the laser beam irradiation may be performed in a region where at least the first electrode that performs ohmic junction is formed in the SiC semiconductor device.

  In addition to Ni and Mo, metals such as titanium (Ti) and tungsten (W) can be employed as the material for the metal thin film 12 and the metal layer 15.

1 n ⁺ type substrate 1a main surface 1b back surface 10 source electrode 11 drain electrode (first electrode)
12 Metal thin film containing impurities 13 Target 14 Impurity layer 15 Metal layer 50 Laser light

Claims (4)

A semiconductor substrate (1) having a main surface (1a) and a back surface (1b) opposite to the main surface and made of single crystal silicon carbide, and a first electrode (ohmic contact with the semiconductor substrate) 11) a method for manufacturing a silicon carbide semiconductor device comprising:
Preparing the semiconductor substrate;
Forming a metal thin film (12) composed of an electrode material containing impurities at a mass concentration of 10 ppm to 2% in a portion of the semiconductor substrate where the first electrode is formed;
After forming the metal thin film, the metal thin film is irradiated with a laser beam (50), thereby simultaneously diffusing the metal atoms constituting the metal thin film and impurities contained in the metal thin film, Electrode formation for forming the first electrode including the metal reaction layer in which the impurities are incorporated by forming a metal reaction layer obtained by reacting at least one of carbon and silicon constituting the semiconductor substrate And a method for manufacturing a silicon carbide semiconductor device, comprising: a step. A semiconductor substrate (1) having a main surface (1a) and a back surface (1b) opposite to the main surface and made of single crystal silicon carbide, and a first electrode (ohmic contact with the semiconductor substrate) 11) a method for manufacturing a silicon carbide semiconductor device comprising:
Preparing the semiconductor substrate;
An impurity layer (14) made of silicon carbide containing impurities at a mass concentration of 10 ppm to 2% and a metal layer made of an electrode material (on the portion of the semiconductor substrate where the first electrode is formed) 15) and laminating
After laminating the impurity layer and the metal layer, the impurity layer and the metal layer are irradiated with laser light (50), whereby the metal atoms constituting the metal layer and the impurities contained in the impurity layer are reduced. Simultaneously diffusing and forming a metal reaction layer in which the metal atoms and at least one of carbon and silicon constituting the semiconductor substrate and the impurity layer are reacted to form the metal reaction in which the impurities are incorporated. Forming a first electrode including a layer, and a method for manufacturing a silicon carbide semiconductor device.   The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein in the step of laminating the impurity layer and the metal layer, the impurity layer is formed in a stripe shape. A semiconductor substrate (1) having a main surface (1a) and a back surface (1b) opposite to the main surface and made of single crystal silicon carbide, and a first electrode (ohmic contact with the semiconductor substrate) 11) a silicon carbide semiconductor device comprising:
Of the first electrode, the junction with the semiconductor substrate is doped with impurities contained in the first electrode, and the metal atoms constituting the first electrode are carbon atoms constituting the semiconductor substrate. And a metal reaction layer formed by reacting with at least one of silicon, and the diffusion depth of the impurity and the diffusion depth of the metal atom in the metal reaction layer are the same. A silicon carbide semiconductor device.

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