JP5706275B2 - Diode, semiconductor device and MOSFET - Google Patents

Description

  The present invention relates to a diode, a semiconductor device, and a MOSFET.

Techniques for improving reverse recovery characteristics of PN diodes and reducing switching loss have been developed. Patent Document 1 discloses an MPS diode in which a PIN diode and a Schottky diode are combined. In the technique of Patent Document 1, by reducing the size of the p anode region to the reach through limit, hole injection from the p anode region to the n ⁻ drift region is suppressed, and switching loss is reduced. Patent Document 2, p anode region and the n ^- between the drift region n ^- than the drift region PIN diode having a n barrier region having a high concentration n-type impurity are disclosed. In the technique of Patent Document 2, injection of holes from the p anode region to the n ⁻ drift region is suppressed by the n barrier region, and switching loss is reduced.

JP 2003-163357 A JP 2000-323488 A

When the Schottky junction is formed between the anode electrode and the n ⁻ drift region (or n barrier region), the operating characteristics of the diode change according to the temperature at the interface of the Schottky junction. When the Schottky junction interface is formed on the semiconductor substrate on which the diode is formed, if the semiconductor substrate generates heat and becomes high temperature, the Schottky junction interface also becomes high temperature, and the operating characteristics of the diode greatly change. . A technology that can reduce switching loss in a diode with a structure that is hardly affected by the temperature rise of a semiconductor substrate due to heat generation is expected.

  In this specification, the technique which solves said subject is provided. The present specification discloses a technique that can realize a reduction in switching loss in a diode with a structure that is hardly affected by the temperature rise of a semiconductor substrate due to heat generation.

  The diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, and an anode region made of a second conductivity type semiconductor. And an anode electrode. The diode includes a barrier region made of a first conductivity type semiconductor having a higher concentration than the drift region, which is formed between the drift region and the anode region. In the diode, the barrier region is electrically connected to the anode electrode via an external rectifying element. In the diode, the forward voltage drop of the rectifying element is smaller than the built-in voltage of the pn junction between the anode region and the barrier region.

  In the above diode, when a forward bias is applied between the anode electrode and the cathode electrode, a forward current flows through the rectifying element. As a result, the potential difference between the barrier region and the anode electrode becomes substantially equal to the voltage drop at the rectifying element. Since the voltage drop at the rectifying element is sufficiently smaller than the built-in voltage of the pn junction between the anode region and the barrier region, injection of holes from the anode region to the drift region is suppressed.

  Next, when the voltage between the anode electrode and the cathode electrode is switched from the forward bias to the reverse bias, the reverse current is limited by the rectifying element, and the reverse current is limited by the pn junction between the anode region and the barrier region. In the above diode, since the injection of holes from the anode region to the drift region is suppressed when a forward bias is applied, the reverse recovery current is small and the reverse recovery time is short. According to the above diode, switching loss can be reduced without performing lifetime control of the drift region.

  In the above diode, when a reverse bias is applied between the anode electrode and the cathode electrode, the electric field is shared not only by the rectifier element but also by a depletion layer extending from the pn junction interface between the anode region and the barrier region. Is done. Thereby, the electric field concerning a rectifier is reduced. According to the above diode, the withstand voltage against reverse bias can be improved.

  Further, in the above diode, the rectifying action is realized by an external rectifying element with respect to the electrical connection between the anode electrode and the barrier region. In general, when a rectifying action is realized by a Schottky junction interface, the operating characteristics are greatly affected by the temperature of the Schottky junction interface. In the case where the Schottky junction interface is formed on the semiconductor substrate where the diode is formed, when the semiconductor substrate generates heat and becomes high temperature, the Schottky junction interface also becomes high temperature and the operating characteristics change. On the other hand, in the above diode, since the rectifying element is provided outside, the operating characteristics do not change even when the semiconductor substrate on which the diode is formed generates heat and becomes high temperature. According to the above diode, the switching loss can be reduced with a structure that is hardly affected by the temperature rise of the semiconductor substrate due to heat generation.

  The external rectifying element described above may be disposed at any location as long as it is not above the semiconductor substrate on which the diode is formed. For example, the external rectifying element may be formed on a semiconductor substrate different from the semiconductor substrate on which the diode is formed, and may be connected to the anode electrode and the barrier region through a wiring.

  In addition, the barrier region in the above diode may be composed of a single semiconductor region having a uniform impurity concentration, or may be composed of a plurality of semiconductor regions having different impurity concentrations.

  The diode preferably further includes an electric field progress prevention region made of a second conductivity type semiconductor and formed between the barrier region and the drift region.

  In the above diode, when a reverse bias is applied between the anode electrode and the cathode electrode, the reverse current is limited by the pn junction between the drift region and the electric field progress prevention region. According to the above diode, it is possible to reduce a leakage current when a reverse bias is applied.

  In the above diode, when a reverse bias is applied between the anode electrode and the cathode electrode, not only the rectifying element but also a depletion layer extending from the interface of the pn junction between the anode region and the barrier region, a drift region, The electric field is also shared at the pn junction interface between the electric field progress prevention regions. Thereby, the electric field applied to the rectifying element and the electric field applied to the pn junction between the anode region and the barrier region are reduced. According to the above diode, the withstand voltage against reverse bias can be further improved.

  In the above diode, it is preferable that a trench extending from the anode region to the drift region is formed, and a trench electrode covered with an insulating film is formed inside the trench.

  In the above diode, when a reverse bias is applied between the anode electrode and the cathode electrode, an electric field concentration occurs at a location near the tip of the trench electrode inside the drift region, whereby an electric field applied to the rectifying element, The electric field applied to the pn junction interface between the anode region and the barrier region is reduced. According to the above diode, the withstand voltage against reverse bias can be further improved.

  The diode preferably further includes a cathode short region made of a second conductivity type semiconductor partially formed in the cathode region.

  In the above diode, when a forward bias is applied between the anode electrode and the cathode electrode, the presence of the cathode short region suppresses the injection of electrons from the cathode region to the drift region. Thereby, the reverse recovery current when switching from the forward bias to the reverse bias can be further reduced, and the reverse recovery time can be further shortened. According to the above diode, the switching loss can be further reduced.

  The present specification further discloses a semiconductor device in which the above diode and IGBT are integrated. In the semiconductor device, the IGBT includes a collector electrode, a collector region made of a second conductivity type semiconductor, a second drift region made of a low concentration first conductivity type semiconductor, which is continuous from the drift region, A body region made of a second conductivity type semiconductor; an emitter region made of a first conductivity type semiconductor; an emitter electrode; and an insulation film for the body region between the emitter region and the second drift region. A gate electrode is provided so as to face each other. In the semiconductor device, the IGBT includes a second barrier region formed between the second drift region and the body region and made of a first conductivity type semiconductor having a concentration higher than that of the second drift region. Yes. In the semiconductor device, the second barrier region is electrically connected to the emitter electrode through an external second rectifying element. In the semiconductor device, the forward voltage drop of the second rectifying element is smaller than the built-in voltage of the pn junction between the body region and the second barrier region.

  In the semiconductor device described above, both the diode and the IGBT parasitic diode have a structure that is not easily affected by the temperature rise of the semiconductor substrate due to heat generation, and can reduce switching loss and improve the withstand voltage against reverse bias.

  The external second rectifying element described above may be disposed at any location as long as it is not above the semiconductor substrate on which the IGBT is formed. For example, the external rectifying element may be formed on a semiconductor substrate different from the semiconductor substrate on which the IGBT is formed, and may be connected to the emitter electrode and the second barrier region through a wiring.

  Note that the second barrier region in the IGBT of the semiconductor device described above may be composed of a single semiconductor region having a uniform impurity concentration, or may be composed of a plurality of semiconductor regions having different impurity concentrations. .

  The semiconductor device preferably further includes a second electric field progress prevention region made of a second conductivity type semiconductor and formed between the second barrier region and the second drift region.

  In the semiconductor device described above, the withstand voltage against reverse bias can be further improved and the leakage current during reverse bias can be reduced for the IGBT parasitic diode. In addition, since the current flowing from the collector electrode to the emitter electrode is suppressed by the pn junction between the electric field progress prevention region and the drift region when the IGBT is driven, the saturation current of the IGBT can be reduced.

  The present specification further discloses a MOSFET. The MOSFET includes a drain electrode, a drain region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, a body region made of a second conductivity type semiconductor, and a first conductivity. A source region made of a semiconductor of a type, a source electrode, and a gate electrode facing the body region between the source region and the drift region with an insulating film interposed therebetween. The MOSFET includes a barrier region made of a first conductivity type semiconductor having a higher concentration than the drift region, which is formed between the drift region and the body region. In the MOSFET, the barrier region is electrically connected to the source electrode through an external rectifying element. In the MOSFET, the forward voltage drop of the rectifying element is smaller than the built-in voltage of the pn junction between the body region and the barrier region.

  According to the above-described MOSFET, it is possible to reduce the switching loss of the parasitic diode and improve the withstand voltage against the reverse bias with a structure that is hardly affected by the temperature rise of the semiconductor substrate due to heat generation.

  The external rectifying element described above may be disposed at any location as long as it is not above the semiconductor substrate on which the MOSFET is formed. For example, the external rectifying element may be formed on a semiconductor substrate different from the semiconductor substrate on which the MOSFET is formed, and may be connected to the source electrode and the barrier region through a wiring.

  The barrier region in the MOSFET may be composed of a single semiconductor region having a uniform impurity concentration, or may be composed of a plurality of semiconductor regions having different impurity concentrations.

  The MOSFET preferably further includes an electric field progress prevention region made of a second conductivity type semiconductor and formed between the barrier region and the drift region.

  In the MOSFET described above, the withstand voltage against reverse bias can be further improved, and the leakage current at the time of reverse bias can be reduced.

  According to the technology disclosed in this specification, it is possible to realize a reduction in switching loss in a diode with a structure that is hardly affected by the temperature rise of the semiconductor substrate due to heat generation.

FIG. 3 is a diagram schematically illustrating a configuration of a diode 2 according to the first embodiment. FIG. 6 is a diagram schematically showing a configuration of a diode 32 of Example 2. FIG. 6 is a diagram schematically showing a configuration of a diode 42 of Example 3. FIG. 6 is a diagram schematically showing a configuration of a diode 52 of Example 4. FIG. 6 is a diagram schematically showing a configuration of a diode 62 of Example 5. FIG. 6 is a diagram schematically illustrating a configuration of a modification of the diode 2 according to the first embodiment. FIG. 6 is a diagram schematically showing a configuration of a modified example of a diode 32 of Example 2. FIG. 10 is a diagram schematically illustrating a configuration of a modified example of the diode 42 of the third embodiment. FIG. 10 is a diagram schematically showing a configuration of a semiconductor device 72 of Example 6. FIG. 10 is a diagram schematically showing a configuration of a semiconductor device 82 of Example 7. FIG. 10 schematically shows a configuration of a semiconductor device 102 according to an eighth embodiment. FIG. 10 is a diagram schematically illustrating a configuration of a semiconductor device 162 according to an embodiment 9; FIG. 10 is a diagram schematically showing a configuration of a semiconductor device 172 of Example 10. FIG. 15 is a diagram schematically showing a configuration of a semiconductor device 182 of Example 11. FIG. 16 is a diagram schematically showing a configuration of a semiconductor device 202 of Example 12. FIG. 16 is a diagram schematically showing a configuration of a semiconductor device 232 of Example 13. FIG. 16 is a diagram schematically showing a configuration of a semiconductor device 242 of Example 14. FIG. 16 is a diagram schematically showing a configuration of a semiconductor device 252 of Example 15.

(Example 1)
As shown in FIG. 1, the diode 2 of the present embodiment is formed using a silicon semiconductor substrate 4. The semiconductor substrate 4 includes an n ⁺ cathode region 6 that is a high concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region, and an n-type. An n barrier region 12 that is a semiconductor region and a p anode region 14 that is a p-type semiconductor region are sequentially stacked. In this embodiment, for example, phosphorus is added as an impurity to the n-type semiconductor region, and boron is added as an impurity to the p-type semiconductor region. In this embodiment, the impurity concentration of the n ⁺ cathode region 6 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ], and the impurity concentration of the n buffer region 8 is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [ cm ⁻³ ], the impurity concentration of the n ⁻ drift region 10 is about 1 × 10 ¹² to 1 × 10 ¹⁵ [cm ⁻³ ], and the impurity concentration of the n barrier region 12 is 1 × 10 ¹⁵ to 1 ×. 10 ¹⁸ is approximately [cm ^-3], the impurity concentration of the p-anode region 14 is approximately ^{1 × 10 16 ~1 × 10 19} [cm -3]. The thickness of the n barrier region 12 is about 0.5 to 3.0 [μm].

A plurality of n-pillar regions 16 that are n-type semiconductor regions are formed on the upper surface of the semiconductor substrate 4 at a predetermined interval. The impurity concentration of the n pillar region 16 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ]. The n pillar region 16 is formed so as to penetrate the p anode region 14 and reach the upper surface of the n barrier region 12. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval. The impurity concentration of the p ⁺ contact region 18 is about 1 × 10 ¹⁷ to 1 × 10 ²⁰ [cm ⁻³ ].

A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 4. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. The cathode electrode 20 is connected to the cathode terminal 21.

A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 4. The anode electrode 22 is joined to the p anode region 14 and the p ⁺ contact region 18 by an ohmic junction. The anode electrode 22 is connected to the anode terminal 23.

  On the upper surface of the semiconductor substrate 4, the insulating film 11 is formed at a location where the anode electrode 22 is not formed. A relay electrode 13 that penetrates the insulating film 11 and reaches the upper surface of the n pillar region 16 is formed on the upper surface of the insulating film 11. The relay electrode 13 is joined to the n pillar region 16 by an ohmic junction. The relay electrode 13 is connected to the anode terminal 23 via a rectifying element 15 provided outside the semiconductor substrate 4.

  The rectifying element 15 allows a forward current from the anode 15a to the cathode 15b and limits a reverse current from the cathode 15b to the anode 15a. The anode 15a of the rectifying element 15 is connected to the anode terminal 23 via the wiring 17a. The cathode 15b of the rectifying element 15 is connected to the relay electrode 13 via the wiring 17b. In this embodiment, the rectifying element 15 is a Schottky barrier diode. The rectifying element 15 may be other than a Schottky barrier diode as long as the forward voltage drop is lower than the built-in voltage of the pn junction between the p anode region 14 and the n barrier region 12. Good. For example, a germanium pn diode or a heterojunction diode may be used as the rectifying element 15.

The operation of the diode 2 will be described. When a forward bias is applied between the anode terminal 23 and the cathode terminal 21, a forward current flows from the anode terminal 23 to the n pillar region 16 through the rectifying element 15. Since the n pillar region 16 and the n barrier region 12 have substantially the same potential, the potential difference between the n barrier region 12 and the anode electrode 22 is substantially equal to the voltage drop in the rectifying element 15. Since the voltage drop at the rectifying element 15 is sufficiently smaller than the built-in voltage of the pn junction between the p anode region 14 and the n barrier region 12, the p ⁺ contact region 18 and the p anode region 14 move to the n ⁻ drift region 10. Hole injection is suppressed. Between the anode terminal 23 and the cathode terminal 21, the wiring 17a, the rectifying element 15, the wiring 17b, the relay electrode 13, the n pillar region 16, the n barrier region 12, the n ⁻ drift region 10, the n buffer region 8, and the n ⁺ cathode A forward current flows through the region 6.

Next, when the voltage between the anode terminal 23 and the cathode terminal 21 is switched from the forward bias to the reverse bias, the reverse current passing through the n-pillar region 16 is limited by the rectifying element 15, and between the p-anode region 14 and the n-barrier region 12. The pn junction limits the reverse current through the p anode region 14. As described above, in the diode 2 of this embodiment, the injection of holes from the p ⁺ contact region 18 and the p anode region 14 to the n ⁻ drift region 10 is suppressed when a forward bias is applied. Low current and short reverse recovery time. According to the diode 2 of the present embodiment, the switching loss can be reduced without performing lifetime control of the n ⁻ drift region 10.

  In the diode 2 of this embodiment, when a reverse bias is applied between the anode terminal 23 and the cathode terminal 21, not only the rectifying element 15 but also the pn junction between the p anode region 14 and the n barrier region 12. The electric field is also shared by the depletion layer extending from the interface. Thereby, the electric field applied to the rectifying element 15 is reduced. According to the diode 2 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

  In the diode 2 of the present embodiment, the impurity concentration in the n pillar region 16 is higher than the impurity concentration in the n barrier region 12. With such a configuration, the potential difference between the n barrier region 12 and the anode electrode 22 when a forward bias is applied can be reduced without reducing the thickness of the p anode region 14. According to the diode 2 of this embodiment, the switching loss can be reduced without lowering the withstand voltage against the reverse bias.

  In the diode 2 of the present embodiment, the electrical connection between the anode electrode 22 and the n barrier region 12 is not a Schottky junction interface formed on the semiconductor substrate 4 but a rectification provided outside the semiconductor substrate 4. The element 15 implements a rectifying action. In general, when a rectifying action is realized by a Schottky junction interface, the operating characteristics are greatly affected by the temperature of the Schottky junction interface. When the Schottky junction interface is formed in the upper part of the semiconductor substrate 4, when the semiconductor substrate 4 generates heat and becomes high temperature, the Schottky junction interface also becomes high temperature and the operation characteristics change. On the other hand, in the diode 2 of this embodiment, since the rectifying element 15 is provided outside, the operating characteristics do not change even when the semiconductor substrate 4 generates heat and becomes high temperature. According to the diode 2 of the present embodiment, the switching loss can be reduced with a structure that is hardly affected by the temperature rise of the semiconductor substrate 4 due to heat generation.

(Example 2)
As shown in FIG. 2, the diode 32 of this embodiment is formed using a silicon semiconductor substrate 34. The semiconductor substrate 34 includes an n ⁺ cathode region 6 that is a high-concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region, and a p-type. A p electric field progress preventing region 36 that is a semiconductor region, an n barrier region 12 that is an n type semiconductor region, and a p anode region 14 that is a p type semiconductor region are sequentially stacked. In the present embodiment, the impurity concentration of the p electric field progress preventing region 36 is about 1 × 10 ¹⁵ to 1 × 10 ¹⁹ [cm ⁻³ ]. The thickness of the p electric field progress preventing region 36 is about 1.0 to 2.0 [μm].

A plurality of n pillar regions 16, which are n type semiconductor regions, are formed on the upper surface of the semiconductor substrate 34 at a predetermined interval. The n pillar region 16 is formed so as to penetrate the p anode region 14 and reach the upper surface of the n barrier region 12. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval.

A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 34. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. The cathode electrode 20 is connected to the cathode terminal 21.

A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 34. The anode electrode 22 is joined to the p anode region 14 and the p ⁺ contact region 18 by an ohmic junction. The anode electrode 22 is connected to the anode terminal 23.

  On the upper surface of the semiconductor substrate 34, the insulating film 11 is formed at a location where the anode electrode 22 is not formed. A relay electrode 13 that penetrates the insulating film 11 and reaches the upper surface of the n pillar region 16 is formed on the upper surface of the insulating film 11. The relay electrode 13 is joined to the n pillar region 16 by an ohmic junction. The relay electrode 13 is connected to the anode terminal 23 via the rectifying element 15 provided outside the semiconductor substrate 34. The anode 15a of the rectifying element 15 is connected to the anode terminal 23 via the wiring 17a. The cathode 15b of the rectifying element 15 is connected to the relay electrode 13 via the wiring 17b.

The operation of the diode 32 will be described. When a forward bias is applied between the anode terminal 23 and the cathode terminal 21, a forward current flows from the anode terminal 23 to the n pillar region 16 through the rectifying element 15. Since the n pillar region 16 and the n barrier region 12 have substantially the same potential, the potential difference between the n barrier region 12 and the anode electrode 22 is substantially equal to the voltage drop in the rectifying element 15. Since the voltage drop at the rectifying element 15 is sufficiently smaller than the built-in voltage of the pn junction between the p anode region 14 and the n barrier region 12, the p ⁺ contact region 18 and the p anode region 14 move to the n ⁻ drift region 10. Hole injection is suppressed. Between the anode terminal 23 and the cathode terminal 21, the wiring 17 a, the rectifying element 15, the wiring 17 b, the relay electrode 13, the n pillar region 16, the n barrier region 12, the p electric field progress preventing region 36, the n ⁻ drift region 10, n A forward current flows through the buffer region 8 and the n ⁺ cathode region 6. Although a pn junction exists between the n barrier region 12 and the p electric field progress preventing region 36, the p type impurity concentration of the p electric field progress preventing region 36 is low and the thickness of the p electric field progress preventing region 36 is thin. The influence on the forward current between the anode terminal 23 and the cathode terminal 21 is small.

Next, when the voltage between the anode terminal 23 and the cathode terminal 21 is switched from the forward bias to the reverse bias, the reverse current passing through the n-pillar region 16 is limited by the rectifying element 15, and between the p-anode region 14 and the n-barrier region 12. The pn junction limits the reverse current through the p anode region 14. The reverse current is also limited by the pn junction between the n ⁻ drift region 10 and the p electric field progress preventing region 36. As described above, in the diode 32 of the present embodiment, the injection of holes from the p ⁺ contact region 18 and the p anode region 14 to the n ⁻ drift region 10 is suppressed when a forward bias is applied, and therefore reverse recovery is performed. Low current and short reverse recovery time. According to the diode 32 of this embodiment, the switching loss can be reduced without performing lifetime control of the n ⁻ drift region 10.

In the diode 32 of this embodiment, when a reverse bias is applied between the anode terminal 23 and the cathode terminal 21, not only the rectifying element 15 but also the pn junction between the p anode region 14 and the n barrier region 12. The electric field is also shared by the depletion layer extending from the interface and the pn junction interface between the n ⁻ drift region 10 and the p electric field progress preventing region 36. Thereby, the electric field applied to the rectifying element 15 and the electric field applied to the pn junction between the p anode region 14 and the n barrier region 12 are reduced. According to the diode 32 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

(Example 3)
As shown in FIG. 3, the diode 42 of the present embodiment is formed using a silicon semiconductor substrate 4 in the same manner as the diode 2 of the first embodiment. The semiconductor substrate 4 includes an n ⁺ cathode region 6 that is a high concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region, and an n-type. An n barrier region 12 that is a semiconductor region and a p anode region 14 that is a p-type semiconductor region are sequentially stacked. A plurality of n-pillar regions 16 that are n-type semiconductor regions are formed on the upper surface of the semiconductor substrate 4 at a predetermined interval. The n pillar region 16 is formed so as to penetrate the p anode region 14 and reach the upper surface of the n barrier region 12. A plurality of trenches 44 are formed at predetermined intervals on the upper side of the semiconductor substrate 4. Each trench 44 penetrates the n barrier region 12 from the upper surface of the p anode region 14 and reaches the inside of the n ⁻ drift region 10. The trench 44 is filled with a trench electrode 48 covered with an insulating film 46. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval.

A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 4. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. The cathode electrode 20 is connected to the cathode terminal 21.

A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 4. The anode electrode 22 is joined to the p anode region 14 and the p ⁺ contact region 18 by an ohmic junction. The anode electrode 22 is connected to the anode terminal 23.

  On the upper surface of the semiconductor substrate 4, the insulating film 11 is formed at a location where the anode electrode 22 is not formed. A relay electrode 13 that penetrates the insulating film 11 and reaches the upper surface of the n pillar region 16 is formed on the upper surface of the insulating film 11. The relay electrode 13 is joined to the n pillar region 16 by an ohmic junction. The relay electrode 13 is connected to the anode terminal 23 via a rectifying element 15 provided outside the semiconductor substrate 4. The anode 15a of the rectifying element 15 is connected to the anode terminal 23 via the wiring 17a. The cathode 15b of the rectifying element 15 is connected to the relay electrode 13 via the wiring 17b.

The operation of the diode 42 of the present embodiment is almost the same as the operation of the diode 2 of the first embodiment. In the diode 42 of this embodiment, the withstand voltage can be improved by adjusting the voltage applied to the trench electrode 48 when a reverse bias is applied between the anode terminal 23 and the cathode terminal 21. For example, when the voltage applied to the trench electrode 48 is adjusted so that the trench electrode 48 and the anode electrode 22 have substantially the same potential when a reverse bias is applied, a location near the tip of the trench electrode 48 inside the n ⁻ drift region 10. As a result, electric field concentration occurs in the rectifying element 15, thereby reducing the electric field applied to the rectifying element 15 and the interface of the pn junction between the p anode region 14 and the n barrier region 12. Note that the potential of the trench electrode 48 is not necessarily the same as that of the anode electrode 22. When the reverse bias is applied, the potential of the trench electrode 48 is made lower than the potential of the cathode electrode 20, so that the rectifying element 15 and the interface of the pn junction between the p anode region 14 and the n barrier region 12 are applied. The electric field can be reduced. According to the diode 42 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

Example 4
As shown in FIG. 4, the diode 52 of the present embodiment is formed using a silicon semiconductor substrate 34 in the same manner as the diode 32 of the second embodiment. The semiconductor substrate 34 includes an n ⁺ cathode region 6 that is a high-concentration n-type semiconductor region, an n buffer region 8 that is an n-type semiconductor region, an n ⁻ drift region 10 that is a low-concentration n-type semiconductor region, and a p-type. A p electric field progress preventing region 36 that is a semiconductor region, an n barrier region 12 that is an n type semiconductor region, and a p anode region 14 that is a p type semiconductor region are sequentially stacked. A plurality of n pillar regions 16, which are n type semiconductor regions, are formed on the upper surface of the semiconductor substrate 34 at a predetermined interval. The n pillar region 16 is formed so as to penetrate the p anode region 14 and reach the upper surface of the n barrier region 12. A plurality of trenches 44 are formed at predetermined intervals on the upper side of the semiconductor substrate 34. Each trench 44 extends from the upper surface of the p anode region 14 to the inside of the n ⁻ drift region 10 through the n barrier region 12 and the p electric field progress preventing region 36. The trench 44 is filled with a trench electrode 48 covered with an insulating film 46. A plurality of p ⁺ contact regions 18 that are high-concentration p-type semiconductor regions are formed on the upper surface of the p anode region 14 at a predetermined interval.

A metal cathode electrode 20 is formed on the lower surface of the semiconductor substrate 34. The cathode electrode 20 is joined to the n ⁺ cathode region 6 by an ohmic junction. The cathode electrode 20 is connected to the cathode terminal 21.

A metal anode electrode 22 is formed on the upper surface of the semiconductor substrate 34. The anode electrode 22 is joined to the p anode region 14 and the p ⁺ contact region 18 by an ohmic junction. The anode electrode 22 is connected to the anode terminal 23.

  On the upper surface of the semiconductor substrate 34, the insulating film 11 is formed at a location where the anode electrode 22 is not formed. A relay electrode 13 that penetrates the insulating film 11 and reaches the upper surface of the n pillar region 16 is formed on the upper surface of the insulating film 11. The relay electrode 13 is joined to the n pillar region 16 by an ohmic junction. The relay electrode 13 is connected to the anode terminal 23 via the rectifying element 15 provided outside the semiconductor substrate 34. The anode 15a of the rectifying element 15 is connected to the anode terminal 23 via the wiring 17a. The cathode 15b of the rectifying element 15 is connected to the relay electrode 13 via the wiring 17b.

The operation of the diode 52 of the present embodiment is almost the same as the operation of the diode 32 of the second embodiment. In the diode 52 of the present embodiment, similarly to the diode 42 of the third embodiment, the voltage applied to the trench electrode 48 is adjusted when a reverse bias is applied between the anode terminal 23 and the cathode terminal 21. The breakdown voltage can be improved. For example, when the voltage applied to the trench electrode 48 is adjusted so that the trench electrode 48 and the anode electrode 22 have substantially the same potential when a reverse bias is applied, a location near the tip of the trench electrode 48 inside the n ⁻ drift region 10. As a result, electric field concentration occurs in the rectifying element 15, the pn junction interface between the p anode region 14 and the n barrier region 12, and the pn junction between the n ⁻ drift region 10 and the p electric field progress preventing region 36. The electric field applied to the interface is reduced. According to the diode 52 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

(Example 5)
As shown in FIG. 5, the diode 62 of the present embodiment has substantially the same configuration as the diode 52 of the fourth embodiment. In the diode 62 of the present embodiment, a plurality of p ⁺ cathode short regions 64 that are high-concentration p-type semiconductor regions are formed in the n ⁺ cathode region 6 at a predetermined interval. 52. In this embodiment, the impurity concentration of the p ⁺ cathode short region 64 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ].

The operation of the diode 62 of this embodiment is substantially the same as that of the diode 52 of the fourth embodiment. In the diode 62 of this embodiment, when a forward bias is applied between the anode terminal 23 and the cathode terminal 21, the p ⁺ cathode short region 64 is formed, so that the n ⁻ drift from the n ⁺ cathode region 6. Electron injection into the region 10 is suppressed. According to the diode 62 of the present embodiment, not only the injection of holes from the p ⁺ contact region 18 and the p anode region 14 to the n ⁻ drift region 10 is suppressed during forward bias application, but also n ⁺ Since the injection of electrons from the cathode region 6 to the n ⁻ drift region 10 is also suppressed, the reverse recovery current can be further reduced and the reverse recovery time can be further shortened. According to the diode 62 of this embodiment, the switching loss can be further reduced.

Note that the improvement of the reverse recovery characteristic by providing the p ⁺ cathode short region 64 as described above is also effective in other types of diodes. That is, like the diode 66 shown in FIG. 6, the diode 2 of the first embodiment can be configured such that the p ⁺ cathode short region 64 is provided in the n ⁺ cathode region 6, or the diode 68 shown in FIG. As described above, the diode 32 of the second embodiment may be configured such that the p ⁺ cathode short region 64 is provided in the n ⁺ cathode region 6, or the diode 42 of the third embodiment as in the diode 70 shown in FIG. 8. In this case, a p ⁺ cathode short region 64 may be provided in the n ⁺ cathode region 6.

(Example 6)
As shown in FIG. 9, the semiconductor device 72 of the present embodiment has a configuration substantially similar to that of the diode 42 of the third embodiment. In the semiconductor device 72, an n ⁺ emitter region 74 that is a high-concentration n-type semiconductor region is formed at a location adjacent to the trench 44 on the upper surface of the p anode region 14. In this embodiment, the impurity concentration of the n ⁺ emitter region 74 is about 1 × 10 ¹⁸ to 1 × 10 ²⁰ [cm ⁻³ ]. The n ⁺ emitter region 74 is joined to the anode electrode 22 through an ohmic junction.

The semiconductor device 72 of this embodiment includes a cathode electrode 20 corresponding to a drain electrode, an n ⁺ cathode region 6 corresponding to a drain region, an n buffer region 8, an n ⁻ drift region 10 and a p corresponding to a body region. an anode region 14, the ^{n +} emitter region 74 corresponding to the source region, an anode electrode 22 that corresponds to the source electrode, the ^{n +} emitter region 74 and the n ^- insulating film with respect to the p anode region 14 between the drift region 10 The structure of the vertical MOSFET provided with the trench electrode 48 corresponding to the gate electrode facing each other with the 46 interposed therebetween.

  Similar to the diode 42 of the third embodiment, according to the semiconductor device 72 of the present embodiment, the reverse recovery characteristic of the parasitic diode can be improved and the switching loss can be reduced. Further, similarly to the diode 42 of the third embodiment, the semiconductor device 72 of the present embodiment can improve the breakdown voltage against the reverse bias.

(Example 7)
As shown in FIG. 10, the semiconductor device 82 of the present embodiment has a configuration substantially similar to that of the diode 52 of the fourth embodiment. In the semiconductor device 82, an n ⁺ emitter region 74 is formed at a location adjacent to the trench 44 on the upper surface of the p anode region 14. The n ⁺ emitter region 74 is joined to the anode electrode 22 through an ohmic junction.

The semiconductor device 82 of this example includes a cathode electrode 20 corresponding to a drain electrode, an n ⁺ cathode region 6 corresponding to a drain region, an n buffer region 8, an n ⁻ drift region 10, and a p corresponding to a body region. an anode region 14, the ^{n +} emitter region 74 corresponding to the source region, an anode electrode 22 that corresponds to the source electrode, the ^{n +} emitter region 74 and the n ^- insulating film with respect to the p anode region 14 between the drift region 10 The structure of the vertical MOSFET provided with the trench electrode 48 corresponding to the gate electrode facing each other with the 46 interposed therebetween.

  Similar to the diode 52 of the fourth embodiment, the semiconductor device 82 of the present embodiment can improve the reverse recovery characteristics of the parasitic diode and reduce the switching loss. Further, similarly to the diode 52 of the fourth embodiment, according to the semiconductor device 82 of the present embodiment, the breakdown voltage against the reverse bias can be improved and the leak current at the time of the reverse bias can be suppressed.

(Example 8)
As shown in FIG. 11, the semiconductor device 102 of this embodiment is formed using a silicon semiconductor substrate 104. The semiconductor device 102 includes an IGBT region 106 and a diode region 108. In the IGBT region 106, the semiconductor substrate 104 includes a p ⁺ collector region 110 that is a high concentration p-type semiconductor region, an n buffer region 112 that is an n type semiconductor region, and an n ⁻ drift region 114 that is a low concentration n type semiconductor region. In addition, an n barrier region 116 that is an n-type semiconductor region and a p body region 118 that is a p-type semiconductor region are sequentially stacked. In this embodiment, the impurity concentration of the p ⁺ collector region 110 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ], and the impurity concentration of the n buffer region 112 is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [ cm ⁻³ ], the impurity concentration of the n ⁻ drift region 114 is about 1 × 10 ¹² to 1 × 10 ¹⁵ [cm ⁻³ ], and the impurity concentration of the n barrier region 116 is 1 × 10 ¹⁵ to 1 ×. 10 ¹⁸ is approximately [cm ^-3], the impurity concentration of the p-body region 118 is approximately ^{1 × 10 16 ~1 × 10 19} [cm -3]. The thickness of the n barrier region 116 is about 0.5 to 3.0 [μm]. In the diode region 108, the semiconductor substrate 104 is an n ⁺ cathode region 120 that is a high concentration n-type semiconductor region, an n buffer region 112, an n ⁻ drift region 114, an n barrier region 122, and a p-type semiconductor region. The p anode region 124 is sequentially stacked. In this embodiment, the impurity concentration of the n ⁺ cathode region 120 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ], and the impurity concentration of the n barrier region 122 is 1 × 10 ¹⁵ to 1 × 10 ¹⁸ [ cm ⁻³ ], and the impurity concentration of the p anode region 124 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ]. The thickness of the n barrier region 122 is about 0.5 to 3.0 [μm]. A plurality of trenches 126 are formed at predetermined intervals on the upper side of the semiconductor substrate 4.

In IGBT region 106, trench 126 extends from the upper surface of p body region 118 through n barrier region 116 to the inside of n ⁻ drift region 114. The trench 126 is filled with a gate electrode 130 covered with an insulating film 128. On the upper surface of p body region 118, n ⁺ emitter region 132, which is a high concentration n-type semiconductor region, is formed at a location adjacent to trench 126. The impurity concentration of the n ⁺ emitter region 132 is about 1 × 10 ¹⁸ to 1 × 10 ²⁰ [cm ⁻³ ]. An n-pillar region 134 that is an n-type semiconductor region is formed on the upper surface of the p body region 118. The impurity concentration of the n pillar region 134 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ]. N pillar region 134 is formed so as to penetrate p body region 118 and reach the upper surface of n barrier region 116. Further, on the upper surface of the p body region 118, ap ⁺ contact region 136 which is a high concentration p-type semiconductor region is formed. The impurity concentration of the p ⁺ contact region 136 is about 1 × 10 ¹⁷ to 1 × 10 ²⁰ [cm ⁻³ ].

In the diode region 108, the trench 126 penetrates the n barrier region 122 from the upper surface of the p anode region 124 and reaches the inside of the n ⁻ drift region 114. The trench 126 is filled with a gate electrode 140 covered with an insulating film 138. On the upper surface of the p anode region 124, an n pillar region 142 which is an n type semiconductor region is formed. The impurity concentration of the n pillar region 142 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ]. The n pillar region 142 is formed so as to penetrate the p anode region 124 and reach the upper surface of the n barrier region 122. A p ⁺ contact region 144 that is a high concentration p-type semiconductor region is formed on the upper surface of the p anode region 124. The impurity concentration of the p ⁺ contact region 144 is about 1 × 10 ¹⁷ to 1 × 10 ²⁰ [cm ⁻³ ].

A metal collector / cathode electrode 146 is formed on the lower surface of the semiconductor substrate 104. The collector / cathode electrode 146 is joined to the p ⁺ collector region 110 and the n ⁺ cathode region 120 through an ohmic junction. The collector / cathode electrode 146 functions as a collector electrode in the IGBT region 106 and functions as a cathode electrode in the diode region 108. The collector / cathode electrode 146 is connected to the collector / cathode terminal 147.

A metal emitter / anode electrode 148 is formed on the upper surface of the semiconductor substrate 104. The emitter / anode electrode 148 is joined to the n ⁺ emitter region 132 and the p ⁺ contact region 136 of the IGBT region 106 and the p ⁺ contact region 144 of the diode region 108 through an ohmic junction. The emitter / anode electrode 148 functions as an emitter electrode in the IGBT region 106 and functions as an anode electrode in the diode region 108. The emitter / anode electrode 148 is connected to the emitter / anode terminal 149.

  On the upper surface of the IGBT region 106 of the semiconductor substrate 104, an insulating film 103 is formed at a location where the emitter / anode electrode 148 is not formed. A relay electrode 105 is formed on the upper surface of the insulating film 103 and reaches the upper surface of the n-pillar region 134 through the insulating film 103. The relay electrode 105 is joined to the n pillar region 134 by an ohmic junction. The relay electrode 105 is connected to the emitter / anode terminal 149 via a rectifying element 107 provided outside the semiconductor substrate 104.

  The rectifying element 107 allows a forward current from the anode 107a to the cathode 107b and limits a reverse current from the cathode 107b to the anode 107a. The anode 107a of the rectifying element 107 is connected to the emitter / anode terminal 149 via the wiring 109a. The cathode 107b of the rectifying element 107 is connected to the relay electrode 105 through the wiring 109b. In this embodiment, the rectifying element 107 is a Schottky barrier diode. As the rectifying element 107, a diode other than a Schottky barrier diode may be used as long as the forward voltage drop is lower than the built-in voltage of the pn junction between the p body region 118 and the n barrier region 116. Good. For example, a germanium pn diode or a heterojunction diode may be used as the rectifying element 107.

  On the upper surface of the diode region 108 of the semiconductor substrate 104, an insulating film 113 is formed at a location where the emitter / anode electrode 148 is not formed. A relay electrode 115 that penetrates the insulating film 113 and reaches the upper surface of the n-pillar region 142 is formed on the upper surface of the insulating film 113. The relay electrode 115 is joined to the n pillar region 142 by an ohmic junction. The relay electrode 115 is connected to the emitter / anode terminal 149 via a rectifying element 117 provided outside the semiconductor substrate 104.

  The rectifying element 117 allows a forward current from the anode 117a to the cathode 117b and limits a reverse current from the cathode 117b to the anode 117a. The anode 117a of the rectifying element 117 is connected to the emitter / anode terminal 149 via the wiring 119a. The cathode 117b of the rectifying element 117 is connected to the relay electrode 115 via the wiring 119b. In this embodiment, the rectifying element 117 is a Schottky barrier diode. As the rectifying element 117, a diode other than a Schottky barrier diode may be used as long as the forward voltage drop is lower than the built-in voltage of the pn junction between the p anode region 124 and the n barrier region 122. Good. For example, a germanium pn diode or a heterojunction diode may be used as the rectifying element 117.

  The gate electrode 130 of the IGBT region 106 is electrically connected to a first gate terminal (not shown). The gate electrode 140 of the diode region 108 is electrically connected to a second gate terminal (not shown).

  As described above, the semiconductor device 102 has a structure in which the IGBT region 106 that functions as a trench IGBT and the diode region 108 that functions as a freewheeling diode are connected in antiparallel.

An operation of the semiconductor device 102 will be described. When no voltage is applied to the gate electrode 130 and thus the IGBT region 106 is not driven, the IGBT region 106 functions as a parasitic diode. In this state, when a forward bias is applied between the emitter / anode terminal 149 and the collector / cathode terminal 147, in the diode region 108, a forward current flows from the emitter / anode terminal 149 to the n pillar region 142 via the rectifier element 117. Flows. Since the n-pillar region 142 and the n-barrier region 122 have substantially the same potential, the potential difference between the n-barrier region 122 and the emitter / anode electrode 148 is substantially equal to the voltage drop at the rectifying element 117. Since the voltage drop at the rectifying element 117 is sufficiently smaller than the built-in voltage of the pn junction between the p anode region 124 and the n barrier region 122, the p ⁺ contact region 144 and the p anode region 124 move to the n ⁻ drift region 114. Hole injection is suppressed. In the IGBT region 106, a forward current flows from the emitter / anode terminal 149 to the n pillar region 134 through the rectifying element 107. Since the n-pillar region 134 and the n-barrier region 116 have substantially the same potential, the potential difference between the n-barrier region 116 and the emitter / anode electrode 148 is almost equal to the voltage drop in the rectifying element 107. Since the voltage drop at the rectifying element 107 is sufficiently smaller than the built-in voltage of the pn junction between the p body region 118 and the n barrier region 116, the p ⁺ contact region 136 and the p body region 118 to the n ⁻ drift region 114. Hole injection is suppressed. Between the emitter / anode terminal 149 and the collector / cathode terminal 147, there are a wiring 119a, a rectifier element 117, a wiring 119b, a relay electrode 115, an n pillar region 142, an n barrier region 122, an n ⁻ drift region 114, and an n buffer region 112. , The forward current passing through the n ⁺ cathode region 120, the wiring 109a, the rectifying element 107, the wiring 109b, the relay electrode 105, the n pillar region 134, the n barrier region 116, the n ⁻ drift region 114, the n buffer region 112, n ⁺ A forward current flows through the cathode region 120.

Next, when the voltage between the emitter / anode terminal 149 and the collector / cathode terminal 147 is switched from the forward bias to the reverse bias, the reverse current passing through the n-pillar region 142 is limited by the rectifying element 117 with respect to the diode region 108, and p The reverse current flowing through the p anode region 124 is limited by the pn junction between the anode region 124 and the n barrier region 122, and for the IGBT region 106, the reverse current through the n pillar region 134 is limited by the rectifier element 107, and the p body The reverse current flowing in p body region 118 is limited by the pn junction between region 118 and n barrier region 116. As described above, in the diode region 108, injection of holes from the p ⁺ contact region 144 and the p anode region 124 to the n ⁻ drift region 114 is suppressed when a forward bias is applied. When a bias is applied, injection of holes from the p ⁺ contact region 136 and the p body region 118 to the n ⁻ drift region 114 is suppressed. Therefore, the semiconductor device 102 has a small reverse recovery current and a short reverse recovery time. According to the semiconductor device 102 of this embodiment, the switching loss can be reduced without performing lifetime control of the n ⁻ drift region 114.

In the semiconductor device 102 of the present embodiment, when a reverse bias is applied between the emitter / anode terminal 149 and the collector / cathode terminal 147, not only the rectifying element 107 but also the p body region 118 in the IGBT region 106. The electric field is also shared by the depletion layer extending from the pn junction interface between the n barrier regions 116. Furthermore, the electric field concentrates near the tip of the trench 126 in the n ⁻ drift region 114, thereby reducing the electric field applied to the rectifying element 107 and the electric field applied to the pn junction between the p body region 118 and the n barrier region 116. The Similarly, when a reverse bias is applied between the emitter / anode terminal 149 and the collector / cathode terminal 147, not only the rectifier element 117 but also the pn between the p anode region 124 and the n barrier region 122 in the diode region 108. The electric field is also shared by the depletion layer extending from the junction interface. Furthermore, the electric field concentrates near the tip of the trench 126 in the n ⁻ drift region 114, thereby reducing the electric field applied to the rectifying element 117 and the electric field applied to the pn junction between the p anode region 124 and the n barrier region 122. The According to the semiconductor device 102 of the present embodiment, the breakdown voltage against the reverse bias can be improved.

Example 9
As shown in FIG. 12, the semiconductor device 162 according to the present embodiment has a configuration substantially similar to that of the semiconductor device 102 according to the eighth embodiment. The semiconductor device 162 is formed using a silicon semiconductor substrate 164. The semiconductor substrate 164 has substantially the same configuration as the semiconductor substrate 104 of the eighth embodiment. In the semiconductor substrate 164, in the IGBT region 106, a p electric field progress prevention region 166 that is a p-type semiconductor region is formed between the n ⁻ drift region 114 and the n barrier region 116, and in the diode region 108, the n ⁻ drift A p electric field progress preventing region 168 which is a p-type semiconductor region is formed between the region 114 and the n barrier region 122. The impurity concentration of the p electric field progress preventing region 166 and the p electric field progress preventing region 168 is about 1 × 10 ¹⁵ to 1 × 10 ¹⁹ [cm ⁻³ ]. Moreover, the thickness of the p electric field progress preventing region 166 and the p electric field progress preventing region 168 is about 1.0 to 2.0 [μm]. In IGBT region 106, trench 126 penetrates n barrier region 116 and p electric field progress preventing region 166 from the upper surface of p body region 118 and reaches the inside of n ⁻ drift region 114. In the diode region 108, the trench 126 penetrates the n barrier region 122 and the p electric field progress preventing region 168 from the upper surface of the p anode region 124 and reaches the inside of the n ⁻ drift region 114.

According to the semiconductor device 162 of the present embodiment, as in the semiconductor device 102 of the eighth embodiment, when a forward bias is applied between the emitter / anode terminal 149 and the collector / cathode terminal 147, in the diode region 108, The injection of holes from the p ⁺ contact region 144 and the p anode region 124 to the n ⁻ drift region 114 is suppressed. In the IGBT region 106, the p ⁺ contact region 136 and the p body region 118 to the n ⁻ drift region 114. Hole injection is suppressed. Therefore, the reverse recovery current when switching from the forward bias to the reverse bias can be reduced, and the reverse recovery time can be shortened. Switching loss can be reduced.

Further, according to the semiconductor device 162 of the present embodiment, when a reverse bias is applied between the emitter / anode terminal 149 and the collector / cathode terminal 147, not only the rectifying element 107 but also the p body region in the IGBT region 106. The electric field is also shared by the depletion layer extending from the pn junction interface between 118 and the n barrier region 116 and the depletion layer extending from the pn junction interface between the n ⁻ drift region 114 and the p electric field progress preventing region 166. Further, the electric field concentrates near the tip of the trench 126 in the n ⁻ drift region 114, so that the electric field applied to the rectifying element 107, the electric field applied to the pn junction between the p body region 118 and the n barrier region 116, n ^- electric field applied to the pn junction between the drift region 114 and the p electric field progress preventing region 166 is reduced. Similarly, when a reverse bias is applied between the emitter / anode terminal 149 and the collector / cathode terminal 147, not only the rectifier element 117 but also the pn between the p anode region 124 and the n barrier region 122 in the diode region 108. The electric field is also shared by the depletion layer extending from the junction interface and the depletion layer extending from the pn junction interface between the n ⁻ drift region 114 and the p electric field progress preventing region 168. Further, the electric field concentrates near the tip of the trench 126 in the n ⁻ drift region 114, so that the electric field applied to the rectifying element 117, the electric field applied to the pn junction between the p anode region 124 and the n barrier region 122, and n ^- electric field applied to the pn junction between the drift region 114 and the p electric field progress preventing region 168 is reduced. According to the semiconductor device 162 of this embodiment, the breakdown voltage against the reverse bias can be improved.

  Further, according to the semiconductor device 162 of the present embodiment, when a reverse bias is applied between the emitter / anode terminal 149 and the collector / cathode terminal 147, the p-field progress preventing region 168 and the n barrier region are formed in the diode region 108. Since the reverse current is limited by the pn junction between 122, the leakage current passing through the rectifying element 117 is reduced, and in the IGBT region 106, the reverse current is reversed by the pn junction between the p electric field progress prevention region 166 and the n barrier region 116. Since the current is limited, the leakage current passing through the rectifying element 107 is reduced. According to the semiconductor device 162 of this embodiment, it is possible to reduce a leakage current when a reverse bias is applied.

  Further, in the semiconductor device 162 of the present embodiment, when the IGBT region 106 is driven by applying a voltage to the gate electrode 130 of the IGBT region 106, the current flows from the collector / cathode electrode 146 to the emitter / anode electrode 148 in the IGBT region 106. Since the current is suppressed by the p electric field progress preventing region 166, the saturation current of the IGBT region 106 can be reduced.

(Example 10)
As shown in FIG. 13, the semiconductor device 172 of this example has a configuration substantially similar to that of the semiconductor device 102 of Example 8. In the semiconductor device 172 of the present embodiment, a plurality of p ⁺ cathode short regions 174 that are high-concentration p-type semiconductor regions are formed in the n ⁺ cathode region 120 of the diode region 108 at a predetermined interval. Different from the semiconductor device 102 of the eighth embodiment. In this embodiment, the impurity concentration of the p ⁺ cathode short region 174 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ]. According to the semiconductor device 172 of the present embodiment, since the injection of electrons from the n ⁺ cathode region 120 to the n ⁻ drift region 114 is suppressed when a forward bias is applied, compared to the semiconductor device 102 of the eighth embodiment. Thus, the reverse recovery current can be further reduced and the reverse recovery time can be further shortened. According to the semiconductor device 172 of this embodiment, the switching loss can be further reduced.

(Example 11)
As shown in FIG. 14, the semiconductor device 182 of the present embodiment has a configuration substantially similar to that of the semiconductor device 162 of the ninth embodiment. The semiconductor device 182 of the present embodiment is different from the semiconductor device 162 of the ninth embodiment in that a plurality of p ⁺ cathode short regions 174 are formed at predetermined intervals in the n ⁺ cathode region 120 of the diode region 108. Different. According to the semiconductor device 182 of the present embodiment, since the injection of electrons from the n ⁺ cathode region 120 to the n ⁻ drift region 114 is suppressed when a forward bias is applied, compared to the semiconductor device 162 of the ninth embodiment. Thus, the reverse recovery current can be further reduced and the reverse recovery time can be further shortened. According to the semiconductor device 182 of this embodiment, the switching loss can be further reduced.

(Example 12)
As shown in FIG. 15, the semiconductor device 202 of this embodiment is formed using a silicon semiconductor substrate 204. The semiconductor substrate 204 includes an n ⁺ cathode region 206 that is a high concentration n-type semiconductor region, an n buffer region 208 that is an n-type semiconductor region, and an n ⁻ drift region 210 that is a low-concentration n-type semiconductor region. Yes. In this embodiment, the impurity concentration of the n ⁺ cathode region 206 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ], and the impurity concentration of the n buffer region 208 is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [ cm ⁻³ ], and the impurity concentration of the n ⁻ drift region 210 is about 1 × 10 ¹² to 1 × 10 ¹⁵ [cm ⁻³ ].

A plurality of n barrier regions 212 that are n-type semiconductor regions are formed on the upper surface of the n ⁻ drift region 210 at a predetermined interval. A p anode region 214 which is a p type semiconductor region is partially formed on the upper surface of the n barrier region 212. An n pillar region 216 that is an n-type semiconductor region is formed on the upper surface of the p anode region 214. The n pillar region 216 is formed to penetrate the p anode region 214 and reach the upper surface of the n barrier region 212. Further, on the upper surface of the p anode region 214, a p ⁺ contact region 218 which is a high concentration p-type semiconductor region and an n ⁺ emitter region 220 which is a high concentration n type semiconductor region are formed. In this embodiment, the impurity concentration of the n barrier region 212 is about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ [cm ⁻³ ], and the impurity concentration of the p anode region 214 is 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm]. ⁻³ ], the impurity concentration of the n-pillar region 216 is about 1 × 10 ¹⁶ to 1 × 10 ¹⁹ [cm ⁻³ ], and the impurity concentration of the p ⁺ contact region 218 is 1 × 10 ¹⁷ to 1 × 10 ²⁰ [cm ^-3] is about, the impurity concentration of ^{n +} emitter region 220 is ^{1 × 10 18 ~1 × 10 20} [cm -3] or so. The thickness of the n barrier region 212 is about 0.5 to 3.0 [μm].

A metal cathode electrode 222 is formed on the lower surface of the semiconductor substrate 204. The cathode electrode 222 is joined to the n ⁺ cathode region 206 through an ohmic junction. The cathode electrode 222 is connected to the cathode terminal 223.

A metal anode electrode 224 and a metal gate electrode 226 are formed on the upper surface of the semiconductor substrate 204. The anode electrode 224 is bonded to a part of the p anode region 214, the p ⁺ contact region 218, and the n ⁺ emitter region 220 through an ohmic junction. The anode electrode 224 is connected to the anode terminal 225. The gate electrode 226 is disposed so as to face a part of the n ⁻ drift region 210, the n barrier region 212, the p anode region 214, and the n ⁺ emitter region 220 with the insulating film 230 interposed therebetween. The gate electrode 226 is electrically connected to the gate terminal 227.

  On the upper surface of the semiconductor substrate 204, an insulating film 211 is formed at a location where the anode electrode 224 and the gate electrode 226 are not formed. A relay electrode 213 that penetrates the insulating film 211 and reaches the upper surface of the n-pillar region 216 is formed on the upper surface of the insulating film 211. The relay electrode 213 is joined to the n pillar region 216 by an ohmic junction. The relay electrode 213 is connected to the anode terminal 225 via a rectifying element 215 provided outside the semiconductor substrate 204.

  The rectifying element 215 allows a forward current from the anode 215a to the cathode 215b and limits a reverse current from the cathode 215b to the anode 215a. The anode 215a of the rectifying element 215 is connected to the anode terminal 225 via the wiring 217a. The cathode 215b of the rectifying element 215 is connected to the relay electrode 213 through the wiring 217b. In this embodiment, the rectifying element 215 is a Schottky barrier diode. As the rectifying element 215, other than the Schottky barrier diode may be used as long as the forward voltage drop is lower than the built-in voltage of the pn junction between the p anode region 214 and the n barrier region 212. Good. For example, as the rectifying element 215, a germanium pn diode or a heterojunction diode may be used.

The semiconductor device 202 of this embodiment includes a cathode electrode 222 corresponding to a drain electrode, an n ⁺ cathode region 206 corresponding to a drain region, a buffer region 208, an n ⁻ drift region 210, and a p anode corresponding to a body region. a region 214, the ^{n +} emitter region 220 corresponding to the source region, an anode electrode 224 corresponding to the source electrode, the ^{n +} emitter region 220 and the n ^- insulating the p anode regions 214 between the drift region 210 film 230 A vertical MOSFET structure having a gate electrode 226 that is opposed to each other is sandwiched.

In the semiconductor device 202 of this embodiment, an n barrier region 212 is formed between the n ⁻ drift region 210 and the p anode region 214, and the n pillar region is electrically connected to the anode electrode 224 via the rectifying element 215. The n barrier region 212 is electrically connected to the anode electrode 224 through 216. With such a configuration, the reverse recovery characteristics of the parasitic diode between the anode terminal 225 and the cathode terminal 223 can be improved and the switching loss can be reduced. Further, the withstand voltage against the reverse bias between the anode terminal 225 and the cathode terminal 223 can be improved.

(Example 13)
As shown in FIG. 16, the semiconductor device 232 of the present example has a configuration substantially similar to the semiconductor device 202 of the twelfth example. The semiconductor device 232 of this embodiment also has a vertical MOSFET structure, similar to the semiconductor device 202 of the twelfth embodiment. In the semiconductor device 232 of the present embodiment, a p electric field progress preventing region 234 that is a p-type semiconductor region is formed between the n ⁻ drift region 210 and the n barrier region 212. The impurity concentration of the p electric field progress preventing region 234 is ^{1 × 10 15 ~1 × 10 19} [cm -3] or so. The thickness of the p electric field progress preventing region 234 is about 1.0 to 2.0 [μm].

  According to the semiconductor device 232 of the present embodiment, as with the semiconductor device 202 of the twelfth embodiment, the reverse recovery characteristics of the parasitic diode between the anode terminal 225 and the cathode terminal 223 are improved and the switching loss is reduced. Can do.

Further, in the semiconductor device 232 of the present embodiment, the p electric field progress preventing region 234 is formed between the n ⁻ drift region 210 and the n barrier region 212, and therefore, compared with the semiconductor device 202 of the twelfth embodiment, the anode terminal The withstand voltage against the reverse bias between 225 and the cathode terminal 223 can be improved, and the leakage current at the time of reverse bias can be reduced.

(Example 14)
As shown in FIG. 17, the semiconductor device 242 of this example has a configuration substantially similar to that of the semiconductor device 202 of Example 12. In the semiconductor device 232 of this embodiment, a p ⁺ collector region 244 that is a high-concentration p-type semiconductor region is partially formed in the n ⁺ cathode region 206. In this embodiment, the impurity concentration of the p ⁺ collector region 244 is about 1 × 10 ^{17 to} 5 × 10 ²⁰ [cm ⁻³ ].

The semiconductor device 242 has a structure in which a planar IGBT and a freewheeling diode are connected in antiparallel. That is, it corresponds to the cathode electrode 222 corresponding to the collector electrode, the p ⁺ collector region 244, the n buffer region 208, the n ⁻ drift region 210, the p anode region 214, the n ⁺ emitter region 220, and the emitter electrode. The anode electrode 224, the insulating film 230, and the gate electrode 226 constitute a planar IGBT, and includes a cathode electrode 222, an n ⁺ cathode region 206, an n buffer region 208, an n ⁻ drift region 210, The p anode region 214, the p ⁺ contact region 218, and the anode electrode 224 constitute a free wheeling diode. In the semiconductor device 242 of this embodiment, for each of the IGBT and the diode as described above, the n barrier region 212 formed between the n ⁻ drift region 210 and the p anode region 214 and the n barrier region 212 are electrically connected. The n-pillar region 216 is connected, and a rectifying element 215 arranged to connect the n-pillar region 216 and the anode electrode 224 is added.

In the semiconductor device 242 of this embodiment, when a forward bias is applied between the anode terminal 225 and the cathode terminal 223, injection of holes from the p anode region 214 and the p ⁺ contact region 218 to the n ⁻ drift region 210 is performed. Is suppressed. Therefore, reverse recovery characteristics can be improved and switching loss can be reduced.

  In the semiconductor device 242 of this embodiment, when a reverse bias is applied between the anode terminal 225 and the cathode terminal 223, not only the rectifying element 215 but also a pn junction between the p anode region 214 and the n barrier region 212. The electric field is also shared by the depletion layer extending from the interface. Therefore, the breakdown voltage against the reverse bias can be improved.

(Example 15)
As shown in FIG. 18, the semiconductor device 252 of this example has a configuration substantially similar to that of the semiconductor device 242 of Example 14. In the semiconductor device 252 of this example, a p electric field progress preventing region 234 that is a p-type semiconductor region is formed between the n ⁻ drift region 210 and the n barrier region 212. The impurity concentration of the p electric field progress preventing region 234 is ^{1 × 10 15 ~1 × 10 19} [cm -3] or so. The thickness of the p electric field progress preventing region 234 is about 1.0 to 2.0 [μm]. The semiconductor device 252 has a structure in which a planar IGBT and a freewheeling diode are connected in antiparallel.

According to the semiconductor device 252 of this embodiment, when a forward bias is applied between the anode terminal 225 and the cathode terminal 223, holes from the p anode region 214 and the p ⁺ contact region 218 to the n ⁻ drift region 210. Injection is suppressed. Therefore, reverse recovery characteristics can be improved and switching loss can be reduced.

In the semiconductor device 252 of this embodiment, when a reverse bias is applied between the anode terminal 225 and the cathode terminal 223, not only the rectifying element 215 but also a pn junction between the p anode region 214 and the n barrier region 212. The electric field is also shared by the depletion layer extending from the interface between the first electrode and the depletion layer extending from the pn junction between the p electric field progress preventing region 234 and the n ⁻ drift region 210. Therefore, the breakdown voltage against the reverse bias can be improved.

In the semiconductor device 252 of the present embodiment, the reverse current is limited by the pn junction between the p electric field progress preventing region 234 and the n ⁻ drift region 210. Therefore, the leakage current passing through the rectifying element 215 when a reverse bias is applied is reduced.

  Further, in the semiconductor device 252 of this embodiment, when a voltage is applied to the gate electrode 226 to drive the IGBT, the current flowing from the cathode electrode 222 corresponding to the collector electrode to the anode electrode 224 corresponding to the emitter electrode is a p electric field. Since it is suppressed by the progress prevention region 234, the saturation current of the IGBT can be reduced.

  As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

  For example, the n pillar regions 16, 134, 142, and 216 in the above embodiment may be formed as a single n barrier region with the same impurity concentration as the corresponding n barrier regions 12, 116, 122, and 212. Alternatively, the n pillar regions 16, 134, 142, and 216 in the above embodiment may be replaced with a metal buried layer.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2 diodes; 4 semiconductor substrate; 6 n ⁺ cathode region; 8 n buffer region; 10 n ⁻ drift region; 11 insulating film; 12 n barrier region; 13 relay electrode; 14 p anode region; 15 rectifier element; 16 n pillar region; 17a wiring; 17b wiring; 18p ⁺ contact region; 20 cathode electrode; 21 cathode terminal; 22 anode electrode; 23 anode terminal; 32 diode; 34 semiconductor substrate; 36p electric field progress prevention region; 44 trench; 46 insulating film; 48 trench electrode; 52 diode; 62 diode; 64 p ⁺ cathode short region; 66 diode; 68 diode; 70 diode; 72 semiconductor device; 74 n ⁺ emitter region; 82 semiconductor device; Semiconductor device; 10 Insulating film; 104 a semiconductor substrate; 105 relay electrode; 106 IGBT region; 107 rectifying element; 107a anode; 107 b cathode; 108 diode region; 109a wiring; 109b wiring; 110 ^{p +} collector region; 112 n buffer region; 113 insulating film; 114 n ^- drift region; 115 relay electrode; 116 n barrier region; 117 rectifying element; 117a anode; 117b cathode; 118 p-body region; 119a wiring; 119b wiring; 120 ^{n +} cathode region; 122 n barrier region; 124 p anode Region: 126 trench; 128 insulating film; 130 gate electrode; 132 n ⁺ emitter region; 134 n pillar region; 136 p ⁺ contact region; 138 insulating film: 140 gate electrode; 142 n pillar region; 144 p ^{+ contact} 146 Cathode electrode; 147 Cathode terminal; 148 Anode electrode; 149 Anode terminal; 162 Semiconductor device; 164 Semiconductor substrate; 166 p Electric field progress prevention region; 168 p Electric field progress prevention region; 172 Semiconductor device: 174 p ⁺ Cathode short area; 182 a semiconductor device; 202 a semiconductor device; 204 a semiconductor substrate; 206 ^{n +} cathode region; 208 n buffer region; 210 n ^- drift region; 211 insulating film; 212 n barrier region; 213 relay electrode; 214 p anode region; 215 215a anode; 215b cathode; 216a wiring; 217b wiring; 218p ⁺ contact region; 220n ⁺ emitter region; 222 cathode electrode; 223 cathode terminal; 224 anode electrode; 225 anode 226 gate electrode; 227 gate terminal; 230 insulating film; 232 semiconductor device; 234 p electric field progress prevention region; 242 semiconductor device; 244 p ⁺ collector region; 252 semiconductor device

Claims (8)

A diode comprising a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, and an anode electrode. And
A barrier region made of a first conductivity type semiconductor having a higher concentration than the drift region, formed between the drift region and the anode region ;
A relay electrode in ohmic contact with the barrier region;
Comprising a rectifying element provided outside the semiconductor substrate on which the diode is formed;
The anode of the rectifying element is connected to the anode electrode via a wiring, and the cathode of the rectifying element is connected to the relay electrode via a wiring,
A diode characterized in that a forward voltage drop of the rectifying element is smaller than a built-in voltage of a pn junction between the anode region and the barrier region.   2. The diode according to claim 1, further comprising an electric field progress preventing region made of a second conductivity type semiconductor formed between the barrier region and the drift region. A trench reaching the drift region from the anode region is formed,
3. The diode according to claim 1, wherein a trench electrode covered with an insulating film is formed inside the trench.   The diode according to any one of claims 1 to 3, further comprising a cathode short region made of a second conductivity type semiconductor partially formed in the cathode region. A semiconductor device in which the diode according to any one of claims 1 to 4 and the IGBT are integrated,
The IGBT includes a collector electrode, a collector region made of a second conductivity type semiconductor, a second drift region made of a low-concentration first conductivity type semiconductor, continuous from the drift region, and a second conductivity type. A body region made of a semiconductor, an emitter region made of a first conductivity type semiconductor, an emitter electrode, and a gate opposed to the body region between the emitter region and the second drift region with an insulating film interposed therebetween With electrodes,
A second barrier region made of a first conductivity type semiconductor having a higher concentration than the second drift region, wherein the IGBT is formed between the second drift region and the body region ;
A second relay electrode in ohmic contact with the second barrier region;
A second rectifier provided outside the semiconductor substrate on which the IGBT is formed,
The anode of the second rectifying element is connected to the emitter electrode via a wiring, and the cathode of the second rectifying element is connected to the second relay electrode via a wiring;
A semiconductor device, wherein a forward voltage drop of the second rectifying element is smaller than a built-in voltage of a pn junction between the body region and the second barrier region.   6. The semiconductor device according to claim 5, further comprising a second electric field progress prevention region made of a second conductivity type semiconductor and formed between the second barrier region and the second drift region. From a drain electrode, a drain region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, a body region made of a second conductivity type semiconductor, and a first conductivity type semiconductor A MOSFET comprising a source region, a source electrode, and a gate electrode facing the body region between the source region and the drift region with an insulating film interposed therebetween,
A barrier region made of a first conductivity type semiconductor having a higher concentration than the drift region, formed between the drift region and the body region ;
A relay electrode in ohmic contact with the barrier region;
A rectifier provided outside the semiconductor substrate on which the MOSFET is formed;
The anode of the rectifying element is connected to the source electrode via a wiring, and the cathode of the rectifying element is connected to the relay electrode via a wiring,
The MOSFET characterized in that a forward voltage drop of the rectifying element is smaller than a built-in voltage of a pn junction between the body region and the barrier region.   8. The MOSFET according to claim 7, further comprising an electric field progress preventing region made of a second conductivity type semiconductor formed between the barrier region and the drift region.

Images