JP5658944B2 - Diode, motor drive circuit, three-phase motor, hybrid vehicle and automobile - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having heterojunction bodies having different forbidden bandwidths.

  A heterojunction of AlGaN and GaN, which is a nitride semiconductor, has a higher dielectric breakdown electric field and a higher sheet carrier concentration than a silicon pn junction. Thus, it has been proposed to improve the diode performance by using such a heterojunction as a diode to improve the breakdown voltage and reduce the on-resistance.

  For example, in the following Patent Document 1, a laminated structure having a heterojunction in which a GaN layer (103) and an AlGaN layer (104) are laminated, and a first end of the laminated structure are formed. A Schottky barrier having a Schottky electrode (106) that is Schottky-connected to the heterojunction and an ohmic electrode (107) that is formed at the second end of the stacked structure and is ohmically connected to the heterojunction A diode is disclosed. In addition, the code | symbol in the said parenthesis is a code | symbol described in patent document 1. FIG.

JP 2009-117485 A

  The present inventor is considering improving the characteristics of a heterojunction in which semiconductor films having different forbidden bandwidths are stacked as a semiconductor device, particularly a diode.

  However, when the present inventors examined, as will be described in detail later, when processing the heterojunction (dry etching), defects are likely to occur in the semiconductor film (for example, GaN layer) exposed from the end of the side wall, There existed the subject that the characteristic deteriorated. In particular, when the diode is reverse-biased, there is a problem that a leak current is likely to occur and a predetermined breakdown voltage cannot be secured.

  In view of the above problems, an object of the present invention is to provide a technique capable of improving the characteristics of a semiconductor device.

  Another object of the present invention is to provide a semiconductor device manufacturing method capable of improving the characteristics of the semiconductor device.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Among the inventions disclosed in the present application, the semiconductor device shown in a representative embodiment includes a first stacked layer having at least one heterojunction in which a first film and a second film having different forbidden band widths are stacked. Have a body. And a second laminated body made of a laminate of the same layer as the first laminated body, and a groove provided between the first laminated body and the second laminated body. Is disposed so as to extend from the top of the first stacked body to the top of the second stacked body, and is disposed so as to be in contact with the first sidewall of the first stacked body, and is connected to the first stacked body by a Schottky connection. And a second electrode disposed so as to be in contact with the second side wall facing the first side wall of the first stacked body.

  Among the inventions disclosed in the present application, a method for manufacturing a semiconductor device shown in a representative embodiment includes a stacked film by repeatedly stacking a first film and a second film having different forbidden bandwidths above a substrate. Forming the groove and selectively removing the laminated film to form a groove that is disposed in the annular region and exposes the first film of the lowermost layer of the laminated film on the bottom surface, and on the outside of the region A step of leaving the first laminated body and leaving the second laminated body inside the region; filling the inside of the groove; and extending from an upper part of the first laminated body to an upper part of the second laminated body. Forming a first electrode in contact with the first side wall, and forming a second electrode in contact with the second side wall facing the first side wall of the first stacked body.

  Among the inventions disclosed in the present application, according to the semiconductor device described in the following representative embodiment, the characteristics of the semiconductor device can be improved.

  In addition, among the inventions disclosed in the present application, according to the method for manufacturing a semiconductor device shown in the following representative embodiment, a semiconductor device with good characteristics can be manufactured.

It is a cross-sectional perspective view of the semiconductor device of Embodiment 1 which is one embodiment of the present invention. It is a top view of the semiconductor device of Embodiment 1 which is one embodiment of the present invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of Embodiment 1 which is one embodiment of this invention. FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment which is an embodiment of the present invention, and is a main-portion cross-sectional view in the manufacturing process of the semiconductor device following FIG. 3; FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment which is an embodiment of the present invention, and is a main-portion cross-sectional view in the manufacturing process of the semiconductor device following FIG. 4; FIG. 6 is a top view showing the manufacturing process of the semiconductor device of the first embodiment which is an embodiment of the present invention, and is a top view in the manufacturing process of the semiconductor device corresponding to FIG. 5; FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first embodiment which is an embodiment of the present invention, and is a main-portion cross-sectional view in the manufacturing process of the semiconductor device following FIG. 5; FIG. 8 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is an embodiment of the present invention, and is a cross-sectional view of main parts in the manufacturing process of the semiconductor device following FIG. 7; It is a top view which shows the other structure of the semiconductor device of Embodiment 1 which is one embodiment of this invention. It is a top view which shows the other structure of the semiconductor device of Embodiment 1 which is one embodiment of this invention. It is a top view which shows the other structure of the semiconductor device of Embodiment 1 which is one embodiment of this invention. It is a cross-sectional perspective view of the semiconductor device of Embodiment 4 which is one embodiment of this invention. It is a top view of the semiconductor device of Embodiment 4 which is one embodiment of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of Embodiment 4 which is one embodiment of this invention. FIG. 15 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is an embodiment of the present invention, and is a cross-sectional view of main parts in the manufacturing process of the semiconductor device following FIG. 14; FIG. 16 is a top view showing a manufacturing process of the semiconductor device of the fourth embodiment which is an embodiment of the present invention, and is a top view in the manufacturing process of the semiconductor device corresponding to FIG. 15; FIG. 16 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is an embodiment of the present invention, and is a cross-sectional view of main parts in the manufacturing process of the semiconductor device following FIG. 15; FIG. 18 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is an embodiment of the present invention, and is a main-portion cross-sectional view in manufacturing process of the semiconductor device following FIG. 17; FIG. 19 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is an embodiment of the present invention, and is a cross-sectional view of main parts in the manufacturing process of the semiconductor device following FIG. 18; FIG. 20 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is an embodiment of the present invention, and is a main-portion cross-sectional view in manufacturing process of the semiconductor device following FIG. 19; It is a cross-sectional perspective view of the semiconductor device of Embodiment 5 which is one embodiment of this invention. It is a top view of the semiconductor device of Embodiment 5 which is one embodiment of the present invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device of Embodiment 5 which is one embodiment of this invention. FIG. 24 is a top view showing a manufacturing process of the semiconductor device of the fifth embodiment which is an embodiment of the present invention, and is a top view in the manufacturing process of the semiconductor device corresponding to FIG. 23; FIG. 24 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is an embodiment of the present invention; FIG. 26 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is an embodiment of the present invention, and is a cross-sectional view of main parts in the manufacturing process of the semiconductor device following FIG. 25; FIG. 27 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is an embodiment of the present invention, and is a cross-sectional view of main parts in the manufacturing process of the semiconductor device following FIG. 26; FIG. 28 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5 which is an embodiment of the present invention, which is subsequent to FIG. 27, in the manufacturing process of the semiconductor device; It is a circuit diagram of a three-phase motor. It is sectional drawing which shows the cross section of the semiconductor device which is a comparative example.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments illustrating the present invention will be described in detail with reference to the drawings.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
The configuration of the semiconductor device (Schottky barrier diode) of the present embodiment will be described with reference to FIGS. FIG. 1 is a cross-sectional perspective view of the semiconductor device of the present embodiment, and FIG. 2 is a top view of the semiconductor device of the present embodiment. FIG. 1 corresponds to, for example, the AA cross section of FIG.

  As shown in FIGS. 1 and 2, the semiconductor device of the present embodiment includes a substrate 103, a buffer layer 105, a stacked body (laminated structure) H, a dummy stacked body (dummy pattern) D, and a stacked body. The insulating film 111 laminated | stacked on the upper part of H and the dummy laminated body D, 1st electrode (Schottky electrode) SE, and 2nd electrode (ohmic electrode) OHE are included. A groove (concave portion) G is disposed between the stacked body H and the dummy stacked body D.

  The substrate 103 is, for example, a Si (silicon) substrate. In addition to the Si substrate, a GaN substrate, a SiC substrate, a sapphire substrate, or the like may be used.

  The buffer layer (buffer layer, stress relaxation layer) 105 is disposed on the substrate 103 and is made of, for example, an undoped AlGaN layer. Note that undoped means that n-type or p-type impurities are not contained, or that the concentration is low even if impurities are contained. The buffer layer is formed for stress relaxation by stacking the substrate 103 and the upper stacked body H and the dummy stacked body D. In addition to the undoped AlGaN layer, an AlN layer or the like may be used, and a film having a film stress (for example, a warp (convex or concave) of the film) and a reverse stress generated when stacked is used as the buffer layer 105.

  The stacked body H has a structure in which semiconductor films that are lattice-matched in a stacked surface are repeatedly stacked although the forbidden band width is different. The semiconductor film constituting the stacked body H is a compound semiconductor. For example, a GaN film and an AlGaN film that are nitride compound semiconductors can be used. Specifically, the stacked body H includes a GaN film 107a1, an AlGaN film 109a1, a GaN film 107a2, and an AlGaN film 109a2 from the lower layer.

  The GaN film 107a1 and the AlGaN film 109a1 of the stacked body H constitute a heterojunction body Ha1, and the GaN film 107a2 and the AlGaN film 109a2 constitute a heterojunction body Ha2. Here, the forbidden band width of GaN is smaller than the forbidden band width of AlGaN, and in one heterojunction, a film having a large forbidden band width is disposed in the upper layer.

As described above, the semiconductor films having lattice matching are joined although the forbidden band width is different. Here, a GaN film and an AlGaN film will be described as an example. When GaN and AlGaN are stacked in the c-axis direction, the lattice constant of GaN on the stacked surface is 0.3189 nm, which is close to the lattice constant of AlN of 0.3114 nm, and the lattice constant of AlGaN is that of AlN. It is a value according to the composition ratio between the lattice constant and the lattice constant of GaN, and takes an approximate value to the lattice constant of GaN. Therefore, the GaN film and the AlGaN film can be grown (formed) as continuous crystals. On the other hand, due to the difference in the forbidden band width of these films, an electron layer (channel) is generated in the vicinity of the interface on the GaN film side (see the broken line in FIG. 1). This electron layer is called a two-dimensional electron gas. For example, in the case of an AlGaN / GaN heterostructure, a high-concentration electron layer on the order of 10 ¹³ (cm ⁻² ) can be obtained, so that the on-resistance can be reduced. Further, by stacking a plurality of heterojunctions (Ha1, Ha2), it is possible to further reduce the on-resistance.

  The dummy stacked body D is composed of a stacked film in the same layer as the stacked body H. In this case, the dummy stacked body D also has a structure in which semiconductor films having lattice matching are repeatedly stacked although the forbidden band width is different. However, since the electrode in contact is only the first electrode SE and no potential difference occurs, the diode operation is not performed. The dummy laminate D includes a GaN film 107a1, an AlGaN film 109b1, a GaN film 107b2, and an AlGaN film 109b2 from the lower layer.

  An insulating film 111 is disposed on the stacked body H and the dummy stacked body D.

  Further, a groove G having a width W is provided between the stacked body H and the dummy stacked body D. On the bottom surface of the groove G, the lowermost GaN film 107a1 is exposed. Further, the inside of the groove G is filled with the first electrode SE, so that the first electrode SE comes into contact with the first side wall (inside a region a described later) of the stacked body H. The first electrode SE is disposed so as to fill the inside of the groove G from the insulating film 111 on the stacked body H, and further extends to the insulating film 111 on the dummy stacked body D.

  In addition, a second electrode (ohmic electrode) OHE is disposed in contact with a second side wall (outside a region a to be described later) facing the first side wall of the multilayer body H. Specifically, the second electrode OHE is arranged in contact with the second side wall from the insulating film 111 on the stacked body H in the direction of the second side wall, and further extends to the lowermost GaN film 107a1. Exist.

  The first electrode SE is a Schottky electrode that is in contact with the semiconductor film constituting the stacked body H and generates a Schottky barrier. The second electrode OHE is an ohmic electrode that is in contact with the semiconductor film constituting the stacked body H and has a relatively linear characteristic (ohmic characteristic) in voltage-current characteristics.

  As the first electrode (Schottky electrode) SE, for example, a Ni / Au laminated electrode, a Pt / Au laminated electrode, a Pd / Au laminated electrode, or the like is used. Further, as the second electrode (ohmic electrode) OHE, for example, a Ti / Al laminated electrode is used.

  Here, the formation area (the shape in a plan view from the upper surface, the pattern shape) of the stacked body H, the dummy stacked body D, and the groove G will be described with reference to FIG.

  As shown in FIG. 2, the stacked body H is disposed in the annular region a, the groove G is disposed in the annular region c along the inside of the annular region a, and the dummy laminate D is formed in the annular region a. It arrange | positions in the substantially circular area | region b inside c. When viewed three-dimensionally, the laminated body H is arranged in a cylindrical shape, and the dummy laminated body D is arranged in a cylindrical shape inside a cylinder made of the laminated body H. The first electrode SE is formed in a circular region that is slightly larger than the region c, and the second electrode OHE is formed in an annular region surrounding the first electrode SE. A region outside the annular region a is defined as a region d.

  Thus, in the above configuration, since the first and second electrodes (SE, OHE) and the stacked body H are brought into contact with each other on the side wall, it is possible to realize low-resistance bonding. Furthermore, the first electrode SE and the electron layer intersect each other substantially perpendicularly, so that no parallel plate capacitor is formed between them, and the capacitance can be reduced.

  Further, since the groove G is provided between the stacked body H and the dummy stacked body D, and the first electrode SE is embedded in the groove G, the processing of the stacked body H, that is, formation of the groove G is performed. At this time, even if impact due to dry etching or the like is applied to both sides (region c) of the laminate H due to impact due to dry etching, the bottom of the groove G has a small area. small. Therefore, when a reverse current is applied to the leakage current caused by contact between the defective portion and the first electrode SE, particularly the semiconductor device (diode), for example, the second electrode OHE is set to the ground potential (0 V), and the first electrode SE is Leakage current (hereinafter referred to as “reverse leakage current”) when a voltage is applied can be reduced.

  Note that a high electric field is not applied to the second electrode OHE side because of ohmic contact. Therefore, there is no need to consider the problem of reverse leakage current, and there is little need to form the dummy stacked body D and the groove G on the second electrode OHE side.

  Next, the method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 3 to 8 and the configuration of the semiconductor device will be further clarified. 3 to 8 are main-portion cross-sectional views or top views showing the manufacturing steps of the semiconductor device of the present embodiment.

  As shown in FIG. 3, for example, a Si substrate is prepared as the substrate 103, and an AlGaN layer, for example, is formed as a buffer layer 105 on the substrate 103 with a film thickness of about 2 μm by using a vapor phase epitaxy method. At this time, an impurity compound is not introduced into the film forming apparatus, and an undoped layer is formed. Subsequently, a GaN film 107 as a compound semiconductor film is formed on the buffer layer 105 to a thickness of about 2 μm by using a vapor phase epitaxy method. Next, an AlGaN film 109 is formed with a film thickness of about 20 nm using a vapor phase epitaxy method. Further, after the GaN film 107 is formed on the AlGaN film 109 with a thickness of about 20 nm, the AlGaN film 109 is formed with a thickness of about 20 nm. As described above, the GaN film and the AlGaN film have approximate lattice constants, and can be formed as continuous crystals only by adjusting the source gas in the vapor phase epitaxy method.

  Here, for the AlGaN film 109, the composition and amount of the supply gas are adjusted so that the molar ratio of AlN is 0.15. The molar ratio of AlN of 0.15 means that AlN is mixed in a proportion of 0.15 mol and GaN of 0.85 mol in AlGaN.

  Next, a silicon oxide film, for example, is deposited as an insulating film 111 on the AlGaN film 109 by a CVD (Chemical Vapor Deposition) method.

  Next, a photoresist film (not shown) is formed on the insulating film 111, and is exposed and developed (photolithography), thereby leaving the photoresist film in a predetermined region (here, region a and region b). Next, the insulating film 111 is etched using the remaining photoresist film as a mask, and the photoresist film is removed. Hereinafter, a process of forming a pattern having a desired shape by forming a film having a predetermined shape and etching (selectively removing) the film as a mask will be referred to as patterning. By this patterning step, the insulating film 111 is formed in the region a and the region b (FIG. 4).

  Next, as shown in FIGS. 5 and 6, using the insulating film 111 remaining in the region a and the region b as a mask, a laminated film of the GaN film 107 and the AlGaN film 109 is applied from the surface of the lowermost GaN film 107 to a predetermined level. Dry etch to depth. As the dry etching, for example, dry etching using chlorine plasma is used. Here, since an annular region c having a width W exists between the annular region a and the circular region b, a groove G is formed in the region c. The width (W) of the region c, that is, the width of the groove G is, for example, about 1 μm. On the bottom surface of the groove G, the lowermost GaN film 107a1 is exposed. Also, the lowermost GaN film 107a1 is exposed outside the region a (region d). Further, by this etching step, the stacked body H is formed in the region a, and the dummy stacked body D made of a film in the same layer as the stacked body H is formed in the region b. The width of the region a, that is, the interval between the first side wall and the second side wall of the stacked body H is, for example, 10 μm. In this dry etching, the surface of the insulating film 111 is also etched, and the final film thickness is about 0.7 μm.

  Here, the film remaining as the stacked body H in the region a is the GaN film 107a1, the AlGaN film 109a1, the GaN film 107a2, and the AlGaN film 109a2, and the film remaining as the dummy stacked body D in the region b is the GaN film 107a1, AlGaN. A film 109b1, a GaN film 107b2, and an AlGaN film 109b2 are used. The stacked body H has a heterojunction body Ha1 composed of the GaN film 107a1 and the AlGaN film 109a1, and a heterojunction body Ha2 composed of the GaN film 107a2 and the AlGaN film 109a2.

  Next, as shown in FIG. 7, the first electrode SE is formed so as to fill at least the groove G and cover the dummy stacked body D. Specifically, the insulating film 111 on the stacked body H is disposed inside the groove G so as to be in contact with the first side wall of the stacked body H, and further extends onto the insulating film 111 on the dummy stacked body D. Thus, the first electrode SE is formed. That is, the first electrode SE is formed on the inner periphery of the region b, the region c, and the region a (see FIG. 2). An example of a method for forming the first electrode SE is a lift-off method. For example, a photoresist film is formed using a photolithography method in a region other than the region where the first electrode SE is formed. Next, on the entire surface of the substrate 103 including the photoresist film, for example, a Schottky metal is deposited as a conductive film to form, for example, a Ni / Au laminated film. Next, by removing the photoresist film together with the Ni / Au laminated film deposited thereon, the Ni / Au laminated film can be left only in a desired region, thereby forming the first electrode SE.

  Next, as illustrated in FIG. 8, the second electrode OHE is formed so as to be in contact with at least the second side wall of the stacked body H. Here, the second electrode OHE is formed so as to extend from the insulating film 111 on the stacked body H to the lowermost GaN film 107a1 while being in contact with the second side wall of the stacked body H. That is, the second electrode OHE is formed on the outer periphery of the region a and the region d (see FIG. 2). The second electrode OHE can also be formed by using the lift-off method in the same manner as the first electrode SE. For example, a photoresist film is formed in a region other than the formation region of the second electrode OHE using a photolithography method. Next, on the entire surface of the substrate including the photoresist film, for example, an ohmic metal is deposited as a conductive film to form, for example, a Ti / Al laminated film. Next, the photoresist film is removed together with the Ti / Al laminated film deposited thereon, so that the Ti / Al laminated film remains only in a desired region to form the second electrode OHE.

  Through the above steps, the semiconductor device of the present embodiment described with reference to FIGS. 1 and 2 is substantially completed.

  As described above, according to the present embodiment, the dummy laminated body D is left at a predetermined distance W from the laminated body H, and the groove G formed between the laminated body H and the dummy laminated body D is used. Since the side wall contact (side contact) between the stacked body H and the first electrode SE is achieved by embedding the first electrode SE in the inside, the contact area between the first electrode SE and the bottom surface of the groove G is reduced. be able to. Therefore, since the area of the lowermost GaN film 107a1 exposed on the first electrode SE side is small even when dry etching is performed during patterning of the stacked body H, crystal defects generated there can be reduced. As a result, the contact probability between the crystal defect and the first electrode SE can be reduced, and the reverse leakage current can be suppressed.

  According to the inventors' investigation, when the reverse breakdown voltage was measured in the semiconductor device of the present embodiment, a good result of 1 ± 0.1 kV was obtained.

  FIG. 30 is a cross-sectional view of a semiconductor device which is a comparative example of the present embodiment. As shown in FIG. 30, the groove G and the dummy stacked body D are not provided, and the lowermost GaN film 107a1 exposed to the dry etching is widely exposed in the dry etching of the stacked body H on the first electrode SE side. In this case, the probability of contact between the crystal defect A on the exposed surface of the GaN film 107a1 and the first electrode SE increases, and the reverse leakage current increases.

  On the other hand, in the semiconductor device of the present embodiment, since the contact area between the first electrode SE and the bottom surface of the groove G is reduced as described above, the probability that the crystal defect and the first electrode SE are in contact can be ignored. Therefore, the reverse leakage current can be reduced.

  As described above, since a low potential such as a normal ground potential (0 V) is applied to the second electrode OHE side, there is no need to consider the problem of reverse leakage current, and on the second electrode OHE side, There is little need to form the dummy laminate D and the groove G.

  In addition, a configuration in which the first electrode SE is extended to the upper portion of the buffer layer 105 and the substrate 103 by dry etching can be considered. However, as described above, the buffer layer 105 is used for stress relaxation applied to the stacked body H or the like. In some cases, the film itself has a large number of crystal defects depending on the film type. Therefore, in the configuration in which the buffer layer 105 and the first electrode SE are in contact with each other, the reverse leakage current may increase, and it is preferable to employ the device configuration of the present embodiment.

  Moreover, in this Embodiment, although the laminated body H was formed using dry etching, you may use another processing method. Whatever processing method is used, a certain impact is likely to be applied to the lowermost GaN film 107a1 during processing, so that the film is likely to be defective. Therefore, even when other processing methods are used, the apparatus characteristics can be improved by adopting the apparatus configuration of the present embodiment.

  However, at present, there is no wet etching agent that can efficiently etch both AlGaN and GaN, and there is no choice but to use dry etching to perform efficient etching. In this dry etching, the surface exposed at the time of etching is easily subjected to an impact and a defect is likely to occur. Therefore, the apparatus configuration of the present embodiment is suitable.

  In the above device configuration, two heterozygotes (Ha1, Ha2) may be laminated, but three or more heterozygotes may be laminated. Thus, by increasing the number of stacked heterojunctions, that is, the number of channels, the on-resistance can be reduced.

  In the above apparatus configuration, the stacked body H is arranged in a ring shape, the first electrode SE is formed inside thereof, and the second electrode OHE is formed outside thereof, but the stacked body H is arranged in a line shape (rectangular shape). The first electrode SE may be disposed at one end (on the first side wall) and the second electrode OHE may be disposed at the other end (on the second side wall). However, by forming the electrodes (SE, OHE) in an annular shape or a circular shape, the electric field concentration at the pattern end can be suppressed, and the device characteristics can be further improved.

  Further, in the above device configuration, the laminate H is formed in an annular shape, and its outer shape (the shape of the second side wall in a plan view from the upper surface, the outer shape of the region a) is circular, but this shape is limited to a circle. However, other shapes such as an ellipse and a polygon may be used. The outer shape of the stacked body H (outer shape of the region a), the outer shape of the region b, and the outer shape of the region c are similar, and various modifications can be made in the same manner. Here, the outer shape of the stacked body H (the shape of the second side wall in the plan view from the upper surface, the outer shape of the region a) is described, but the same applies to the outer shape of the region b and the outer shape of the region c.

  Hereinafter, an example of a modification will be described with reference to FIGS.

  9 to 11 are top views showing other configurations of the semiconductor device of the present embodiment.

  In the semiconductor device shown in FIG. 9, the outer shape of the stacked body H (the shape of the second side wall in the plan view from the upper surface, the outer shape of the region a) is substantially elliptical. As described above, the outer shape of the stacked body H (the shape of the second side wall in a plan view from the upper surface, the outer shape of the region a) may be a substantially elliptical shape that is a combined shape of a rectangle and two semicircles. In this case, a plurality of semiconductor devices (semiconductor elements) may be arranged symmetrically with respect to a line in the long side direction of a substantially ellipse. That is, a plurality of semiconductor elements may be arranged in the x direction. By arranging in this way, semiconductor elements can be arranged at high density, and a high-performance semiconductor device with a small area can be realized. In addition, by disposing the second electrode OHE outside the region a, the second electrode OHE of each semiconductor element can be easily brought into contact and electrically connected. In other words, it can be a continuous pattern. Therefore, also in this respect, high integration of elements can be achieved. Thus, by arranging the second electrode OHE on the outside and sharing it, a simple configuration and easy patterning (manufacturing process) can be realized.

  Note that it is possible to dispose the second electrode OHE inside the region a and the first electrode SE outside the region a, but in this case, the second electrode OHE is arranged outside the region a. The first electrode SE comes into contact. At this time, if a crystal defect occurs in any one of the plurality of semiconductor elements and comes into contact with the first electrode SE, reverse leakage current is generated in all connected elements, that is, the entire apparatus, and the device characteristics are greatly improved. It deteriorates to.

  On the other hand, according to the present embodiment, the second electrode OHE is arranged on the outside and shared, so that the deterioration of the characteristics can be avoided.

  In the semiconductor device shown in FIG. 10, the outer shape of the stacked body H (the shape of the second side wall in a plan view from the upper surface, the outer shape of the region a) is rectangular. As described above, the outer shape of the stacked body H may be rectangular, and a plurality of semiconductor devices (semiconductor elements) may be arranged in line symmetry with respect to the long side and the short side of the rectangle. That is, a plurality of semiconductor elements may be arranged in an array in the x direction and the y direction. By arranging in this way, semiconductor elements can be arranged highly integrated, and a high-performance semiconductor device with a small area can be realized. Also in this case, similarly to the semiconductor device shown in FIG. 9, since the second electrode OHE is arranged outside and used in common, the device can be highly integrated and the device characteristics can be improved. Further, the second electrode OHE can be shared by easy patterning (manufacturing process).

  In the semiconductor device shown in FIG. 11, the outer shape of the stacked body H (the shape of the second side wall in the plan view from the upper surface, the outer shape of the region a) is a hexagonal shape. As described above, the outer shape of the stacked body H may be hexagonal, and a plurality of semiconductor devices (semiconductor elements) may be arranged side by side in line symmetry with respect to the hexagonal long-side line. That is, a plurality of semiconductor elements may be arranged in the x direction, and in the y direction, the two sides that intersect at an angle of 120 degrees may be alternately arranged. By arranging in this way, semiconductor elements can be arranged highly integrated, and a high-performance semiconductor device with a small area can be realized. Also in this case, similarly to the semiconductor device shown in FIG. 9, since the second electrode OHE is arranged outside and used in common, higher integration of the device and further improvement of the device characteristics can be achieved. Further, the second electrode OHE can be shared by easy patterning (manufacturing process). In addition, by patterning so that a predetermined plane orientation (for example, {1-100} plane, etc.) is exposed on two sides that intersect at an angle of 120 degrees, the etched surface becomes flatter and reverse leakage current is reduced. Further improvements in device characteristics such as reduction can be achieved.

  In FIG. 10, the outer shape of the laminate H may be a regular square, and in FIG. 11, the outer shape of the laminate H may be a regular hexagon.

(Embodiment 2)
In the first embodiment, the first and second side walls of the multilayer body H are formed perpendicularly (approximately 90 degrees) to the uppermost layer film of the multilayer body H (see FIG. 1 and the like). May be tapered.

  For example, in the manufacturing process of the semiconductor device of the first embodiment, the AlN molar ratio in the AlGaN film is set to 0.04, and 100 sets of heterojunctions of GaN film and AlGaN film are stacked. Next, by adjusting the dry etching conditions, the angle formed between the uppermost layer film of the stacked body H and the first sidewall and the angle formed between the uppermost layer film of the stacked body H and the second sidewall are about 97 degrees. The 100 sets of heterozygotes are etched so as to be. In this case, the difference between the shortest channel length of the uppermost heterojunction and the longest channel length of the lowermost heterojunction is 10% or less of the average channel length. In such a case, considering variations in manufacturing conditions, 100 channels can be regarded as almost uniform, and there is no problem in operation. Therefore, for example, when heterojunctions (total film thickness: 4 μm) are stacked with a width of about 10 μm, an inclination greater than 90 degrees and not more than 97 degrees may be provided on the sidewall.

  Further, according to the inventor's study, in the semiconductor device having the tapered laminated film H of the present embodiment, the resistance per channel is higher than that of the semiconductor device shown in the first embodiment (FIG. 1). It has been found that the on-resistance can be reduced to 1/10 by increasing the number of channels by 50 times.

  Further, even if the AlN molar ratio in the AlGaN film is increased to 0.09, it is possible to stack about 20 heterojunctions of GaN film and AlGaN film. In this case, the semiconductor shown in Embodiment 1 It was found that the on-resistance can be reduced to ¼ compared to the device (FIG. 1).

(Embodiment 3)
In Embodiment 1, a GaN film and an AlGaN film are used as a heterojunction, but other semiconductor films may be used. For example, an InAlN film may be used instead of the AlGaN film. That is, a laminated film of a GaN film and an InAlN film may be used as the heterojunction body. As described above, the lattice constant of GaN on the stacked surface is 0.3189 nm, the lattice constant of AlN is 0.3114 nm, and the lattice constant of InN is 0.3548 nm. Therefore, the lattice constant of InGaN is a value according to the composition ratio between the lattice constant of AlN and the lattice constant of InN, and takes a value approximate to the lattice constant of GaN. Here, the forbidden band width of GaN is smaller than the forbidden band width of InGaN, and in one heterojunction, an InAlN film that is a film having a large forbidden band width is disposed in the upper layer.

  As described above, by using a heterojunction of a GaN film and an InAlN film and stacking about 100 heterojunctions, the number of channels can be significantly increased, and the on-resistance can be reduced. .

  About the manufacturing process of the semiconductor device of this Embodiment, it can form by the process similar to Embodiment 1. FIG. The difference is that after the GaN film is formed in the same manner as in the first embodiment, an InAlN film may be formed thereon instead of the AlGaN film (109) film forming step. For example, the composition and amount of the supply gas may be adjusted so that the molar ratio of InN is 0.18, and the InAlN film may be formed to a thickness of about 20 nm using a vapor phase epitaxy method. Next, the GaN film and the InAlN film are alternately formed to form 100 sets of laminated films (heterojunction). Thereafter, as in the first embodiment, after an insulating film is formed, a laminated body, a groove and a dummy laminated body are formed by dry etching, and further, a first electrode and a second electrode may be formed.

  According to the inventor's study, in the semiconductor device of the present embodiment, the resistance per channel can be maintained equal to that of the semiconductor device shown in the first embodiment (FIG. 1), and the number of channels is 50. It was found that the on-resistance can be reduced to 1/50 by being able to be doubled. Further, it was found that the on-resistance is about 1/5 as compared with the semiconductor device of the second embodiment.

(Embodiment 4)
In the present embodiment, the reverse leakage current is reduced by providing an insulating film between the lowermost GaN film 107a1 and the first electrode SE.

  The configuration of the semiconductor device (Schottky barrier diode) of the present embodiment will be described with reference to FIGS. FIG. 12 is a cross-sectional perspective view of the semiconductor device of the present embodiment, and FIG. 13 is a top view of the semiconductor device of the present embodiment. FIG. 12 corresponds to, for example, the AA cross section of FIG.

  As shown in FIGS. 12 and 13, the semiconductor device of this embodiment includes a substrate 103, a buffer layer 105, a stacked body H, an insulating film 113 a stacked on the stacked body H, and a first electrode. (Schottky electrode) SE, second electrode (ohmic electrode) OHE, and insulating films 113b and 113d located on the lowermost GaN film 107a1. The lowermost GaN film 107a1 and the first electrode SE are insulated by an insulating film 113b. The lowermost GaN film 107a1 and the second electrode OHE are also insulated by the insulating film 113d.

  The substrate 103, the buffer layer 105, and the stacked body H have the same structure as in Embodiment 1, and are formed using the same material.

  The first electrode SE is disposed in contact with the first side wall of the multilayer body H (inside a region a to be described later). Specifically, the first electrode SE is arranged in contact with the first side wall from the insulating film 113a on the stacked body H in the direction of the first side wall, and further extends onto the insulating film 113b. Yes.

  In addition, the second electrode OHE is disposed in contact with the second side wall (outside the region a described later) facing the first side wall of the multilayer body H. Specifically, the second electrode OHE is arranged in contact with the second side wall from the insulating film 113a on the stacked body H in the direction of the second side wall, and further extends onto the insulating film 113d. Yes.

  The first electrode SE is a Schottky electrode that is in contact with the semiconductor film constituting the stacked body H and generates a Schottky barrier. The second electrode OHE is an ohmic electrode that is in contact with the semiconductor film constituting the stacked body H and has a relatively linear characteristic (ohmic characteristic) in voltage-current characteristics.

  As the first electrode (Schottky electrode) SE, for example, a Ni / Au laminated electrode, a Pt / Au laminated electrode, a Pd / Au laminated electrode, or the like is used. Further, as the second electrode (ohmic electrode) OHE, for example, a Ti / Al laminated electrode is used.

  Here, the formation region (shape in plan view from the upper surface) of the stacked body H will be described with reference to FIG.

  As shown in FIG. 13, the laminated body H is arrange | positioned at the cyclic | annular area | region a, and the substantially circular area | region b inside it is a recessed part. The first electrode SE is formed so as to cover the substantially circular region b, and the second electrode OHE is formed in an annular region surrounding the first electrode SE.

  Thus, in the above configuration, since the first and second electrodes (SE, OHE) and the stacked body H are brought into contact with each other on the side wall, it is possible to realize low-resistance bonding. Furthermore, since the first electrode SE and the electronic layer intersect each other substantially perpendicularly, and no parallel plate capacitor is formed between them, the capacitance can be reduced.

  Further, in the above configuration, since the insulating film 113b is disposed on the lowermost GaN film 107a1, even when crystal defects are generated on both sides of the stacked body H due to impact due to dry etching or the like when the stacked body H is processed. The defect portion and the first electrode SE are not in contact with each other, and the reverse leakage current can be reduced.

  Next, the method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 14 to 20 and the configuration of the semiconductor device will be further clarified. 14 to 20 are main-portion cross-sectional views or top views showing the manufacturing process of the semiconductor device of the present embodiment.

  As shown in FIG. 14, for example, a Si substrate is prepared as the substrate 103, and an AlGaN layer, for example, is formed as a buffer layer 105 on the substrate 103 with a film thickness of about 2 μm using a vapor phase epitaxy method. At this time, an impurity compound is not introduced into the film forming apparatus, and an undoped layer is formed. Subsequently, a GaN film 107 is formed on the buffer layer 105 as a compound semiconductor film to a thickness of about 2 μm. Next, an AlGaN film 109 is formed with a thickness of about 20 nm. Further, after the GaN film 107 is formed on the AlGaN film 109 with a thickness of about 20 nm, the AlGaN film 109 is formed with a thickness of about 20 nm. As described above, the GaN film and the AlGaN film have approximate lattice constants, and can be formed as continuous crystals only by adjusting the source gas in the vapor phase epitaxy method.

  Here, for the AlGaN film 109, the composition and amount of the supply gas are adjusted so that the molar ratio of AlN is 0.15. An AlN molar ratio of 0.15 means that AlGaN is mixed crystal at a ratio of 0.15 mol of AlN and 0.85 mol of GaN.

  Next, for example, a silicon oxide film is deposited on the AlGaN film 109 as an insulating film (not shown) by a CVD method. Next, a mask for dry etching is formed by patterning the insulating film. Here, the insulating film is left in the region a (see FIGS. 15 and 16).

  Next, as shown in FIGS. 15 and 16, using the insulating film remaining in the region a as a mask, the laminated film of the GaN film 107 and the AlGaN film 109 is dry-etched from the surface of the lowermost GaN film 107 to a predetermined depth. To do. As the dry etching, for example, dry etching using chlorine plasma is used. By this etching step, the stacked body H is formed in the region a, and the lowermost GaN film 107a1 is exposed inside and outside the annular region a. The width of the region a, that is, the interval between the first side wall and the second side wall is, for example, 10 μm. In the present embodiment, a region inside the region a is a region b, and a region outside the region a is a region d.

  Next, as shown in FIG. 17, the dry etching mask is removed, and an insulating film 113 is formed on the entire surface of the substrate 103, that is, on the exposed surfaces of the stacked body H and the lowermost GaN film 107 a 1 by sputtering. Form. As the insulating film 113, for example, a silicon oxide film can be used. According to the sputtering method, many particles are deposited in the flat portion, but the particles hardly adhere to the side wall portion of the stacked body H. As a result, the film thickness of the flat portion is large and the film thickness of the side wall portion is Get smaller. The film thickness of the side wall here refers to the film thickness in the direction parallel to the substrate surface. Using the sputtering method, the flat part, that is, the insulating film 113 on the lowermost GaN film 107a1 and the insulating film 113 on the stacked body H are deposited so as to have a thickness of about 1 μm. In this case, the film thickness of the insulating film 113 on the side wall portion of the stacked body H is about 0.2 μm.

  Next, the surface of the insulating film 113 is isotropically etched. For example, a buffered hydrofluoric acid solution is used to isotropically etch the silicon oxide film constituting the insulating film 113 from the surface to a thickness of about 0.3 μm. As a result, as shown in FIG. 18, the insulating film on the side wall portion of the multilayer body H is removed, and the side wall of the multilayer body H is exposed. On the other hand, the flat portion, that is, the insulating film (113) on the lowermost GaN film 107a1 and the insulating film (113) on the stacked body H remain, and the film thickness becomes about 0.7 μm. In FIG. 18, the insulating films on the lowermost GaN film 107a1 are shown as 113b and 113d, and the insulating films on the stacked body H are shown as 113a.

  Next, as shown in FIG. 19, the first electrode SE is formed so as to be in contact with the first side wall of the multilayer body H. Specifically, the insulating film 113a on the stacked body H is disposed so as to be in contact with the first side wall of the stacked body H, and further extends to the insulating film 113b positioned on the lowermost GaN film 107a1. The first electrode SE is formed. That is, the first electrode SE is formed on the inner periphery of the region b and the region a (see FIG. 13). The first electrode SE can be formed, for example, by a lift-off method as in the first embodiment, using a Ni / Au laminated film or the like.

  Next, as illustrated in FIG. 20, the second electrode OHE is formed so as to be in contact with at least the second side wall of the stacked body H. Specifically, the insulating film 113a on the stacked body H is disposed so as to be in contact with the second side wall of the stacked body H, and further extends to the insulating film 113d located on the lowermost GaN film 107a1. Thus, the second electrode OHE is formed. That is, the second electrode OHE is formed on the outer periphery of the region a and the region d (see FIG. 13). The second electrode OHE can also be formed by a lift-off method using a Ti / Al laminated film or the like, as in the first embodiment.

  Through the above steps, the semiconductor device of the present embodiment described with reference to FIGS. 12 and 13 is substantially completed.

  As described above, according to the present embodiment, since the insulating films 113b and 113d are formed on the lowermost GaN film 107a1 and the first electrode SE and the second electrode OHE are disposed thereon, the stacked body H Even when crystal defects are generated on both sides of the stacked body H due to an impact caused by dry etching or the like during the processing, the defect portion and the first electrode SE do not contact each other, and the reverse leakage current can be reduced.

  Further, according to the inventors' investigation, when the reverse breakdown voltage was measured in the semiconductor device of the present embodiment, a good result of 1 ± 0.1 kV was obtained.

(Embodiment 5)
In the present embodiment, the structure in which the stacked body H, the dummy stacked body D, and the groove G are provided in the same manner as in the first embodiment, but the most exposed from the bottom of the groove G and the end of the second side wall of the stacked body H. By providing an insulating film on the lower GaN film 107a1, the reverse leakage current is reduced.

  The configuration of the semiconductor device (Schottky barrier diode) of the present embodiment will be described with reference to FIGS. FIG. 21 is a cross-sectional perspective view of the semiconductor device of the present embodiment, and FIG. 22 is a top view of the semiconductor device of the present embodiment. FIG. 21 corresponds to, for example, the AA cross section of FIG.

  As shown in FIGS. 21 and 22, the semiconductor device of the present embodiment is arranged on a substrate 103, a buffer layer 105, a stacked body H, a dummy stacked body (dummy pattern) D, and the stacked body H. The insulating film 113a, the insulating film 113b disposed on the dummy stacked body D, the groove (concave portion) G provided between the stacked body H and the dummy stacked body D, and the bottom of the groove G An insulating film 113c, an insulating film 113d disposed on the lowermost GaN film 107a1 exposed from the end of the second side wall (side wall opposite to the first side wall, outside the region a) of the stacked body H, and the first It has an electrode (Schottky electrode) SE and a second electrode (ohmic electrode) OHE.

  The first electrode SE is embedded in the groove G, so that the first electrode SE is in contact with the first side wall (inside a region a to be described later) of the stacked body H. Since the insulating film 113c is disposed, the lowermost GaN film 107a1 exposed from the bottom surface of the groove G does not contact the first electrode SE, and the reverse leakage current can be reduced.

  Each component has the same configuration as that in Embodiment 1 or Embodiment 2, and can be configured in the same shape using the same material.

  Next, with reference to FIGS. 23 to 28, the method for manufacturing the semiconductor device of the present embodiment will be described, and the configuration of the semiconductor device will be clarified. 23 to 28 are main-portion cross-sectional views or top views showing the manufacturing steps of the semiconductor device of the present embodiment.

  As shown in FIG. 23, for example, a Si substrate is prepared as the substrate 103, and for example, an AlGaN layer is formed on the substrate 103 as a buffer layer 105 with a film thickness of about 2 μm by vapor phase epitaxy. At this time, an impurity compound is not introduced into the film forming apparatus, and an undoped layer is formed. Subsequently, a GaN film (107) is formed as a compound semiconductor film with a film thickness of about 2 μm on the buffer layer 105 as in the first embodiment. Next, an AlGaN film (109) is formed to a thickness of about 20 nm. Further, after forming a GaN film (107) with a thickness of about 20 nm on the AlGaN film (109), an AlGaN film (109) is formed with a thickness of about 20 nm. As described above, the GaN film and the AlGaN film have approximate lattice constants, and can be formed as continuous crystals only by adjusting the source gas in the vapor phase epitaxy method.

  Next, a silicon oxide film, for example, is deposited as an insulating film on the AlGaN film (109) by a CVD method, and the insulating film is patterned to form a dry etching mask (not shown). Here, the insulating film is left in the annular region a and the inner circular region b (see FIG. 24).

  Next, using the insulating film remaining in the regions a and b as a mask, the laminated film of the GaN film (107) and the AlGaN film (109) is dry-etched from the surface of the lowermost GaN film (107) to a predetermined depth. . As the dry etching, for example, dry etching using chlorine plasma is used. By this etching process, the stacked body H is formed in the region a, and the dummy stacked body D is formed in the region b. Here, since an annular region c having a width W1 exists between the annular region a and the circular region b, a groove G is formed in the region c. On the bottom surface of the groove G, the lowermost GaN film 107a1 is exposed. In the region d outside the region a, the lowermost GaN film 107a1 is exposed.

  Next, the dry etching mask is removed, and an insulating film 113 is formed by a sputtering method as shown in FIG. According to this sputtering method, a large amount of particles are deposited in the flat portion, but the particles hardly adhere to the side wall portion of the stacked body H. As a result, the film thickness of the flat portion is large and the film thickness of the side wall portion is large. Becomes smaller.

  Next, the surface of the insulating film 113 is isotropically etched. For example, using a buffered hydrofluoric acid solution, the silicon oxide film constituting the insulating film 113 is isotropically etched from the surface by a thickness corresponding to at least the thickness of the side wall portion of the stacked body H. As a result, as shown in FIG. 26, the insulating film on the side wall portion of the multilayer body H is removed, and the side wall of the multilayer body H is exposed. On the other hand, the insulating film such as the flat portion, that is, the lowermost GaN film 107a1 exposed from the bottom of the groove G or the end of the second side wall of the stacked body H remains. In FIG. 26, 113c is the insulating film at the bottom of the groove G, and 113d is the insulating film on the lowermost GaN film 107a1 exposed from the end of the second side wall of the stacked body H. An insulating film on the stacked body H is denoted by 113a, and an insulating film on the dummy stacked body D is denoted by 113b.

  Next, as shown in FIG. 27, the first electrode SE is formed so as to fill at least the groove G and cover the dummy stacked body D. Specifically, the first electrode SE is disposed in the groove G so as to be in contact with the first side wall of the multilayer body H from the insulating film 113a on the multilayer body H, and further, the insulation on the dummy multilayer body D. It is formed to extend over the film 113b. That is, the first electrode SE is formed on the inner periphery of the region a, the region c, and the region b (see FIG. 22). The first electrode SE can be formed, for example, by a lift-off method as in the first embodiment, using a Ni / Au laminated film or the like.

  Next, as illustrated in FIG. 28, the second electrode OHE is formed so as to be in contact with at least the second side wall of the stacked body H. Specifically, the second electrode OHE extends from the insulating film 113a on the stacked body H to the insulating film 113d on the lowermost GaN film 107a1 while being in contact with the second side wall of the stacked body H. It is formed. That is, it is formed to extend from the outer periphery of the region a to the region d (see FIG. 22). The second electrode OHE can also be formed by a lift-off method using a Ti / Al laminated film or the like, as in the first embodiment.

  Through the above steps, the semiconductor device of the present embodiment described with reference to FIGS. 21 and 22 is substantially completed.

  As described above, according to the present embodiment, since the insulating film 113c is provided at the bottom of the groove G, the crystal defect and the first defect are generated even when a crystal defect occurs on the bottom surface of the groove G although the area is small. There is no contact with the one electrode SE, and the reverse leakage current can be reduced.

  In particular, when the embedding characteristics deteriorate due to the material and the embedding method embedded in the groove G, the width of the groove G must be increased. In such a case, the configuration and manufacturing method of the semiconductor device of the present embodiment Is preferable.

  In the second to fifth embodiments, various application examples and modifications described in the first embodiment such as various element configurations and layouts described with reference to FIGS. 9 to 11 can be adopted. Needless to say.

  In the first, fourth, and fifth embodiments, it is needless to say that the heterojunction having various compositions described in the second and third embodiments can be adopted, and the laminated film H can adopt a tapered shape.

  In the first to fifth embodiments, the electrodes (SE, OHE) are extended to places other than the side wall of the stacked body H. For example, a method such as a selective chemical vapor deposition method or an oblique deposition method is used. Thus, the electrode (particularly, the first electrode SE) may be in contact with only the side wall of the multilayer body H. However, it is difficult to control and select a material when forming a film only on the side wall. By adopting the device configuration and the manufacturing method of the first to fifth embodiments, a semiconductor device with good controllability and good characteristics can be obtained. Formation is possible.

(Embodiment 6)
Next, application examples of the semiconductor device (Schottky barrier diode) described in the first to fifth embodiments will be described.

  The semiconductor device can be used, for example, in a drive circuit for a three-phase motor used in a hybrid vehicle or the like.

  FIG. 29 is a circuit diagram of a three-phase motor. As shown in FIG. 29, the three-phase motor circuit has a three-phase motor 1, a power semiconductor device 2, and a control circuit 3. The three-phase motor 1 is configured to be driven by three-phase voltages having different phases. The power semiconductor device 2 includes a switching element that controls the three-phase motor 1. For example, an IGBT 4 and a diode 5 are provided corresponding to the three phases. That is, in each single phase, the IGBT 4 and the diode 5 are connected in antiparallel between the power supply potential (Vcc) and the input potential of the three-phase motor, and the input potential of the three-phase motor and the ground potential (GND) The IGBT 4 and the diode 5 are also connected in antiparallel between them. That is, in the three-phase motor 1, two IGBTs 4 and two diodes 5 are provided for each single phase (each phase), and six IGBTs 4 and six diodes 5 are provided for three phases. A control circuit 3 is connected to the gate electrode of each IGBT 4 although a part of the illustration is omitted, and the IGBT 4 is controlled by the control circuit 3. In the three-phase motor drive circuit configured in this way, the control circuit 3 controls the current flowing through the IGBT 4 (switching element) constituting the power semiconductor device 2 to rotate the three-phase motor 1. Yes. That is, the IGBT 4 functions as a switching element that supplies a power supply potential (Vcc) to the three-phase motor 1 or supplies a ground potential (GND), and the on / off timing of the IGBT 4 is determined. By controlling with the control circuit 3, the three-phase motor 1 can be driven.

  The IGBT 4 and the diode 5 are connected in antiparallel as shown in FIG. 29. The function of the diode at this time will be described.

  The diode 5 is not necessary when the load is a pure resistance that does not include an inductance because there is no energy to circulate. However, when a circuit including an inductance such as a motor (for example, a three-phase motor) is connected to the load, there is a mode in which a load current flows in a direction opposite to the ON switch (IGBT4). At this time, the switching element such as the IGBT 4 alone does not have a function of allowing the reverse current to flow, so it is necessary to connect a diode in antiparallel to the switching element such as the IGBT 4. That is, in the inverter circuit, when the load includes an inductance as in motor control, when the switching element such as the IGBT 4 is turned off, the energy (1 / 2LI2) stored in the inductance must be released. The IGBT 4 alone cannot flow a reverse current for releasing the energy stored in the inductance. Therefore, in order to recirculate the electric energy stored in the inductance, the diode 5 is connected in antiparallel with the IGBT 4. That is, the diode 5 has a function of flowing a reverse current in order to release the electric energy stored in the inductance.

  By using the semiconductor device described in the above embodiment as the diode 5, the circuit characteristics can be improved.

  Needless to say, the three-phase motor circuit is merely an example of application of the semiconductor device described in the above embodiment, and can be applied to various circuits by taking advantage of its good diode characteristics.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. .

  The present invention is effective when applied to a semiconductor device.

1 Three-phase motor 2 Power semiconductor device 3 Control circuit 4 IGBT
5 Diode 103 Substrate 105 Buffer layer 107, 107a1 GaN film 107a2 GaN film 107b2 GaN film 109, 109a1 AlGaN film 109a2 AlGaN film 109b1 AlGaN film 109b2 AlGaN film 111 Insulating film 113 Insulating film 113a-113d Insulating film A Crystal defect a D dummy laminate G groove H laminate Ha1 heterojunction Ha2 heterojunction OHE second electrode SE first electrode W width W1 width

Claims (8)

A first stacked body having at least one heterojunction in which a first film and a second film having different forbidden bandwidths are stacked;
The first stacked body, and a first electrode to be Schottky-connected,
The first laminate and a second electrode that is ohmically connected;
A second laminate comprising a laminate of the same layer as the first laminate,
A groove provided between the first stacked body and the second stacked body so as to surround the second stacked body;
I have a,
The second stacked body is disposed in a formation region of the first electrode,
The first electrode is disposed inside the groove;
The second electrode is a diode that is not in contact with the second stacked body . The diode of claim 1, wherein
The first film is a GaN film, and the second film is an AlGaN film or an InAlN film. The diode of claim 1, wherein
The width of the groove is about 1 μm. The diode of claim 1, wherein
The groove has a sidewall having an inclination greater than 90 degrees and less than 97 degrees.   A motor drive circuit comprising the diode according to claim 1.   A three-phase motor having the motor drive circuit according to claim 5.   A hybrid vehicle comprising the three-phase motor according to claim 6.   An automobile having the three-phase motor according to claim 6.

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