JP2009117820A - Nitride semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor device capable of suppressing dielectric breakdown and shrinking the chip area, and to provide a method of manufacturing the same. <P>SOLUTION: The nitride semiconductor device includes a nitride semiconductor stacked layer structure 5 in which an n<SP>+</SP>-type GaN substrate 1, n<SP>-</SP>-type GaN layer 2, p-type GaN layer 3, and n<SP>+</SP>-type GaN layer 4 are stacked in this order. A trench 7 is formed in the nitride semiconductor stacked layer structure 5. On the wall faces 8 of the trench 7, a gate electrode 10 is formed via a gate insulating film 9. On the n<SP>+</SP>-type GaN layer 4, a source electrode 15 forms an ohmic contact. On the other side surface of the n<SP>+</SP>-type GaN substrate 1, a drain electrode 18 forms an ohmic contact. A Schottky electrode 17 is formed on the n<SP>-</SP>-type GaN layer 2 exposed from contact opening 16 of the gate insulating film 9. The Schottky electrode 17 forms a Schottky contact to the n<SP>-</SP>-type GaN layer 2. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a nitride semiconductor device using a group III nitride semiconductor and a method for manufacturing the same.

Conventionally, power devices using silicon semiconductors are used in power amplifier circuits, power supply circuits, motor drive circuits, and the like.
However, due to the theoretical limits of silicon semiconductors, the increase in breakdown voltage, reduction in resistance, and increase in speed of silicon devices are reaching their limits, and it is becoming difficult to meet market demands.
Therefore, development of nitride semiconductor devices having characteristics such as high breakdown voltage, high temperature operation, large current density, high-speed switching, and low on-resistance has been studied.

FIG. 12 is a schematic cross-sectional view for explaining the structure of a conventional MOSFET.
The MOSFET 100 includes a sapphire substrate 81 and a stacked structure portion 93 formed on the sapphire substrate 81.
The stacked structure unit 93 includes an undoped GaN layer 82, an n-type GaN layer 83, a p-type GaN layer 84, and an n-type GaN layer 85 that are stacked in this order from the sapphire substrate 81 side. A mesa-shaped mesa laminated portion 92 is formed in the laminated structure portion 93 by dry etching from the surface of the n-type GaN layer 85 to the middle of the n-type GaN layer 83.

Both side surfaces of the mesa laminated portion 92 are inclined surfaces 91 inclined with respect to the laminated interface of the laminated structure portion 93. A gate insulating film 86 made of SiO ₂ (silicon oxide) is formed on the surface (including the inclined surface 91) of the multilayer structure portion 93.
In the gate insulating film 86, contact holes that partially expose the n-type GaN layer 85 and the n-type GaN layer 83 are formed. A source electrode 88 is formed on the n-type GaN layer 85 exposed from the contact hole so as to be in ohmic contact with the n-type GaN layer 85. On the other hand, a drain electrode 89 is formed in the n-type GaN layer 83 exposed from the contact hole so as to be in ohmic contact with the n-type GaN layer 83.

A gate electrode 87 is formed on a portion of the gate insulating film 86 facing the inclined surface 91. The source electrode 88, the drain electrode 89, and the gate electrode 87 are insulated from each other by interposing an interlayer insulating film 90 made of polyimide between adjacent electrodes.
Next, the operation of MOSFET 100 will be described. For example, first, a bias (reverse bias) in which the drain electrode 89 side becomes positive is applied between the source electrode 88 and the drain electrode 89 (between the source and drain). As a result, a reverse voltage is applied to the interface (pn junction) between the n-type GaN layer 83 and the p-type GaN layer 84, and as a result, between the n-type GaN layer 85 and the n-type GaN layer 83, That is, the source and drain are cut off (reverse bias state).

  From this state, when a bias equal to or higher than the gate threshold voltage that is positive with the source electrode 88 as a reference potential is applied to the gate electrode 87, the interface between the inclined surface 91 and the gate insulating film 86 in the p-type GaN layer 84. Electrons are induced in the vicinity (channel region) to form an inversion layer (channel). The operation of the MOSFET 100 is realized by conducting conduction between the source and the drain through the inversion layer.

However, in MOSFET 100, when a bias is applied to the drain electrode 89 so that the source electrode 88 side is positive (when the potential of the source electrode 88 is higher than the potential of the drain electrode 89), the n-type GaN layer 85 and the p-type The electric field concentrates between the GaN layer 84 and there is a risk of causing dielectric breakdown. Therefore, the MOSFET 100 is usually mounted on a semiconductor chip with a diode 94 connected between the source and drain so that the source electrode 88 is on the anode side, as shown in FIG. As a result, even when the potential of the source electrode 88 becomes higher than the potential of the drain electrode 89, current flows preferentially to the diode 94, so that the occurrence of dielectric breakdown can be suppressed.
JP 2003-163354 A

However, as shown in FIG. 13, in the configuration in which the MOSFET 100 and the diode 94 are separately manufactured, the area (chip area) of the semiconductor chip on which the MOSFET 100 is mounted is increased.
SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device and a method for manufacturing the same that can suppress dielectric breakdown and can reduce the chip area.

  In order to achieve the above object, an invention according to claim 1 is provided, wherein an n-type first layer made of a group III nitride semiconductor, a second layer containing p-type impurities stacked on the first layer, and the second layer A nitride semiconductor multilayer structure having an n-type third layer stacked on a layer and having a wall surface straddling the first, second, and third layers; and the first, second, and third layers on the wall surface A gate insulating film formed over the layers, a gate electrode formed so as to face the second layer across the gate insulating film, and a source electrode formed in ohmic contact with the third layer A drain electrode formed in ohmic contact with the first layer, and a Schottky electrode formed in Schottky contact with the first layer.

  According to this configuration, the npn-structured nitride semiconductor multilayer structure is formed by stacking the n-type first layer, the p-type impurity-containing second layer, and the n-type third layer made of a group III nitride semiconductor. The part is formed. A gate insulating film is disposed on the wall surface formed across the first, second, and third layers. A portion forming the wall surface of the second layer forms a channel region with the gate insulating film interposed therebetween, and a gate electrode is opposed to the channel region. Further, a source electrode is formed so as to be in ohmic contact with the third layer, and a drain electrode is formed so as to be in ohmic contact with the first layer.

Note that the source electrode and the drain electrode only need to be in ohmic contact with the third layer and the first layer, respectively, and two or more semiconductor layers having different compositions and impurities are stacked between these electrodes and the semiconductor layer. There may be.
Thus, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed in the nitride semiconductor element.

In addition, a Schottky electrode is formed in the nitride semiconductor element so as to be in Schottky contact with the first layer of the MOSFET, and an SBD (Schottky Barrier Diode: shot) composed of the first layer and the Schottky electrode. Key barrier diode).
Note that a group III nitride semiconductor is a semiconductor in which a group III element and nitrogen are combined, and aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are representative examples. In general, it can be expressed as Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

Next, the operation of this nitride semiconductor device will be described.
A bias with a positive drain side is applied between the source electrode and the drain electrode. As a result, a reverse voltage is applied to the pn junction at the interface between the first layer and the second layer, and as a result, between the third layer and the first layer, that is, between the source electrode and the drain electrode. (Between the source and drain) is cut off (reverse bias state). From this state, when a bias equal to or higher than the gate threshold voltage, which is positive with the source electrode as the reference potential, is applied to the gate electrode, the region near the wall surface (channel region) facing the gate electrode in the second layer has electrons. Is induced to form an inversion layer (channel).

The first layer and the third layer are electrically connected through the inversion layer. Thus, conduction between the source and the drain is established. That is, when a predetermined bias is applied to the gate electrode, the source and the drain become conductive, and when no bias is applied to the gate electrode, the source and the drain are cut off. In this way, a normally-off operation is realized.
In this nitride semiconductor device, the SBD and the source electrode are connected to each other, so that a bias that is positive on the source electrode side is applied to the drain electrode (the potential of the source electrode is higher than the potential of the drain electrode). The current can be preferentially passed through the SBD when the state is high. As a result, even when the potential of the source electrode is higher than the potential of the drain electrode, electric field concentration at the pn junction between the second layer and the third layer can be suppressed, and the MOSFET is insulated. Destruction can be suppressed.

Furthermore, since the diode for suppressing the occurrence of dielectric breakdown is formed as SBD using the first layer of the MOSFET, the MOSFET and the diode for countermeasure against dielectric breakdown can be integrated. As a result, it is possible to reduce the chip area of the nitride semiconductor device.
According to a second aspect of the present invention, the first layer includes a lower layer having a relatively high n-type impurity concentration and an upper layer having an n-type impurity concentration lower than the lower layer, and the Schottky electrode includes the first layer The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is formed so as to be in Schottky contact with an upper layer.

  According to this configuration, since the n-type impurity concentration of the upper layer is higher than the n-type impurity concentration of the lower layer, when the upper layer and the lower layer are compared, the upper layer spreads when the Schottky barrier is in the reverse bias state. It has a so-called high breakdown voltage structure that has a large depletion layer width and can withstand higher voltages. In this configuration, since the Schottky electrode is in Schottky contact with the upper layer having the high breakdown voltage structure, an SBD having excellent breakdown voltage performance can be formed by the configuration including the upper layer and the Schottky electrode.

  The nitride semiconductor multilayer structure portion is preferably formed on a conductive substrate. If the nitride semiconductor multilayer structure is formed on the conductive substrate, the drain electrode can be brought into ohmic contact with the first layer via the conductive substrate. Accordingly, the drain electrode is brought into ohmic contact with the conductive semiconductor substrate so as to face the nitride semiconductor multilayer structure portion, so that a space for contacting the drain electrode in the nitride semiconductor multilayer structure portion can be omitted. . That is, since the area of the nitride semiconductor multilayer structure portion can be reduced, the chip area of the nitride semiconductor element can be further reduced. The conductive substrate may also serve as the first layer. That is, in such a configuration, the Schottky electrode can be brought into Schottky contact with the conductive substrate.

The nitride semiconductor element preferably further includes a contact electrode formed so as to be in contact with the second layer and short-circuited to the source electrode.
According to this configuration, the contact electrode is formed so as to contact the second layer and to be short-circuited to the source electrode. Therefore, the potential of the second layer can be stabilized at the reference potential via the contact electrode by connecting the source electrode to the reference potential (for example, the ground potential).

The contact electrode is preferably made of the same metal as the Schottky electrode. The metal in Schottky contact with the n-type first layer makes ohmic contact with the second layer containing the p-type impurity. Therefore, if the contact metal and the Schottky electrode are formed using the same kind of metal, the contact electrode can be brought into ohmic contact with the second layer.
According to a third aspect of the present invention, in the nitride semiconductor multilayer structure portion, an annular trench that reaches the first layer from the third layer through the second layer is formed. A plurality of source electrodes are provided in a mesa stacked portion surrounded by the trench in the nitride semiconductor stacked structure portion, and one Schottky electrode is provided so as to surround the mesa stacked portion, and a plurality of the source electrodes are provided. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is connected to electrodes at a time.

  According to this configuration, one Schottky electrode that is collectively connected to the plurality of source electrodes is provided so as to surround the mesa laminated portion. Therefore, compared with the case where one Schottky electrode is provided for each source electrode, the space required for installation of the Schottky electrode in the entire chip can be reduced. As a result, the chip area of the nitride semiconductor device can be further reduced.

  According to a fourth aspect of the present invention, there is provided a first layer forming step of forming an n-type first layer made of a group III nitride semiconductor, and a p-type impurity made of a group III nitride semiconductor on the first layer. A second layer forming step of forming a second layer including the third layer forming step of forming an n-type third layer made of a group III nitride semiconductor on the second layer; A wall surface forming step for forming a wall surface straddling the third layer, a gate insulating film forming step for forming a gate insulating film on the wall surface so as to straddle the first, second and third layers, and the gate insulation A gate electrode forming step of forming a gate electrode so as to face the second layer across the film; a source electrode forming step of forming a source electrode so as to be in ohmic contact with the third layer; Drain that forms a drain electrode so as to be in ohmic contact with one layer A Schottky electrode for forming a Schottky electrode so as to be in Schottky contact with an exposed surface of the first layer exposed by the exposing step, an electrode forming step, an exposing step of partially exposing the first layer A method for manufacturing a nitride semiconductor device. By this method, the nitride semiconductor device according to claim 1 can be manufactured.

  The exposing step may be a step of dry etching the first, second and third layers to form a second wall surface extending over the first, second and third layers. In the case where the first layer forming step is a step of epitaxially growing the first layer, the exposing step is a step of forming an insulating film for partially stopping the growth of the first layer. The Schottky electrode forming step may be a step of forming a Schottky electrode so that the exposed surface of the first layer exposed by removing the insulating film is in Schottky contact. .

  According to a fifth aspect of the present invention, the first layer forming step includes a lower layer forming step of forming a lower layer having a relatively high n-type impurity concentration, and an n-type impurity concentration higher than the lower layer on the lower layer. An upper layer forming step of forming a lower upper layer, wherein the exposing step is a step of partially exposing at least the upper layer, and the Schottky electrode forming step is performed on the exposed surface of the upper layer exposed by the exposing step. The method for manufacturing a nitride semiconductor device according to claim 4, which is a step of forming a Schottky electrode. By this method, the nitride semiconductor device according to claim 2 can be manufactured.

The method for manufacturing a nitride semiconductor device may further include a step of forming a contact electrode made of the same kind of metal as the Schottky electrode so as to be in contact with the second layer and short-circuited to the source electrode. It is preferable to provide.
According to this method, the contact electrode formed so as to be in contact with the second layer and short-circuited to the source electrode is made of the same kind of metal as the Schottky electrode. The step of forming the electrode can be performed in parallel. Therefore, the process time of the nitride semiconductor element manufacturing process can be shortened, and the manufacturing cost can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device according to the first embodiment of the present invention. This nitride semiconductor device includes a conductive n ⁺ -type GaN substrate 1 (lower layer) and a nitride semiconductor multilayer structure portion 5 formed on one surface of the n ⁺ -type GaN substrate 1.
The nitride semiconductor multilayer structure 5 includes an n ⁻ -type GaN layer 2 (upper layer), a p-type GaN layer 3 (second layer) stacked on the n ⁻ -type GaN layer 2, and the p-type GaN layer 3. And a laminated n ⁺ -type GaN layer 4 (third layer).

The n ⁺ -type GaN substrate 1 and the n ⁺ -type GaN layer 4 have an n-type impurity concentration higher than that of the n ⁻ -type GaN layer 2, and the concentration is, for example, 3 × 10 ¹⁸ cm ⁻³ . On the other hand, the n type impurity concentration of the n ⁻ type GaN layer 2 is, for example, 1 × 10 ¹⁷ cm ⁻³ .
The nitride semiconductor multilayer structure portion 5 is etched in a direction crossing the multilayer interface from the n ⁺ -type GaN layer 4 to a depth at which the n ⁻ -type GaN layer 2 is exposed so that the cross section is substantially trapezoidal. The n ⁻ -type GaN layer 2 is drawn from both sides of the nitride semiconductor multilayer structure portion 5 in the lateral direction along the surface of the n ⁺ -type GaN substrate 1 (hereinafter, this direction is referred to as “width direction”). And has a drawer portion 6. In other words, the lead-out portion 6 is constituted by an extension of the n ⁻ -type GaN layer 2 in this embodiment.

On the other hand, a trench 7 having a depth extending from the n ⁺ -type GaN layer 4 to the middle portion of the n ⁻ -type GaN layer 2 through the p-type GaN layer 3 is located near the middle in the width direction of the nitride semiconductor multilayer structure portion 5. Is formed. In this embodiment, the trench 7 is formed in a substantially V-shaped cross section, and the inclined side surface of the trench 7 extends over the n ⁻ -type GaN layer 2, the p-type GaN layer 3 and the n ⁺ -type GaN layer 4. Is forming. A gate insulating film 9 is formed on the surfaces of the n ⁻ -type GaN layer 2, the p-type GaN layer 3 and the n ⁺ -type GaN layer 4 so as to cover the entire area of the wall surface 8.

The n ⁻ -type GaN layer 2, the p-type GaN layer 3 and the n ⁺ -type GaN layer 4 are formed on the n ⁺ -type GaN substrate 1 by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). It is epitaxially grown.
For example, when an n ⁺ -type GaN substrate 1 having a c-plane (0001) as the main surface is used, an n ⁻ -type GaN layer 2, a p-type GaN layer 3 and n that are grown on the n ⁺ -type GaN substrate 1 by epitaxial growth. ^{The +} -type GaN layer 4 is also laminated with the c-plane (0001) as the main surface. Further, the plane orientation of the wall surface 8 of the nitride semiconductor multilayer structure portion 5 is, for example, a plane (a plane other than the c plane) inclined in a range of 15 ° to 90 ° with respect to the c plane (0001). More specifically, for example, non-polar surfaces such as m-plane (10-10) or a-plane (11-20), and semipolar surfaces such as (10-13), (10-11), and (11-22) It becomes a surface.

The gate insulating film 9 can be made of, for example, nitride or oxide. More specifically, the gate insulating film 9 can be composed of SiN (silicon nitride), SiO ₂ (silicon oxide), or a combination thereof. A gate electrode 10 is formed on the gate insulating film 9.
The gate electrode 10, the wall surface 8 through the gate insulating film 9, namely n ^- faces the -type GaN layer 2, p-type GaN layer 3 and the n ⁺ -type GaN layer 4, furthermore, the n ⁺ -type GaN layer 4 The upper surface is formed to extend to the vicinity of the edge of the trench 7. The gate electrode 10 is made of, for example, Ni and Au laminated on the Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au alloy, Pd / Pt / Au alloy, Pt, Al. It can be made of a conductive material such as polysilicon.

A region near the wall surface 8 in the p-type GaN layer 3 is a channel region 11 facing the gate electrode 10. In this channel region 11, an inversion channel is formed that electrically conducts between the n ⁻ -type GaN layer 2 and the n ⁺ -type GaN layer 4 by applying an appropriate bias to the gate electrode 10.
In the nitride semiconductor multilayer structure portion 5, a contact electrode trench 12 is formed at a location different from the trench 7. In this embodiment, a pair of contact electrode trenches 12 are formed on both sides of the trench 7. The contact electrode trench 12 is formed at a depth from the upper surface of the n ⁺ -type GaN layer 4 to the p-type GaN layer 3. A contact electrode 13 is embedded in the contact electrode trench 12.

  The contact electrode 13 is in ohmic contact with the p-type GaN layer 3. For example, a Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au made of Ni and Au laminated on the Ni is used. An alloy, a Pd / Pt / Au alloy, and a metal such as Pt can be used. Since these metals have a low contact resistance with respect to the p-type GaN layer 3, the contact electrode 13 can be satisfactorily brought into ohmic contact with the p-type GaN layer 3.

A contact opening 14 is formed in the gate insulating film 9 to expose the upper surface of the contact electrode 13. The contact opening 14 is formed so that the contact electrode 13 is exposed and the edge of the contact electrode 13 on the upper surface of the n ⁺ -type GaN layer 4 is exposed. A source electrode 15 is formed on the contact electrode 13 and the n ⁺ -type GaN layer 4 exposed from the contact opening 14.

The source electrode 15 is in ohmic contact with the n ⁺ -type GaN layer 4 and the contact electrode 13. For example, the source electrode 15 is configured by using Ti and a metal such as a Ti / Al alloy made of Al laminated on the Ti. can do. By configuring the source electrode 15 with a metal containing Al, the source electrode 15 can be satisfactorily brought into ohmic contact with the n ⁺ -type GaN layer 4 and the contact electrode 13. In addition, the source electrode 15 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

A drain electrode 18 is formed in contact with the other surface of the n ⁺ -type GaN substrate 1. The drain electrode 18 is in ohmic contact with the n ⁺ -type GaN substrate 1. The drain electrode 18 can be configured using, for example, the same type of metal as the source electrode 15, that is, a metal such as a Ti / Al alloy. In addition, the drain electrode 18 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

Thus, in this nitride semiconductor element, a MOSFET 20 (Metal Oxide Semiconductor Field Effect Transistor: MOS) in which the gate electrode 10, the gate insulating film 9, the source electrode 15 and the drain electrode 18 are formed in the nitride semiconductor multilayer structure portion 5 is formed. Field effect transistor).
In this nitride semiconductor device, a contact opening 16 is formed in the gate insulating film 9 to expose the upper surface of the lead portion 6 of the n ⁻ -type GaN layer 2. A Schottky electrode 17 is formed on the n ⁻ -type GaN layer 2 exposed from the contact opening 16.

The Schottky electrode 17 fills up the contact opening 16 and extends to the vicinity of the edge of the contact opening 16 in the gate insulating film 9. The Schottky electrode 17 is in Schottky contact with the n ⁻ -type GaN layer 2 and is the same type of metal as the contact electrode 13, that is, Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au alloy, Pd / Pt / Au alloy and metal such as Pt can be used. In addition, the Schottky electrode 17 is electrically connected to the source electrode 15 through the wiring 21. Since the Schottky electrode 17 is in Schottky contact with the n ⁻ -type GaN layer 2, the nitride semiconductor element includes an SBD 19 (Schottky comprising the Schottky electrode 17 and the n ⁻ -type GaN layer 2. Barrier Diode: Schottky barrier diode) is provided.

Next, the operation of the nitride semiconductor device will be described.
A bias is applied between the source electrode 15 and the drain electrode 18 so that the drain electrode 18 side becomes positive. Thus, a reverse voltage is applied to the pn junction at the interface between the n ⁻ -type GaN layer 2 and the p-type GaN layer 3, and as a result, between the n ⁺ -type GaN layer 4 and the n ⁻ -type GaN layer 2, That is, the source electrode 15 and the drain electrode 18 (between the source and the drain) are cut off (reverse bias state). In this state, when a bias equal to or higher than a gate threshold voltage that is positive with the source electrode 15 as a reference potential is applied to the gate electrode 10, electrons are induced in the vicinity of the interface with the gate insulating film 9 in the channel region 11. Thus, an inversion layer (channel) is formed.

The n ⁻ -type GaN layer 2 and the n ⁺ -type GaN layer 4 are electrically connected via the inversion layer. Thus, conduction between the source and the drain is established. That is, when a predetermined bias is applied to the gate electrode 10, the source and the drain are conducted, and when no bias is applied to the gate electrode 10, the source and the drain are cut off. In this way, a normally-off operation is realized.

3A to 3H are schematic cross-sectional views showing a first manufacturing method of the nitride semiconductor device of FIG. 1 in the order of steps.
When manufacturing this nitride semiconductor device, first, as shown in FIG. 3A, an n ⁺ -type GaN substrate 1 is prepared (lower layer forming step), and on this n ⁺ -type GaN substrate 1, for example, MOCVD ( The n ⁻ -type GaN layer 2 is formed by Metal Organic Chemical Vapor Deposition (metal organic vapor phase epitaxy) (upper layer forming step). Thus, the n ⁻ type GaN layer 2 is formed on the n ⁺ type GaN substrate 1. For example, Si may be used as an n-type impurity when the n ⁻ -type GaN layer 2 is grown.

Subsequent to the formation of the n ⁻ -type GaN layer 2, as shown in FIG. 3B, the p-type GaN layer 3 is formed on the n ⁻ -type GaN layer 2 by, for example, MOCVD (second layer formation step), Further, the n ⁺ -type GaN layer 4 is formed (third layer forming step). For example, Mg or C may be used as a p-type impurity when the p-type GaN layer 3 is grown. Further, for example, Si may be used as an n-type impurity when the n ⁺ -type GaN layer 4 is grown. Thus, a nitride semiconductor multilayer structure portion 5 including the n ⁻ type GaN layer 2, the p type GaN layer 3 and the n ⁺ type GaN layer 4 is formed on one surface of the n ⁺ type GaN substrate 1.

After the nitride semiconductor multilayer structure portion 5 is formed, the nitride semiconductor multilayer structure portion 5 is etched in a stripe shape as shown in FIG. 3C. That is, a trench 22 having a substantially inverted trapezoidal cross section is formed by etching from the n ⁺ -type GaN layer 4 through the p-type GaN layer 3 and reaching the middle layer thickness of the n ⁻ -type GaN layer 2. As a result, a plurality of nitride semiconductor multilayer structures 5 are shaped into stripes (not shown), and lead-out portions 6 made of extensions of the n ⁻ -type GaN layer 2 are simultaneously formed (exposure process). . The trench 22 can be formed, for example, by dry etching (anisotropic etching) using a chlorine-based gas.

Then, a trench 7 having a substantially V-shaped cross section is formed in the vicinity of the intermediate portion in the width direction of each nitride semiconductor multilayer structure portion 5 along the longitudinal direction of the nitride semiconductor multilayer structure portion 5 (wall surface forming step). The trench 7 can be formed by dry etching (anisotropic etching) using a chlorine-based gas, similarly to the trench 22.
In addition, after the dry etching, a wet etching process for improving the wall surface 8 of the trench 7 damaged by the dry etching may be performed as necessary. For wet etching, HF (hydrofluoric acid), HCl (hydrochloric acid), or the like is preferably used. As a result, Si-based oxide, Ga oxide, and the like are removed, and the wall surface 8 can be leveled. Also, the damaged wall surface 8 can be improved by wet etching with KOH (potassium hydroxide), NaOH (sodium hydroxide), or the like, and the wall surface 8 with less damage can be obtained. By reducing the damage to the wall surface 8, the crystal state of the channel region 11 (see FIG. 1) can be kept good, and the interface between the wall surface 8 and the gate insulating film 9 should be a good interface. Therefore, the interface state can be reduced. Thereby, the channel resistance can be reduced and the leakage current can be suppressed. Note that a low-damage dry etching process can be applied instead of the wet etching process.

Next, as shown in FIG. 3D, the gate insulating film 9 covers the wall surface 8 of the substantially V-shaped trench 7 and covers the surfaces of the n ⁻ -type GaN layer 2, the p-type GaN layer 3, and the n ⁺ -type GaN layer 4. Is formed (step of forming a gate insulating film). For the formation of the gate insulating film 9, it is preferable to apply an ECR (Electron Cyclotron Resonance) sputtering method.
Thereafter, the gate insulating film 9 is dry-etched in stripes by a known photolithography technique through a photoresist (not shown) having openings in regions where the contact openings 14 and 16 are to be formed. Thereby, as shown in FIG. 3E, the contact opening 14 and the contact opening 16 are formed, and the n ⁺ -type GaN layer 4 and the n ⁻ -type GaN layer 2 are partially exposed. Subsequently, the n ⁺ -type GaN layer 4 and the p-type GaN layer 3 are dried by a known photolithography technique through a photoresist (not shown) having an opening in a region where the contact electrode trench 12 is to be formed. Etched. Thus, as shown in FIG. 3E, a contact electrode trench 12 having a depth from the n ⁺ -type GaN layer 4 to the p-type GaN layer 3 is formed.

Subsequently, as a material of the contact electrode 13 and the Schottky electrode 17 through a photoresist (not shown) having an opening in a region where the contact electrode 13 and the Schottky electrode 17 are to be formed by a known photolithography technique. The metals used (for example, Ni and Au) are sputtered in the order of Ni / Au by sputtering. Thereafter, by removing the photoresist, unnecessary portions of metal (portions other than the contact electrode 13 and the Schottky electrode 17) are lifted off together with the photoresist. By these steps, as shown in FIG. 3F, the contact electrode 13 is formed (contact electrode forming step), and at the same time, the Schottky electrode 17 is formed (Schottky electrode forming step). After the contact electrode 13 and the Schottky electrode 17 are formed, a thermal alloy (annealing process) is performed, so that the contact between the contact electrode 13 and the p-type GaN layer 3 becomes an ohmic contact. ^- contact type GaN layer 2 is a Schottky contact. The SBD 19 is formed by Schottky contact between the Schottky electrode 17 and the n ⁻ -type GaN layer 2.

Next, a metal (for example, Ti and Al) used as a material for the source electrode 15 is formed by a known photolithography technique through a photoresist (not shown) having an opening in a region where the source electrode 15 is to be formed. Then, sputtering is performed in the order of Ti / Al by sputtering. Thereafter, the photoresist is removed, so that unnecessary portions of metal (portions other than the source electrode 15) are lifted off together with the photoresist. By these operations, as shown in FIG. 3G, the source electrode 15 is formed (source electrode formation step). After the source electrode 15 is formed, a thermal alloy (annealing process) is performed, so that the contact between the source electrode 15 and the n ⁺ -type GaN layer 4 becomes an ohmic contact.

Thereafter, in the same manner as in the case of the source electrode 15, as shown in FIG. 3G, the gate facing the edge of the trench 7 on the wall surface 8 and the upper surface of the n ⁺ -type GaN layer 4 with the gate insulating film 9 interposed therebetween. The electrode 10 is formed (gate electrode forming step).
Then, as shown in FIG. 3H, the drain electrode 18 is formed on the other surface of the n ⁺ -type GaN substrate 1 by the same method as that for the source electrode 15 (drain electrode forming step). In this way, the MOSFET 20 in which the gate electrode 10, the gate insulating film 9, the source electrode 15 and the drain electrode 18 are formed in the nitride semiconductor multilayer structure portion 5 is formed. Thereafter, the source electrode 15 and the Schottky electrode 17 are connected by the wiring 21, whereby the nitride semiconductor device shown in FIG. 1 can be obtained.

Each of the plurality of nitride semiconductor multilayer structures 5 forms a unit cell. The gate electrode 10 and the source electrode 15 of the nitride semiconductor multilayer structure portion 5 are commonly connected at positions not shown. The drain electrode 18 is formed in contact with the n ⁺ -type GaN substrate 1 and is a common electrode for all cells.
4A to 4K are schematic cross-sectional views showing a second manufacturing method of the nitride semiconductor device of FIG. 1 in the order of steps.

In this second manufacturing method, first, as shown in FIG. 4A, an n ⁺ -type GaN substrate 1 is prepared, and an n ⁻ -type GaN layer 23 is formed on the n ⁺ -type GaN substrate 1 by, for example, MOCVD. Is formed. This n ⁻ -type GaN layer 23 has the same n-type impurity concentration as that of the n ⁻ -type GaN layer 2, for example, 1 × 10 ¹⁷ cm ⁻³ . For example, Si may be used as an n-type impurity when the n ⁻ -type GaN layer 23 is grown. In addition, the n ⁺ -type GaN substrate 1 and the n ⁻ -type GaN layer 23 formed on the n ⁺ -type GaN substrate 1 are regarded as a “conductive substrate”, and this conductive substrate (n ⁻ -type GaN layer 23 is ) And a group III nitride semiconductor layer stacked thereon may be considered to constitute a “nitride semiconductor multilayer structure”.

Next, an insulating material (for example, SiO ₂ ) is formed by, for example, an ECR sputtering method through a photoresist (not shown) having an opening in a region where the lead portion 6 is to be formed by a known photolithography technique. Is sputtered. Thus, as shown in FIG. 4B, n ^- on the -type GaN layer 23, n ^- -type insulating film 24 to the surface partially exposed in the GaN layer 23 is formed.

Subsequently, n ⁻ -type GaN is grown from the surface of the n ⁻ -type GaN layer 23 exposed from the insulating film 24 by, for example, MOCVD. on the n ^- -type GaN layer 23 for insulating film 24 is formed, n ^- -type GaN layer 23, the growth is stopped (the portion covered with the insulating film 24) partially. Therefore, as shown in FIG. 4C, the n ^- type from the surface of the GaN layer 23 of substantially trapezoidal cross section n ^- -type GaN-grow, the n ^- -type GaN and the n ^- -type GaN layer 23 n ^- A type GaN layer 2 is formed. In the n ⁻ -type GaN layer 2, a portion covered with the insulating film 24 becomes a lead portion 6 drawn in the width direction.

After the n ⁻ -type GaN layer 2 is formed, as shown in FIG. 4D, the p-type GaN layer 3 is formed on the n ⁻ -type GaN layer 2 by, for example, MOCVD (second layer forming step). Further, the n ⁺ -type GaN layer 4 is formed (third layer forming step). Thus, the nitride semiconductor multilayer structure portion 5 formed of the n ⁻ -type GaN layer 2, the p-type GaN layer 3, and the n ⁺ -type GaN layer 4 formed in a stripe shape is formed on the n ⁺ -type GaN substrate 1. . In the nitride semiconductor multilayer structure portion 5, the portion covered with the insulating film 24 extends from the n ⁺ -type GaN layer 4 through the p-type GaN layer 3 to the middle portion of the n ⁻ -type GaN layer 2. The resulting trench 25 has a substantially inverted trapezoidal cross section.

Then, a trench 7 having a substantially V-shaped cross section is formed in the vicinity of the intermediate portion in the width direction of each nitride semiconductor multilayer structure portion 5 along the longitudinal direction of the nitride semiconductor multilayer structure portion 5 (wall surface forming step).
Next, as shown in FIG. 4F, the insulating film 24 is dry-etched by a known photolithography technique through a photoresist (not shown) having an opening in a region corresponding to the shape of the insulating film 24. . Thereby, the insulating film 24 on the n ⁻ -type GaN layer 2 is removed, and the upper surface of the lead portion 6 is exposed (exposure process).

Next, as shown in FIG. 4G, the gate insulating film 9 covers the wall surface 8 of the substantially V-shaped trench 7 and covers the surfaces of the n ⁻ -type GaN layer 2, the p-type GaN layer 3 and the n ⁺ -type GaN layer 4. Is formed (step of forming a gate insulating film). For the formation of the gate insulating film 9, it is preferable to apply an ECR (Electron Cyclotron Resonance) sputtering method.
Thereafter, the gate insulating film 9 is dry-etched in stripes by a known photolithography technique through a photoresist (not shown) having openings in regions where the contact openings 14 and 16 are to be formed. Thereby, as shown in FIG. 4H, contact opening 14 and contact opening 16 are formed, and n ⁺ -type GaN layer 4 and n ⁻ -type GaN layer 2 are partially exposed. Subsequently, the n ⁺ -type GaN layer 4 and the p-type GaN layer 3 are dried by a known photolithography technique through a photoresist (not shown) having an opening in a region where the contact electrode trench 12 is to be formed. Etched. Thus, as shown in FIG. 4H, a contact electrode trench 12 having a depth from the n ⁺ -type GaN layer 4 to the p-type GaN layer 3 is formed.

Subsequently, as a material of the contact electrode 13 and the Schottky electrode 17 through a photoresist (not shown) having an opening in a region where the contact electrode 13 and the Schottky electrode 17 are to be formed by a known photolithography technique. The metals used (for example, Ni and Au) are sputtered in the order of Ni / Au by sputtering. Thereafter, by removing the photoresist, unnecessary portions of metal (portions other than the contact electrode 13 and the Schottky electrode 17) are lifted off together with the photoresist. Through these steps, as shown in FIG. 4I, the contact electrode 13 is formed (contact electrode forming step), and at the same time, the Schottky electrode 17 is formed (Schottky electrode forming step). After the contact electrode 13 and the Schottky electrode 17 are formed, a thermal alloy (annealing process) is performed, so that the contact between the contact electrode 13 and the p-type GaN layer 3 becomes an ohmic contact. ^- contact type GaN layer 2 is a Schottky contact. The SBD 19 is formed by Schottky contact between the Schottky electrode 17 and the n ⁻ -type GaN layer 2. The n ⁺ -type GaN substrate 1 and the n ⁻ -type GaN layer 23 formed on the n ⁺ -type GaN substrate 1 are regarded as a “conductive substrate”, and this conductive substrate (n ⁻ -type GaN layer 23 is ) And the group III nitride semiconductor layer laminated thereon, the Schottky electrode 17 is a “conductive substrate that also serves as a“ first layer ”. Will be in Schottky contact.

Next, a metal (for example, Ti and Al) used as a material for the source electrode 15 is formed by a known photolithography technique through a photoresist (not shown) having an opening in a region where the source electrode 15 is to be formed. Then, sputtering is performed in the order of Ti / Al by sputtering. Thereafter, the photoresist is removed, so that unnecessary portions of metal (portions other than the source electrode 15) are lifted off together with the photoresist. By these operations, as shown in FIG. 4J, the source electrode 15 is formed (source electrode formation step). After the source electrode 15 is formed, a thermal alloy (annealing process) is performed, so that the contact between the source electrode 15 and the n ⁺ -type GaN layer 4 becomes an ohmic contact.

Thereafter, in the same manner as in the case of the source electrode 15, as shown in FIG. 4J, the gate facing the edge of the trench 7 on the wall surface 8 and the upper surface of the n ⁺ -type GaN layer 4 with the gate insulating film 9 interposed therebetween. The electrode 10 is formed (gate electrode forming step).
Then, as shown in FIG. 4K, the drain electrode 18 is formed on the other surface of the n ⁺ -type GaN substrate 1 by the same method as that for the source electrode 15 (drain electrode forming step). In this way, the MOSFET 20 in which the gate electrode 10, the gate insulating film 9, the source electrode 15 and the drain electrode 18 are formed in the nitride semiconductor multilayer structure portion 5 is formed. Thereafter, the source electrode 15 and the Schottky electrode 17 are connected by the wiring 21, whereby the nitride semiconductor device shown in FIG. 1 can be obtained.

Each of the plurality of nitride semiconductor multilayer structures 5 forms a unit cell. The gate electrode 10 and the source electrode 15 of the nitride semiconductor multilayer structure portion 5 are commonly connected at positions not shown. The drain electrode 18 is formed in contact with the n ⁺ -type GaN substrate 1 and is a common electrode for all cells.
As described above, in this nitride semiconductor element, the MOSFET 20 is formed in which the gate electrode 10, the gate insulating film 9, the source electrode 15, and the drain electrode 18 are formed in the nitride semiconductor multilayer structure portion 5.

Further, in this nitride semiconductor element, a contact opening 16 is formed in the gate insulating film 9 of the MOSFET 20 to expose the upper surface of the lead portion 6 of the n ⁻ -type GaN layer 2, and the n exposed through the contact opening 16. ^- on -type GaN layer 2, the Schottky electrode 17 is formed. The Schottky electrode 17 is in Schottky contact with the n ⁻ -type GaN layer 2. Since the Schottky electrode 17 is in Schottky contact with the n ⁻ -type GaN layer 2, the nitride semiconductor element includes the SBD 19 including the Schottky electrode 17 and the n ⁻ -type GaN layer 2. It has been. The SBD 19 is connected to the source electrode 15 through the wiring 21.

Therefore, when a bias that is positive on the source electrode 15 side is applied to the drain electrode 18 (when the potential of the source electrode 15 is higher than the potential of the drain electrode 18), the SBD 19 is preferentially supplied with current. Can flow. As a result, for example, when a nitride semiconductor element is operated, a high current generated by the bias is applied from the drain electrode 18 to the Schottky electrode 17 even when a bias that is positive on the source electrode 15 side is applied. Can be flowed through. Therefore, electric field concentration at the junction between the n ⁺ -type GaN layer 4 and the p-type GaN layer 3 can be suppressed, and the occurrence of dielectric breakdown can be suppressed.

In addition, a diode for suppressing the occurrence of dielectric breakdown in this manner is an SBD 19 including the lead portion 6 of the n ⁻ -type GaN layer 2 in the MOSFET 20 and the Schottky electrode 17 formed on the upper surface of the lead portion 6. It is formed as. Therefore, as shown in FIG. 2, the MOSFET 20 and the diode for countermeasures against dielectric breakdown can be integrated. As a result, it is possible to reduce the chip area of the nitride semiconductor device.

Further, when the n ⁺ -type GaN substrate 1 and the n ⁻ -type GaN layer 2 are compared, the n ⁻ -type GaN layer 2 has a lower n-type impurity concentration, so that it expands when the Schottky barrier is in a reverse bias state. It has a so-called high breakdown voltage structure that has a large depletion layer width and can withstand higher voltages. In this nitride semiconductor device, since the Schottky electrode 17 is in Schottky contact with the n ⁻ -type GaN layer 2 having a high breakdown voltage structure, the n ^- type GaN layer 2 and the Schottky electrode 17 are configured. Thus, the SBD 19 having excellent pressure resistance performance can be formed.

In this embodiment, since the substrate supporting the nitride semiconductor multilayer structure 5 is the conductive n ⁺ -type GaN substrate 1, the drain electrode 18 is formed in contact with the other surface of the n ⁺ -type GaN substrate 1. Thus, the drain electrode 18 and the n ⁻ -type GaN layer 2 can be brought into ohmic contact via the n ⁺ -type GaN substrate 1. Since the drain electrode 18 can be formed in contact with the other surface of the n ⁺ -type GaN substrate 1, a space for contacting the drain electrode 18 in the nitride semiconductor multilayer structure 5 can be omitted. That is, since the area of the nitride semiconductor multilayer structure portion 5 can be reduced, the chip area of the nitride semiconductor element can be further reduced.

In this embodiment, the contact electrode 13 is in ohmic contact with the p-type GaN layer 3 and is in contact (short circuit) with the source electrode 15 on the upper surface thereof. Therefore, the potential of the p-type GaN layer 3 can be stabilized at the reference potential via the contact electrode 13 by connecting the source electrode 15 to the reference potential (for example, the ground potential).
Further, in the manufacturing process of the nitride semiconductor device, since the contact electrode 13 and the Schottky electrode 17 are made of the same kind of metal (for example, Ni / Au alloy), the step of forming the Schottky electrode 17 and the contact electrode 13 are formed. The process of forming can be performed in parallel. Therefore, the process time of the nitride semiconductor element manufacturing process can be shortened, and the manufacturing cost can be reduced.

FIG. 5 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device according to the second embodiment of the present invention. In FIG. 5, parts corresponding to the parts shown in FIG. 1 are denoted by the same reference numerals as those parts. Further, in the following, detailed description of the parts denoted by the same reference numerals is omitted.
In this embodiment, a sapphire substrate 26 is used. A nitride semiconductor multilayer structure 5 is formed on one surface of the sapphire substrate 26. In this embodiment, the nitride semiconductor multilayer structure 5 is laminated on the n ⁻ -type GaN layer 2 formed on one surface of the sapphire substrate 26, the p-type GaN layer 3 laminated thereon. And an n ⁺ -type GaN layer 4.

In this embodiment, the wall surface 8 includes the n-type GaN layer 2, the p-type GaN layer 3, and the n-type GaN layer 3 formed in the nitride semiconductor multilayer structure portion 5 as the lead portion 6 is formed in the nitride semiconductor multilayer structure portion 5. The side surface straddling the n-type GaN layer 4 is configured.
Gate electrode 10 faces wall 8, the edge of wall 8 on the upper surface of n ⁻ -type GaN layer 2, and the edge of wall 8 on the upper surface of n ⁺ -type GaN layer 2 with gate insulating film 9 interposed therebetween. Is formed.

The drain electrode 18 penetrates the gate insulating film 9 and is formed on the upper surface of the lead portion 6 of the n ⁻ -type GaN layer 2. The drain electrode 18 is in ohmic contact with the n ⁻ -type GaN layer 2. Other configurations are the same as those in the first embodiment described above, and the operations are also the same.
FIG. 6 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device according to the third embodiment of the present invention. In FIG. 6, portions corresponding to the respective portions shown in FIG. 1 are denoted by the same reference numerals as those respective portions. Further, in the following, detailed description of the parts denoted by the same reference numerals is omitted.

Also in this embodiment, the sapphire substrate 26 is used as in the second embodiment. A nitride semiconductor multilayer structure 5 is formed on one surface of the sapphire substrate 26. In this embodiment, the nitride semiconductor multilayer structure 5 is laminated on the n ⁻ -type GaN layer 2 formed on one surface of the sapphire substrate 26, the p-type GaN layer 3 laminated thereon. And an n ⁺ -type GaN layer 4.

In this embodiment, the Schottky electrode 17 is formed on the upper surface of one lead portion 6 of the n ⁻ -type GaN layer 2 drawn in the width direction along the surface of the sapphire substrate 26 from both sides of the nitride semiconductor multilayer structure portion 5. Is formed. The drain electrode 18 is formed on the upper surface of the other lead portion 6. That is, the Schottky electrode 17 and the drain electrode 18 are distributed on the upper surface of the n ⁻ -type GaN layer 2 to one side and the other side of the nitride semiconductor multilayer structure portion 5 having a substantially trapezoidal cross section. Other configurations are the same as those in the first embodiment described above, and the operations are also the same.

FIG. 7 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device according to the fourth embodiment of the present invention. In FIG. 7, parts corresponding to the parts shown in FIG. 1 are denoted by the same reference numerals as those parts. Further, in the following, detailed description of the parts denoted by the same reference numerals is omitted.
Also in this embodiment, the sapphire substrate 26 is used as in the second embodiment. A nitride semiconductor multilayer structure 5 is formed on one surface of the sapphire substrate 26. In this embodiment, the nitride semiconductor multilayer structure 5 is laminated on the n ⁻ -type GaN layer 2 formed on one surface of the sapphire substrate 26, the p-type GaN layer 3 laminated thereon. And an n ⁺ -type GaN layer 4.

In this embodiment, the Schottky electrode 17 and the drain electrode 18 are one lead-out portion of the n ⁻ -type GaN layer 2 drawn from both sides of the nitride semiconductor multilayer structure portion 5 in the width direction along the surface of the sapphire substrate 26. 6 are formed adjacent to each other. Other configurations are the same as those in the first embodiment described above, and the operations are also the same.
FIG. 8 is a schematic plan view for explaining the structure of the nitride semiconductor device according to the fifth embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of the nitride semiconductor device of FIG. 8 taken along the cutting line indicated by IX-IX.

This nitride semiconductor device includes a conductive n ⁺ -type GaN substrate 31 (lower layer) and a nitride semiconductor multilayer structure portion 35 formed on one surface of the n ⁺ -type GaN substrate 31.
The nitride semiconductor multilayer structure 35 includes an n ⁻ type GaN layer 32 (upper layer), a p type GaN layer 33 (second layer) stacked on the n ⁻ type GaN layer 32, and the p type GaN layer 33. And a stacked n ⁺ -type GaN layer 34 (third layer).

The n ⁺ -type GaN substrate 31 and the n ⁺ -type GaN layer 34 have an n-type impurity concentration higher than that of the n ⁻ -type GaN layer 32, and the concentration is, for example, 3 × 10 ¹⁸ cm ⁻³ . On the other hand, the n-type impurity concentration of the n ⁻ -type GaN layer 32 is, for example, 1 × 10 ¹⁷ cm ⁻³ .
The nitride semiconductor multilayer structure portion 35 is etched in a direction crossing the multilayer interface from the n ⁺ -type GaN layer 34 to a depth at which the n ⁻ -type GaN layer 32 is exposed, in an annular pattern in plan view. As a result, a first trench 53 having a ring shape in plan view is formed in the nitride semiconductor multilayer structure portion 35.

The nitride semiconductor multilayer structure portion 35 includes a mesa multilayer portion 98 surrounded by the first trench 53 and a lateral direction extending from the mesa multilayer portion 98 to the surface of the n ⁺ -type GaN substrate 31 (hereinafter, this direction is referred to as a “width direction”). And a lead portion 36 made of the n ⁻ -type GaN layer 32. That is, the annular drawing portion 36 in plan view is formed by an extension of the n ⁻ -type GaN layer 32 in this embodiment.

The mesa stacked portion 98 is etched in a direction crossing the stacked interface from the n ⁺ -type GaN layer 34 to a depth at which the n ⁻ -type GaN layer 32 is exposed in a plan view lattice pattern. As a result, the second trench 37 having a lattice shape in a plan view and a U shape in a cross section is formed in the mesa laminated portion 98.
The depth of the second trench 37 is deeper than the depth of the first trench 53. The maximum width of the second trench 37 is preferably 0.5 to 2 μm.

Due to the second trench 37 having such a shape, the n ⁻ -type GaN layer 32, the p-type GaN layer 33, and the n ⁺ -type are formed in the mesa stacked portion 98 in the window portion surrounded by the lattice-shaped second trench 37. A quadrangular columnar (cuboid) columnar portion 54 having four wall surfaces 38 that are inclined with respect to the lamination interface of the mesa laminated portion 98 (nitride semiconductor laminated structure portion 35) is formed across the GaN layer 34.
The columnar portions 54 are arranged in a matrix as a whole so that each columnar portion 54 is spaced from the adjacent columnar portion 54 by a predetermined width (the width of the second trench 37).

One side in the plan view of each columnar part 54 is preferably 2 to 10 μm, that is, each columnar part 54 is preferably 2 μm square to 10 μm square in plan view. Each columnar portion 54 has an npn stacked structure including an n ⁻ -type GaN layer 32, a p-type GaN layer 33, and an n ⁺ -type GaN layer 34, and is a minimum unit having a transistor function in the nitride semiconductor element. (Unit cell). The n ⁻ -type GaN layer 32 exposed in the second trench 37 is shared by each unit cell.

The nitride semiconductor multilayer structure portion 35 is formed on the n ⁺ -type GaN substrate 31 by, for example, the MOCVD method.
For example, when an n ⁺ -type GaN substrate 31 having a c-plane (0001) as the main surface is used, an n ⁻ -type GaN layer 32, a p-type GaN layer 33, and an n ⁻ -type GaN layer that are grown on the n ⁺ -type GaN substrate 31 by epitaxial growth. ^{The +} -type GaN layer 34 is also laminated with the c-plane (0001) as the main surface. Therefore, the plane orientation of the wall surface 38 inclined with respect to the lamination interface of the nitride semiconductor multilayer structure portion 35 is, for example, a plane inclined in a range of 15 ° to 90 ° with respect to the c plane (0001) (other than the c plane). Surface). More specifically, for example, non-polar surfaces such as m-plane (10-10) or a-plane (11-20), and semipolar surfaces such as (10-13), (10-11), and (11-22) It becomes a surface.

A gate insulating film 39 is formed on the entire surface of the columnar portion 54 and the lead portion 36 except for a part thereof. The gate insulating film 39 can be made of, for example, nitride or oxide. More specifically, the gate insulating film 39 can be composed of SiN (silicon nitride), SiO ₂ (silicon oxide), or a combination thereof.
On the gate insulating film 39, the gate electrode 40 is formed so as to face the wall surface 38 in each columnar portion 54. The gate electrode 40 covers the entire area of the four wall surfaces 38 from the peripheral edge of the square n ⁺ -type GaN layer 34 in the columnar portion 54 and reaches the n ⁻ -type GaN layer 32 exposed in the second trench 37. Is formed. Thereby, the gate width in each unit cell (each columnar part 54) is substantially the same as the outer periphery (total length of square sides) of the columnar part 54 in plan view.

Further, the gate electrode 40 formed in one columnar portion 54 and the gate electrode 40 formed in another adjacent columnar portion 54 are integrally connected on the n ⁻ -type GaN layer 32. That is, the gate electrode 40 is shared by all the columnar portions 54 by connecting the portions formed in the columnar portions 54 integrally on the n ⁻ -type GaN layer 32.
Further, the gate electrode 40 is made of, for example, Ni and Au laminated on the Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au alloy, Pd / Pt / Au alloy, Pt, Al. It can be made of a conductive material such as polysilicon.

A region near the wall surface 38 in the p-type GaN layer 33 is a channel region 41 facing the gate electrode 40. In this channel region 41, an inversion channel is formed to electrically connect the n ⁻ -type GaN layer 32 and the n ⁺ -type GaN layer 34 by applying an appropriate bias to the gate electrode 40.
In each columnar portion 54, a contact electrode trench 42 is formed. The contact electrode trench 42 is formed at a depth from the upper surface of the n ⁺ -type GaN layer 34 to the p-type GaN layer 33. A contact electrode 43 is embedded in the contact electrode trench 42.

  The contact electrode 43 is in ohmic contact with the p-type GaN layer 33. For example, a Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au made of Ni and Au laminated on the Ni is used. An alloy, a Pd / Pt / Au alloy, and a metal such as Pt can be used. Since these metals have a low contact resistance with respect to the p-type GaN layer 33, the contact electrode 43 can be satisfactorily brought into ohmic contact with the p-type GaN layer 33.

In the gate insulating film 39, a contact opening 44 that exposes the upper surface of the n ⁺ -type GaN layer 34 is formed in each columnar portion 54. The contact opening 44 is formed in a square shape in plan view in a portion surrounded by the gate electrode 40 on the n ⁺ -type GaN layer 34. A source electrode 45 is formed on the contact electrode 43 and the n ⁺ -type GaN layer 34 exposed in the contact opening 44.

The source electrode 45 is in ohmic contact with the n ⁺ -type GaN layer 34 and the contact electrode 43, and is composed of, for example, a metal such as Ti and a Ti / Al alloy made of Al laminated on the Ti. can do. By configuring the source electrode 45 with a metal containing Al, the source electrode 45 can be in good ohmic contact with the n ⁺ -type GaN layer 34 and the contact electrode 43. In addition, the source electrode 45 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

A drain electrode 48 is formed in contact with the other surface of the n ⁺ -type GaN substrate 31. The drain electrode 48 is in ohmic contact with the n ⁺ -type GaN substrate 31 and can be configured using, for example, the same type of metal as the source electrode 45, that is, a metal such as a Ti / Al alloy. In addition, the drain electrode 48 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

Thus, in this nitride semiconductor element, a MOSFET 96 (Metal Oxide Semiconductor Field Effect Transistor: MOS) in which the gate electrode 40, the gate insulating film 39, the source electrode 45, and the drain electrode 48 are formed in the nitride semiconductor multilayer structure portion 35 is formed. Field effect transistor).
In the gate insulating film 39, a contact opening 46 that exposes the upper surface of the n ⁻ -type GaN layer 32 is formed on the lead portion 36. The contact openings 46 are formed in a U shape in plan view so as to surround the columnar portions 54 arranged in a matrix. A Schottky electrode 47 is formed on the n ⁻ -type GaN layer 32 exposed in the contact opening 46. The Schottky electrode 47 is in Schottky contact with the n ⁻ -type GaN layer 32, and is the same kind of metal as the contact electrode 43, that is, Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au alloy, Pd / Pt / Au alloy and metal such as Pt can be used.

On the gate insulating film 39, an interlayer insulating film 55 covering the source electrode 45, the gate electrode 40, and the Schottky electrode 47 is laminated. The interlayer insulating film 55 can be configured using, for example, silicon nitride (SiN) or silicon oxide (SiO ₂ ).
In the interlayer insulating film 55, a source contact hole 56 having a rectangular shape in plan view is formed in a portion facing the source electrode 45. A source contact electrode 57 for contact with the source electrode 45 is embedded in the source contact hole 56. The source contact electrode 57 can be configured using, for example, aluminum (Al).

  In the interlayer insulating film 55, a Schottky contact hole 101 is formed at a portion facing the Schottky electrode 47. A Schottky contact electrode 51 for contact with the Schottky electrode 47 is embedded in the Schottky contact hole 101. Schottky contact electrode 51 can be formed using, for example, aluminum (Al).

  A source pad 58 is formed on the surface of the interlayer insulating film 55. The source pad 58 can be configured using, for example, aluminum (Al). The source pad 58 is arranged over the entire region on the columnar portions 54 and the Schottky electrodes 47 arranged in a matrix, and on the source contact electrodes 57 and the Schottky electrodes 47 formed on the columnar portions 54. In contact with the Schottky contact electrode 51 formed on the substrate. As a result, the source electrode 45 formed on the columnar portion 54 is collectively electrically connected (ohmic connection) to the source pad 58 via the source contact electrode 57.

Further, the Schottky electrode 47 is connected to the source pad 58 through the Schottky contact electrode 51. Thus, the Schottky electrode 47 is collectively electrically connected to the source electrode 45 formed in each columnar portion 54 via the source pad 58. Since the Schottky electrode 47 is in Schottky contact with the n ⁻ -type GaN layer 32, the nitride semiconductor element includes an SBD 49 (Schottky comprising the Schottky electrode 47 and the n ⁻ -type GaN layer 32. Barrier Diode: Schottky barrier diode) is provided.

  A gate pad 59 that is electrically connected to the gate electrode 40 is formed on the surface of the interlayer insulating film 55 in a portion adjacent to the source pad 58. The gate pad 59 is disposed opposite to a portion of the mesa laminated portion 98 where the columnar portion 54 is not formed in plan view. The gate pad 59 penetrates the interlayer insulating film 55 and is in contact with the gate wiring routed at a position not shown. Thereby, the gate pad 59 is electrically connected (ohmic connection) to the gate electrode 40 via the gate wiring.

In FIG. 8, the interlayer insulating film 55 is omitted for easy understanding of the structure of the nitride semiconductor device.
The operation of the nitride semiconductor device according to this embodiment is the same as the operation of the nitride semiconductor device according to the first embodiment described above.
As described above, according to this nitride semiconductor device, the SBD 49 including the n ⁻ -type GaN layer 32 of the MOSFET 96 and the Schottky electrode 47 is provided, as in the above-described embodiment. The SBD 49 is collectively electrically connected to the source electrode 45 of each columnar portion 54 via the Schottky contact electrode 51 and the source pad 58.

Therefore, when a bias that is positive on the source electrode 45 side is applied to the drain electrode 48 (when the potential of the source electrode 45 becomes higher than the potential of the drain electrode 48), the SBD 49 is preferentially supplied with current. Can flow.
As a result, for example, when a nitride semiconductor element is operated, a high current generated by the bias is allowed to flow from the drain electrode 48 to the Schottky electrode 47 even when a bias that is positive on the source electrode 45 side is applied. it can. Therefore, electric field concentration at the junction between the n ⁺ -type GaN layer 34 and the p-type GaN layer 33 can be suppressed, and the occurrence of dielectric breakdown can be suppressed.

In addition, a diode for suppressing the occurrence of dielectric breakdown in this way is an SBD 49 configured by the n ⁻ -type GaN layer 32 of the MOSFET 96 and the Schottky electrode 47 formed on the upper surface of the n ⁻ -type GaN layer 32. It is formed as.
Therefore, the MOSFET 96 and the diode (SBD 49) for measures against dielectric breakdown can be integrated.

As a result, it is possible to reduce the chip area of the nitride semiconductor device.
Further, a Schottky electrode 47 connected to the plurality of source electrodes 45 at once is formed in a U shape in plan view so as to surround the columnar portions 54 arranged in a matrix.
Therefore, compared with the case where one Schottky electrode is provided for each source electrode 45, the space required for installation of the Schottky electrode in the entire chip can be reduced.

As a result, the chip area of the nitride semiconductor device can be further reduced.
Further, the gate electrode 40 is opposed to the entire area of the four wall surfaces 38, and the gate width in each unit cell (each columnar portion 54) is substantially equal to the outer periphery (total length of the square side) of the columnar portion 54 in plan view. Since they are the same, a long gate width can be secured in each unit cell.
Therefore, since the current density can be increased, a higher output power device can be realized.

FIG. 10 is a schematic plan view for explaining the structure of the nitride semiconductor device according to the sixth embodiment of the present invention. FIG. 11 is a schematic cross-sectional view of the nitride semiconductor device of FIG. 10 taken along the cutting line indicated by XI-XI.
This nitride semiconductor element includes a conductive n ⁺ -type GaN substrate 61 (lower layer) and a nitride semiconductor multilayer structure portion 65 formed on one surface of the n ⁺ -type GaN substrate 61.

The nitride semiconductor multilayer structure 65 includes an n ⁻ type GaN layer 62 (upper layer), a p type GaN layer 63 (second layer) stacked on the n ⁻ type GaN layer 62, and the p type GaN layer 63. And a laminated n ⁺ -type GaN layer 64 (third layer).
The n ⁺ -type GaN substrate 61 and the n ⁺ -type GaN layer 64 have an n-type impurity concentration higher than that of the n ⁻ -type GaN layer 62, and the concentration is, for example, 3 × 10 ¹⁸ cm ⁻³ . On the other hand, the n-type impurity concentration of the n ⁻ -type GaN layer 62 is, for example, 1 × 10 ¹⁷ cm ⁻³ .

The nitride semiconductor multilayer structure portion 65 is etched in a direction crossing the multilayer interface in a circular pattern in plan view from the n ⁺ -type GaN layer 64 to a depth at which the n ⁻ -type GaN layer 62 is exposed. As a result, the first trench 28 having a ring shape in plan view is formed in the nitride semiconductor multilayer structure portion 65.
The nitride semiconductor multilayer structure portion 65 includes a mesa multilayer portion 99 surrounded by the first trench 28, and a lateral direction from the mesa multilayer portion 99 to the surface of the n ⁺ -type GaN substrate 61 (hereinafter, this direction is referred to as a “width direction”). And a lead portion 66 made of the n ⁻ -type GaN layer 62. In other words, the lead-out portion 66 having an annular shape in plan view is configured by an extension of the n ⁻ -type GaN layer 62 in this embodiment.

The mesa stacked portion 99 is etched in a direction crossing the stacked interface from the n ⁺ -type GaN layer 64 to a depth at which the n ⁻ -type GaN layer 62 is exposed. As a result, a second trench 67 having a U-shape in cross section is formed in the mesa laminated portion 99.
The second trench 67 has a plurality of minimum units aligned such that one side of one minimum unit and one side of another minimum unit are shared with a minimum unit of six sides forming a regular hexagonal outline in plan view. Thus, the honeycomb structure is formed as a whole in plan view. Further, the depth of the second trench 67 is deeper than the depth of the first trench 28. The maximum width of the second trench 67 is preferably 0.5 to 2 μm.

Due to the second trench 67 having such a shape, the mesa stacked portion 99 includes an n ⁻ -type GaN layer 62, a p-type GaN layer 63, and an n ⁺ -type in a portion surrounded by each minimum unit of the second trench 67. A regular hexagonal columnar portion 29 having six wall surfaces 68 that are inclined with respect to the lamination interface of the mesa multilayer portion 99 (nitride semiconductor multilayer structure portion 65) is formed across the GaN layer 64.
The columnar portions 29 are formed in the same number (plurality) as the minimum units of the second trenches 67, and are formed in a honeycomb shape as a whole so that each columnar portion 29 has a predetermined width (the width of the second trench 67) from the adjacent columnar portions 29. Is arranged.

One side in the plan view of each columnar portion 29 is preferably 2 to 10 μm. Each columnar portion 29 has an npn stacked structure composed of an n ⁻ -type GaN layer 62, a p-type GaN layer 63, and an n ⁺ -type GaN layer 64, and is a minimum unit having a transistor function in a nitride semiconductor device. (Unit cell). The n ⁻ -type GaN layer 62 exposed in the second trench 67 is shared by the unit cells.

The nitride semiconductor multilayer structure portion 65 is formed on the n ⁺ -type GaN substrate 61 by, for example, the MOCVD method.
For example, when an n ⁺ -type GaN substrate 61 having a c-plane (0001) as the main surface is used, an n ⁻ -type GaN layer 62, a p-type GaN layer 63, and an n-type GaN layer grown on the n ⁺ -type GaN substrate 61 by epitaxial growth. ^{The +} -type GaN layer 64 is also laminated with the c-plane (0001) as the main surface. Therefore, the plane orientation of the wall surface 68 inclined with respect to the lamination interface of the nitride semiconductor multilayer structure portion 65 is, for example, a plane inclined in a range of 15 ° to 90 ° with respect to the c plane (0001) (other than the c plane) Surface). More specifically, for example, non-polar surfaces such as m-plane (10-10) or a-plane (11-20), and semipolar surfaces such as (10-13), (10-11), and (11-22) It becomes a surface.

A gate insulating film 69 is formed on the entire surface of the columnar portion 29 and the lead portion 66 except for a part thereof. The gate insulating film 69 can be made of nitride or oxide, for example. More specifically, the gate insulating film 69 can be composed of SiN (silicon nitride), SiO ₂ (silicon oxide), or a combination thereof.
On the gate insulating film 69, a gate electrode 70 that faces the wall surface 68 in each columnar portion 29 is formed. In the columnar portion 29, the gate electrode 70 covers the entire area of the six wall surfaces 68 from the peripheral portion of the regular hexagonal n ⁺ -type GaN layer 64 in plan view and reaches the n ⁻ -type GaN layer 62 exposed in the second trench 67. It is formed as follows. Thereby, the gate width in each unit cell (each columnar part 29) is substantially the same as the outer periphery (total length of regular hexagonal sides) of the columnar part 29 in plan view.

In addition, the gate electrode 70 formed in the one columnar portion 29 and the gate electrode 70 formed in the other adjacent columnar portion 29 are integrally connected on the n ⁻ -type GaN layer 62. That is, the gate electrode 70 is shared by all the columnar portions 29 by integrally connecting the portions formed in each columnar portion 29 on the n ⁻ -type GaN layer 62.
The gate electrode 70 is made of, for example, Ni and Au laminated on the Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au alloy, Pd / Pt / Au alloy, Pt, Al. It can be made of a conductive material such as polysilicon.

A region near the wall surface 68 in the p-type GaN layer 63 is a channel region 71 facing the gate electrode 70. In this channel region 71, an inversion channel is formed that electrically conducts between the n ⁻ -type GaN layer 62 and the n ⁺ -type GaN layer 64 by applying an appropriate bias to the gate electrode 70.
A contact electrode trench 72 is formed in each columnar portion 29. The contact electrode trench 72 is formed at a depth from the upper surface of the n ⁺ -type GaN layer 64 to the p-type GaN layer 63. A contact electrode 73 is embedded in the contact electrode trench 72.

  The contact electrode 73 is in ohmic contact with the p-type GaN layer 63. For example, a Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au made of Ni and Au laminated on the Ni is used. An alloy, a Pd / Pt / Au alloy, and a metal such as Pt can be used. Since these metals have a low contact resistance with respect to the p-type GaN layer 63, the contact electrode 73 can be satisfactorily brought into ohmic contact with the p-type GaN layer 63.

In the gate insulating film 69, a contact opening 74 exposing the upper surface of the n ⁺ -type GaN layer 64 is formed in each columnar portion 29. The contact opening 74 is formed in a square shape in plan view in a portion surrounded by the gate electrode 70 on the n ⁺ -type GaN layer 64. A source electrode 75 is formed on the contact electrode 73 and the n ⁺ -type GaN layer 64 exposed in the contact opening 74.

The source electrode 75 is in ohmic contact with the n ⁺ -type GaN layer 64 and the contact electrode 73. For example, the source electrode 75 is made of Ti and a metal such as a Ti / Al alloy made of Al laminated on the Ti. can do. By configuring the source electrode 75 with a metal containing Al, the source electrode 75 can be in good ohmic contact with the n ⁺ -type GaN layer 64 and the contact electrode 73. In addition, the source electrode 75 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

A drain electrode 78 is formed in contact with the other surface of the n ⁺ -type GaN substrate 61. The drain electrode 78 is in ohmic contact with the n ⁺ -type GaN substrate 61, and can be configured using, for example, the same type of metal as the source electrode 75, that is, a metal such as a Ti / Al alloy. In addition, the drain electrode 78 may be made of Mo or Mo compound (for example, molybdenum silicide), Ti or Ti compound (for example, titanium silicide), or W or W compound (for example, tungsten silicide).

Thus, in this nitride semiconductor element, a MOSFET 97 (Metal Oxide Semiconductor Field Effect Transistor: MOS) in which the gate electrode 70, the gate insulating film 69, the source electrode 75, and the drain electrode 78 are formed in the nitride semiconductor multilayer structure portion 65 is formed. Field effect transistor).
In the gate insulating film 69, a contact opening 76 that exposes the upper surface of the n ⁻ -type GaN layer 62 is formed on the lead portion 66. The contact openings 76 are formed in a substantially U shape in plan view so as to surround the columnar portions 29 arranged in a honeycomb shape. A Schottky electrode 77 is formed on the n ⁻ -type GaN layer 62 exposed in the contact opening 76. The Schottky electrode 77 is in Schottky contact with the n ⁻ -type GaN layer 62, and is the same type of metal as the contact electrode 73, that is, Ni / Au alloy, Pd / Au alloy, Pd / Ti / Au alloy, Pd / Pt / Au alloy and metal such as Pt can be used.

On the gate insulating film 69, an interlayer insulating film 30 covering the source electrode 75, the gate electrode 70, and the Schottky electrode 77 is laminated. The interlayer insulating film 30 can be configured using, for example, silicon nitride (SiN) or silicon oxide (SiO ₂ ).
In the interlayer insulating film 30, a source contact hole 50 having a regular hexagonal shape in plan view is formed in a portion facing the source electrode 75. A source contact electrode 52 for contact with the source electrode 75 is embedded in the source contact hole 50. The source contact electrode 52 can be configured using, for example, aluminum (Al).

  In the interlayer insulating film 30, a Schottky contact hole 102 is formed at a portion facing the Schottky electrode 77. A Schottky contact electrode 27 for contact with the Schottky electrode 77 is embedded in the Schottky contact hole 102. The Schottky contact electrode 27 can be configured using, for example, aluminum (Al).

  A source pad 60 is formed on the surface of the interlayer insulating film 30. The source pad 60 can be configured using, for example, aluminum (Al). The source pad 60 is arranged over the entire region on the columnar portions 29 and the Schottky electrodes 77 arranged in a honeycomb shape, and on the source contact electrodes 52 and the Schottky electrodes 77 formed on the respective columnar portions 29. In contact with the Schottky contact electrode 27. As a result, the source electrode 75 formed on the columnar portion 29 is collectively electrically connected (ohmically connected) to the source pad 60 via the source contact electrode 52.

The Schottky electrode 77 is connected to the source pad 60 through the Schottky contact electrode 27. As a result, the Schottky electrode 77 is collectively electrically connected to the source electrode 75 formed in each columnar portion 29 via the source pad 60. Since the Schottky electrode 77 is in Schottky contact with the n ⁻ -type GaN layer 62, the nitride semiconductor element includes an SBD 79 (Schottky comprising the Schottky electrode 77 and the n ⁻ -type GaN layer 62. Barrier Diode: Schottky barrier diode) is provided.

Further, on the surface of the interlayer insulating film 30, a gate pad 95 that is electrically connected to the gate electrode 70 is formed in a portion adjacent to the source pad 60, similarly to the gate pad 59 shown in FIG.
In FIG. 10, the interlayer insulating film 30 is omitted for easy understanding of the structure of the nitride semiconductor device.

The operation of the nitride semiconductor device according to this embodiment is the same as the operation of the nitride semiconductor device according to the first embodiment described above.
As described above, according to this nitride semiconductor device, the SBD 79 composed of the n ⁻ -type GaN layer 62 of the MOSFET 97 and the Schottky electrode 77 is provided as in the above-described embodiment. The SBD 79 is collectively electrically connected to the source electrode 75 of each columnar portion 29 via the Schottky contact electrode 27 and the source pad 60.

Therefore, when a bias that is positive on the source electrode 75 side is applied to the drain electrode 78 (when the potential of the source electrode 75 becomes higher than the potential of the drain electrode 78), a current is preferentially passed to the SBD 79. Can flow.
As a result, for example, when a nitride semiconductor element is operated, a high current generated by the bias is allowed to flow from the drain electrode 78 to the Schottky electrode 77 even when a bias that is positive on the source electrode 75 side is applied. it can. Therefore, electric field concentration at the junction between the n ⁺ -type GaN layer 64 and the p-type GaN layer 63 can be suppressed, and the occurrence of dielectric breakdown can be suppressed.

In addition, a diode for suppressing the occurrence of dielectric breakdown in this way is an SBD 79 constituted by an n ⁻ -type GaN layer 62 of MOSFET 97 and a Schottky electrode 77 formed on the upper surface of this n ⁻ -type GaN layer 62. It is formed as.
Therefore, the MOSFET 97 and the diode (SBD 79) for countermeasures against dielectric breakdown can be integrated.

As a result, it is possible to reduce the chip area of the nitride semiconductor device.
Further, a Schottky electrode 77 connected to the plurality of source electrodes 75 is formed in a substantially U shape in plan view so as to surround the columnar portions 29 arranged in a honeycomb shape.
Therefore, compared to the case where one Schottky electrode is provided for each source electrode 75, the space required for installing the Schottky electrode in the entire chip can be reduced.

As a result, the chip area of the nitride semiconductor device can be further reduced.
Further, the gate electrode 70 is opposed to the entire area of the six wall surfaces 68, and the gate width in each unit cell (each columnar portion 29) is the outer circumference of the columnar portion 29 in plan view (the total length of the sides of the regular hexagon). Therefore, it is possible to secure a long gate width in each unit cell.
Therefore, since the current density can be increased, a higher output power device can be realized.

Although a plurality of embodiments of the present invention have been described above, the present invention can also be implemented in other forms.
For example, in the above-described embodiment, an example in which the trench 7 having a substantially V-shaped cross section is formed in the nitride semiconductor multilayer structure portion 5 has been described. The shape of the trench 7 may be an inverted trapezoid, a U shape, a rectangle, a trapezoid, or the like. Other shapes may be used. The shapes of the second trenches 37 and 67 may be other shapes such as a V shape, an inverted trapezoid, a rectangle, and a trapezoid.

In the above-described embodiment, the n ⁺ -type GaN substrate 1 is exemplified as a substrate constituting a part of the nitride semiconductor multilayer structure portion 5 (first embodiment), and the nitride semiconductor multilayer structure portion 5 is illustrated. A sapphire substrate 26 has been exemplified as a substrate for supporting the substrate (second to fourth embodiments). Instead of these substrates, for example, a conductive material such as a ZnO substrate, a Si substrate, a GaAs substrate, and a SiC substrate can be used. A substrate may be applied, and the nitride semiconductor multilayer structure portion 5 may be formed on one surface of the conductive substrate. A drain electrode 18 can be formed on the other surface of the conductive substrate. Accordingly, the drain electrode 18 and the n ⁻ -type GaN layer 2 can be in ohmic contact with each other through the conductive substrate, so that a space for contacting the drain electrode 18 in the nitride semiconductor multilayer structure portion 5 is omitted. can do.

In the above-described embodiment, the wall surfaces 8, 38, 68 are planes inclined with respect to the n ⁺ -type GaN substrates 1, 31, 61. However, the wall surfaces 8, 38, 68 do not have to be inclined and are flat. There is no need. That is, the wall surfaces 8, 38, 68 may be planes perpendicular to the n ⁺ -type GaN substrates 1, 31, 61, or may be curved surfaces.
Also, the present invention includes a form in which the configurations of the nitride semiconductor elements according to the above-described embodiments are combined.

  In addition, various design changes can be made within the scope of matters described in the claims.

1 is a schematic cross-sectional view for explaining the structure of a nitride semiconductor device according to a first embodiment of the present invention. FIG. 2 is a circuit diagram of the nitride semiconductor device shown in FIG. 1. FIG. 6 is a schematic cross-sectional view for explaining a first method for manufacturing the nitride semiconductor device of FIG. 1. It is typical sectional drawing which shows the next process of FIG. 3A. It is typical sectional drawing which shows the next process of FIG. 3B. FIG. 3D is a schematic cross-sectional view showing the next step of FIG. 3C. FIG. 3D is a schematic cross-sectional view showing a step subsequent to FIG. 3D. It is typical sectional drawing which shows the next process of FIG. 3E. It is typical sectional drawing which shows the next process of FIG. 3F. It is typical sectional drawing which shows the next process of FIG. 3G. FIG. 6 is a schematic cross-sectional view for explaining a second manufacturing method of the nitride semiconductor device of FIG. 1. FIG. 4B is a schematic cross-sectional view showing the next step of FIG. 4A. It is typical sectional drawing which shows the next process of FIG. 4B. FIG. 4D is a schematic sectional view showing a step subsequent to FIG. 4C. FIG. 4D is a schematic cross-sectional view showing a step subsequent to FIG. 4D. It is typical sectional drawing which shows the next process of FIG. 4E. It is typical sectional drawing which shows the next process of FIG. 4F. It is typical sectional drawing which shows the next process of FIG. 4G. It is typical sectional drawing which shows the process of FIG. 4H. FIG. 4D is a schematic sectional view showing a step subsequent to FIG. 4I. FIG. 4D is a schematic cross-sectional view showing a step subsequent to FIG. 4J. It is a typical sectional view for explaining the structure of a nitride semiconductor device concerning a 2nd embodiment of the present invention. It is a typical sectional view for explaining the structure of a nitride semiconductor device concerning a 3rd embodiment of the present invention. It is typical sectional drawing for demonstrating the structure of the nitride semiconductor element which concerns on the 4th Embodiment of this invention. FIG. 6 is a schematic plan view for explaining the structure of a nitride semiconductor device according to a fifth embodiment of the present invention. It is typical sectional drawing when the nitride semiconductor element of FIG. 8 is cut | disconnected by the cutting line shown by IX-IX. FIG. 10 is a schematic plan view for explaining the structure of a nitride semiconductor device according to a sixth embodiment of the present invention. It is typical sectional drawing when the nitride semiconductor element of FIG. 10 is cut | disconnected by the cutting line shown by XI-XI. It is typical sectional drawing for demonstrating the structure of the conventional MOSFET. FIG. 13 is a circuit diagram showing a state where a diode is connected to the MOSFET shown in FIG. 12.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 n ⁺ type GaN board | substrate 2 n ^- type GaN layer 3 p-type GaN layer 4 n ⁺ type GaN layer 5 Nitride semiconductor laminated structure part 6 drawer | drawing-out part 7 trench 8 wall surface 9 gate insulating film 10 gate electrode 13 contact electrode 15 source electrode 17 Schottky electrode 18 Drain electrode 19 SBD
20 MOSFET
28 First trench 31 n ⁺ type GaN substrate 32 n ⁻ type GaN layer 33 p type GaN layer 34 n ⁺ type GaN layer 35 Nitride semiconductor laminated structure part 36 lead part 37 second trench 38 wall surface 39 gate insulating film 40 gate electrode 43 Contact electrode 45 Source electrode 47 Schottky electrode 48 Drain electrode 49 SBD
53 1st trench 61 n ⁺ type GaN substrate 62 n ⁻ type GaN layer 63 p type GaN layer 64 n ⁺ type GaN layer 65 nitride semiconductor laminated structure part 66 lead part 67 second trench 68 wall surface 69 gate insulating film 70 gate electrode 73 Contact electrode 75 Source electrode 77 Schottky electrode 78 Drain electrode 79 SBD
96 MOSFET
97 MOSFET
98 Mesa lamination part 99 Mesa lamination part

Claims (5)

An n-type first layer made of a group III nitride semiconductor, a second layer containing p-type impurities stacked on the first layer, and an n-type third layer stacked on the second layer, A nitride semiconductor multilayer structure having a wall surface straddling the first, second and third layers;
A gate insulating film formed on the wall surface across the first, second and third layers;
A gate electrode formed to face the second layer with the gate insulating film interposed therebetween;
A source electrode formed in ohmic contact with the third layer;
A drain electrode formed in ohmic contact with the first layer;
And a Schottky electrode formed so as to be in Schottky contact with the first layer. The first layer includes a lower layer having a relatively high n-type impurity concentration and an upper layer having an n-type impurity concentration lower than the lower layer,
The nitride semiconductor device according to claim 1, wherein the Schottky electrode is formed so as to make a Schottky contact with the upper layer. In the nitride semiconductor multilayer structure portion, an annular trench is formed from the third layer to the first layer through the second layer,
A plurality of the source electrodes are provided in a mesa multilayer part surrounded by the trench in the nitride semiconductor multilayer structure part,
3. The nitride semiconductor device according to claim 1, wherein one Schottky electrode is provided so as to surround the mesa stacked portion, and is connected to the plurality of source electrodes at once. A first layer forming step of forming an n-type first layer made of a group III nitride semiconductor;
A second layer forming step of forming a second layer containing a p-type impurity made of a group III nitride semiconductor on the first layer;
A third layer forming step of forming an n-type third layer made of a group III nitride semiconductor on the second layer;
A wall surface forming step of forming a wall surface straddling the first, second and third layers;
Forming a gate insulating film on the wall surface so as to straddle the first, second and third layers;
Forming a gate electrode so as to face the second layer with the gate insulating film interposed therebetween;
A source electrode forming step of forming a source electrode so as to be in ohmic contact with the third layer;
Forming a drain electrode so as to be in ohmic contact with the first layer; and
An exposing step of partially exposing the first layer;
And a Schottky electrode forming step of forming a Schottky electrode so as to be in Schottky contact with the exposed surface of the first layer exposed by the exposing step. The first layer forming step includes a lower layer forming step of forming a lower layer having a relatively high n-type impurity concentration, and an upper layer forming step of forming an upper layer having a lower n-type impurity concentration than the lower layer on the lower layer. Including
The exposing step is a step of partially exposing at least the upper layer;
The method of manufacturing a nitride semiconductor device according to claim 4, wherein the Schottky electrode forming step is a step of forming a Schottky electrode on the exposed surface of the upper layer exposed by the exposing step.

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