JP5620718B2 - Integrated circuit device having voltage regulator - Google Patents

Description

  The present invention relates to an integrated circuit device having a voltage regulator.

  Recent integrated circuit devices such as microprocessors incorporate a voltage regulator that steps down or boosts the external power supply to save power. The voltage regulator generates an internal power supply having a predetermined voltage from an external power supply and supplies it as a power supply voltage for the internal circuit.

  An integrated circuit device incorporating a voltage regulator is described in, for example, Patent Documents 1 and 2.

JP 2002-358130 A JP 2002-83872 A

  On the other hand, an integrated circuit device is required to operate in various operation modes. For this purpose, the integrated circuit device has a mode terminal for designating an operation mode from the outside, and has a built-in mode decoder that decodes a mode signal input to the mode terminal and determines a requested operation mode.

  At the same time, in the test mode, there is an operation mode in which a test power supply is supplied from the outside in order to inspect an operation margin with respect to the voltage level of the internal power supply of the internal circuit. In this case, a mode signal designating that the operation mode of the test is input from the mode terminal, and the test power is supplied from the terminal connected to the internal power supply.

  As described above, the mode terminal for designating the operation mode reduces the degree of freedom of the limited external terminals of the integrated circuit device, and restricts the number of input / output terminals necessary for the original operation.

  Accordingly, an object of the present invention is to provide an integrated circuit device in which the number of mode terminals is reduced.

The first side surface of the integrated circuit device includes a first power supply wiring connected to the first power supply terminal and supplying a first power supply voltage;
A voltage regulator that generates a second power supply voltage from the first power supply voltage and outputs the second power supply voltage to a second power supply wiring;
A capacitor terminal connected to the output of the voltage regulator and connected to an external capacitor;
A mode decoder for determining an operation mode according to a mode signal;
An internal circuit to which the second power supply voltage is supplied,
A first operation mode in which the voltage regulator operates without applying a third power supply voltage to the capacitor terminal; and a second operation in which the voltage regulator is stopped while the third power supply voltage is applied to the capacitor terminal. Operating mode, and
Further, a first state in which the third power supply voltage is not applied to the capacitor terminal and a second state in which the third power supply voltage is applied are determined, and the determination result is supplied to the mode decoder as the mode signal. Has a determination circuit for operating the voltage regulator when in the first state and stopping the voltage regulator when in the second state.

  According to the first aspect, since the state of the capacitor terminal to which the third power supply voltage is applied in the second operation mode is supplied as a mode signal to the mode decoder, the number of mode terminals specifying the operation mode Can be reduced.

It is a block diagram of the integrated circuit device relevant to this Embodiment. It is a block diagram of the integrated circuit device relevant to this Embodiment. 3 is a chart showing states of terminals and operation modes of the integrated circuit device of FIGS. It is a chart which shows the state and operation mode of each terminal of the integrated circuit device in this Embodiment. It is a block diagram of the integrated circuit device in this Embodiment. FIG. 6 is a diagram illustrating an operation of the integrated circuit device of FIG. 5. It is a block diagram of the integrated circuit device in this Embodiment. It is a figure which shows operation | movement of the integrated circuit device of FIG. It is a block diagram of the integrated circuit device in this Embodiment.

  1 and 2 are configuration diagrams of an integrated circuit device related to the present embodiment. This integrated circuit device 10 is connected to a first power supply terminal VCC and supplies a first power supply wiring 11 for supplying a first power supply voltage VDDE, and generates a second power supply voltage VDDI from the first power supply voltage VDDE. Voltage regulator 12 that outputs to the second power supply wiring 13 and a capacitor terminal C that is connected to the output 13 of the voltage regulator 12 and to which the external capacitor Cout is connected. Further, the integrated circuit device 10 includes a mode decoder 14 that determines the operation modes M1 to M4 according to mode signals input from the mode terminals MD1 and MD0, an internal circuit 16 that is supplied with the second power supply voltage VDDI, It has an input / output circuit 18 to which a first power supply voltage VDDE is supplied and an input / output terminal group 20 connected thereto. In addition, the external circuit has an external reset terminal INITX that supplies a start signal to the internal circuit 16, and the start signal is supplied from the reset circuit 1 on the external system side.

  For example, the voltage regulator 12 steps down the first power supply voltage VDDE that is the external power supply Vcc and generates the second power supply voltage VDDI that is the internal power supply. An external capacitor Cout is connected to the capacitor terminal C so that the voltage level of the second power supply voltage VDDI is stabilized. The lowered second power supply voltage VDDI is used as an internal power supply for the internal circuit 16. By using the second power supply voltage with the internal circuit 16 stepped down, the power consumption of the internal circuit 16 is saved. The first power supply voltage VDDE is used as a power supply for the input / output circuit 18 and is matched in voltage level with the power supply Vcc of the external system.

  For example, the mode decoder 14 determines four operation modes M1 to M4 from a combination of mode signals input from two mode terminals MD1 and MD0. In this example, the mode terminal MD1 is connected to the voltage regulator 12, and according to the mode signal of the mode terminal MD1, the voltage regulator 12 performs a voltage generation operation and outputs the second power supply voltage VDDI (in the case of FIG. 1). ), The operation is stopped and the second power supply voltage VDDI is not output (in the case of FIG. 2), the operation mode is controlled differently. In the operation mode in which the voltage regulator is stopped, the third power supply voltage Vtest is applied as the internal power supply VDDI from the capacitor terminal C as shown in FIG. The distinction between the different operation modes is performed by the mode signal of the mode terminal MD1.

  FIG. 3 is a table showing the states and operation modes of the terminals of the integrated circuit device of FIGS. For example, 3V is applied to the first power supply terminal VCC as the external power supply Vcc. On the other hand, the mode decoder 14 determines four operation modes M1 to M4 (modes 1 to 4) based on a combination of mode signals of the mode terminals MD1 and MD0.

  Further, in the operation modes M1 and M2, the third power supply voltage Vtest is not applied to the capacitor terminal C as shown in FIG. Then, the voltage regulator 12 operates in response to the mode signal (L level or “0”) of the mode terminal MD1, and generates the second power supply voltage VDDI. Therefore, the generated second power supply voltage VDDI is output to the capacitor terminal C, and the voltage level is stabilized by the external capacitor Cout. The operation modes M1 and M2 are distinguished by a mode signal from the mode terminal MD0.

  On the other hand, in the operation modes M3 and M4, the third power supply voltage Vtest is applied to the capacitor terminal C as shown in FIG. Then, the voltage regulator stops operating in response to the mode signal (H level or “1”) of the mode terminal MD1. That is, the third power supply voltage Vtest is input from the capacitor terminal C as the second power supply voltage VDDI which is an internal power supply. For example, in the test process, the second power supply is controlled by controlling the operation modes M3 and M4 and performing an operation test of the internal circuit while variably controlling the external third power supply voltage Vtest in the vicinity of 1.8V, for example. An operation margin of the voltage VDDI is confirmed. Also in this case, the operation modes M3 and M4 are distinguished by the mode signal of the mode terminal MD1.

  FIG. 4 is a table showing the states and operation modes of the terminals of the integrated circuit device according to this embodiment. FIG. 5 is a configuration diagram of the integrated circuit device according to the present embodiment.

  1 and 2, the integrated circuit device includes a first power supply terminal VCC, a first power supply wiring 11, a voltage regulator 12, a second power supply wiring 13, a mode decoder 14, an internal circuit, and the like. 16, an input / output circuit 18, an input / output terminal group 20, a capacitor terminal C, a mode terminal MD0, and an external reset terminal INITX. However, the mode terminal MD1 is not provided.

  Further, the integrated circuit device of FIG. 5 includes a determination circuit 21. The determination circuit 21 has a first state in which the third power supply voltage Vtest is not applied to the capacitor terminal C and a second state in which the third power supply voltage Vtest is applied. The signal S21 corresponding to the determination result is supplied to the mode decoder 14 as a mode signal, and at the same time, the signal S21 is supplied to the voltage regulator 12 as a control signal. When the signal S21 is in the first state, the voltage regulator 12 And the voltage regulator 12 is stopped in the second state.

  In the integrated circuit device of FIG. 5, the capacitor terminal C is connected to the external resistor R1 in addition to the external capacitor Cout, and in the first state where the third power supply voltage Vtest is not applied to the capacitor terminal C. Before the voltage regulator 12 starts operation, the voltage at the capacitor terminal C becomes the ground level (L level or “0”).

  In the integrated circuit device of FIG. 5, unlike FIGS. 1 and 2, the mode terminal MD1 is removed, and instead, the voltage level of the capacitor terminal C is determined by the determination circuit 21, and the signal S21 corresponding to the determination result is the mode S21. The signal is supplied to the mode decoder 14 as a signal. That is, the capacitor terminal C replaces the function of the mode terminal MD1 of FIGS.

  In the integrated circuit device of FIG. 5, since the third power supply voltage Vtest is not input to the capacitor terminal C, the voltage is at least ground (0 V, L level or “0”) before the voltage regulator 12 operates. FIG. 4 is a configuration of modes 1 and 2 of the operation mode shown in FIG.

  The determination circuit 21 includes a latch circuit 22 that latches the voltage at the capacitor terminal C at a determination timing after a predetermined time after the first power supply voltage Vcc is applied to the first power supply terminal VCC, as shown in the figure. . When the latch circuit 22 latches the first state (L level or “0”) in which the third power supply Vtest is not input to the capacitor terminal C, the determination circuit 21 outputs the signal S21 of H level or “1”. When the second state (H level or “1”) is supplied to the voltage regulator 12 as an operation signal and the third power supply Vtest is input to the capacitor terminal, the L level or “0” signal S21 is applied as a voltage. The regulator 12 is supplied as a stop signal.

  Furthermore, the determination circuit 21 includes a power-on reset circuit 24 that outputs a power-on reset signal as a signal C_DETECT indicating determination timing, and an AND gate 26. The power-on reset circuit 24 detects that the first power supply Vcc is applied to the first power supply terminal VCC and the voltage of the first power supply wiring 11 rises, and uses the power-on reset signal as the determination timing signal C_DETECT. Output. The latch circuit 22 latches and holds the signal at the data terminal D in response to the input of the gate signal G. When the determination timing signal C-DETECT rises to H level, the voltage C-LEVEL of the capacitor terminal C is latched by the latch circuit 22 and the determination signal S21 is output via the AND gate 26.

  Therefore, when capacitor terminal C is at L level, determination signal S21 is at H level, voltage regulator 12 operates, and when capacitor terminal C is at H level, determination signal S21 is at L level, and voltage regulator 12 is stopped. To do.

  The first state corresponds to modes 1 and 2 in FIG. 4, and the second state corresponds to modes 3 and 4 in FIG. The mode signal at the mode terminal MD0 is used to distinguish between modes 1 and 2, or between modes 3 and 4, as in FIG.

  FIG. 6 is a diagram illustrating the operation of the integrated circuit device of FIG. As described above, the integrated circuit device in FIG. 5 corresponds to the first state in modes 1 and 2 in FIG. 4, and FIG. 6 shows the operation in the first state in modes 1 and 2. In FIG. 6, VCC indicates the voltage of the first power supply terminal VCC and the first power supply wiring 11, C_LEVEL indicates the voltage of the C terminal, C-DETECT is a determination timing signal, and the output signal of the power-on reset circuit 24 C_JUDGE is an output signal of the latch circuit, S21 is an output of the AND gate 26 and indicates a control signal to the voltage regulator, and INITX indicates an external reset signal.

  As shown in FIG. 5, in the first state of modes 1 and 2, the third power supply voltage Vtest is not applied to the capacitor terminal C, and is at the ground potential by the resistor R1. In FIG. 6, when the first power supply voltage Vcc is applied to the first power supply terminal VCC at time t1, the power-on reset circuit 24 detects the rise of the power supply voltage VDDE of the first power supply wiring 11, and the power supply voltage The determination timing signal C_DETECT is raised to H level at time t2 after a predetermined time has elapsed from the rise of VDDE.

  In response to the rise of the determination timing signal C_DETECT, at time t3, the latch circuit 22 latches the L-level voltage C_LEVEL = L of the capacitor terminal C, and the output C_JUDGE of the latch circuit remains at the L level. Accordingly, the output S21 of the AND gate 26 becomes H level, and the voltage regulator 12 starts to operate. The output S21 is also supplied to the mode decoder 14 as a mode signal.

  When the operation of the voltage regulator 12 starts, the power supply voltage VDDI of the second power supply wiring 13 rises to H level, and the voltage C_LEVEL of the capacitor terminal C connected to the second power supply wiring 13 rises to H level at time t5. The external resistor R1 is high enough to keep the capacitor terminal C at the H level. As will be described later, the resistor R1 may be disconnected from the capacitor terminal C after the internal circuit 16 starts operating.

  Eventually, a start signal is supplied from the externally provided reset circuit 1 to the external reset terminal INITX, and the internal circuit 16 starts its operation. At this time, the mode decoder 14 detects either mode 1 or 2 out of the four modes based on the mode signal S12 and the mode signal from the mode terminal MD0.

  FIG. 7 is a configuration diagram of the integrated circuit device according to the present embodiment. This integrated circuit device corresponds to the second state of modes 3 and 4 in FIG. 4, the third power supply voltage Vtest is applied to the capacitor terminal C, and no resistor is connected to the capacitor terminal C. The other configuration is the same as FIG.

  In the integrated circuit device of FIG. 7, since the third power supply voltage Vtest is applied to the capacitor terminal C and is set to the H level, the determination circuit 21 detects the H level of the voltage C_LEVEL of the capacitor terminal C, and the signal S21 is L At this level, the voltage regulator 12 is stopped. Instead, an external third power supply voltage Vtest applied to the capacitor terminal C is applied to the second power supply wiring 13.

  FIG. 8 is a diagram illustrating the operation of the integrated circuit device of FIG. Each signal in the figure is the same as in FIG.

  As shown in FIG. 4, in the second state of modes 3 and 4, the third power supply voltage Vtest is applied to the capacitor terminal C. Correspondingly, also in FIG. 8, the voltage C_LEVEL of the capacitor terminal C rises at time t11. At time t12, the first power supply voltage Vcc is applied to the first power supply terminal VCC and rises. In response to the rise of the power supply voltage VDDE of the first power supply wiring 11, the latch circuit 22 starts to operate, and the H level of the voltage C_LEVEL of the data terminal C applied to the data terminal D is applied to the output terminal Q. Is output, and the judgment signal C_JUDGE also goes high.

  At time t13 after a predetermined time has elapsed after time t12, the power-on reset circuit 24 raises the output determination timing signal C_DETECT to H level. In response to this, at time t14, the latch circuit 22 takes in the H level of the voltage C_LEVEL of the data terminal C and determines the determination signal C_JUDGE = H of the output Q. As a result, at time t15, the output signal S21 of the AND gate 26 is maintained at the L level, the voltage regulator 12 remains stopped, and the L level of the output signal S21 is supplied to the mode decoder 14 as a mode signal. . Thereby, the mode decoder 14 determines the mode 3 or 4.

  Eventually, at time t16, the external reset signal INITX rises and the internal circuit 16 starts operating. In this state, the voltage regulator 12 stops operating, and the third power supply voltage Vtest applied to the capacitor terminal C is supplied to the internal circuit 16 as the second power supply voltage VDDI. The mode decoder 14 determines mode 3 or 4 according to the mode signal from the mode terminal MD0 and the signal S21 from the determination circuit 21.

  FIG. 9 is a configuration diagram of a modified example of the integrated circuit device of the present embodiment. The integrated circuit device of FIG. 9 corresponds to FIG. 5, and the third power supply voltage Vtest is not applied to the capacitor terminal C. Instead of the external resistor R1, an N-channel MOS transistor N1, a resistor R2, and an inverter 30 connected to the capacitor terminal C are built in the integrated circuit device 10.

  A signal obtained by inverting the external reset signal INITX by the inverter 30 is applied to the gate of the transistor N1. Therefore, while the external reset signal INITX is at the L level, the transistor N1 is conductive, and is connected to the ground through the resistor R2 and the transistor N1 in which the capacitor terminal C is conductive. This state is the same as the configuration of FIG.

  On the other hand, when the external reset signal INITX becomes H level and the internal circuit 16 starts to operate, the transistor N1 is turned off and the resistor R2 is disconnected from the capacitor terminal C. As a result, the internal power supply voltage VDDI of the second power supply wiring 13 is prevented from being connected to the ground via the resistor R2. This brings about a power saving effect.

  As described above, according to the present embodiment, the operation state of the voltage regulator 12 is controlled by the state of the capacitor terminal C to which the external power supply Vtest is applied, and the mode signal is input to the mode decoder 14. Thus, the mode terminal can be saved.

10: integrated circuit device Vcc: first power supply VCC: first power supply terminal 11: first power supply wiring VDDE: first power supply voltage 12: voltage regulator VDDI: second power supply voltage 13: second power supply wiring 14: Mode decoder C: Capacitor terminal MD1: Mode terminal 16: Internal circuit 18: Input / output circuit 20: Input / output signal terminal group INITX: External reset signal

Claims (4)

A first power supply wiring connected to a first power supply terminal for supplying a first power supply voltage;
A voltage regulator that generates a second power supply voltage from the first power supply voltage and outputs the second power supply voltage to a second power supply wiring;
A capacitor terminal connected to the output of the voltage regulator and connected to an external capacitor;
A mode decoder for determining an operation mode according to a mode signal input from a mode terminal ;
An internal circuit to which the second power supply voltage is supplied,
A first operation mode in which the voltage regulator operates without applying a third power supply voltage to the capacitor terminal; and a second operation in which the voltage regulator is stopped while the third power supply voltage is applied to the capacitor terminal. Operating mode, and
Further, a first state in which the third power supply voltage is not applied to the capacitor terminal and a second state in which the third power supply voltage is applied are determined, and the determination result is supplied to the mode decoder as the mode signal. There have a determination circuit, wherein to operate said voltage regulator when in the first state, stopping the voltage regulator in the case of the second state,
The integrated circuit device , wherein the mode decoder identifies at least three modes based on a combination of a mode signal input from the mode terminal and the operation mode . In claim 1,
The determination circuit includes a latch circuit that latches the voltage of the capacitor terminal at a determination timing after a predetermined time after the first power supply voltage is applied to the first power supply terminal. An operation signal is supplied to the voltage regulator when the voltage at the capacitor terminal in the first state is latched, and a stop signal is supplied to the voltage regulator when the voltage at the capacitor terminal in the second state is latched. Integrated circuit device. In claim 2,
The latch circuit of the determination circuit latches the voltage of the capacitor terminal using the reset signal of the power-on reset circuit that detects that the first power supply voltage is applied to the first power supply terminal as the determination timing. Integrated circuit device. In claim 2 or 3,
The integrated circuit device, wherein the capacitor terminal is connected to the ground at least until the determination timing in addition to being connected to the external capacitor.

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