JP5608969B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device using a nitride semiconductor or the like, a manufacturing method thereof, and the like.

  In recent years, an electronic device in which an aluminum gallium nitride (AlGaN) / GaN heterostructure is grown on a substrate and the GaN layer functions as an electron transit layer has been actively developed. As such an electronic device, for example, a high electron mobility transistor (HEMT) is known. The band gap of GaN is 3.4 eV, which is larger than 1.4 eV of GaAs. For this reason, GaN is expected as a semiconductor material that can realize a high-breakdown-voltage electronic device.

  And it is thought that silicon carbide (SiC) and gallium nitride (GaN) are suitable as materials for the substrate of HEMT. This is because the lattice constant of SiC and GaN is close to the lattice constant of the GaN-based crystal, and a GaN-based crystal layer with few dislocations can be easily grown. However, at present, the production of the SiC substrate and the GaN substrate is not easy, and the price of these substrates is high. Wireless LAN (local area network) and mobile phone base station amplifiers are required to be reduced in cost in order to be easily spread. In addition, there is a demand for cost reduction in power application devices for consumer applications.

  Therefore, studies have been conducted on the use of sapphire substrates and silicon (Si) substrates, which are cheaper than these, as substrates to replace SiC substrates and GaN substrates.

  However, it is difficult to grow a GaN-based crystal layer with few dislocations on a sapphire substrate and a silicon (Si) substrate by a conventional method. Further, the thermal conductivity of the sapphire substrate is low, and it is difficult to release heat generated from HEMT including a GaN-based crystal layer. For this reason, when a sapphire substrate is used as a HEMT substrate, the output tends to decrease due to a self-heating effect in a high power region where the current / voltage product is large. Also, in the Si substrate, as compared with the SiC substrate, the element characteristics of the GaN-based HEMT formed thereon are deteriorated due to heat.

JP 2007-250727 A JP 2006-351762 A JP 2005-167275 A JP 2007-158274 A

  An object of the present invention is to provide a compound semiconductor device that can be manufactured using an inexpensive substrate and can obtain good characteristics, and a manufacturing method thereof.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

In one embodiment of the compound semiconductor device, a first conductivity type first semiconductor layer, a depleted second conductivity type second semiconductor layer formed on the first semiconductor layer, the first conductivity type, And a third semiconductor layer formed on the second semiconductor layer. Furthermore, an active layer formed on the third semiconductor layer and an electrode layer formed on the active layer are provided. The first semiconductor layer is a p-type GaN layer, and the second semiconductor layer is an n-type GaN layer.

In one embodiment of the method for manufacturing a compound semiconductor device, a separation layer is formed on a substrate, and then a first conductivity type first semiconductor layer is formed on the separation layer. Next, a depleted second conductivity type second semiconductor layer is formed on the first semiconductor layer. Next, a third semiconductor layer is formed on the second semiconductor layer. Next, an active layer is formed on the third semiconductor layer. Next, an electrode layer is formed on the active layer. Then, the substrate is removed by removing the separation layer. The first semiconductor layer is a p-type GaN layer, and the second semiconductor layer is an n-type GaN layer.

  According to the above compound semiconductor device or the like, a good crystalline active layer can be obtained even if an inexpensive substrate such as a sapphire substrate is used. Therefore, good characteristics can be obtained. In addition, leakage of current to the outside of the compound semiconductor device can be suppressed.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of a GaN-based HEMT (compound semiconductor device) mounting body according to the first embodiment.

In the first embodiment, as shown in FIG. 1A, an n-type GaN layer 3 is formed on a p-type GaN layer 2, and an undoped GaN layer 4 is formed on the n-type GaN layer 3. . For example, the thickness of the p-type GaN layer 2 is about 0.5 μm, and the p-type GaN layer 2 contains Mg at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . For example, the thickness of the n-type GaN layer 3 is about 0.5 μm, and the n-type GaN layer 3 contains Si at a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ / cm ³ . In this embodiment, the n-type GaN layer 3 is depleted by the diffusion potential between the pn junctions. The undoped GaN layer 4 has a thickness of about 30 μm to 100 μm, for example. In the present embodiment, the active layer 5 and the electrode layer 6 are formed in this order on the GaN layer 4. Details of the active layer 5 and the electrode layer 6 will be described with reference to FIG.

  The HEMT 1 in the first embodiment includes the p-type GaN layer 2, the n-type GaN layer 3, the GaN layer 4, the active layer 5, and the electrode layer 6. Has been implemented. For example, the mounting substrate 21 is made of metal, and the paste 22 is AuSn paste.

Here, the active layer 5 and the electrode layer 6 will be described. As shown in FIG. 1B, an electron transit layer 7, an electron supply layer 8 and a protective layer 9 are formed on the GaN layer 4. The electron transit layer 7 is, for example, an undoped GaN layer having a thickness of about 1 μm to 3 μm. The electron transit layer 7 is preferably GaN with as few impurities as possible. The electron supply layer 8 is, for example, an n-type AlGaN layer having a thickness of 10 nm to 30 nm. An undoped AlGaN layer may be additionally disposed above or below the electron supply layer 8. The protective layer 9 is an n-type GaN layer having a thickness of about 3 nm to 8 nm, for example. In the n-type AlGaN layer and the n-type GaN layer, for example, Si is used as an impurity at a carrier concentration of 1 × 10 ^{18 to} 5 × 10 ¹⁸ / cm ³ . In the protective layer 9, an opening for a source electrode and an opening for a drain electrode are formed, and a source electrode 11s and a drain electrode 11d are formed in these openings, respectively. The source electrode 11s and the drain electrode 11d include a titanium (Ti) film and an aluminum (Al) film formed thereon. A SiN film 10 is formed on the protective layer 9 to cover the source electrode 11s and the drain electrode 11d. In the SiN film 10, an opening 10a for a gate electrode is formed. A gate electrode 11g extending from the opening 10a to the SiN film 10 is formed. The gate electrode 11g may be formed without providing the gate opening. The gate electrode 11g includes a nickel (Ni) film and a gold (Au) film formed thereon, and the gate electrode 11g is Schottky bonded to the protective layer 9. An electron transit layer 7, an electron supply layer 8, and a protective layer 9 are included in the active layer 5, and a source electrode 11 s, a drain electrode 11 d, a gate electrode 11 g, and a SiN film 10 are included in the electrode layer 6.

  The layout of the electrode layer 6 is as shown in FIG. 2, for example. That is, the planar shape of the gate electrode 11g, the source electrode 11s, and the drain electrode 11d is a comb shape, and the source electrodes 11s and the drain electrodes 11d are alternately arranged. A gate electrode 11g is disposed between them. By adopting such a multi-finger gate structure, the output can be improved. The cross-sectional view shown in FIG. 1B is a cross-sectional view taken along the line II in FIG. Further, the periphery of the active layer 5 is made an inactive region by ion implantation or mesa etching. For example, the inactive region includes, for example, an insulating film embedded in a trench that reaches the GaN layer 4 through the protective layer 9, the electron supply layer 8, and the electron transit layer 7.

  In such a first embodiment, in addition to the spontaneous polarization effect due to the wurtzite crystal arrangement, a piezopolarization effect due to lattice distortion occurs in the vicinity of the interface between the electron supply layer 8 and the electron transit layer 7. For this reason, positive polarization charges appear, and electrons are induced in the vicinity of the interface between the electron transit layer 7 and the electron supply layer 8. As a result, a two-dimensional electron gas layer (2DEG) appears.

  An n-type GaN layer 3 and a p-type GaN layer 2 are provided on the opposite side of the GaN layer 4 from the active layer 5. For this reason, even if a high electric field is applied to the active layer 5 and the current 20 flows into the lower portion of the GaN layer 4 functioning as a buffer layer, the current 20 leaks to the mounting substrate 21 as shown in FIG. It is suppressed.

  Next, a method for manufacturing a GaN-based HEMT (compound semiconductor device) mounting body according to the first embodiment will be described. 4A to 4E are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT (compound semiconductor device) mounting body according to the first embodiment in the order of steps.

  In the first embodiment, first, as shown in FIG. 4A, an undoped AlN (aluminum nitride) layer 32 is formed on the sapphire substrate 31 as a separation layer. The thickness of the AlN layer 32 is, for example, about 1 μm. Next, the p-type GaN layer 2, the n-type GaN layer 3, and the undoped GaN layer 4 are formed in this order on the AlN layer 32. The formation method of the AlN layer 32, the p-type GaN layer 2, the n-type GaN layer 3, and the GaN layer 4 is not particularly limited, and is formed by, for example, hydride vapor phase epitaxy (HVPE). Although it may be formed by a molecular beam epitaxy (MBE) method or a metal organic chemical vapor deposition (MOCVD) method, the HVPE method is excellent in terms of high-speed growth. In the present embodiment, since the GaN layer 4 having a thickness of about 30 μm to 100 μm is formed, a method capable of high-speed growth is preferable.

  Thereafter, the active layer 5 and the electrode layer 6 are formed on the GaN layer 4. Here, a method of forming the active layer 5 and the electrode layer 6 will be described. 5A to 5E are cross-sectional views showing a method of forming the active layer 5 and the electrode layer 6 in the order of steps.

  First, as shown in FIG. 5A, an electron transit layer 7, an electron supply layer 8, and a protective layer 9 are formed in this order on the GaN layer 4. The formation method of the electron transit layer 7, the electron supply layer 8, and the protective layer 9 is not particularly limited.

When these layers are formed by the reduced pressure MOCVD method, for example, trimethylaluminum, trimethylgallium, and ammonia gas are used as source gases. Further, depending on the composition of the layer to be formed, the presence / absence and flow rate of trimethylaluminum as an Al source and trimethylgallium as a Ga source are appropriately set. Moreover, the flow rate of ammonia gas which is a common raw material is set to, for example, 100 cc / min to 10 liters / min. Further, for example, the growth pressure is set to about 6.7 kPa to 40 kPa (50 Torr to 300 Torr), and the growth temperature is set to about 1000 ° C. to 1200 ° C. When an n-type AlGaN layer is formed as the electron supply layer 8 and when an n-type GaN layer is formed as the protective layer 9, diluted silane (SiH ₄ ) is mixed with the raw material gas at several cc / min. Supply at a flow rate of. As a result, Si is added to the n-type AlGaN layer and the n-type GaN layer.

  After the electron transit layer 7, the electron supply layer 8, and the protective layer 9 are formed, a resist pattern is formed on the protective layer 9 to open regions where the source electrode 11 s and the drain electrode 11 d are to be formed. Next, by etching the protective layer 9 using the resist pattern as a mask, an opening for the source electrode and an opening for the drain electrode are formed in the protective layer 9 as shown in FIG. 5B. As this etching, for example, dry etching using a chlorine-based gas is performed. In addition, regarding the depth of these openings, a part of the protective layer 9 may be left, or a part of the electron supply layer 8 may be removed. That is, the depth of the opening does not need to match the thickness of the protective layer 9. Thereafter, the source electrode 11s and the drain electrode 11d are formed in these openings by a lift-off method, respectively. In forming the source electrode 11s and the drain electrode 11d, Ti and Al are vapor-deposited, and then Ti and Al adhering to the resist pattern are removed together with the resist pattern. And it heat-processes in 400 degreeC-1000 degreeC, for example, 550 degreeC in nitrogen atmosphere, and establishes ohmic characteristics.

  Subsequently, as shown in FIG. 5C, a SiN film 10 is formed on the entire surface by plasma CVD.

  Next, a resist pattern is formed on the SiN film 10 to open a region where an opening 10a is to be formed. Thereafter, the SiN film 10 is etched using the resist pattern as a mask, thereby forming an opening 10a in the SiN film 10 as shown in FIG. 5D. Then, the resist pattern is removed.

  Subsequently, a resist pattern that opens a region where the gate electrode 11g is to be formed is formed, Ni and Au are deposited, and then the Ni and Au adhering to the resist pattern are removed together with the resist pattern. In other words, the gate electrode 11g is formed by lift-off processing as shown in FIG. 5E.

  In this way, the active layer 5 and the electrode layer 6 are formed.

  After the formation of the active layer 5 and the electrode layer 6, as shown in FIG. 4B, the sapphire substrate 31 and each layer thereon are cut along the dicing line 33 and subdivided into individual chip sizes (dicing). . In this cutting, for example, mechanical processing using a diamond saw or the like is performed. The sapphire substrate 31 may be thinned by grinding the back surface of the sapphire substrate 31 before cutting.

  Next, the subdivided sapphire substrate 31 and the like are immersed in, for example, hot phosphoric acid. As a result, as shown in FIG. 4C, the undoped AlN layer 32 as the separation layer is gradually removed. When the AlN layer 32 disappears, the HEMT 1 is separated from the sapphire substrate 31 as shown in FIG. 4D.

  In this way, HEMT1 is obtained.

  Thereafter, each HEMT 1 is picked up by tweezers or the like and mounted on the mounting substrate 21 in the package using the paste 22 as shown in FIG. 4E.

  In this way, the GaN-based HEMT mounting body shown in FIGS. 1 and 2 is obtained.

  In such a manufacturing method, since the sapphire substrate 31 is used, cost can be reduced. Moreover, since the thick GaN layer 4 is provided below the active layer 5 while using the sapphire substrate 31, the crystallinity of the active layer 5 can be improved. That is, the active layer 5 with few dislocations can be formed.

  Moreover, since the sapphire substrate 31 is separated from the GaN layer 4, the low heat dissipation of the sapphire substrate 31 does not affect the operation of the HEMT 1, and good heat dissipation can be ensured. Therefore, even if heat is generated in a high power region where the current / voltage product is large, a high output can be maintained. Further, after the HEMT 1 is separated, the pick-up using tweezers or the like is performed as described above, but since the thick GaN layer 4 is provided, the pick-up and mounting are easy to handle.

  When the GaN layer 4 is directly formed on the sapphire substrate 31, as described above, there is a possibility that a leakage current leaks to the mounting substrate 21 when a high electric field is applied to the active layer 5. However, in this embodiment, since the p-type GaN layer 2 and the n-type GaN layer 3 are formed before the GaN layer 4 is formed to raise the potential, the leakage of leakage current is suppressed as described above. be able to.

  Further, the thickness of the GaN layer 4 is preferably 30 μm or more. This is because when the thickness of the GaN layer 4 is less than 30 μm, polymerization of dislocations does not proceed sufficiently, and a large number of dislocations may occur in the active layer 5. And when many dislocations exist in the active layer 5, electron mobility will fall easily. Further, the thinner the GaN layer 4 is, the lower the handling property at the time of pick-up is.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment is different from the first embodiment in the method for manufacturing the HEMT 1. 6A to 6C are cross-sectional views showing a method of manufacturing a GaN-based HEMT (compound semiconductor device) mounting body according to the second embodiment in the order of steps.

  In the second embodiment, first, similarly to the first embodiment, processing up to the formation of the electrode layer 6 is performed (see FIG. 4A). Next, as shown in FIG. 6A, grooves 34 are formed in the electrode layer 6, the active layer 5, the GaN layer 4, the n-type GaN layer 3, and the p-type GaN layer 2 along the dicing line 33, and an undoped AlN layer is formed. 32 surfaces are partially exposed. In forming the groove 34, for example, dry etching using a resist pattern is performed. It is also possible to form mechanically by half-cut dicing. Before forming the groove 34, the back surface of the sapphire substrate 31 may be ground to make the sapphire substrate 31 thinner. The groove 34 may reach the middle of the AlN layer 32.

  Next, the sapphire substrate 31 and the like are immersed in, for example, hot phosphoric acid. As a result, as shown in FIG. 6B, the undoped AlN layer 32 is gradually removed from the exposed surface. When the AlN layer 32 disappears, the HEMT 1 is separated from the sapphire substrate 31 as shown in FIG. 6C.

  In this way, HEMT1 is obtained.

  Thereafter, in the same manner as in the first embodiment, each HEMT 1 is picked up with tweezers or the like and mounted on the mounting substrate 21 in the package using the paste 22 (see FIG. 4E).

  In this manner, the GaN-based HEMT mounting body shown in FIGS. 1 and 2 is also obtained by the second embodiment.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment is different from the first and second embodiments in the method for manufacturing the HEMT 1. 7A to 7E are cross-sectional views showing a method of manufacturing a GaN-based HEMT (compound semiconductor device) mounting body according to the third embodiment in the order of steps.

  In the third embodiment, first, similarly to the first embodiment, processing up to the formation of the electrode layer 6 is performed (see FIG. 4A). Next, as shown in FIG. 7A, a support substrate 41 is bonded onto the electrode layer 6 using an adhesive 42. For example, the thickness of the support substrate 41 is about 500 μm. The support substrate 41 is preferably transparent.

  Thereafter, the sapphire substrate 31 and the like are immersed in, for example, hot phosphoric acid. As a result, as shown in FIG. 7B, the undoped AlN layer 32 is gradually removed. When the AlN layer 32 disappears, as shown in FIG. 7C, a stacked body of the electrode layer 6, the active layer 5, the GaN layer 4, the n-type GaN layer 3, and the p-type GaN layer 2 supported by the support substrate 41. Is separated from the sapphire substrate 31.

  Subsequently, as shown in FIG. 7D, the support substrate 41 and the laminated body are cut along the dicing line 33 and subdivided into individual chip sizes (dicing). In this cutting, for example, a diamond saw or the like is used.

  Next, the adhesive force of the adhesive 42 is reduced using a solvent, and the HEMT 1 is separated from the support substrate 41 as shown in FIG. 7E.

  In this way, HEMT1 is obtained.

  Thereafter, in the same manner as in the first embodiment, each HEMT 1 is picked up with tweezers or the like and mounted on the mounting substrate 21 in the package using the paste 22 (see FIG. 4E).

  In this manner, the GaN-based HEMT mounting body shown in FIGS. 1 and 2 is also obtained by the third embodiment.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment is different from the first to third embodiments in the method for manufacturing the HEMT 1. 8A to 8C are cross-sectional views illustrating a method of manufacturing a GaN-based HEMT (compound semiconductor device) mounting body according to the fourth embodiment in the order of steps.

  In the fourth embodiment, first, similarly to the third embodiment, processing up to the adhesion of the support substrate 41 is performed (see FIG. 7A). Next, as shown in FIG. 8A, grooves 35 are formed in the sapphire substrate 31, the AlN layer 32, the p-type GaN layer 2, and the n-type GaN layer 3 along the dicing line 33. In forming the groove 35, for example, mechanical processing using a diamond saw or the like is performed. Before forming the groove 35, the back surface of the sapphire substrate 31 may be ground to make the sapphire substrate 31 thinner. The groove 35 may reach the middle of the GaN layer 4.

  Thereafter, the sapphire substrate 31 and the like are immersed in, for example, hot phosphoric acid. As a result, as shown in FIG. 8B, the undoped AlN layer 32 is gradually removed from the exposed surface. When the AlN layer 32 disappears, as shown in FIG. 8C, a stacked body of the electrode layer 6, the active layer 5, the GaN layer 4, the n-type GaN layer 3, and the p-type GaN layer 2 supported by the support substrate 41. Is separated from the sapphire substrate 31.

  Thereafter, as in the third embodiment, the HEMT 1 is obtained by performing segmentation and the like, and further, each HEMT 1 is picked up with tweezers or the like and packaged using the paste 22 as in the first embodiment. It is mounted on the mounting board 21 (see FIG. 4E).

  In this manner, the GaN-based HEMT mounting body shown in FIGS. 1 and 2 can be obtained also by the fourth embodiment.

(Fifth embodiment)
Next, a fifth embodiment will be described. In the fifth embodiment, a layer provided between the sapphire substrate 31 and the p-type GaN layer 2 is different from the fourth embodiment. FIG. 9 is a cross-sectional view illustrating a method for manufacturing a GaN-based HEMT (compound semiconductor device) mounting body according to the fifth embodiment.

  As shown in FIG. 9, in the fifth embodiment, instead of the undoped AlN layer 32 in the first to fourth embodiments, an InGaN layer 36 is used as a separation layer. The InGaN layer 36 can be removed by photoelectrochemical (PEC) etching. Therefore, in the fifth embodiment, the InGaN layer 36 is removed by photoelectrochemical etching instead of wet etching of the AlN layer 32 using hot phosphoric acid in the first to fourth embodiments. Other processes are the same as those in the first to fourth embodiments.

  Also according to the fifth embodiment, the GaN-based HEMT mounting body shown in FIGS. 1 and 2 can be obtained.

  In any of the embodiments, a silicon substrate, a SiC substrate, a GaN substrate, a GaAs substrate, or the like may be used instead of the sapphire substrate 31. In addition, these substrates may be conductive, semi-insulating, or insulating. Although the SiC substrate is expensive, the processing of the SiC substrate is not required in the second and third embodiments, and can be reused.

  Further, the structures of the gate electrode 11g, the source electrode 11s, and the drain electrode 11d are not limited to those of the above-described embodiment. For example, these may be composed of a single layer. Moreover, these formation methods are not limited to the lift-off method. Furthermore, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode 11s and the drain electrode 11d may be omitted. Further, heat treatment may be performed on the gate electrode 11g.

  Further, the thickness and material of each layer are not limited to those of the above-described embodiment. Further, as the HEMT structure, a MIS (metal insulator semiconductor) type may be adopted instead of the Schottky type.

  Next, a simulation performed by the present inventors will be described. In this simulation, the relationship between the thickness of the GaN layer and the high frequency characteristics was verified. FIG. 10A is a cross-sectional view showing a structure to be simulated, and FIG. 10B is a graph showing the result of the simulation.

  As shown in FIG. 10A, the simulation target includes the GaN layer 54, the electron transit layer 57, the electron supply layer 58, and the protective layer 59, the GaN layer 4, the electron transit layer 7 of the first embodiment, It is provided similarly to the electron supply layer 8 and the protective layer 9. Further, the gate electrode 61g, the source electrode 61s, the drain electrode 61d, and the SiN film 60 are provided similarly to the gate electrode 11g, the source electrode 11s, the drain electrode 11d, and the SiN film 10 of the first embodiment. The HEMT configured as described above is mounted on the mounting substrate 71 using the paste 72. Note that the resistivity of the mounting substrate 71 is 0.05 Ω · cm. This value is comparable to that of an n-type SiC substrate. The gate width is 36 mm.

  As shown in FIG. 10B, a high gain can be obtained if the thickness of the GaN layer 54 is 10 μm or more, and a high gain can be stably obtained if the thickness is 15 μm or more.

  Next, experiments conducted by the inventors will be described. In this experiment, the relationship between the thickness of the GaN layer and the crystallinity of the active layer was verified. FIG. 11 is a graph showing the results of the experiment. The vertical axis in FIG. 11 indicates the half-value width of X-ray diffraction from the (0002) plane of GaN, and the unit is arcsec. The full width at half maximum of X-ray diffraction varies depending on the density of dislocations present in the crystal. The smaller the dislocation, the narrower the full width at half maximum.

  As shown in FIG. 11, it was found that when the thickness of the GaN layer grown on the sapphire substrate is 30 μm or more, crystallinity equivalent to or higher than that of the GaN layer epitaxially grown on the SiC substrate can be obtained.

It is sectional drawing which shows the structure of the GaN-type HEMT (compound semiconductor device) mounting body which concerns on 1st Embodiment. 1 is a layout diagram showing a structure of a GaN-based HEMT according to a first embodiment. It is a band figure which shows the band structure of GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment. FIG. 4B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4A. 4B is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4B. 4C is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4C. 4D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 4D. 3 is a cross-sectional view showing a method for forming an active layer 5 and an electrode layer 6. FIG. It is sectional drawing which shows the formation method of the active layer 5 and the electrode layer 6 following FIG. 5A. 5B is a cross-sectional view illustrating a method for forming the active layer 5 and the electrode layer 6 following FIG. 5B. It is sectional drawing which shows the formation method of the active layer 5 and the electrode layer 6 following FIG. 5C. It is sectional drawing which shows the formation method of the active layer 5 and the electrode layer 6 following FIG. 5D. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 2nd Embodiment. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 6A. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 6B. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 3rd Embodiment. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7A. FIG. 7B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7B. 7C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7C. FIG. 7D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 7D. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 4th Embodiment. It is sectional drawing which shows the method of manufacturing the GaN-type HEMT which concerns on 4th Embodiment following FIG. 8A. FIG. 9B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the fourth embodiment, following FIG. 8B. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 5th Embodiment. It is a figure which shows the structure and result of the object of simulation. It is a figure which shows the result of experiment.

Explanation of symbols

1: HEMT
2: p-type GaN layer 3: n-type GaN layer 4: GaN layer 5: active layer 6: electrode layer 7: electron transit layer 8: electron supply layer 9: protective layer 10: SiN film 10a: opening 11d: drain electrode 11 g: Gate electrode 11 s: Source electrode 21: Mounting substrate 22: Paste 31: Sapphire substrate 32: AlN layer 33: Dicing line 34, 35: Groove 36: InGaN layer 41: Support substrate 42: Adhesive

Claims (7)

A first semiconductor layer of a first conductivity type;
A depleted second conductivity type second semiconductor layer formed on the first semiconductor layer;
A third semiconductor layer formed on the second semiconductor layer;
An active layer formed on the third semiconductor layer;
An electrode layer formed on the active layer;
I have a,
The first semiconductor layer is a p-type GaN layer;
It said second semiconductor layer, n-type GaN Sodea Rukoto compound wherein a.   The compound semiconductor device according to claim 1, wherein a thickness of the third semiconductor layer is 30 μm or more.   The compound semiconductor device according to claim 1, wherein the compound semiconductor device is mounted on a mounting substrate from the first semiconductor layer side. Before Symbol third semiconductor layer, a compound semiconductor device according to any one of claims 1 to 3, characterized in that an undoped GaN layer. The third semiconductor layer is an undoped GaN layer having a thickness of 30 μm or more;
The active layer is
An electron transit layer formed above the GaN layer;
An electron supply layer formed above the electron transit layer;
The compound semiconductor device according to claim 1, comprising: Forming a separation layer on the substrate;
Forming a first semiconductor layer of a first conductivity type on the separation layer;
Forming a depleted second conductivity type second semiconductor layer on the first semiconductor layer;
Forming a third semiconductor layer on the second semiconductor layer;
Forming an active layer on the third semiconductor layer;
Forming an electrode layer on the active layer;
Removing the separation layer;
I have a,
The first semiconductor layer is a p-type GaN layer;
Said second semiconductor layer, the manufacturing method of a compound semiconductor device comprising an n-type GaN Sodea Rukoto.   The method of manufacturing a compound semiconductor device according to claim 6, wherein an AlN layer or an InGaN layer is formed as the separation layer.

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