JP4635444B2 - Epitaxial wafer for field effect transistor - Google Patents

Description

  The present invention relates to an epitaxial wafer for a field effect transistor used in an electronic device such as a field effect transistor (FET) or a high electron mobility transistor (HEMT), and more particularly between a source and a drain electrode. The present invention relates to an epitaxial wafer for a field effect transistor with reduced leakage current.

  Field effect transistors such as FETs and HEMTs that use compound semiconductor crystals have higher electron mobility than silicon semiconductors, and therefore high-frequency equipment amplifiers that require high-speed operation and high efficiency such as mobile phones and satellite broadcast receivers. (See, for example, Patent Document 1).

  Such a field effect transistor is manufactured by growing a metal thin film on a semi-insulating GaAs substrate by a metal organic vapor phase epitaxy (hereinafter referred to as “MOVPE method”).

  In the MOVPE method, a group III organometallic source gas and a group V source gas are introduced into a reaction furnace as a mixed gas with a high-purity hydrogen carrier gas, and the source material is pyrolyzed near the substrate heated in the reaction furnace. A compound semiconductor crystal grows epitaxially on the substrate.

  FIG. 5 shows a structure of a double hetero type high electron mobility transistor (D-HEMT) having carrier supply layers above and below a conventional channel layer. This double hetero type high electron mobility transistor 1 includes a semi-insulating GaAs substrate 2 and first to third buffers made of a high resistance p-type conductive film formed on the semi-insulating GaAs substrate 2. A buffer layer 30 comprising layers 30a to 30c for suppressing deterioration of device characteristics due to residual impurities on the semi-insulating GaAs substrate 2, and first and second carrier supplies for generating free electrons and supplying electrons to the channel layer 6 First and second spacer layers 5 and 7 for preventing free electrons flowing through the channel layers 6 and n-type impurities of the first and second carrier supply layers 4 and 8 from being scattered, The channel layer 6 through which free electrons flow, the Schottky layer 9 that forms a Schottky junction, and the contact layer 10 that forms an ohmic junction with a source electrode and a drain electrode (not shown) are epitaxially formed. It is obtained by Shall growth.

  Table 3 shows details of these epitaxial layers.

  Here, the HEMT has high mobility that is less susceptible to ionized impurity scattering by forming a two-dimensional electron gas (2DEG) in the channel layer 6 adjacent to the first and second carrier supply layers 4 and 8. The electron is used.

Japanese Patent No. 3542216 (FIG. 3)

  However, in the case of an epitaxial wafer for a field effect transistor prepared by a conventional MOVPE method, the interface between the semi-insulating GaAs substrate and the epitaxial layer formed thereon, more precisely, the semi-insulating GaAs substrate and the buffer layer A low resistance conductive layer is formed at the interface. The reason why such a low resistance layer is formed is that Si is originally attached to the surface of the semi-insulating GaAs substrate, and this Si is taken into the crystal during the growth of the epitaxial crystal and becomes an n-type carrier. It is because it ends.

  When a field effect transistor is formed using an epitaxial wafer having a low resistance layer as described above, a leakage current is generated between the source electrode and the drain electrode through the conductive layer present at the interface between the epitaxial layer and the growth substrate (mirror wafer). There is a problem that the electrical characteristics of the transistor deteriorate.

  Accordingly, an object of the present invention is to provide an epitaxial wafer for a field effect transistor with reduced leakage current between the source and drain electrodes.

  In order to achieve the above object, the present invention provides a field effect transistor having a buffer layer on a semi-insulating GaAs substrate for suppressing deterioration of device characteristics due to residual impurities on the semi-insulating GaAs substrate and a channel layer through which free electrons flow. In the epitaxial wafer, the buffer layer includes a crystal layer (leakage current reducing layer) having a predetermined value in which the product of the carrier concentration and the layer thickness reduces the leakage current between the source and drain electrodes. An epitaxial wafer for a transistor is provided.

The predetermined value of the crystal layer is preferably 1.5 × 10 ¹¹ to 2.5 × 10 ¹¹ cm ⁻² .

The buffer layer preferably includes a p-AlGaAs layer having an Al composition ratio smaller than that of the p-AlGaAs crystal layer on the p-AlGaAs crystal layer .

It is preferable to provide a carrier supply layer in the upper layer and the lower layer of the channel layer .

The crystal layer is preferably Al _x Ga _1-x As (0.35 <x <1.0).

  The crystal layer preferably includes a total of three elements including any two elements of Al element, Ga element, and In element and any one element of As element or P element.

  The crystal layer preferably includes a total of four elements including an Al element, a Ga element, an In element, and an As element or a P element.

  According to the epitaxial wafer for a field effect transistor of the present invention, since the product of the carrier concentration and the layer thickness includes a crystal layer in a predetermined range in which the leakage current between the source and drain electrodes is reduced, the buffer layer includes the crystal layer. Since the leakage path can be canceled, the leakage current between the source and the drain can be reduced.

According to the epitaxial wafer for a field effect transistor of the present invention, the crystal layer in which the product of the carrier concentration and the thickness of the crystal having the carrier concentration is 6.0 × 10 ^{10 to} 4.0 × 10 ¹¹ cm ⁻² is provided. Therefore, since the crystal layer can cancel the leak path, the leak current between the source and the drain can be reduced.

  According to the epitaxial wafer for a field effect transistor of the present invention, since the crystal layer is formed in the buffer layer via another layer, the crystal layer can effectively cancel the leak path. The leakage current between the drains could be reduced.

  According to the epitaxial wafer for field effect transistor of the present invention, since the crystal layer is formed in contact with the semi-insulating GaAs substrate, the product of the carrier concentration and the thickness of the crystal having the carrier concentration is within a predetermined range. Since the crystal layer can cancel the leak path, the leak current between the source and the drain can be reduced.

According to the epitaxial wafer for field effect transistors of the present invention, since the crystal layer is Al _x Ga _1-x As (0.35 <x <1.0), the carrier concentration and the thickness of the crystal having the carrier concentration are Since the crystal layer has a crystal layer in a predetermined range, the crystal layer can cancel the leak path, so that the leak current between the source and the drain can be reduced.

  According to the epitaxial wafer for a field effect transistor of the present invention, the crystal layer is composed of any two elements of Al element, Ga element, and In element and any one element of As element or P element. Since it includes two elements, the product of the carrier concentration and the thickness of the crystal having the carrier concentration has a crystal layer having a predetermined range, so that the crystal layer can cancel the leak path, so that the leakage current between the source and drain is reduced. I was able to make it smaller.

  According to the epitaxial wafer for a field effect transistor of the present invention, the crystal layer contains a total of four elements of Al element, Ga element and In element, and any one element of As element or P element. And the thickness of the crystal having the carrier concentration have a crystal layer in a predetermined range, so that the crystal layer can cancel the leak path, so that the leak current between the source and the drain can be reduced.

  FIG. 1 shows a structure of a double hetero type high electron mobility transistor (D-HEMT) according to an embodiment of the present invention. The double hetero type high electron mobility transistor 1 includes a semi-insulating GaAs substrate 2 and first to fourth layers made of a high resistance p-type conductive film formed on the semi-insulating GaAs substrate 2. A buffer layer 3 comprising buffer layers 3a to 3d, which suppresses deterioration of device characteristics due to residual impurities on the semi-insulating GaAs substrate 2, and first and second carrier supplies for generating free electrons and supplying electrons to the channel layer 6 First and second spacer layers 5 and 7 for preventing free electrons flowing through the channel layers 6 and n-type impurities of the first and second carrier supply layers 4 and 8 from being scattered, A channel layer 6 through which free electrons flow, a Schottky layer 9 that forms a Schottky junction, and a contact layer 10 that forms an ohmic junction with a source electrode and a drain electrode (not shown) are respectively epitaxy. It is obtained by Le growth.

The difference from the conventional example is that the buffer layer 3 has p-type conductivity in carrier concentration (Np, unit is cm ⁻³ ) and the thickness of the crystal having the carrier concentration (unit is nm = 10 ⁻⁷ cm) The second buffer layer 3b having a product (Nd product) of 6.0 × 10 ^{10 to} 4.0 × 10 ¹¹ cm ⁻² is formed. The first buffer layer 3a, the first buffer layer 30a of the conventional example, the third buffer layer 3c, the second buffer layer 30b of the conventional example, and the fourth buffer layer 3d and the first buffer layer of the conventional example. 3 buffer layers 30c correspond to each other, and are formed with the same composition, the same carrier concentration, and the same layer thickness (layer thickness).

  Here, the D-HEMT is less susceptible to ionized impurity scattering by forming a two-dimensional electron gas (2 DEG) in the channel layer 6 adjacent to the first and second carrier supply layers 4 and 8. It uses mobility electrons.

  According to this embodiment, by including a layer having a certain range of Nd product in the buffer layer 3, this layer can cancel the leakage path, so that the leakage current between the source and the drain can be reduced. did it.

FIG. 2 shows a MOVPE apparatus. The MOVPE apparatus 20 includes a reaction furnace 21 connected to an exhaust unit 26 equipped with a vacuum pump and an exhaust device (not shown), a susceptor 22 on which a substrate 27 is placed, a heater 23 that heats the susceptor 22, A control shaft 24 that rotates and moves the susceptor 22 up and down, a quartz nozzle 25 that supplies a source gas obliquely or horizontally toward the substrate 27, a TMG (trimethylgallium) gas generator 31 that generates Ga, and Al is generated. TMA (trimethylaluminum) gas generating device 32, AsH ₃ gas generating device 33 generating As, TMI (trimethylindium) gas generating device 34 generating In, and disilane generating Si for doping Si (Si ₂ H ₆ ) gas generator 35 and the like are provided. In addition, you may increase / decrease the number of gas generators as needed. NH ₃ is used as a nitrogen source, and H ₂ is used as a carrier gas. The raw material gas combination is changed depending on the metal to be grown.

  In order to form a thin film by the MOVPE apparatus 20, for example, the following is performed. First, the substrate 27 is held by the susceptor 22 with the surface on which the thin film is formed facing upward, and is installed in the reaction furnace 21. The substrate 27 is kept at a predetermined temperature by the heater 23, and the group III organometallic source gas and the group V source gas are introduced into the reaction furnace 21 as a mixed gas of high-purity hydrogen carrier gas. In the introduced mixed gas, the source gas was thermally decomposed in the vicinity of the heated substrate 27, and crystals having various compositions were epitaxially grown on the substrate 27.

  Table 1 shows details of the epitaxial layer formed on the semi-insulating GaAs substrate 2 of the D-HEMT produced in this example. “No.” indicates the order of epitaxial growth on the semi-insulating GaAs substrate 2. n-, p- and un- indicate that the crystal is n-type conductive, p-type conductive and semi-insulating, respectively.

In the examples, no. As a first layer, a first buffer layer 3a made of p-GaAs is grown by 250 nm. A second buffer layer 3b made of p-Al _0.38 Ga _0.62 As is formed as a leakage current reducing layer. The leakage current reducing layer exhibits p-type conductivity, and has a carrier concentration of 2.5 × 10 ¹⁷ cm ⁻³ , a thickness of 10 nm, (Nd product: 2.5 × 10 ¹¹ cm ⁻² ). Thereafter, the layers shown in Table 1 were grown. The conventional example is the same except for the presence or absence of the second buffer layer 3b until the substrate used, the growth conditions, and the state in the reactor are reached.

After the growth, the two epitaxial wafers were simultaneously subjected to a simple process, a sample for leak current measurement was prepared, and the leak current between the source and drain was measured.
FIG. 3 shows the measurement results.

In the structure of Table 1, the Nd product was changed and the leakage current between the source and the drain was measured.
FIG. 4 is a graph comparing the leak current values between the source and the drain when 15 V is applied while changing the Nd product. Here, the value when the Nd product = 0 is a value when the leakage current reducing layer in the embodiment of the present invention is not grown (conventional example).

  Further, when the Nd product is made constant and the position of the leakage current reducing layer is inserted in the middle of the buffer layer, it is inserted in the lowermost part of the buffer layer (immediately above the semi-insulating GaAs substrate) and in the uppermost part of the buffer layer. The case of insertion was compared.

  Table 2 shows the result of comparing the leak current values between the source and drain when a voltage of 15 V is applied.

According to the epitaxial wafer for field effect transistors of this example, the leakage current was reduced by an order of magnitude or more compared to the conventional product. In addition, there was no sudden rise when applying voltage. For this reason, it can be said that the lower the leakage current value, the more effective the leakage current reducing layer of the present invention. Thereby, it can be seen that the Nd product is effective in the range of 6.0 × 10 ^{10 to} 4.0 × 10 ¹¹ cm ⁻² . The effect when the leakage current reducing layer is inserted in the middle of the buffer layer and the case where it is inserted at the bottom are almost the same, but when it is inserted at the top of the buffer layer, the effect cannot be expected so much. Therefore, the effect can be obtained regardless of where it is inserted in the buffer layer, but in order to obtain a greater effect, it can be seen that it is better to insert it in the lowermost part of the buffer layer or in the middle of the buffer layer.

  Note that the present invention can be applied to all field effect transistors having a buffer layer.

It is sectional drawing which shows the structure of D-HEMT which concerns on embodiment of this invention. It is a figure which shows the MOVPE apparatus for manufacturing D-HEMT of embodiment of this invention. It is a figure which shows the leakage current measurement result between the source-drain of D-HEMT of the Example of this invention. It is a figure which shows the relationship between the Nd product in D-HEMT of the Example of this invention, and the leakage current between source-drain. It is sectional drawing which shows the structure of the conventional D-HEMT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Double hetero type high electron mobility transistor 2 Semi-insulating GaAs substrate 3 Buffer layer 3a 1st buffer layer 3b 2nd buffer layer 3c 3rd buffer layer 3d 4th buffer layer 4 1st carrier supply layer 5 First spacer layer 6 Channel layer 7 Second spacer layer 8 Second carrier supply layer 9 Schottky layer 10 Contact layer 20 MOVPE apparatus 21 Reactor 22 Susceptor 23 Heater 24 Control shaft 25 Quartz nozzle 26 Exhaust part 27 Substrate 30 buffer layer 30a first buffer layer 30b second buffer layer 30c third buffer layer 31 TMG gas generator 32 TMA gas generator 33 AsH ₃ gas generator 34 TMI gas generator 35 disilane gas generator

Claims (7)

In an epitaxial wafer for a field effect transistor having a semi-insulating GaAs substrate, a buffer layer formed on the semi-insulating GaAs substrate, and a channel layer formed on the buffer layer and through which free electrons flow .
The buffer layer includes a p-GaAs layer and a p-AlGaAs crystal layer from the semi-insulating GaAs substrate side. The p-AlGaAs crystal layer has a product of carrier concentration and layer thickness of 1.5 × 10 ^11. An epitaxial wafer for a field effect transistor, characterized in that it is ˜2.5 × 10 ¹¹ cm ⁻² . 2. The field effect transistor epitaxial wafer according to claim 1, wherein the buffer layer includes a p-AlGaAs layer having an Al composition ratio smaller than that of the p-AlGaAs crystal layer on the p-AlGaAs crystal layer. . The field effect transistor epitaxial wafer according to claim 1 , further comprising a carrier supply layer in an upper layer and a lower layer of the channel layer . 2. The epitaxial wafer for a field effect transistor according to claim 1, wherein the p-AlGaAs crystal layer has the carrier concentration of 2.5 × 10 ¹⁷ cm ⁻³ and the layer thickness of 10 nm . 2. The epitaxial wafer for a field effect transistor according to claim 1, wherein the crystal layer is made of Al _x Ga _1-x As (0.35 <x <1.0).   2. The crystal layer includes a total of three elements including any two elements of an Al element, a Ga element, and an In element and any one element of an As element or a P element. The epitaxial wafer for field effect transistors as described.   2. The epitaxial wafer for a field effect transistor according to claim 1, wherein the crystal layer includes a total of four elements including an Al element, a Ga element, an In element, and an As element or a P element.

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