JP5604596B2 - DC / DC converter - Google Patents

Description

  The present invention relates to a DC / DC converter that converts a DC voltage into another DC voltage.

  As a DC / DC converter control system, a PWM (Pulse Width Modulation) system using a feedback function is widely used. By utilizing the feedback function, the ratio between the on time and the off time of the switching element is automatically determined according to the value of the input voltage, and the output voltage can be made to exactly match the expected value.

  However, in feedback control, it is necessary to use an amplifier with a high gain, so that oscillation may occur. Since the oscillation conditions vary depending on the output load current, output load capacity, etc., it is necessary to carefully add an oscillation prevention circuit according to the usage conditions. It is very difficult for users who are unfamiliar with oscillation prevention.

  As another problem, since the output voltage is set by feedback, it takes time until the ratio of the on time to the off time becomes an optimum value. For this reason, it takes time to become stable when the input voltage or the output voltage fluctuates.

  In order to improve the reactivity, a method for feedforward control of a DC / DC converter is also widely used. For example, MK Kazimierczuk et al. Disclose a feedforward control circuit applied to a PWM boost converter (Patent Document 1 (US Pat. No. 5,982,156) and Non-Patent Document 1 (MK Kazimierczuk and A. Massarini, “ Feedforward control of DC / DC PWM boost converter, "IEEE Transactions on Circuits and Systems, Part I, vol. 44, no. 2, pp.143-148, February 1997)).

  In the feedforward control circuit proposed by M. K. Kazimierczuk et al., A triangular wave having a constant peak voltage and a constant period is input to the non-inverting input terminal of the comparator. A divided voltage obtained by dividing the input voltage of the boost converter is input to the inverting input terminal of the comparator. The output voltage of the comparator is input to the gate of the switching element. At this time, when the output voltage of the comparator is at a high level, the switching element is turned on.

MK Kazimierczuk et al. Also discloses a case where a similar feedforward control circuit is applied to a PWM step-down converter (Non-Patent Document 2 (MK Kazimierczuk and AJ Edstrom, “Open-loop peak voltage feedforward control of a PWM buck converter, ”IEEE Transactions on Circuits and Systems, Part I, Vol. 47, pp.740-746, May 2000)). In the feedforward control circuit described in Non-Patent Document 2, a constant voltage is input to the non- inverting input terminal of the comparator, the peak voltage is proportional to the input voltage of the step-down converter, and the cycle is applied to the inverting input terminal of the comparator. A constant triangular wave is input. The output voltage of the comparator is input to the gate of the switching element. At this time, when the output voltage of the comparator is at a high level, the switching element is turned on.

US Pat. No. 5,982,156

M. K. Kazimierczuk and A. Massarini, "Feedforward control of DC / DC PWM boost converter," IEEE Transactions on Circuits and Systems, Part I, vol. 44, no. 2, pp.143-148, February 1997 M. K. Kazimierczuk and A. J. Edstrom, “Open-loop peak voltage feedforward control of a PWM buck converter,” IEEE Transactions on Circuits and Systems, Part I, Vol. 47, pp.740-746, May 2000

  By the way, when a low voltage such as the output of a solar cell or a fuel cell is boosted by a DC / DC converter, the ratio of the on time Ton and the off time Toff of the switching element (hereinafter referred to as “Ton / Toff ratio”). Becomes larger. In such a case, when the PWM method described in the above-mentioned document is used, the OFF time Toff itself is shortened, so that there is a problem that the variation of the set Ton / Toff ratio becomes large.

  An object of the present invention is to improve the setting accuracy of the Ton / Toff ratio in a DC / DC converter using feedforward control.

  A DC / DC converter according to an embodiment of the present invention includes a conversion circuit and a control circuit. The conversion circuit includes a switching element, and converts the input DC voltage into a DC voltage having a magnitude corresponding to the ratio between the ON time and the OFF time of the switching element and outputs the converted DC voltage. Here, the switching element is turned off when the on signal is deactivated, and is turned on when the off signal is deactivated. The control circuit controls on / off of the switching element. Specifically, the control circuit includes an on signal generation unit that generates an on signal and an off signal generation unit that generates an off signal. The on signal generation unit activates the on signal from the time when the off signal is deactivated until the time corresponding to the on time determined according to the magnitude of the input DC voltage elapses. . The off signal generation unit activates the off signal from when the on signal is deactivated until a time corresponding to the off time determined according to the magnitude of the input DC voltage elapses. .

  According to the above embodiment, the on time and the off time are individually set by the on signal generation circuit and the off signal generation circuit. For this reason, since ON time and OFF time can be adjusted according to an input voltage level, the setting precision of Ton / Toff ratio can be raised.

1 is a circuit diagram showing a configuration of a DC / DC converter 1 according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the pulse generator PG of FIG. FIG. 3 is a circuit diagram showing an example of the configuration of one-shot pulse generators 50A and 50B in FIG. FIG. 4 is a circuit diagram illustrating an example of a configuration of a delay circuit 51 in FIG. 3. FIG. 4 is a timing diagram showing voltage waveforms at various parts in FIG. 3. FIG. 3 is a timing diagram showing voltage waveforms at various parts in FIG. 2. FIG. 2 is a waveform diagram of a clock signal clk when the Ton / Toff ratio is fixed in the DC / DC converter 1 of FIG. 1. It is a figure for demonstrating the inductor current in the case of a boost converter. It is a figure for demonstrating the method to determine ON time Ton and OFF time Toff using a triangular wave. 2 is a circuit diagram showing a configuration of a general triangular wave generation circuit 900. FIG. It is a circuit diagram which shows the structure of the DC / DC converter 2 as a modification of the DC / DC converter 1 of FIG. FIG. 12 is a circuit diagram illustrating an example of the configuration of the non-overlap circuit 100 of FIG. 11. FIG. 13 is a timing chart showing voltage waveforms of respective parts of the circuit of FIG. 12. It is a circuit diagram which shows the structure of the pulse generator PGA applied to the DC / DC converter by Embodiment 2 of this invention. It is a circuit diagram which shows an example of a structure of OTA120 of FIG. It is a circuit diagram which shows the structure of the DC / DC converter 200 by Embodiment 3 of this invention. It is a circuit diagram which shows the structure of the control circuit 220 of FIG. 3 is a circuit diagram showing a configuration example of a maximum voltage selection circuit 240. FIG. FIG. 18 is a diagram for explaining the operation of the control circuit of FIG. 17. It is a circuit diagram which shows the structure of the pulse generator PGB of FIG. It is a circuit diagram which shows the structure of the DC / DC converter 3 by Embodiment 4 of this invention. It is a circuit diagram which shows the structure of the pulse generator PGC of FIG. FIG. 22 is a waveform diagram of a clock signal when the Ton / Toff ratio is fixed in the DC / DC converter 3 of FIG. 21. It is a figure for demonstrating the inductor current in the case of a step-down converter. It is a circuit diagram which shows the structure of the pulse generator PGD applied to the DC / DC converter by Embodiment 5 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Configuration of DC / DC Converter 1]
FIG. 1 is a circuit diagram showing a configuration of a DC / DC converter 1 according to Embodiment 1 of the present invention. DC / DC converter 1 is a boost converter that boosts voltage Vin (for example, 1V to 2V) input to input node 15 and outputs boosted voltage Vout (for example, 3V) from output node 16.

  As shown in FIG. 1, the DC / DC converter 1 includes a conversion circuit (boost chopper) 10, a control circuit 20, a current sensor 30, and a voltage divider that divides the voltage Vout of the output node 16 by resistance elements 31A and 31B. Circuit 31. The input node 15 is connected to a DC power source 9 such as a solar battery cell, and the output node 16 is connected to a load (load current Iload) via a PMOS (Positive-channel Metal Oxide Semiconductor) transistor pps as a power switch. The power supply voltage of the control circuit 20 is supplied from the output node 16 (hereinafter also referred to as “power supply node VDD”).

(Configuration and operation of conversion circuit 10)
The conversion circuit 10 includes an inductor 11, a diode 12, an NMOS (Negative-channel Metal Oxide Semiconductor) transistor n_dr as a switching element, and a capacitor 13. Inductor 11 and diode 12 are connected in series between input node 15 and output node 16 in this order. NMOS transistor n_dr is connected between connection node 14 of inductor 11 and diode 12 and ground node GND. Capacitor 13 is connected between output node 16 and ground node GND.

  In order to make the output voltage Vout higher than the input voltage Vin, it is necessary to prevent the backflow from the output node 16 to the inductor 11 while supplying the current of the inductor 11 to the output node 16. There are two rectification methods: diode rectification and synchronous rectification. FIG. 1 shows a configuration example of a diode rectification method. The diode 12 is connected so that the direction from the connection node 14 to the output node 16 is the forward direction, thereby preventing a reverse current flow. The synchronous rectification method will be described with reference to FIG.

  Boosting is performed as follows. When the NMOS transistor n_dr is turned on, a current flows through the inductor 11. Next, the NMOS transistor n_dr is turned off. In the diode rectification method, this inductor current is supplied to the output node 16 via the diode 12. The NMOS transistor n_dr is turned on / off repeatedly.

When the on time is Ton, the off time is Toff, and the inductance of the inductor 11 is L, the increase ΔIon of the current flowing through the inductor 11 during the NMOS transistor n_dr is on is:
ΔIon ＝ Vin ・ Ton / L… (1)
It is expressed as The decrease ΔIoff of the current flowing through the inductor 11 during the period when the NMOS transistor n_dr is off is:
ΔIoff ＝ (Vout−Vin) ・ Toff / L… (2)
It is expressed as However, in the above formulas (1) and (2), the forward voltage drop of the diode 12 and the voltage drop due to parasitic resistance were ignored. In the steady state, the inductor current ΔIon increased during the ON period cancels out the decrease ΔIoff during the OFF period. That is, since ΔIon = ΔIoff, the ratio of on time to off time (Ton / Toff) is
Ton / Toff = Vout / Vin −1 (3)
Stable at a ratio of.

(Schematic configuration of the control circuit 20)
The control circuit 20 is a circuit for controlling the on-time and off-time of the NMOS transistor n_dr, and has a circuit configuration that automatically sets the Ton / Toff ratio from the input voltage Vin by feedforward control. As a result, power efficiency can be improved without generating unnecessary current. The control circuit 20 further has a function of stopping switching of the NMOS transistor n_dr when the inductor current is an overcurrent and when the output voltage Vout exceeds the expected value Vout *.

  Specifically, as shown in FIG. 1, the control circuit 20 includes a pulse generator PG, comparators CMP <b> 1 and CMP <b> 2, an overcurrent protection circuit 22, and an AND gate 21.

  The pulse generator PG determines the on time Ton and the off time Toff based on the input voltage Vin so that the output voltage Vout is substantially equal to the expected value Vout *. Then, the pulse generator PG outputs a clock signal clk that becomes a high level (H level) and a low level (L level) during the determined on time Ton and off time Toff. Details of the pulse generator PG will be described later with reference to FIG.

  The comparator CMP1 compares the reference voltage Vref with the divided voltage Vout2 output from the voltage dividing circuit 31, and outputs a signal that becomes L level when the divided voltage Vout2 exceeds the reference voltage Vref. The reference voltage Vref is given by α × Vout * using the voltage division ratio α of the voltage dividing circuit 31 and the expected value Vout * of the output voltage.

  Note that the voltage dividing ratio of the voltage dividing circuit 31 is expressed by using the resistance values R1 and R2 of the resistance elements 31A and 31B constituting the voltage dividing circuit 31. The partial pressure ratio α is equal to R1 / (R1 + R2).

  The overcurrent protection circuit 22 includes a current detection circuit 23, PMOS transistors 24 and 25, and a resistance element 26. The current detection circuit 23 detects a current (inductor current IL) flowing through the NMOS transistor n_dr using the current sensor 30. The output current Id of the current detection circuit 23 is copied by a current mirror composed of PMOS transistors 24 and 25 and supplied to the resistance element 26.

  The comparator CMP2 compares the reference voltage Vref with the voltage applied to the resistance element 26 of the overcurrent protection circuit 22, and outputs a signal that becomes L level when the voltage of the resistance element 26 exceeds the reference voltage Vref. The voltage applied to the resistance element 26 is given by Id × Rmx using the output current Id of the current detection circuit 23 and the resistance value Rmx of the resistance element 26.

  In FIG. 1, for the sake of simplicity, the reference voltage Vref input to the comparator CMP1 and the reference voltage Vref input to the comparator CMP2 are the same, but they may be different. It is necessary to adjust the voltage dividing ratio α of the voltage dividing circuit 31 (that is, the ratio between the resistance values R1 and R2 of the resistance elements 31A and 31B) according to the value of the reference voltage Vref input to the comparator CMP1. Similarly, it is necessary to adjust the resistance value Rmx of the resistance element 26 in accordance with the value of the reference voltage Vref input to the comparator CMP2.

  The AND gate 21 outputs a logical product of the clock signal clk output from the pulse generator PG, the output of the comparator CMP1, and the output of the comparator CMP2 to the gate of the NMOS transistor n_dr as the clock signal clk_dr.

[Detailed configuration of pulse generator PG]
FIG. 2 is a circuit diagram showing a configuration of the pulse generator PG of FIG. Referring to FIG. 2, pulse generator PG includes voltage / current converter 60, current signal generator 70, on signal generator 40A, off signal generator 40B, inverters 91 and 92, and RS latch. Circuit 90.

(Configuration of voltage / current converter 60)
The voltage / current converter 60 generates a conversion current Ia having a current value proportional to the input voltage Vin.

  Specifically, as shown in FIG. 2, the voltage / current converter 60 includes a differential amplifier 61, an NMOS transistor 62, and a resistance element 63. The NMOS transistor 62 and the resistance element 63 are connected in series between the output node 64 of the voltage / current conversion unit 60 and the ground node GND in this order. The input voltage Vin is input to the non-inverting input terminal of the differential amplifier 61. An inverting input terminal of the differential amplifier 61 is connected to a connection node between the NMOS transistor 62 and the resistance element 63.

According to the configuration of the voltage / current converter 60 described above, when the resistance value of the resistance element 63 is Rs, the conversion current Ia is
Ia ＝ Vin ／ Rs… (4)
Determined by.

(Configuration of current signal generator 70)
Based on the constant current Ics having a constant current value and the conversion current Ia, the current signal generation unit 70 is configured to determine whether the first current signal I1 and the first current signal I1 increase in current value as the input voltage Vin increases. A second current signal I2 having different dependency on the input voltage Vin is generated. The first current signal I1 is supplied to the on signal generator 40A, and the second current signal I2 is supplied to the off signal generator 40B.

In the case of a control circuit for a boost converter, the first current signal I1 is
I1 = Ia (5)
The second current signal I2 is given by
I2 ＝ Ics−Ia (6)
Given in.

  Specifically, as shown in FIG. 2, the current signal generation unit 70 includes PMOS transistors 71, 72, and 73 that form a current mirror, NMOS transistors 74 and 75 that form a current mirror, a constant current generation unit 80, and the like. including.

  The conversion current Ia flowing through the output node 64 of the voltage / current conversion unit 60 is copied by the current mirror circuit as the first current signal I 1 that is the drain current of the PMOS transistor 72. Further, the conversion current Ia is copied as the drain current of the NMOS transistor 75 connected to the output node 84 of the constant current generator 80.

  The constant current generator 80 includes a constant current source 81 that generates a constant current Ics, and PMOS transistors 82 and 83. The constant current Ics is copied by a current mirror circuit configured by the PMOS transistors 82 and 83 and output from the constant current generation unit 80. The second current signal I2 that is finally supplied from the output node 84 to the off signal generation unit 40B is given by the above-described equation (6).

(Schematic configuration of the ON signal generator 40A and the OFF signal generator 40B)
The on signal generation unit 40A generates an on signal Son based on the first current signal I1. The off signal generation unit 40B generates an off signal Soff based on the second current signal I2. In the case of FIG. 1, the ON signal Son and the OFF signal Soff are L active signals that are activated when they are at the L level.

  More specifically, the ON signal generation unit 40A is determined according to the magnitude of the input voltage Vin from when the OFF signal Soff is received and the OFF signal Soff is deactivated (switched to the H level). Until the time (corresponding to the ON time Ton) elapses, the ON signal Son is set in the active state (L level). The off signal generation unit 40B receives the on signal Son, and the time determined according to the magnitude of the input voltage Vin (off time Toff from when the on signal Son is deactivated (switched to the H level)). The off signal Soff is kept in an active state (L level) until the time elapses). The NMOS transistor n_dr constituting the conversion circuit 10 of FIG. 1 is turned off when the on signal Son is deactivated (switched to H level), and the off signal Soff is deactivated (switched to H level). ) To turn it on.

(Detailed configuration of ON signal generation unit 40A)
Specifically, as illustrated in FIG. 2, the ON signal generation unit 40A includes a charging circuit 41A and a comparison circuit 45A.

  The charging circuit 41A is charged by the first current signal I1, and the charging voltage is reset when the off signal Soff is deactivated (switched to the H level). More specifically, the charging circuit 41A includes a one shot pulse generator 50A that receives an off signal Soff, a capacitor 44A that is charged by the first current signal I1, and an NMOS transistor that is connected in parallel with the capacitor 44A. n1. The one-shot pulse generator 50A generates a pulse that is at the H level for a predetermined time when the off signal Soff is switched to the H level. The pulse generated by the one-shot pulse generator 50A is input to the gate of the NMOS transistor n1, and the NMOS transistor n1 is turned on for a predetermined time. When the NMOS transistor n1 is turned on, the voltage of the capacitor 44A is discharged (reset).

  The comparison circuit 45A includes a comparator 42A and an inverter 43A that inverts the output of the comparator 42A and outputs it as an ON signal Son. The comparator 42A compares the reference voltage Vref with the charging voltage of the capacitor 44A, and outputs an L level signal when the charging voltage of the capacitor 44A exceeds the reference voltage Vref. When the output of the comparison circuit 45A becomes L level, the ON signal Son is inactivated (H level).

(Detailed configuration of the off signal generation unit 40B)
The configuration of the off signal generation unit 40B is the same as the configuration of the on signal generation unit 40A. That is, the off signal generation unit 40B includes a charging circuit 41B and a comparison circuit 45B.

  The charging circuit 41B is charged by the second current signal I2, and the charging voltage is reset when the ON signal Son is deactivated (switched to H level). More specifically, the charging circuit 41B includes a one-shot pulse generator 50B that receives the ON signal Son, a capacitor 44B that is charged by the second current signal I2, and an NMOS transistor n2 that is connected in parallel with the capacitor 44B. The one-shot pulse generator 50B generates a pulse that is at the H level for a predetermined time when the ON signal Son is switched to the H level. The pulse generated by the one-shot pulse generator 50B is input to the gate of the NMOS transistor n2, and the NMOS transistor n2 is turned on for a predetermined time. When the NMOS transistor n2 is turned on, the voltage of the capacitor 44B is discharged (reset).

  The comparison circuit 45B includes a comparator 42B and an inverter 43B that inverts the output of the comparator 42B and outputs it as an off signal Soff. The comparator 42B compares the reference voltage Vref and the charging voltage of the capacitor 44B, and outputs an L level signal when the charging voltage of the capacitor 44B exceeds the reference voltage Vref. When the output of the comparison circuit 45B becomes L level, the off signal Soff is deactivated (becomes H level).

  The reference voltage Vref input to the comparators 42A and 42B is the same as the reference voltage Vref input to the comparators CMP1 and CMP2 in FIG. 1 for simplicity, but may be different. The reference voltage Vref input to the comparator 42A and the reference voltage Vref input to the comparator 42B may differ in principle, but they are equal to increase the setting accuracy of the on time Ton and the off time Toff. It is desirable to set.

(Example of the configuration of the one-shot pulse generators 50A and 50B)
FIG. 3 is a circuit diagram showing an example of the configuration of the one-shot pulse generators 50A and 50B in FIG. Referring to FIG. 3, each of one-shot pulse generators 50 </ b> A and 50 </ b> B includes a delay circuit 51, an inverter 52, and an AND gate 53. A signal from the input node IN1 is input to the first input terminal of the AND gate 53, and sequentially passes through the delay circuit 51 and the inverter 52 and is input to the second input terminal of the AND gate 52.

  FIG. 4 is a circuit diagram showing an example of the configuration of the delay circuit 51 of FIG. Referring to FIG. 4, delay circuit 51 includes inverters 54A, 54B, 54C, 54D connected in series between input node IN2 and output node OUT2, and each connection node of these inverters and ground node GND. And capacitors 55A, 55B, and 55C connected therebetween.

  FIG. 5 is a timing diagram showing voltage waveforms at various parts in FIG. The timing diagram of FIG. 5 shows, in order from the top, the voltage waveform of the input node IN1 of the one-shot pulse generator, the voltage waveform of the output node IN_d of the inverter 52, and the voltage waveform of the output node OUT1 of the one-shot pulse generator. Yes.

  As shown in FIG. 5, the voltage at the output node IN_d of the inverter 52 falls at time t2 delayed by the delay time of the delay circuit 51 from the rise time t1 of the voltage at the input node IN1. The voltage at the output node IN_d of the inverter 52 rises at time t4 delayed by the delay time of the delay circuit 51 from the time t3 when the voltage at the input node IN1 falls. As a result, a pulse that becomes H level between time t1 and time t2 is generated at the output node OUT1 of the one-shot pulse generator. Thus, the pulse width of the pulses generated by the one-shot pulse generators 50A and 50B can be determined by the delay value of the delay circuit 51.

(Regarding the RS latch circuit 90)
Referring again to FIG. 2, the ON signal Son is inverted and input to the set terminal S of the RS latch circuit 90 by the inverter 91, and the OFF signal is input to the reset terminal R of the RS latch circuit 90 by the inverter 92. Inverted and input. As a result, from the output terminal Q of the RS latch circuit, the clock signal clk which becomes H level when the ON signal Son is in the active state (L level) and L level when the OFF signal Soff is in the active state (L level). Is output.

[Operation of DC / DC Converter 1]
Next, the operation of the DC / DC converter 1 having the above configuration will be described. Referring to FIG. 2, the period during which the ON signal Son is at the L level is the ON period of the NMOS transistor n_dr. Therefore, the ON time Ton is defined by the capacitance value of the capacitor 44A as C1.
Ton = C1 / Vref / I1 = C1 / Vref / Ia = C1 / Vref / Rs / Vin (7)
It is expressed as On the other hand, since the period during which the off signal Soff is at the L level is the off period of the NMOS transistor n_dr, the off time Toff is defined by the capacitance value of the capacitor 44B as C2.
Toff = C2 / Vref / I2 = C2 / Vref / (Ics-Ia) = C2 / Vref / Rs / (Ics / Rs-Vin) (8)
It can be expressed as From these equations
Ton / Toff = C1 ・ (Ics ・ Rs / Vin −1) / C2 (9)
Is obtained. Therefore,
C1 = C2 (10)
Ics ・ Rs ＝ Vout ＊ （expected value）… (11)
If the capacitance values C1 and C2 of the capacitors 44A and 44B, the constant current Ics output from the constant current source 81, and the resistance value Rs of the resistance element 63 are set so that Therefore, the desired Ton / Toff ratio can be obtained.

  FIG. 6 is a timing diagram showing voltage waveforms at various parts in FIG. The timing chart of FIG. 6 shows the voltage Von of the capacitor 44A, the on signal Son, the gate voltage VG (n2) of the transistor n2, the voltage Voff of the capacitor 44B, the off signal Soff, and the gate voltage VG (n1) of the transistor n1 in order from the top. ).

  2 and 6, the capacitor 44A is charged with the first current signal I1 (= Ia). When the voltage Von of the capacitor 44A reaches the reference voltage Vref at time t1, the on signal Son changes to a high level. At the same time, the pulse generated from the one-shot pulse generator 50B causes the gate voltage VG (n2) of the NMOS transistor n2 to rise for a predetermined time until time t2. As a result, the voltage Voff of the capacitor 44B is discharged to the ground voltage level.

  The capacitor 44B is charged with the second current signal I2 (= Ics−Ia). When the voltage Voff of the capacitor 44B reaches the reference voltage Vref at time t3, the off signal Soff changes to a high level. At the same time, the pulse generated from the one-shot pulse generator 50A causes the gate voltage VG (n1) of the NMOS transistor n1 to rise for a predetermined time until time t4. As a result, the voltage Von of the capacitor 44A is discharged to the ground voltage level. After time t5, the operation from time t1 is repeated. The on time Ton corresponds to the L level period of the on signal Son, and the off time Toff corresponds to the L level period of the off signal Soff.

[Effect of Embodiment 1]
(1. No risk of oscillation)
According to the DC / DC converter 1 of the first embodiment, since the Ton / Toff ratio can be determined from the input voltage Vin without feedback, there is no concern about oscillation. External elements such as oscillation prevention capacitors and resistors are not required.

(2. High efficiency)
Furthermore, according to the DC / DC converter 1, it is possible to shorten the transition time to the stable state with respect to the change of the input / output voltage and to obtain the maximum power efficiency corresponding to the input voltage Vin. Hereinafter, a description will be given in contrast to a case where the Ton / Toff ratio is fixed without being adjusted according to the input voltage Vin.

When the Ton / Toff ratio is fixed, it is necessary to set the Ton / Toff ratio to the largest value so that the voltage can be boosted under the lowest input voltage Vin. When the input voltage range is 1V to 2V and the output voltage is 3V, the condition with the largest Ton / Toff ratio is
Ton / Toff = 3V / 1V-1 = 2 (12)
It becomes. When the cycle of the clock signal clk is 1 μs, Ton = 0.67 μs and Toff = 0.33 μs are set.

  FIG. 7 is a waveform diagram of the clock signal clk when the Ton / Toff ratio is fixed in the DC / DC converter 1 of FIG. The graph of FIG. 7 shows the clock signal clk_dr, the output voltage Vout of the DC / DC converter, and the inductor current IL in order from the top.

  Referring to FIG. 7, when output voltage Vout reaches desired target voltage Vout *, clock signal clk_dr is stopped by the output of comparator CMP1 in FIG. Time t1) in FIG. When the Ton / Toff ratio is fixed, it is necessary to set the Ton / Toff ratio to the largest value. Therefore, the period during which the clock signal clk_dr is stopped (from time t1 to time t2 in FIG. 7) becomes longer. On the other hand, in this embodiment, since the Ton / Toff ratio is set according to the input voltage Vin, the stop period of the clock signal clk_dr can be shortened.

  The same applies when the inductor current IL exceeds the specified value ILmax. In this case, in order to prevent destruction of the switching element, the clock signal clk_dr is stopped by the output of the comparator CMP2 in FIG. 1 (time t3 in FIG. 7). When the Ton / Toff ratio is fixed, the Ton period is set to be long, so that more current than necessary flows through the inductor. Therefore, the stop period of the clock signal clk_dr in this case (from time t3 to time t4) Also gets longer.

Next, the influence of the clock signal stop period will be quantitatively described.
FIG. 8 is a diagram for explaining the inductor current in the case of the boost converter. Referring to FIG. 8, the inductor current increases by ΔIon during the on period Ton, and the inductor current decreases by ΔIff during the off period Toff. These values are expressed by the aforementioned equations (1) and (2). The average inductor current Iav is obtained by using the average output current Iout.
Iav = (Ton / Toff +1) · Iout… (13)
Given by.

When the input voltage Vin to the DC / DC converter 1 is 2V, the Ton / Toff ratio should be 3V / 2V-1 = 0.5. However, since the Ton / Toff ratio is fixed corresponding to the case where the input voltage is 1 V which is the minimum, the Ton / Toff ratio is set to 2. In this case, assuming that the inductance L of the inductor 11 is 20 uH and the output current Iout is 20 mA, Ton is 0.67 μs. Therefore, the maximum current ILmax of the inductor can be calculated using the equations (1) and (13).
ILmax = (Ton / Toff + 1) · Iout + ΔIon / 2
= (Ton / Toff +1) · Iout + Vin · Ton / (2 · L)
= 3 × 20mA + 2V × 0.67μs / (2 × 20μH) = 93mA (14)
It becomes.

On the other hand, in the case of the present embodiment, the Ton / Toff ratio can be optimized with respect to the input voltage Vin. Therefore, when the input voltage Vin is 2 V, Ton / Toff = 0.5 and the on time Ton = 0. .33 μs, OFF time Toff = 0.67 μs. Therefore, the maximum current ILmax of the inductor is
ILmax = (Ton / Toff +1) · Iout + Vin · Ton / (2 · L)
= 1.5 × 20mA + 2V × 0.33μs / (2 × 20μH) = 46.5mA (15)
It becomes.

  In this way, when the Ton / Toff ratio is fixed, a current twice as much as the current necessary flows. As the unnecessary current increases, the amount of heat consumed by the parasitic resistance also increases, so that the power conversion efficiency decreases. On the other hand, in the case of the DC / DC converter 1 according to the first embodiment, the Ton / Toff ratio is set according to the input voltage Vin, so that the power conversion efficiency can be improved.

(3. Ton / Toff ratio setting accuracy is high)
The step-up DC / DC converter 1 according to the first embodiment has a feature that the setting accuracy of the Ton / Toff ratio is higher than that of the step-up converter described in Non-Patent Document 1 described above. This will be specifically described below.

  In the case of Non-Patent Document 1, the feedforward control for determining the Ton / Toff ratio from the input voltage VI is the same as in this embodiment, but the method for determining Ton / Toff is the same as that of this embodiment. Very different from the case. In the case of Non-Patent Document 1, the PWM control determines the on time Ton and the off time Toff using a triangular wave.

FIG. 9 is a diagram for explaining a method of determining the on time Ton and the off time Toff using a triangular wave. Referring to FIG. 9, in the case of Non-Patent Document 1, determination voltage VREF obtained by dividing input voltage VI by resistance elements having resistance values R1 and R2 is input and compared with triangular wave voltage VT. A period of VT> VREF is set as an on period (Ton), and a period of VT <VREF is set as an off period (Toff) period. If the maximum value of the triangular wave voltage is VTm and the output voltage is VO,
VO = (R1 / R2 + 1) ・ VTm (16)
VREF = R2 ・ VI / (R1 + R2) (17)
There is a relationship. A triangular wave is usually made up of a constant current source and a capacitor.

  FIG. 10 is a circuit diagram showing a configuration of a general triangular wave generation circuit 900. Referring to FIG. 10, the triangular wave generation circuit includes a capacitor 901, an NMOS transistor 902, a one-shot pulse generator 903, a comparator 904, and a constant current source 905. The capacitor 901 is charged by the current from the constant current source 905. Comparator 904 switches the output to L level when the charging voltage of capacitor 901 exceeds reference voltage VR. The one-shot pulse generator 903 outputs a pulse that is at the H level for a predetermined time when the output signal of the comparator 904 is switched from the H level to the L level. The NMOS transistor 902 conducts in response to the pulse output from the one-shot pulse generator 903, whereby the voltage of the capacitor 901 is discharged.

  The Ton / Toff ratio setting method of Non-Patent Document 1 as described above has the following problems.

First, as the input voltage VI decreases, the accuracy of the Ton / Toff ratio deteriorates. When the input voltage VI is 0.5 V, the output voltage VO is 5 V, and the maximum value VTm of the triangular wave voltage is 1 V, R1 / R2 = 4 from Equation (16). From equation (17), VREF = 0.1V. Therefore, if the input offset of the PWM comparator is ΔV, the Ton / Toff ratio is
Ton / Toff = [(VTm−VREF) ± ΔV] / (VREF ± ΔV) (18)
It becomes. When ΔV = 50 mV, the Ton / Toff ratio varies greatly from 6.7 to 19. This is because the offset voltage increases relatively as the determination voltage VREF decreases.

  Further, there is a problem that the influence of the delay time Δt when resetting the triangular wave shown in FIG. 9 increases as the Ton / Toff ratio increases (that is, VI decreases).

  Second, in the case of Non-Patent Document 1, since the Ton / Toff ratio must be set according to the voltage level of the input voltage VI, the capacitor 901 shown in FIG. 10 has a double-poly capacitor. ) And the like are indispensable elements. Since such an element generally has a large area and increases the number of process steps, it cannot be used in a low-cost semiconductor process.

In the DC / DC converter 1 of the first embodiment, the above problem is solved.
Regarding the first problem, in this embodiment, the input voltage Vin itself is not used for setting the Ton time. A conversion current Ia proportional to the input voltage Vin is generated, and the capacitor 44A is charged with the conversion current Ia. The time when the terminal voltage Von of the capacitor 44A reaches the constant value Vref is defined as Ton time. By adjusting the magnitude of the conversion current Ia and the capacitance of the capacitor 44A, the input voltage to the comparator 42A can be set relatively high, so that the influence of the offset voltage of the comparator 42A is reduced.

  Specifically, the input voltages Von and Voff to the comparators 42A and 42B in FIG. 2 are 0.5V or more, and the reference voltage Vref is 0.8V to 1.2V. Compared with the determination voltage VREF = 0.1 V in Non-Patent Document 1, the influence of the input offset of the comparator is greatly reduced.

  Furthermore, in the case of this embodiment, the delay time required for resetting the voltages Von and Voff in FIG. 6 affects the on-time Ton and the off-time Toff longer. On the other hand, in the case of a non-patent document, only the on-time Ton becomes longer, so the influence on the Ton / Toff ratio is great.

  Further, in the case of this embodiment, the on time Ton is set by the time during which the capacitor 44A is charged with the conversion current Ia proportional to the input voltage Vin. The off time Toff is set by the time for charging the capacitor 44B with the current I2 obtained by subtracting the conversion current Ia from the constant current Ics. By setting the on times Ton and Toff in this way, the cycle Tcycle (= Ton + Toff) becomes longer as the input voltage Vin becomes lower (Ton / Toff ratio becomes larger). For this reason, the influence of the delay time when resetting the charging voltages Von and Voff of the capacitors 44A and 44B can be reduced.

  Regarding the second problem, in the case of the DC / DC converter 1 of this embodiment, the on-time Ton and the off-time Toff are such that the charging voltages Von and Voff of the capacitors 44A and 44B in FIG. 2 reach the reference voltage Vref. It is set as the time until. For this reason, the capacitors C1 and C2 of the capacitors 44A and 44B do not need to be linear capacitors. For example, a low-cost MOS transistor capacitor can be used.

  As another advantage, in the DC / DC converter 1 of this embodiment, since the on-time Ton and the off-time Toff can be individually set, when the Ton / Toff ratio deviates from the design value, the on-time Ton and the off-time It is possible to easily set to the design value by individually adjusting the length of Toff.

[Modification of Embodiment 1]
FIG. 11 is a circuit diagram showing a configuration of a DC / DC converter 2 as a modification of the DC / DC converter 1 of FIG. 11 is different from the conversion circuit 10 in FIG. 1 in that the diode 12 is replaced with a PMOS transistor p_sw.

  The boosting operation of the input voltage Vin by the DC / DC converter 2 is the same as that of the DC / DC converter 1 of FIG. That is, when the NMOS transistor n_dr is turned on, a current flows through the inductor 11. Next, the NMOS transistor n_dr is turned off. In the synchronous rectification method shown in FIG. 11, the PMOS transistor p_sw is turned on to supply current to the output.

  Here, if there is an overlap period in which the PMOS transistor p_sw is turned on before the NMOS transistor n_dr is turned off, a large through current flows. A non-overlap circuit 100 is further provided in the control circuit 20A of FIG. 12 so that the on period of the NMOS transistor n_dr and the on period of the PMOS transistor p_sw do not overlap. Based on the clock signal clk_dr received from the AND gate 21, the non-overlap circuit 100 outputs the clock signal ncnt to the gate of the NMOS transistor n_dr and outputs the clock signal pcnt to the gate of the PMOS transistor p_sw.

  FIG. 12 is a circuit diagram showing an example of the configuration of the non-overlap circuit 100 of FIG. Referring to FIG. 12, non-overlap circuit 100 includes inverters 107, 108A to 108C, 109A to 109C, PMOS transistors 101 to 103, and NMOS transistors 104 to 106.

  PMOS transistor 101 and NMOS transistors 104 and 105 are connected in series between power supply node VDD and ground node GND in this order. PMOS transistors 102 and 103 and NMOS transistor 106 are connected in series between power supply node VDD and ground node GND in this order. The clock signal clk_dr is input to the gates of the transistors 101, 105, 102, and 106 via the inverter 107. The voltage at the connection node 110 of the transistors 101 and 104 is output as the clock signal pcnt and input to the gate of the transistor 103 via the inverters 109A to 109C. The voltage at the connection node 111 of the transistors 103 and 106 is output as the clock signal ncnt and also input to the gate of the transistor 104 via the inverters 108A to 108C.

  FIG. 13 is a timing chart showing voltage waveforms at various parts of the circuit of FIG. Hereinafter, the operation of the non-overlap circuit 100 will be described with reference to FIGS.

  When the clock signal clk_dr is switched from the H level to the L level at time t1 in FIG. 13, the PMOS transistors 101 and 102 are turned off and the NMOS transistors 105 and 106 are turned on. As a result, the clock signal ncnt is switched from the H level to the L level.

  Next, the NMOS transistor 104 is turned on and the PMOS transistor 103 is turned off at time t2 when a delay time corresponding to the inverters 108A to 108C and 109A to 109C connected in series has elapsed. As a result, the clock signal pcnt is switched from the H level to the L level.

  When the clock signal clk_dr is switched from the L level to the H level at the next time t3, the PMOS transistors 101 and 102 are turned on and the NMOS transistors 105 and 106 are turned off. As a result, the clock signal pcnt is switched from the L level to the H level.

  Next, the PMOS transistor 103 is turned on and the NMOS transistor 104 is turned off at time t4 when the delay time corresponding to the inverters 108A to 108C and 109A to 109C connected in series has elapsed. As a result, the clock signal ncnt is switched from the L level to the H level.

<Embodiment 2>
In the control circuit 20 of the first embodiment, the optimum value of the Ton / Toff ratio is set first, and thereafter, the value of the Ton / Toff ratio is not changed. Therefore, when the input voltage Vin is considerably smaller than the expected value Vout * of the output voltage (when the optimum value of Ton / Toff ratio is relatively large), the output voltage Vout reaches the expected value Vout *. There is a problem that it takes time. If the Ton / Toff ratio can be set larger than the optimum value during the period when the output voltage Vout is lower than the expected value Vout *, the time until the output voltage Vout reaches the expected value Vout * can be shortened. In the second embodiment, a circuit configuration for that purpose is disclosed.

  FIG. 14 is a circuit diagram showing a configuration of a pulse generator PGA applied to the DC / DC converter according to Embodiment 2 of the present invention. In the DC / DC converter 1 of FIG. 1, the pulse generator PG is replaced with the pulse generator PGA of FIG. The configuration other than the pulse generator PGA is the same as that of the first embodiment shown in FIG.

  Referring to FIG. 14, current signal generation unit 70 </ b> A differs from current signal generation unit 70 of FIG. 2 in that it further includes an operational transconductance amplifier (OTA) 120. The reference voltage Vref is input to the non-inverting input terminal of the OTA 120, and the output voltage Vout2 of the voltage dividing circuit 31 in FIG. 1 is input to the inverting input terminal of the OTA 120. The reference voltage Vref is set according to the expected value Vout * of the output voltage Vout. If the voltage dividing ratio of the voltage dividing circuit 31 is α, the reference voltage Vref is given by α × Vout *. Note that the reference voltage input to the OTA 120 need not be the same as the reference voltage input to the comparators CMP1, CMP2, 42A, and 42B described so far.

The OTA 120 outputs a correction current Imd corresponding to the voltage difference between the reference voltage Vref and the output voltage Vout2 of the voltage dividing circuit 31 to the output node 84 of the constant current generator 80. When Vref> Vout2, the correction current Imd is positive, and when Vref <Vout2, the correction current Imd is negative. If the transfer conductance of the OTA 120 is G, the correction current Imd is
Imd = G ・ (Vref−Vout2)… (19)
It is expressed as Other configurations in FIG. 14 are the same as those in FIG. 2, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof is not repeated.

In the case of FIG. 14, the current signal output from the current signal generator 70A to the off signal generator 40B is corrected to a value I2 ′ obtained by adding the correction current Imd to the second current signal I2 of the first embodiment.
I2 ′ = I2 + Imd = Ics + Imd−Ia (20)
It becomes. Therefore, the off time Toff is
Toff = C2 / Vref / I2 '= C2 / Vref / (Ics + Imd-Ia)
= C2 / Vref / R / [(Ics + Imd) / R-Vin] (21)
It is expressed as

  When the output Vout is lower than the expected value Vout *, since the correction current Imd is supplied from the OTA 120 (Imd> 0), the off period Toff is set to be short. That is, since the Ton / Toff ratio is set to be large, the increase in the inductor current during the on-period Ton becomes large, which is used to increase the output voltage. When the output voltage Vout reaches the expected value Vout *, the correction current Imd output from the OTA 120 becomes zero and is set to the Ton / Toff ratio during steady operation.

  On the other hand, when the output Vout is higher than the expected value Vout *, the OTA 120 draws the correction current Imd (Imd <0), so the off period Toff is set to be long. Since the amount of current supplied from the inductor 11 is smaller than the current Iout consumed by the load, the output voltage Vout approaches the expected value Vout * more quickly.

  FIG. 15 is a circuit diagram showing an example of the configuration of the OTA 120 in FIG. Referring to FIG. 15, OTA 120 includes PMOS transistors 121 to 124, NMOS transistors 125 to 128, and a current source 130.

  Transistors 121 and 125 are connected in series in this order between power supply node VDD and ground node GND, and transistors 122 and 128 are connected in series in this order between power supply node VDD and ground node GND. Transistors 123 and 126 are connected in series in this order between node 129 and ground node GND, and transistors 124 and 127 are connected in series in this order between node 129 and ground node GND. Constant current source 120 is connected between power supply node VDD and node 129.

  The gate of the PMOS transistor 121 is connected to the drain thereof and to the gate of the PMOS transistor 122. That is, the PMOS transistors 121 and 122 constitute a current mirror. The gate of the NMOS transistor 126 is connected to the drain thereof and to the gate of the NMOS transistor 125. That is, the NMOS transistors 125 and 126 constitute a current mirror. The gate of the NMOS transistor 127 is connected to the drain thereof and to the gate of the NMOS transistor 128. That is, the NMOS transistors 127 and 128 constitute a current mirror.

  In the OTA 120 configured as described above, the gate of the PMOS transistor 124 is used as the non-inverting input terminal INp of the OTA 120, and the gate of the PMOS transistor 123 is used as the inverting input terminal INn of the OTA 120. A connection node 131 of the transistors 122 and 128 is used as the output node OUT3 of the OTA 120. Therefore, if the voltage of the non-inverting input terminal INp increases more than the voltage of the inverting input terminal INn, the current flowing through the transistors 124, 127, 128 decreases according to the increase amount, and the transistors 123, 126, 125, 121, The current flowing through 122 increases. As a result, the current flowing out from the output node to the outside from OUT3 increases. Conversely, if the voltage at the non-inverting input terminal INp is lower than the voltage at the inverting input terminal INn, the current flowing through the transistors 124, 127, 128 increases according to the amount of decrease, and the transistors 123, 126, 125, 121 are increased. , 122 decreases in current. As a result, the current flowing from the outside into the output node OUT3 increases.

<Embodiment 3>
An example in which the pulse generator PG described in the first embodiment is applied to the boost control of the DC / DC converter 200 having one input and multiple outputs will be described.

  FIG. 16 is a circuit diagram showing a configuration of DC / DC converter 200 according to Embodiment 3 of the present invention. The DC / DC converter 200 of FIG. 16 is a configuration example in the case of two systems of outputs by the synchronous rectification method. The DC / DC converter 200 can be applied to a power generation system using sunlight or indoor lighting. For example, the voltage (0.5 V to 3 V) of the solar cell 201 is boosted to 4 V to 5 V and output. The DC / DC converter 200 charges the secondary battery 202 from the first output 206 of the two outputs, and supplies power to the microcomputer 203, the RF transceiver 204, and the sensor 205 from the second output 207. The microcomputer 203, the RF transceiver 204, and the sensor 205 are prepared for automatically measuring, for example, temperature, atmospheric pressure, sunlight, illuminance of indoor lighting, and the like, and automatically transmitting the results to the counting system periodically.

  A specific circuit configuration will be described. The DC / DC converter 200 includes a conversion circuit 210, a control circuit 220, voltage dividing circuits 217 and 218, and power switch PMOS transistors psx and psy.

  The conversion circuit 210 has two outputs on the output side of the conversion circuit 10A shown in FIG. 11, and includes an inductor 211, an NMOS transistor n_dr as a switching element, PMOS transistors prx and play as synchronous rectification elements, and a capacitor 212. , 213.

  Inductor 211 and NMOS transistor n_dr are connected in series between input node 208 and ground node GND in this order. For example, a solar cell 201 is connected to the input node 208. The PMOS transistor prx is connected between the connection node 214 of the inductor 211 and the NMOS transistor n_dr and the first output node 215. The PMOS transistor play is connected between the connection node 214 and the second output node 216. Capacitor 212 is connected between output node 215 and ground node GND, and capacitor 213 is connected between output node 216 and ground node GND. Clock signals clk_dr, clkx, and clky are output from the control circuit 220 to the gates of the transistors n_dr, prx, and pry, respectively.

  The voltage dividing circuit 217 divides the voltage dvoutx of the output node 215 by the resistance elements (resistance values Rx0 and Rx1), and outputs the divided voltage fbx to the control circuit 220. The voltage dividing circuit 218 divides the voltage dvouty of the output node 216 by the resistance elements (resistance values Ry0 and Ry1), and outputs the divided voltage fby to the control circuit 220.

  The power switch PMOS transistor psx is provided between the output node 215 of the conversion circuit 210 and the first output 206 of the DC / DC converter 200. The power switch PMOS transistor psy is provided between the output node 216 of the conversion circuit 210 and the second output 207 of the DC / DC converter 200.

  Among the above-described configurations, the control circuit 220, the NMOS transistor n_dr, the PMOS transistors prx, pri, psx, psi, and the voltage dividing circuits 217, 218 are configured as a semiconductor device 209 integrated on a semiconductor substrate.

  FIG. 17 is a circuit diagram showing a configuration of control circuit 220 in FIG. Referring to FIGS. 16 and 17, control circuit 220 includes comparators CMPX and CMPY, level shifters 231, 232 and 233, pulse generator PGB, non-overlap circuit 230, and logic circuit 228. .

  The control circuit 220 uses the voltage dvouty of the output node 216 in FIG. 16 as the power supply voltage. Hereinafter, the expected value of the voltage dvoutx at the output node 215 is 5V, and the expected value of the voltage dvouty at the output node 216 is 3V. It is assumed that the power switch PMOS transistors psx and psy are both turned on.

  The comparator CMPX compares the output voltage fbx of the voltage dividing circuit 217 of FIG. 16 with the reference voltage Vref, and outputs an H level signal when the output voltage fbx is higher than the reference voltage Vref. . The comparator CMPY compares the output voltage fby of the voltage dividing circuit 218 with the reference voltage Vref, and outputs an H level signal when the output voltage fby is higher than the reference voltage Vref.

  Reference voltage Vref is set to 0.8 V, for example. The output voltage fbx of the voltage dividing circuit 217 is a voltage monitor signal of the voltage dvoutx of the output node 215. In FIG. 16, when Rx0: Rx1 = 5.25: 1 is set, fbx = 0.8V when dvoutx = 5V. That is, the comparator CMPX outputs the H level if the voltage dvoutx of the output node 215 is higher than the expected value (5 V), and otherwise outputs the L level.

  The same applies to the voltage dvouty at the output node 216. When Ry0: Ry1 = 2.75: 1 is set, the comparator CMPY outputs an H level if the voltage dvouty is higher than the expected value (3V), and otherwise outputs an L level.

  Level shifters (LS) 231, 232, and 233 convert the voltage level of the input signal from the voltage dvouty of the output node 216 to vmax. vmax is a higher one of the voltage dvoutx at the output node 215 and the voltage dvouty at the output node 216. The voltage vmax is determined by a maximum voltage selection circuit provided in the control circuit 220.

  FIG. 18 is a circuit diagram showing a configuration example of the maximum voltage selection circuit 240. Referring to FIG. 18, maximum voltage selection circuit 240 operates with comparator 241 that operates at voltage dvouty, level shifter 242 that converts the voltage level of the output signal of comparator 241 from voltage dvouty to vmax, and voltage vmax. Inverter 243 and PMOS transistors 224 and 245 are included. The voltage dvouty is input to the source of the PMOS transistor 244, and the drain is connected to the output node 246 (voltage vmax) of the maximum voltage selection circuit 240. The output signal of the level shifter 242 is input to the gate of the PMOS transistor 244. The voltage dvoutx is input to the source of the PMOS transistor 245, and the drain is connected to the output node 246 of the maximum voltage selection circuit 240. A signal obtained by inverting the output signal of the level shifter 242 by the inverter 243 is input to the gate of the PMOS transistor 245.

  Referring to FIG. 17 again, the non-overlap circuit 230 receives the clock signal clk output from the pulse generator PCB, and outputs a clock signal pcnt for driving the PMOS transistors prx and pry, and an NMOS transistor n_dr. A clock signal ncnt for driving is generated. The configuration of the non-overlap circuit 230 is the same as that of the non-overlap circuit 100 shown in FIG. However, in FIG. 12, a clock signal clk is input as an input signal. The non-overlap circuit 230 is provided to prevent such a period since a through current flows when the clock signal pcnt is at the L level during the period when the clock signal ncnt is at the H level. The clock signal ncnt is level-converted by the level shifter 233 and input to the gate of the NMOS transistor n_dr as the clock signal clk_dr. The clock signal pcnt is input to the OR gates 223 and 224.

  Logic circuit 228 includes AND gate 221, OR gates 222-224, and inverters 225-227.

  The output signal of the comparator CMPX is supplied to the first input terminal of the AND gate 221 and also supplied to the first input terminal of the OR gate 222. The output signal of the comparator CMPY is supplied to the second input terminal of the AND gate 221, inverted by the inverter 225, and then supplied to the second input terminal of the OR gate 222. The output signal of the AND gate 221 is used as a non-operation signal nop. A signal obtained by inverting the output signal of the OR gate 222 by the inverter 226 is used as the selection signal sctx. A signal obtained by inverting the output signal of the comparator CMPY by the inverter 227 is used as the selection signal scty.

  The OR gate 223 calculates the logical sum of the output signal of the OR gate 222 and the clock signal pcnt. The output signal of the OR gate 223 is level-converted by the level shifter 231 and input to the gate of the PMOS transistor prx as the clock signal clkx. The OR gate 224 calculates the logical sum of the output signal of the comparator CMPY and the clock signal pcnt. The output signal of the OR gate 224 is level-converted by the level shifter 232 and input to the gate of the PMOS transistor play as the clock signal clky.

  FIG. 19 is a diagram for explaining the operation of the control circuit of FIG. The table shown in FIG. 19 shows how the logic levels of the selection signals sctx and scty and the non-operation signal nop change according to the logic levels of the output signals of the comparators CMPX and CMPY in FIG. . Furthermore, the table shown in FIG. 19 indicates whether each clock signal clkx, clky, clk_dr is enabled or disabled according to the logic level of the output signals of the comparators CMPX, CMPY. When the clock signal is invalid, the clock signal becomes a signal of a certain logic level.

  Referring to FIGS. 17 and 19, control circuit 220 uses voltage dvouty at output node 216 as a drive voltage, and therefore charges voltage dvouty at output node 216 with priority over voltage dvoutx at output node 215.

  First, when voltages dvoutx and dvouty at output nodes 215 and 216 are both lower than expected values, both comparators CMPX and CMPY output L level. However, since priority is given to the charging of the voltage dvouty of the output node 216, the selection signal scty becomes H level. Charging of the output node 215 (voltage dvoutx) is blocked, and the selection signal sctx becomes L level. The non-operation signal nop becomes L level. Since the clock signal clk_dr that drives the NMOS transistor n_dr and the clock signal clky that drives the PMOS transistor pry for synchronous rectification become valid, the output node 216 is charged.

  Next, when the voltage dvouty of the output node 216 reaches the expected value and the voltage dvoutx of the output node 215 does not reach the expected value, the comparator CMPX outputs an L level and the comparator CMPY outputs an H level. . At this time, the selection signal sctx becomes H level and the selection signal scty becomes L level. The non-operation signal nop becomes L level. Since the clock signal clk_dr for driving the NMOS transistor n_dr and the clock signal clkx for driving the PMOS transistor prx for synchronous rectification become valid, the output node 215 is charged. The clock signal “clky” for driving the synchronous rectification PMOS transistor “ply” becomes invalid.

  Next, when the voltages dvoutx and dvouty at the output nodes 215 and 216 reach the expected values, the comparators CMPX and CMPY both output the H level. At this time, both the selection signals sctx and scty are at the L level, and the non-operation signal nop is at the H level. In this case, the output signal from pulse generator PGB is fixed at the L level, and the boosting operation is not performed.

  FIG. 20 is a circuit diagram showing a configuration of the pulse generator PGB of FIG. The power supply node VDD in FIG. 20 corresponds to the output node 216 in FIG.

  Referring to FIG. 20, pulse generator PGB differs from pulse generator PG of FIG. 2 in that it further includes an AND gate 93 and an inverter 94. An output signal of the RS latch circuit 90 is input to the first input terminal of the AND gate 93, and a signal obtained by inverting the non-operation signal nop by the inverter 94 is input to the second input terminal of the AND gate 93. The When the non-operation signal is at L level, the AND gate 93 outputs a valid clock signal clk. When the non-operation signal is at the H level, the AND gate 93 outputs an L level signal.

  In the pulse generator PGB of FIG. 20, the configuration of the voltage / current converter 60A is different from that of the voltage / current converter 60 of FIG. The voltage / current conversion unit 60A includes resistance elements 63x and 63y and an NMOS transistor 65 in place of the resistance element 63 of FIG. Resistance elements 63x and 63y are connected in this order between ground node GND and the source of NMOS transistor 62. The NMOS transistor 65 is connected in parallel with the resistance element 63x. The selection signal scty is input to the gate of the NMOS transistor 65.

  In FIG. 20, the pulse generator PGB needs to determine an optimal Ton / Toff ratio without delay in accordance with switching between the voltages dvoutx and dvouty to be charged. Therefore, the NMOS transistor 65 is switched on / off according to the selection signal scty. As a result, the resistance value between the source of the NMOS transistor 62 and the ground node GND is switched, so that the magnitude of the conversion current Ia changes.

When charging the voltage dvoutx of the output node 215 in FIG. 16, the selection signal scty is L, so that the NMOS transistor 65 is turned off. The Ton / Toff ratio in this case is obtained from the equations (9) and (10).
Ton / Toff = Ics · (Rx + Ry) / Vin −1 (22)
Is set. However, the resistance value of the resistance element 63x is Rx, and the resistance value of the resistance element 63y is Ry. On the other hand, when charging the voltage dvouty of the output node 216, the selection signal scty is at a high level, so that the NMOS transistor 65 is turned on. The Ton / Toff ratio in this case is obtained from the equations (9) and (10).
Ton / Toff = Ics · Ry / Vin −1 (23)
It becomes. Therefore, by setting Ics, Rx, and Ry so that Ics × (Rx + Ry) = 5V and Ics × Ry = 3V, when charging is switched between the first and second outputs of the DC / DC converter 200, The conversion rate from the voltage Vin to the conversion current Ia is switched, and as a result, an optimum Ton / Toff ratio can be obtained without delay.

  As described above, according to the configuration of the pulse generator PGB described above, when there are a plurality of output destinations of the DC / DC converter, when the output destination to be charged is switched, the optimum Ton / Toff ratio is switched without delay. be able to. Therefore, the output voltage can be obtained stably.

  The other points in FIG. 20 are the same as those in FIG. 2, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Embodiment 4>
[Configuration of DC / DC Converter 3]
FIG. 21 is a circuit diagram showing a configuration of DC / DC converter 3 according to the fourth embodiment of the present invention. The DC / DC converter 3 is a step-down converter that steps down the voltage Vin (for example, 4V to 5V) input to the input node 15 and outputs the stepped-down voltage Vout (for example, 2V) from the output node 16.

  As shown in FIG. 21, the DC / DC converter 3 includes a conversion circuit (step-down chopper) 10B, a control circuit 20B, and a voltage divided by the resistive elements 31A and 31B (resistance values R1 and R2). Pressure circuit 31. A DC power supply 9 such as a solar battery cell is connected to the input node 15, and an output node 16 is connected to a load (load current Iout). The power supply voltage of the control circuit 20B is supplied from the output node 16 (referred to as “power supply node VDD”).

(Configuration and operation of conversion circuit 10B)
The conversion circuit 10B includes an inductor 11, a PMOS transistor p_dr as a switching element, an NMOS transistor n_sw as a synchronous rectification element, and a capacitor 13. The PMOS transistor p_dr and the inductor 11 are connected in series between the input node 15 and the output node 16 in this order. NMOS transistor n_sw is connected between connection node 14 of PMOS transistor p_dr and inductor 11 and ground node GND. Capacitor 13 is connected between output node 16 and ground node GND.

  A period in which the PMOS transistor p_dr is on is Ton, and a period in which the PMOS transistor p_dr is off is Toff. If Ton is set longer, the output voltage Vout increases, and if the Toff period is set longer, the output voltage Vout decreases. If there is an overlap period in which the NMOS transistor n_sw is turned on before the PMOS transistor p_dr is turned off, a large through current flows. The non-overlap circuit 29 provided in the control circuit 20B is controlled so that the ON period of the PMOS transistor p_dr and the ON period of the NMOS transistor n_sw do not overlap.

If the inductance of the inductor 11 is L, the increase ΔIon of the current flowing through the inductor 11 during the period when the PMOS transistor p_dr is on is
ΔIon ＝ (Vin−Vout) ・ Ton / L… (24)
It is expressed as The decrease ΔIoff of the current flowing through the inductor 11 during the period when the PMOS transistor p_dr is off is
ΔIoff ＝ Vout ・ Toff / L… (25)
It is expressed as However, in the above formulas (24) and (25), the voltage drop due to the parasitic resistance was ignored. In the steady state, the inductor current ΔIon increased during the ON period cancels out the decrease ΔIoff during the OFF period. That is, from ΔIon = ΔIoff, the Ton / Toff ratio is
Ton / Toff = Vout / (Vin−Vout) (26)
Stable at a ratio of.

(Schematic configuration of the control circuit 20B)
The control circuit 20B is a circuit for controlling the on-time and off-time of the PMOS transistor p_dr, and has a circuit configuration that automatically sets the Ton / Toff ratio from the input voltage Vin by feedforward control. As a result, power efficiency can be improved without generating unnecessary current. The control circuit 20B further has a function of stopping the switching of the PMOS transistor p_dr when the output voltage Vout exceeds the expected value Vout *.

  Specifically, as shown in FIG. 21, the control circuit 20B includes a pulse generator PGC, a comparator CMP1, an AND gate 27, and an inverter.

  The pulse generator PG determines the on time Ton and the off time Toff based on the input voltage Vin so that the output voltage Vout is substantially equal to the expected value Vout *. Then, the pulse generator PG outputs a clock signal clk that becomes H level and L level during the determined on time Ton and off time Toff.

  The comparator CMP1 compares the reference voltage Vref with the divided voltage Vout2 output from the voltage dividing circuit 31, and outputs a signal that becomes L level when the divided voltage Vout2 exceeds the reference voltage Vref. Using the voltage division ratio α (= R1 / (R1 + R2)) of the voltage dividing circuit 31 and the expected value Vout * of the output voltage, the reference voltage Vref is given by α × Vout *.

  The AND gate 21 outputs a signal obtained by inverting the logical product of the clock signal clk output from the pulse generator PGC and the output of the comparator CMP1 by the inverter 28 to the gate of the PMOS transistor p_dr as the clock signal clk_dr.

[Detailed configuration of pulse generator PG]
FIG. 22 is a circuit diagram showing a configuration of the pulse generator PGC of FIG. Referring to FIG. 22, pulse generator PGC includes voltage / current converter 60, current signal generator 70B, on signal generator 40A, off signal generator 40B, inverters 91 and 92, and RS latch. Circuit 90.

  In the pulse generator PGC of FIG. 22, the configuration of the current signal generator 70B is different from that of the current signal generator 70 of FIG. Since the other components of pulse generator PGC are the same as those of pulse generator PG in FIG. 2, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  As in the case of the current signal generation unit 70 in FIG. 2, the current signal generation unit 70B increases as the input voltage Vin increases based on the constant current Ics and the conversion current Ia having a constant current value. The first current signal I1 and the first current signal I1 generate a second current signal I2 having different dependency on the input voltage Vin. The first current signal I1 is supplied to the on signal generator 40A, and the second current signal I2 is supplied to the off signal generator 40B.

However, in the case of a control circuit for a step-down converter, the first current signal I1 is
I1 = Ia−Ics (27)
The second current signal I2 is given by
I2 = Ics (28)
Given in.

  Specifically, as shown in FIG. 22, the current signal generation unit 70B includes PMOS transistors 71 and 72 constituting a current mirror, NMOS transistors 74 and 75 constituting a current mirror, and a constant current generation unit 80A. .

  The conversion current Ia flowing through the output node 64 of the voltage / current conversion unit 60 is copied as the drain current of the PMOS transistor 72 by the current mirror circuit. Further, the output signal Ics of the constant current generator 80A is copied as the drain current of the NMOS transistor 75. The first current signal I1 supplied from the current signal generator 70B to the on signal generator 40A is obtained by subtracting the drain current of the NMOS transistor 75 from the drain current of the PMOS transistor 72, and is given by the above equation (27). It is done.

  The constant current generator 80 includes a constant current source 81 that generates a constant current Ics, and PMOS transistors 82, 83, and 85. The constant current Ics is copied by a current mirror circuit composed of PMOS transistors 82 and 83, and is output from the constant current generator 80 as the second current signal I2 (see the above equation (28)). Further, the constant current Ics is copied by a current mirror circuit composed of PMOS transistors 82 and 85 and supplied to the NMOS transistor 74.

[Operation of DC / DC converter 3]
Next, the operation of the DC / DC converter 3 configured as described above will be described. Referring to FIG. 22, the period during which the ON signal Son is at the L level is the ON period of the PMOS transistor p_dr, and therefore the ON time Ton is determined to be Ics = Vout / Rs.
Ton = C1 / Vref / (Ia-Ics) = C1 / Vref / Rs / (Vin-Vout) (29)
It is expressed as On the other hand, since the period during which the signal Soff is at the L level is the off period of the PMOS transistor p_dr, the off time Toff is:
Toff = C2 / Vref / Ics = C2 / Vref / Rs / Vout (30)
It can be expressed as From these equations
Ton / Toff = C1 / Vin / [C2- (Vin−Vout)] (31)
Is obtained. Therefore, when setting so that C1 = C2, a desired Ton / Toff ratio can be obtained.

[Effect of Embodiment 4]
According to the DC / DC converter 3 of the fourth embodiment, since the Ton / Toff ratio can be determined from the input voltage Vin without feedback, there is no concern about oscillation. External elements such as oscillation prevention capacitors and resistors are not required.

  Furthermore, according to the DC / DC converter 3, it is possible to shorten the transition time to the stable state with respect to the change of the input / output voltage and to obtain the maximum power efficiency corresponding to the input voltage Vin. Hereinafter, a description will be given in contrast to a case where the Ton / Toff ratio is fixed without being adjusted according to the input voltage Vin.

When the Ton / Toff ratio is fixed, it is necessary to set the Ton / Toff ratio to the largest value so that the voltage can be stepped down even when the input voltage is the lowest. When the input voltage range is 4V to 5V and the output voltage is 2V, the condition with the largest Ton / Toff ratio is
Ton / Toff = Vout / (Vin−Vout) = 2V / (4V−2V) = 1 (32)
It becomes. When the cycle of the clock signal clk is 1 μs, Ton = 0.5 μs and Toff = 0.5 μs are set.

  FIG. 23 is a waveform diagram of a clock signal when the Ton / Toff ratio is fixed in the DC / DC converter 3 of FIG. The graph of FIG. 23 shows the clock signal clk_dr and the output voltage Vout in order from the top.

  Referring to FIG. 23, after switching from the ON period to the OFF period at time t1, before the OFF time Toff elapses, the output voltage Vout exceeds the expected value Vout *, so that the clock signal is output by the output of the comparator CMP1. clk_dr stops. When the output voltage Vout becomes equal to or lower than the expected value Vout * at time t2, the output of the clock signal clk_dr is started.

  When the Ton / Toff ratio is fixed, it is necessary to set the Ton / Toff ratio to the largest value, so the period during which the clock signal clk_dr is stopped (from time t1 to time t2 in FIG. 23) becomes longer. On the other hand, in this embodiment, since the Ton / Toff ratio is set according to the input voltage Vin, the stop period of the clock signal clk_dr can be shortened. Hereinafter, the influence on the power conversion efficiency during the stop period of the clock signal will be quantitatively described.

FIG. 24 is a diagram for explaining the inductor current in the case of the step-down converter. FIG. 24 is a diagram for describing an average current flowing through inductor 11 in FIG. 21 with reference to FIG. The inductor current increases by ΔIon during the on period Ton, and the inductor current decreases by ΔIff during the off period Toff. These values are expressed by the aforementioned equations (24) and (25). The average inductor current Iav is obtained by using the average output current Iout.
Iav ＝ Iout… (33)
Given by.

When the input voltage to the DC / DC converter 3 is 5V, the Ton / Toff ratio should be 2V / (5V-2V) = 0.67. However, since the Ton / Toff ratio is fixed at 4 V where the input voltage is minimum, the Ton / Toff ratio is set to 1. In this case, assuming that the inductance L of the inductor 11 is 20 μH and the output current Iout is 20 mA, Ton is 0.5 μs. Therefore, the maximum current ILmax of the inductor can be calculated using the equations (24) and (33).
ILmax ＝ Iout + (Vin−Vout) ・ Ton ／ (2 ・ L)
＝ 20mA + 3V × 0.5μs / (2 × 20μH) = 57.5mA (34)
It becomes.

On the other hand, in the case of the present embodiment, the Ton / Toff ratio can be optimized with respect to the change of the input voltage. Therefore, when the input voltage Vin is 5 V, Ton / Toff = 0.67, Ton = 0. 33 μs and Toff = 0.67 μs. Therefore, the maximum current ILmax of the inductor is
ILmax ＝ Iout + (Vin−Vout) ・ Ton ／ (2 ・ L)
= 20mA + 3V × 0.33μs / (2 × 20μH) = 44.8mA (35)
It becomes.

  In this way, when the Ton / Toff ratio is fixed, a current that is 13 mA more than the originally required current flows. Excess current is consumed as heat by the parasitic resistance, reducing power conversion efficiency. On the other hand, in the case of the DC / DC converter 3 of this embodiment, since the Ton / Toff ratio is set according to the input voltage Vin, the power conversion efficiency can be improved.

<Embodiment 5>
In the control circuit 20B of the fourth embodiment, the optimum value of the Ton / Toff ratio is set first, and thereafter, the value of the Ton / Toff ratio is not changed. If the Ton / Toff ratio can be set larger than the optimal value during the period when the output voltage Vout is lower than the expected value, the time until the expected value is reached can be shortened. In the fifth embodiment, a circuit configuration for that purpose is disclosed.

  FIG. 25 is a circuit diagram showing a configuration of a pulse generator PGD applied to a DC / DC converter according to Embodiment 5 of the present invention. In the DC / DC converter 3 of FIG. 21, the pulse generator PGC is replaced with the pulse generator PGD of FIG. The configuration other than the pulse generator PGD is the same as that of the fourth embodiment shown in FIG.

Referring to FIG. 25, current signal generation unit 70 </ b> C is different from current signal generation unit 70 </ b> B in FIG. 22 in that OTA 120 is further included. The configuration of the OTA 120 is the same as that described with reference to FIGS. The reference voltage Vref is input to the non-inverting input terminal of the OTA 120, and the output voltage Vout2 of the voltage dividing circuit 31 in FIG. 21 is input to the inverting input terminal of the OTA 120. The reference voltage Vref is set according to the expected value Vout * of the output voltage Vout. If the voltage dividing ratio of the voltage dividing circuit 31 is α, the reference voltage Vref is given by α × Vout *. The OTA 120 generates a correction current Imd corresponding to the voltage difference between the reference voltage Vref and the output voltage Vout2 of the voltage dividing circuit 31. Output to the output node 84 of the constant current generator 80A. If the transfer conductance of the OTA 120 is G, the correction current Imd is
Imd = G ・ (Vref−Vout2)… (36)
It is expressed as Other configurations in FIG. 25 are the same as those in FIG. 22, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof is not repeated.

In the case of FIG. 25, the current signal output from the current signal generator 70C to the off signal generator 40B is corrected to a value I2 ′ obtained by adding the correction current Imd to the second current signal I2 of the fourth embodiment.
I2 '= I2 + Imd = Ics + Imd (37)
It becomes. Therefore, the off time Toff is
Toff = C2 / Vref / I2 '= C2 / Vref / (Ics + Imd) (38)
It is expressed as

  When the output Vout is lower than the expected value Vout *, since the correction current Imd is supplied from the OTA 120 (Imd> 0), the off period Toff is set to be short. That is, since the Ton / Toff ratio is set to be large, the increase in the inductor current during the on-period Ton becomes large, which is used to increase the output voltage. When the output voltage Vout reaches the expected value Vout *, the correction current Imd output from the OTA 120 becomes zero and is set to the Ton / Toff ratio during steady operation.

  On the other hand, when the output Vout is higher than the expected value Vout *, the OTA 120 draws the correction current Imd (Imd <0), so the off period Toff is set to be long. Since the amount of current supplied from the inductor 11 is smaller than the current Iout consumed by the load, the output voltage Vout approaches the expected value Vout * more quickly.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1-3, 200 DC / DC converter, 9 DC power supply, 10, 10A, 10B, 210 conversion circuit, 11, 211 inductor, 12 diode, 20, 20A, 20B, 220 control circuit, n_dr NMOS transistor (switching element), p_dr PMOS transistor (switching element), 40A on signal generator, 40B off signal generator, 41A, 41B charging circuit, 42A, 42B comparator, 45A, 45B comparison circuit, 50A one-shot pulse generator, 60, 60A Current converter, 70, 70A, 70B, 70C Current signal generator, 80, 80A constant current generator, 90 RS latch circuit, 120 OTA, I1 first current signal, I2 second current signal, Ia conversion current, Ics constant Current, Imd correction current, PG, PG , PCB, PGC, PGD pulse generator, Soff off signal, Son-on signal, Toff off time, Ton on time, Vin input voltage.

Claims (9)

Including a switching element, comprising a conversion circuit that converts an input DC voltage into a DC voltage having a magnitude corresponding to a ratio between an on time and an off time of the switching element and outputs the converted DC voltage;
The switching element is turned off when the on signal is deactivated, and is turned on when the off signal is deactivated,
A control circuit for controlling on / off of the switching element;
The control circuit includes:
An on signal generation unit for generating the on signal;
An off signal generation unit for generating the off signal,
The on signal generation unit activates the on signal from the time when the off signal is deactivated until the time corresponding to the on time determined according to the magnitude of the input DC voltage elapses. State
The off signal generation unit activates the off signal from the time when the on signal is deactivated until the time corresponding to the off time determined according to the magnitude of the input DC voltage elapses. DC / DC converter to put into a state. The control circuit further includes:
A voltage / current converter for generating a conversion current having a current value proportional to the input DC voltage;
Based on the constant current having a constant current value and the conversion current, the first current signal whose current value increases as the input DC voltage increases, and the first current signal has dependency on the input DC voltage. A current signal generator that generates a different second current signal;
The on signal generation unit generates the on signal based on the first current signal,
The DC / DC converter according to claim 1, wherein the off signal generation unit generates the off signal based on the second current signal. The on-signal generator is
A first charging circuit that is charged by the first current signal and that resets a charging voltage when the off signal is deactivated;
The first charging circuit compares the charging voltage of the first charging circuit with a predetermined first reference voltage, and generates the on signal that is deactivated when the charging voltage of the first charging circuit exceeds the first reference voltage. 1 comparison circuit,
The off-signal generator is
A second charging circuit that is charged by the second current signal and whose charging voltage is reset when the ON signal is deactivated;
The second charging circuit compares a charging voltage of the second charging circuit with a predetermined second reference voltage, and generates the off signal that is deactivated when the charging voltage of the second charging circuit exceeds the second reference voltage. The DC / DC converter according to claim 2, comprising two comparison circuits. The current signal generation unit includes an operational transconductance amplifier that generates a third current signal proportional to a voltage obtained by subtracting a voltage proportional to the output voltage of the conversion circuit from a predetermined third reference voltage,
The DC / DC converter according to claim 2, wherein the current signal generation unit generates the off signal based on a signal obtained by adding the second current signal and the third current signal. The on-signal generator is
A first charging circuit that is charged by the first current signal and that resets a charging voltage when the off signal is deactivated;
The first charging circuit compares the charging voltage of the first charging circuit with a predetermined first reference voltage, and generates the on signal that is deactivated when the charging voltage of the first charging circuit exceeds the first reference voltage. 1 comparison circuit,
The off-signal generator is
A second charging circuit that is charged by a signal obtained by adding the second current signal and the third current signal, and a charging voltage is reset when the ON signal is deactivated;
The second charging circuit compares a charging voltage of the second charging circuit with a predetermined second reference voltage, and generates the off signal that is deactivated when the charging voltage of the second charging circuit exceeds the second reference voltage. The DC / DC converter according to claim 4, comprising two comparison circuits. The DC / DC converter is a boost converter that boosts the input DC voltage.
The current signal generation unit generates the conversion current as the first current signal, and generates a current obtained by subtracting the conversion current from the constant current as the second current signal. The DC / DC converter according to any one of 5. The DC / DC converter is a step-down converter that steps down the input DC voltage,
The current signal generation unit generates a signal obtained by subtracting the constant current from the converted current as the first current signal, and generates the constant current as the second current signal. The DC / DC converter according to any one of 5.   3. The DC / DC according to claim 2, wherein the voltage / current conversion unit switches a conversion rate when converting the input DC voltage to the conversion current according to a target value of the DC voltage output from the conversion circuit. converter. An output voltage detector that detects a DC voltage output from the converter circuit;
The control circuit further includes:
A comparison circuit that compares the DC voltage detected by the output voltage detector with a predetermined fourth reference voltage and outputs a comparison result;
A latch circuit that is in a set state when the on signal is activated and is in a reset state when the off signal is activated;
The comparison result by the comparison circuit and the output signal of the latch circuit are received, and when the DC voltage detected by the output voltage detector is equal to or lower than the fourth reference voltage, the output signal of the latch circuit is turned on of the switching element. The DC / DC converter according to claim 1, further comprising a gate circuit that is passed as a control signal for controlling OFF.

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