JP2012029415A - Dc-dc converter and switching control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve power efficiency of a switching regulator type DC-DC converter on a light load.SOLUTION: A switching control circuit comprises: an error amplifier (21) that outputs voltage in response to a feedback voltage; a first current detection circuit (26a) that outputs a current proportional to a current flowing through a driving switching element; a second current detection circuit (26b) that outputs a current proportional to a current flowing through a rectifier element; a waveform generator (23) that generates a waveform signal having a slope according to an amount of a current obtained by combining a current outputted from these current detection circuits with a current from a constant current source; a first voltage comparison circuit (22) to which the error amplifier output and the waveform generator output are applied; a second voltage comparison circuit (24) that compares the waveform generator output and a predetermined voltage; and a drive control circuit (25) that generates off/on driving signals of the driving switching element based on the output of these voltage comparison circuits.

Description

  The present invention relates to a switching regulator type DC-DC converter for converting a DC voltage and a switching control circuit thereof, and performs DC-DC driving by changing a switching frequency and a pulse width according to the magnitude of a current flowing through a load. The present invention relates to an effective technology applied to a converter.

  There is a switching regulator type DC-DC converter as a circuit for converting a DC input voltage and outputting DC voltages of different potentials. In such a DC-DC converter, a driving switching element that applies a DC voltage supplied from a DC power source such as a battery to an inductor (coil) to flow current and accumulate energy in the coil, and the driving switching element is turned off. There is a DC-DC converter provided with a rectifying element that rectifies the current of the coil during the energy release period and a control circuit that controls on and off of the driving switching element.

  Conventionally, in the switching regulator type DC-DC converter, the magnitude of the output voltage is detected by an error amplifier and fed back to a PWM (pulse width modulation) comparator or PFM (pulse frequency modulation) comparator. When the output voltage decreases, the on-time of the switching element is lengthened, and when the output voltage increases, the on-time of the switching element is shortened.

In PWM control, the period (frequency) of the drive pulse is made constant and the pulse width is changed according to the output voltage. Therefore, the pulse width becomes narrower as the load becomes lighter. However, when the load becomes very light, there may be a case where there is too much output current even when driving with a pulse having the minimum pulse width.
Therefore, as shown in FIG. 5, both the PWM comparator 22 and the PFM comparator 24 are provided, and the PWM control is normally performed. When the current flowing through the load is reduced, that is, when the load is light, it is driven with a fixed pulse having a constant pulse width. There is also a DC-DC converter that shifts to PFM control in which the cycle is changed according to the load. As an invention related to such a DC-DC converter, there is one described in Patent Document 1, for example.
The PWM control is also performed in an insulating switching power supply device using a transformer. As an invention related to such a power supply device, there is one described in Patent Document 2, for example.

JP 2003-219637 A JP 2002-252979 A

  In the PFM control mode at the time of light load in the DC-DC converter that switches the PWM control and the PFM control as shown in FIG. 5 to drive the switching element, as shown in FIG. When the reference voltage Vref2 is exceeded, the output of the PFM comparator 24 changes to a low level (timing t1 in FIG. 6B). Then, the output of the inverter changes to a high level, opens the AND gate G1, and supplies a pulse from the pulse generation circuit 31 that generates a pulse with a fixed pulse width to the switching elements SW1 and SW2 via the selector 29 and turns on. To drive off.

  In the PWM / PFM switching type DC-DC converter of FIG. 5, the switching frequency is reduced and the switching loss is reduced at light load, so that the power efficiency at light load is lower than that of the DC-DC converter only with PWM control. There is an advantage that can be improved.

However, in the DC-DC converter as shown in FIG. 5, even if the load is constant in the light load PFM control mode, the output of the error amplifier 21 changes as shown in FIG. In the lower period T1, as shown in FIG. 6E, the gate input voltage of the switching element SW1 is at a high level, so that SW1 is turned off for a relatively long time. Since the off period of SW1 is different every time, the ripple (variation width) of the output voltage varies, and the ripples become large.
Although the PWM control operates in heavy load, the PWM control has a fixed period. Therefore, in the PWM control mode, there is a problem that the ripple increases as the duty increases. Moreover, the conventional DC-DC converter that switches the mode between PWM and PFM has a problem that malfunction and characteristic deterioration are likely to occur due to a delay in switching the mode.

  Furthermore, the pulse generated by the pulse generation circuit 31 in FIG. 6 is generally designed so that the pulse width is fixed and the duty is 50% at maximum, that is, the on time and the off time are the same. The duty is limited, that is, when the input voltage falls below a certain level, the duty of the pulse does not increase any more, so that the current flowing through the coil is insufficient and the desired output voltage cannot be obtained, and switching is performed to allow more current to flow. It has been found that there is a problem that the number of times increases and power efficiency decreases.

The present invention has been made paying attention to the above-described problems. The object of the present invention is to improve the power efficiency at the time of light load and heavy load and improve the power efficiency in a switching regulator type DC-DC converter. It is an object of the present invention to provide a control technique capable of reducing output ripple during load.
Another object of the present invention is to provide a control technique for obtaining a desired output voltage in a switching regulator type DC-DC converter in a lower input voltage range as compared with the prior art.

In order to achieve the above object, the present invention
A switching control circuit that generates and outputs an off / on drive signal of a driving switching element that causes a current to flow through an inductor for voltage conversion,
An error amplification circuit that outputs a voltage corresponding to the feedback voltage;
A first current detection circuit for detecting a current flowing through the driving switching element and outputting a current proportional to the current;
A second current detection circuit for detecting a current flowing through a rectifying element connected in series with the driving switching element and outputting a current proportional to the current;
A capacitive element that is charged by a current obtained by synthesizing a current output from the first current detection circuit and the second current detection circuit and a current of a constant current source; and a discharging unit that can discharge the charge of the capacitive element. A waveform generation circuit for generating a waveform signal having a slope according to the magnitude of the combined current;
A first voltage comparison circuit that receives the output of the error amplification circuit and the output of the waveform generation circuit;
A second voltage comparison circuit for comparing the output of the waveform generation circuit with a predetermined voltage;
And a drive control circuit for generating an on / off drive signal for the drive switching element based on the output of the first voltage comparison circuit and the output of the second voltage comparison circuit.

  According to the above means, since the cycle of the waveform signal generated by the waveform generation circuit is changed according to the current flowing through the driving switching element and the current flowing through the rectifying element, the driving switching element is turned off. The frequency of the ON drive signal is changed according to the output current, the first voltage comparison circuit compares the output of the error amplification circuit and the output of the waveform generation circuit, and the drive control circuit outputs the first voltage. Since the ON / OFF timing of the driving switching element is determined based on the output of the comparison circuit, the pulse width of the driving switching element OFF / ON driving signal changes according to the output voltage. Therefore, when the output current is small, the switching frequency can be reduced to avoid a reduction in power efficiency, and when the input voltage is reduced, the on-time of the driving switching element is lengthened, so that the input voltage is considerably reduced. However, a desired output voltage can be obtained. In addition, when the load is heavy, the output frequency of the DC-DC converter can be reduced by increasing the switching frequency.

  Preferably, the drive control circuit determines an off timing of the drive switching element based on an output of the first voltage comparison circuit, and the drive control circuit determines the drive based on an output of the second voltage comparison circuit. The on-timing of the switching element is determined. As a result, a control loop capable of variably controlling the switching frequency and the pulse width of the drive signal according to the output voltage and the output current can be easily constructed.

  Preferably, the drive control circuit includes a flip-flop in which an output of the first voltage comparison circuit is input to a reset terminal or a set terminal, and an output of the second voltage comparison circuit is input to a set terminal or a reset terminal. It is configured by a circuit. As a result, a circuit capable of determining the on-timing and off-timing of the driving switching element can be realized with a simple circuit, and the design becomes easy.

  Further preferably, the discharge means of the waveform generating circuit is configured by a field effect transistor, and the transistor is controlled to be turned on and off by the output of the second voltage comparison circuit so that the charge of the capacitive element can be discharged. To do. As a result, a waveform generation circuit can be configured with one transistor and one capacitor, which facilitates circuit design and reduces the chip size when the occupied area is reduced to form an IC.

Preferably, each of the driving switching element and the rectifying element is a field effect transistor, and the first current detection circuit receives a source voltage and a drain voltage of the driving switching element as a first voltage-current conversion circuit. The second current detection circuit is constituted by a second voltage-current conversion circuit that receives the source voltage and drain voltage of the rectifying element, and the first voltage-current conversion circuit and the second voltage-current conversion. The circuit is configured such that a source voltage and a drain voltage when the corresponding transistor is turned on are input and a current corresponding to the voltage difference is output. Thereby, the current proportional to the output current can be accurately generated, and the accuracy of the switching control can be improved.
Here, the first voltage-current conversion circuit and the second voltage-current conversion circuit can be configured by a voltage input-current output type differential amplifier. As a result, a voltage-current conversion circuit can be realized using a known circuit, so that circuit design can be easily performed.

  Further preferably, there is provided switch means for flowing or blocking the currents of the first voltage-current conversion circuit and the second voltage-current conversion circuit into the waveform generation circuit. Thus, for example, PWM control is normally performed by generating a fixed frequency waveform signal using the current of a constant current source, and the output current from the voltage-current conversion circuit is added or subtracted at light load or heavy load Thus, by generating the waveform signal, it is possible to perform variable control of the frequency and the pulse width, and the efficiency in both the light load state and the heavy load state can be improved.

  Furthermore, the switching control circuit configured as described above, an inductor for voltage conversion, a driving switching element for passing a current through the inductor, and rectifying the coil current during a period in which the driving switching element is off. And a smoothing capacitor connected to the output terminal, and a voltage obtained by dividing the voltage at the output terminal is input as a feedback voltage to the error amplifier circuit. Thereby, a DC-DC converter with small output ripple can be realized.

  According to the present invention, in a switching regulator type DC-DC converter, it is possible to improve power efficiency at light load and heavy load and reduce output ripple at heavy load. In addition, there is an effect that a desired output voltage can be obtained up to a lower input voltage range than in the prior art.

It is a circuit block diagram which shows one Embodiment of the DC-DC converter to which this invention is applied. It is a timing chart which shows the mode of the change of the signal of each part and electric potential in the DC-DC converter of embodiment of FIG. It is a circuit block diagram which shows the 1st modification of the switching control circuit which comprises the DC-DC converter of embodiment of FIG. It is a circuit block diagram which shows the 2nd modification of the switching control circuit which comprises the DC-DC converter of embodiment of FIG. It is a circuit block diagram which shows the structure of the DC / DC converter of the conventional PWM / PFM switching system. It is a timing chart which shows the mode of the change of the signal of each part and electric potential in the conventional DC / DC converter of a PWM / PFM switching system.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.
FIG. 1 shows an embodiment of a switching regulator type DC-DC converter to which the present invention is applied.

  The DC-DC converter of this embodiment includes a coil L1 serving as an inductor, a voltage input terminal IN to which a DC input voltage Vin is applied, and one terminal of the coil L1, and a P channel for passing a current through the coil L1. A driving transistor SW1 as a switching element composed of a MOSFET (insulated gate field effect transistor), a rectifying transistor SW2 composed of an N-channel MOSFET connected in series with SW1 between the voltage input terminal IN and the ground point, A switching control circuit 20 that controls on / off of the transistors SW1 and SW2 and a smoothing capacitor C1 connected between the other terminal of the coil L1 and a ground point are provided.

  Although not particularly limited, among the elements constituting the DC-DC converter, elements other than the coil L1 and the smoothing capacitor C1 are formed on a semiconductor chip, and the switching control circuit 20 and the transistors SW1 and SW2 are integrated in a semiconductor integrated circuit. It is configured as a circuit (power supply driving IC), and the coil L1 and the capacitor C1 are connected as external elements to external terminals provided in the IC.

  In the DC-DC converter of this embodiment, the switching control circuit 20 generates a drive signal that complementarily turns on and off the transistors SW1 and SW2. In the steady state, the drive transistor SW1 Is turned on, the DC input voltage Vin is applied to the coil L1 and a current directed to the output terminal flows to charge the smoothing capacitor C1. When the driving transistor SW1 is turned off, the rectifying transistor SW2 is turned on instead. Then, a current is supplied to the coil L1 through the turned-on transistor SW2. Then, the pulse width and frequency of the drive signal input to the control terminal (gate terminal) of SW1 are controlled according to the output, so that the DC output voltage Vout obtained by stepping down the DC input voltage Vin is generated.

  The switching control circuit 20 of this embodiment is connected in series between an output feedback terminal FB and a ground point and divides the output voltage Vout by a resistance ratio, and the bleeder resistors R1 and R2 divide the output voltage Vout. An error amplifier 21 that compares the compressed voltage with the reference voltage Vref1 and outputs a voltage corresponding to the potential difference; a first comparator 22 that outputs an output of the error amplifier 21 to an inverting input terminal; It has a waveform generation circuit 23 that generates a sawtooth waveform signal RAMP input to the non-inverting input terminal.

  The switching control circuit 20 includes a second comparator 24 in which the output of the waveform generation circuit 23 is input to the non-inverting input terminal and the reference voltage Vref2 is input to the inverting input terminal, and the output of the second comparator 24 is set to the set terminal. RS flip-flop 25 having an input and an output of the first comparator 22 input to a reset terminal, and the transistors SW1 and SW2 are turned on and off by the output QN of the flip-flop 25. . Accordingly, the flip-flop 25 functions as a drive control circuit. Normally, a driver is provided at the subsequent stage of the flip-flop 25, but in FIG. 1, the output stage of the flip-flop 25 is configured as a driver.

  Further, the switching control circuit 20 of this embodiment includes a current detection amplifier 26a for detecting the switch current on the P channel side, a current detection amplifier 26b for detecting the switch current on the N channel side, and a drive. A switch MOS transistor Q1 that transmits the source voltage of the transistor SW1 to the inverting input terminal of the current detection amplifier 26a; a switch MOS transistor Q2 that transmits the drain voltage of the rectification transistor SW2 to the non-inverting input terminal of the current detection amplifier 26b; A selector 27 (changeover switch) is provided for transmitting the source voltage or drain voltage of the driving transistor SW1 to the non-inverting input terminal of the current detection amplifier 26a. The current detection amplifiers 26a and 26b are composed of, for example, a gm amplifier (voltage input-current output type differential amplifier), and function as a voltage-current conversion circuit.

  The voltage difference generated when the output QN of the flip-flop 25 is applied to the gate terminal of the switch MOS transistor Q2, which is the same as the voltage applied to the gate terminal of the rectifying transistor SW2, and the drain current flows when the rectifying transistor SW2 is turned on. Is detected by the current detection amplifier 26b. That is, the current detection amplifier 26b outputs a current proportional to the drain current that flows when the rectifying transistor SW2 is turned on.

On the other hand, a ground potential is applied to the gate terminal of the switch MOS transistor Q1 so that it is always turned on, and its drain terminal is connected to the inverting input terminal of the current detection amplifier 26a. The source voltage is applied to the inverting input terminal of the current detection amplifier 26a. The selector 27 is switched by the output QN of the flip-flop 25, and while the drive transistor SW1 is turned on, the drain voltage of SW1 is transmitted to the non-inverting input terminal of the current detection amplifier 26a, and SW1 is turned off. During this time, the source voltage of SW1 is transmitted to the non-inverting input terminal of the current detection amplifier 26a.
That is, the current detection amplifier 26a detects a voltage difference generated when the driving transistor SW1 is turned on and the drain current flows, and outputs a current proportional to the drain current flowing when the SW1 is turned on. While SW1 is off, the selector 27 supplies the same voltage to the two input terminals of the current detection amplifier 26a, and the output current of the current detection amplifier 26a becomes zero.

Similarly to the drive transistor SW1, the output QN of the flip-flop 25 may be applied to the gate terminal of the switch MOS transistor Q1, and the drain voltage of Q1 may be applied to the inverting input terminal of the current detection amplifier 26a. However, since the operation speed of the P-channel MOS is slower than that of the N-channel MOS, the ground potential is applied to the gate terminal of the switch MOS transistor Qs1 so that the drive transistor SW1 is always turned on. In addition, by inputting the source voltage and the drain voltage to the current detection amplifier 26a, it is possible to cause the current detection amplifier 26a to output a current proportional to the drain current flowing when SW1 is turned on without causing a delay.
Incidentally, since the currents flowing through SW1 and SW2 are proportional to the load current IL, the output currents of the current detection amplifiers 26a and 26b are proportional to the load current IL. The driving transistor SW1 and the rectifying transistor SW2 are each provided with a MOS transistor connected in a current mirror, and a current proportional to the current flowing through the SW1 and SW2 is supplied. The current is detected by the current detection amplifiers 26a and 26b. You may comprise so that it may do.

The waveform generation circuit 23 includes a constant current source CS1 and a capacitor C2 connected in series between a power supply voltage terminal and a ground point, and a discharge N-channel MOS transistor Q3 connected in parallel with the capacitor C2. Has been. The output terminal of the second comparator 24 is connected to the gate terminal of the transistor Q 3, and Q 3 is on / off controlled by the output of the second comparator 24.
The output terminal of the current detection amplifiers 26a and 26b is connected to the connection node N2 between the capacitor C2 and the transistor Q3. The capacitor C2 is connected to the current of the constant current source CS1 and the output current of the current detection amplifiers 26a and 26b. It is configured to be charged with a current obtained by adding (or subtracting). The potential of the connection node N2 is input to the non-inverting input terminals of the first comparator 22 and the second comparator 24.

As a result, when the transistor Q3 is turned off by the output of the second comparator 24, the waveform generation circuit 23 is charged with the capacitor C2, the potential V2 of the node N2 rises, and the potential V2 of the node N2 becomes the reference voltage Vref2. When it reaches, the output of the second comparator 24 changes to high level and the transistor Q3 is turned on. As a result, the charge of the capacitor C2 is discharged, the potential V2 of the node N2 falls sharply, and V2 has a waveform that changes in a sawtooth shape as shown in FIG.
This sawtooth wave is supplied to the non-inverting input terminals of the first comparator 22 and the second comparator 24. The slope of the waveform when the potential V2 of the node N2 rises is proportional to the combined current obtained by adding or subtracting the output currents of the current detection amplifiers 26a and 26b to the current of the constant current source CS1, and the slope increases as the combined current increases. Is steep, and the slope becomes gentler as the combined current becomes smaller.

  Next, the operation of the switching control circuit 20 will be described with reference to the timing chart of FIG. In FIG. 2B, what is indicated by V error is the output voltage of the error amplifier 21, and this voltage V error and the potential V 2 of the node N 2 are input to the first comparator 22.

  When the load current IL is small as in the periods T1 and T3 shown in FIG. 2A, the potential V2 of the node N2 gradually increases as shown in FIG. 2B, and V2 is the output voltage Verror of the error amplifier 21. 2, the output of the first comparator 22 changes from the low level to the high level as shown in FIG. 2C, the RS flip-flop 25 is reset, and the gate drive signal GP1 becomes the low level as shown in FIG. To high level (timing t1).

Thereafter, when the potential V2 of the node N2 further rises and reaches the reference voltage Vref2 that is the discrimination level of the second comparator 24, the output of the second comparator 24 changes to a high level as shown in FIG. The RS flip-flop 25 is set, and the gate drive signal GP1 changes from the high level to the low level as shown in FIG. 2E (timing t2). At the same time, the transistor Q3 is turned on and the capacitor C2 is discharged, whereby the potential V2 of the node N2 falls sharply.
Then, the output of the first comparator 22 changes from high level to low level. Further, since the output of the second comparator 24 also changes to a low level, a short pulse-like waveform is obtained as shown in FIG. By repeating the above operation, the switching operation of the driving transistor SW1 is repeatedly performed. Further, the rectifying transistor SW2 is turned on and off complementarily with SW1 by the drive signal GP1.

  As in the period T2 shown in FIG. 2A, when the load current IL is large, the circuit operation itself is the same as when the IL is small, but the output currents of the current detection amplifiers 26a and 26b increase. , The gradient of the potential V2 of the node N2 increases. As a result, the pulse width of the gate drive signal GP1 of the drive transistor SW1 is narrowed, but at the same time the cycle is shortened, and the drive transistor SW1 is driven on and off with such a pulse.

  Further, when the load fluctuates and the output voltage Vout changes, the output Verror of the error amplifier 21 changes accordingly, thereby changing the pulse width of the gate drive signal GP1. Specifically, for example, during periods T1 and T3 shown in FIG. 2A, during the period when the load is small and Verror of the error amplifier 21 is low, the pulse of the output of the first comparator 22 as shown in FIG. The width is wide and the off period of SW1 becomes longer and the cycle becomes longer. On the other hand, during the period when the load is large and the Verror of the error amplifier 21 is high as in the period T2 shown in FIG. 2A, the pulse width of the output of the first comparator 22 becomes narrow, and the low level period of the gate drive signal GP1. That is, the ON period of the driving transistor SW1 becomes longer and the cycle becomes shorter.

  As described above, in the DC-DC converter according to this embodiment, both the pulse period and pulse width of the drive signal are controlled in accordance with the load variation. For this reason, for example, when the input voltage drops, the duty is not limited, and when the load current is small, the switching frequency is lowered, thereby reducing the number of switchings and avoiding the decrease in efficiency due to the through current. Will come to be. Further, when the load is increased, the switching frequency is increased and the period is shortened, so that there is an advantage that ripple (variation in output voltage) is reduced.

(Modification 1)
Next, a modification of the switching control circuit and the DC-DC converter of the above embodiment will be described with reference to FIG.
In the modification shown in FIG. 3, an on / off switch SW3 is provided between the output terminals of the current detection amplifiers 26a and 26b and the waveform generation circuit 23 in the embodiment of FIG. In this modification, when the switch SW3 is turned on, the output currents of the current detection amplifiers 26a and 26b are supplied to the waveform generation circuit 23, and the switching control circuit 20 operates exactly the same as the control circuit of the embodiment of FIG. The driving transistor SW1 is driven with a variable pulse whose frequency and pulse width change according to the output (first mode).

  On the other hand, when the switch SW3 is turned off, the output currents of the current detection amplifiers 26a and 26b are not supplied to the waveform generation circuit 23, and the waveform generation circuit 23 operates only with the current of the constant current source CS1, and has a fixed duty pulse. Is generated. As a result, the PWM transistor operates in the same manner as the PWM control mode in the PWM / PFM switching type DC-DC converter shown in FIG. 6, and the driving transistor SW1 has a fixed frequency and a pulse width that changes according to the output voltage. Driven by PWM pulse (second mode).

  The signal for controlling the switch SW3 can be configured to be supplied from a control circuit such as an external CPU. Therefore, in this modification, for example, the CPU that controls the entire system changes the control signal according to the state of the load to turn on the switch SW3 and does not use the output current of the current detection amplifiers 26a and 26b (the first mode). By switching from the (2 mode) to the mode (first mode) in which the output currents of the current detection amplifiers 26a and 26b are used, the switching frequency and the pulse width can be made to change according to the load.

  Further, instead of inputting the control signal of the switch SW3 from the outside, an input voltage detection circuit is provided for detecting whether or not the input voltage Vin is equal to or lower than a predetermined level, and the input voltage Vin is equal to or higher than a predetermined level. In this case, the supply of the output currents of the current detection amplifiers 26a and 26b to the waveform generation circuit 23 is cut off, and when the input voltage Vin becomes lower than or higher than a predetermined level, the output of the current detection amplifiers 26a and 26b. You may comprise so that an electric current may be supplied to the waveform generation circuit 23. FIG.

(Modification 2)
FIG. 4 shows a second modification of the switching control circuit of the above embodiment.
The second modification shown in FIG. 4 is a MOS transistor that is current-mirror connected to the driving transistor SW1 and the rectifying transistor SW2, respectively, instead of the MOS transistors Q1 and Q2 functioning as switch elements in the embodiment of FIG. Q1 ′ and Q2 ′ and current detection resistors Rs1 and Rs2 connected in series with these transistors Q1 ′ and Q2 ′ are provided, and both terminal voltages of the resistors Rs1 and Rs2 are respectively set as current detection amplifiers 26a, 26b is configured to output current corresponding to the voltage difference.

  Note that the MOS transistor Q1 'is a P-channel type, and Q2' is an N-channel type, and each size is one-tenth or hundredth of the size of the driving transistor SW1 and the rectifying transistor SW2. However, the size ratio between SW1 and Q1 'and the size ratio between SW2 and Q2' are the same. In the switching control circuit of the second modification example, a current value proportional to the current value flowing through the driving transistor SW1 and the rectifying transistor SW2 is detected in substantially the same manner as the switching control circuit of the embodiment of FIG. A sawtooth-shaped waveform signal RAMP having a slope corresponding to the magnitude of the load current is generated by the waveform generation circuit 23 and supplied to the comparators 22 and 24, and the pulse width and frequency change according to the magnitude of the load current. The driving transistor SW1 can be switched and driven by generating a pulse.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment. For example, in the above-described embodiment, on-chip elements are used as the switching elements SW1 and SW2, but external elements formed separately from the control IC may be used. In the above embodiment, the synchronous rectification type DC-DC converter is shown in which the rectification transistor SW2 is connected in series with the drive transistor SW1 and turned on and off complementarily with the SW1, but instead of the rectification transistor SW2 It is also possible to apply to a diode rectification type DC-DC converter using a diode.

  Furthermore, in the embodiment, an RS flip-flop having a set terminal and a reset terminal is used as the flip-flop 25, but another type of flip-flop may be used. Further, the switch transistors SW1 and SW2 are turned on / off by the output of the flip-flop 25, but the so-called dead time is prevented so that through current does not flow in the subsequent stage of the flip-flop 25 because SW1 and SW2 are simultaneously turned on. A drive signal generation circuit for generating a gate drive signal having the above may be provided.

  In the above description, the present invention is applied to a step-down DC-DC converter. However, the present invention is not limited thereto, and a step-up DC-DC converter or a negative voltage is generated. The present invention can also be applied to an inverting DC-DC converter.

20 switching control circuit 21 error amplifier 22 first comparator 23 waveform generation circuit 24 second comparator 25 flip-flop (drive control circuit)
26a, 26b Current detection amplifier 27 Selector (changeover switch)
L1 coil (inductor)
C1 Smoothing capacitor SW1 Coil driving transistor (driving switching element)
SW2 Synchronous rectifier transistor (rectifier switching element)
CS1 constant current source

Claims (8)

A switching control circuit that generates and outputs an off / on drive signal of a driving switching element that causes a current to flow through an inductor for voltage conversion,
An error amplification circuit that outputs a voltage corresponding to the feedback voltage;
A first current detection circuit for detecting a current flowing through the driving switching element and outputting a current proportional to the current;
A second current detection circuit for detecting a current flowing in a rectifying element connected in series with the driving switching element and outputting a current proportional to the current;
A capacitive element that is charged by a current obtained by synthesizing a current output from the first current detection circuit and the second current detection circuit and a current of a constant current source; and a discharging unit that can discharge the charge of the capacitive element. A waveform generation circuit for generating a waveform signal having a slope according to the magnitude of the combined current;
A first voltage comparison circuit that receives the output of the error amplification circuit and the output of the waveform generation circuit;
A second voltage comparison circuit for comparing the output of the waveform generation circuit with a predetermined voltage;
A drive control circuit for generating an off / on drive signal for the drive switching element based on an output of the first voltage comparison circuit and an output of the second voltage comparison circuit;
A switching control circuit comprising:   The drive control circuit determines an off timing of the driving switching element based on an output of the first voltage comparison circuit, and an on timing of the driving switching element based on an output of the second voltage comparison circuit. The switching control circuit according to claim 1, wherein the switching control circuit is configured to determine   The drive control circuit includes a flip-flop circuit in which an output of the first voltage comparison circuit is input to a reset terminal or a set terminal, and an output of the second voltage comparison circuit is input to a set terminal or a reset terminal. The switching control circuit according to claim 2, wherein:   The discharge means of the waveform generation circuit is constituted by a field effect transistor, and the transistor is controlled to be turned on and off by an output of the second voltage comparison circuit, and is configured to be able to discharge the charge of the capacitive element. The switching control circuit in any one of 1-3. Each of the driving switching element and the rectifying element is a field effect transistor,
The first current detection circuit is constituted by a first voltage-current conversion circuit that receives a source voltage and a drain voltage of the driving switching element,
The second current detection circuit is constituted by a second voltage-current conversion circuit that receives a source voltage and a drain voltage of the rectifier element as inputs.
The first voltage-current conversion circuit and the second voltage-current conversion circuit are each configured to input a source voltage and a drain voltage when the corresponding transistor is turned on and output a current corresponding to the voltage difference. The switching control circuit according to claim 1, wherein the switching control circuit is provided.   6. The switching control circuit according to claim 5, wherein the first voltage-current conversion circuit and the second voltage-current conversion circuit are configured by a voltage input-current output type differential amplifier.   7. The switching according to claim 5, further comprising switch means for flowing or blocking currents of the first voltage-current conversion circuit and the second voltage-current conversion circuit into the waveform generation circuit. Control circuit.   Inductor for voltage conversion, driving switching element for passing current through the inductor, rectifying element for rectifying coil current while the driving switching element is off, and smoothing capacitor connected to the output terminal And a switching control circuit according to any one of claims 1 to 7, wherein a voltage obtained by dividing the voltage of the output terminal is input to the error amplifier circuit as a feedback voltage. DC converter.

Images