JP5597963B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a high voltage power MOSFET (field-effect transistor having a metal-oxide film-semiconductor structure), which is an insulated gate semiconductor device used for a power conversion device such as an inverter or an RF (Radio Frequency, high frequency) power amplifier, And IGBT (Insulated Gate Bipolar Transistor).

  In an RF power amplifier for a radio base station, a semiconductor device is used to amplify the power of a signal supplied to an antenna. A semiconductor device currently used for an RF power amplifier is mainly a lateral MOSFET, that is, an LDMOS (Lateral Diffused MOS). LDMOS has several features. The first feature is that the source region and the drain region can be formed in a self-aligned manner (self-alignment) with respect to the gate electrode. Therefore, the overlapping portion between the gate electrode and the source region or between the gate electrode and the drain region is reduced, and the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) which are parasitic capacitances due to the area of the overlapping portion. ) Can be reduced. Such a parasitic capacitance becomes an input capacitance (Ciss) or a feedback capacitance (Crss), and causes an increase in switching loss of the MOSFET. Therefore, it is indispensable to reduce the parasitic capacitance in the high frequency operation of the MOSFET. The second feature is that the source region formed on the surface is connected to the back surface of the chip via a deep p-type diffusion layer (usually called a sinker). The back side of the chip is connected on the metal plate of the package. When the package metal plate is at ground potential, if this p-type sinker is used, a wire connecting the source on the chip surface and the metal plate at the ground potential of the package becomes unnecessary. For this reason, deterioration of the amplification characteristics of the MOSFET due to the parasitic inductance or parasitic resistance of the wire can be prevented.

    These characteristics become remarkable when compared with VDMOS (Vertical Diffused MOS) which is a vertical MOSFET. That is, in the case of VDMOS, the drain region that occupies the back side of the chip is not formed in a self-aligned manner with respect to the gate electrode. For this reason, the area of the overlapping portion between the gate electrode and the drain region increases, and Cgd increases. In general, in the VDMOS, a drain electrode is formed on the back surface of the chip. For this reason, when it fixes to a package, the back surface of a chip | tip is connected on the metal plate of drain electric potential. When the metal plate on the package is at the ground potential, it is necessary to insulate with an insulating film having high thermal conductivity between the back surface of the chip and the metal plate serving as the ground. In addition, in order to connect the source electrode on the chip surface to the metal plate having the ground potential of the package, connection with a wire is required. For this reason, amplification characteristics deteriorate due to parasitic inductance and parasitic resistance due to wire connection.

For the above reasons, LDMOS is widely applied as a switching element of an RF power amplifier.
LDMOS is used in various other applications. For example, there is an electric relay. In the case of a device that requires a plurality of electrical relays, the LDMOS as the electrical relay and the circuit for driving and controlling the LDMOS are both formed on one semiconductor chip, thereby reducing the cost. The electrical relay is required for the LDMOS to have a low conduction resistance (on-resistance) when a current is flowing, because of the demand for downsizing the device due to low power consumption and low heat generation.

    On the other hand, VDMOS has a merit that resistance at the time of current conduction is lower than LDMOS, and is suitable for downsizing of a chip. As described above, in the LDMOS, both the source electrode and the drain electrode are formed on the surface. Therefore, since the current path is limited to a depth of about several μm from the surface, the cross-sectional area of the path is reduced, and as a result, the electrical resistance during conduction is increased. Therefore, LDMOS is generally not suitable for medium / high current applications (1 ampere or more). However, the VDMOS has a drain electrode provided on the back surface of the semiconductor substrate and the current path is formed along the depth direction of the chip. Therefore, the electrical resistance during conduction can be reduced, and it can be used for medium and large currents (1 ampere or more). Is also applicable. Therefore, if VDMOS can be applied to an RF power amplifier, the device can be easily downsized. Furthermore, since the length of the gate electrode can be shortened by this miniaturization, the gate resistance is lower than that in the case of using the LDMOS, and the deterioration of the high frequency characteristics due to the gate resistance can be reduced. Moreover, if it can be used as an electric relay, the application apparatus can be reduced in size.

    However, considering that such an applied device is composed of VDMOS, the drain region cannot generally be selectively formed because the drain electrode is on the back surface of the semiconductor chip. Therefore, it is impossible to dispose a plurality of VDMOSs on one chip and provide drain electrodes corresponding to the respective VDMOSs, and it is difficult to apply VDMOSs to high-frequency RF amplifiers and electric relays. .

    In order to achieve miniaturization of high-frequency RF amplifiers and electrical relays, a conventional VDMOS called a source electrode and a gate electrode selectively formed on the chip surface, and a drain electrode formed entirely on the back surface of the chip. Instead of this structure, it is necessary to adopt a structure of a drain electrode and a gate electrode selectively formed on the chip surface and a source electrode formed entirely on the back surface of the chip. Hereinafter, the VDMOS having such a structure is referred to as a back source type VDMOS. Several proposals have been made in the past for the structure of the back source type VDMOS.

For example, Patent Document 1 shown in FIGS. 7-1, 7-2, and 7-3 discloses the following structure. FIG. 7A is a cross-sectional view corresponding to the active portion of the back source type VDMOS. The source electrode 5 and the n ⁺ source region 4 are formed on the back surface side (the lower side of the paper surface) of the semiconductor chip, and the drain electrode 9 and An n ⁺ drain region 8 is formed on the front side of the chip. A p base region 28 is formed in contact with the n ⁺ source region 4, and a p ⁻ base region 29 is formed in contact with the p base region 28. A trench gate 1 is provided at the bottom of the trench via a gate oxide film 3, and a PSG film 30 is embedded in the upper portion of the trench. An n ⁻ drift region 6 is formed in a self-aligned manner with respect to the gate electrode 1 on the trench side wall facing the PSG film. Therefore, the gate electrode 1 and the n ⁻ drift region 6 do not overlap with each other and the gate-drain capacitance is reduced. Further, FIG. 7-2 is a plan view showing the drain electrode 9 and the base / source short-circuited portion 31, but the base / source short-circuited portion 31 is disposed away from the drain electrode 9 of the active portion. A cross-sectional view of the base-source short-circuit portion 31 is shown in FIG. A groove reaching the n ⁺ source region 4 from the chip surface is provided, and a base-source short-circuit line 34 is embedded in the groove using a conductor. Therefore, the p ⁻ base region 29, the p base region 28 and the n ⁺ source region 4 are short-circuited by the base / source short-circuit line 34.

    In Patent Document 2 shown in FIG. 8, in addition to the trench 100 in which the gate electrode 104 is formed, a trench 108 in which a metal electrode 110 that electrically connects the source region 92 and the base region 95 is embedded is provided at the bottom. A cross-sectional structure is shown. The electrode 110 is disposed only at the bottom of the trench 108 so as not to contact the drift region formed over the entire chip surface, and an insulator 112 is provided on the remaining portion of the upper portion of the trench 108. . The n-type drift region 96 is stacked on the p-type base region 95.

Patent Document 3 shown in FIG. 9 discloses the following cross-sectional structure. A drain electrode 75 is formed on the upper surface of the chip, and a source electrode 76 is formed on the lower surface of the chip. A p base region 51 is formed on the n ⁺ source region 50, and an n drift region is formed on the p base region 51. An n ⁺ drain region 52 is formed on the n drift region and is in contact with the drain electrode 75. On the upper surface of the chip, trenches 60 and 62 for the gate electrode 67 and a trench 61 for shorting the base and the source are formed. The inside of the trench corresponding to the upper portion of the gate electrode 67 is in contact with the n drift region, and an oxide film 69 is buried. On the other hand, a conductive layer 71 is provided at the bottom of the base / source short-circuiting trench 61 so as to short-circuit the n ⁺ source region 50 and the p base region 51, and the conductive layer 71 includes the p base region 51. It is formed to the inner height. Over the conductive layer 71, an insulating oxide film 72 is buried up to the top surface of the chip.

JP 2003-51598 A JP-A-4-212469 US Pat. No. 7,323,745

  In general, a short circuit between a base region and a source region of a MOSFET is provided in order to prevent a bipolar transistor (hereinafter referred to as a parasitic BJT) in the drain region-base region-source region parasitic on the MOSFET from operating. When the MOSFET is turned off, the space charge region spreads from the pn junction between the base region and the source region, so that holes serving as a displacement current flow in the p-type base region toward the source electrode. At this time, if the base region and the source region are not short-circuited, all holes are injected into the n-type source region, so that electrons are also injected into the p-type base region. Since the pn junction between the base region and the drift region is always in a reverse bias state, the concentration of electrons injected into the p-type base region is attenuated, but a part of the pn junction is between the base region and the drift region. Then, it flows into the space charge region formed and is accelerated. That is, since electrons flow into the drift region without passing through the MOS gate, the gate controllability is lost and a latch-up state is established. In order to prevent the occurrence of this latch-up state, the base region and the source region are short-circuited.

  However, in the case of the structure shown in Patent Document 1, the base region and the source region are active regions (regions where MOSFETs are formed, and regions in the chip seen through the drain electrode 9 in FIG. 7-2). It is short-circuited in the remote region 31. Therefore, at the time of turn-off, holes flowing from the unit cell of the MOSFET farthest from the short-circuit portion 31 in the active portion move in the p base region 28 toward the short-circuit portion 31 over a very long distance. At this time, a voltage drop occurs in the path through which the holes flow due to the resistance of the p base region 28. When this voltage drop exceeds the built-in voltage of the pn junction between the base region and the source region, the aforementioned latch-up occurs. That is, when the base region and the source region are short-circuited at a portion away from the active portion as shown in FIG. 7-2, if the distance is long, the short-circuiting effect is lost, and latch-up of the parasitic BJT at the turn-off easily occurs. End up.

  On the other hand, the structures shown in Patent Documents 2 and 3 have a configuration in which an n-type drift region is stacked over the entire surface of a chip on a p-type base region. Therefore, it is necessary to etch back the conductor deeply over the thickness of the n-type drift region after depositing the conductor for short-circuiting (metal such as aluminum) inside the trench for shorting the base and the source. Also, the conductor must not contact the n-type drift region. This is because the n-type source region and the n-type drain region are short-circuited through the drift region. Therefore, the upper surface of the short-circuit conductor is higher than the height of the pn junction between the n-type source region and the p-type base region and lower than the height of the pn junction between the base region and the n-type drift region. Must be set. Furthermore, when the gate is off, the depletion layer extending from the pn junction between the p-type base region and the n-type drift region to the inside of the p-type base region must not contact the short-circuit conductor. Therefore, the upper surface of the short-circuit conductor does not have to be merely in the p-type base region, but the upper surface of the conductor must be lower than the lower end of the depletion layer. Therefore, the metal must be etched back so that the upper surface of the conductor is in such a narrow range. If a slight etch-back defect occurs in a part of the chip, the n-type drift region and the n-type source region are short-circuited, resulting in a breakdown voltage failure between the drain electrode and the source electrode. Therefore, it is very complicated to form the conductor in the short-circuit trench, and it is very difficult to form the short-circuit trench that requires deep etch back. Also, an insulator for insulating the conductor from the drain electrode must be embedded from the upper surface of the chip to the upper surface of the conductor deeply etched back, which further complicates the production.

      The present invention has been made in view of the above circumstances, and solves at least one of the above-described problems, and provides a back-source type semiconductor device capable of high-frequency operation with low loss and a method for manufacturing the same.

In order to achieve the above object, the configuration of the present invention is as follows.
(1) a first conductivity type source region;
A source electrode connected to the lower surface of the source region;
A second conductivity type first base region provided adjacent to an upper surface of the source region;
A second conductivity type second base region provided adjacent to an upper surface of the first base region and having a lower concentration than the first base region;
A first trench that penetrates the second base region and the first base region from the upper surface of the second base region and reaches the inside of the source region;
A gate insulating film provided inside the first trench,
A gate electrode is provided inside the gate insulating film, and an upper end portion of the gate electrode has a height such that the gate electrode covers the second base region;
A first conductivity type drift region is provided between the sidewall of the first trench and the second base region from the upper surface portion of the second base region along the first trench sidewall , and the drift region Lower end of the gate electrode is lower than the upper end of the gate electrode,
An insulator is provided on the gate electrode,
The upper surface of the insulator is deeper than the upper surface of the second base region, and the upper surface of the insulator and the upper surface of the gate insulating film are flush with each other,
Exposing the first trench sidewall above the top surface of the insulator;
A first conductivity type drain region having a concentration higher than that of the drift region is formed between the sidewall portion of the first trench and the drift region along the first trench sidewall from the upper surface portion of the second base region. And
The lower end of the drain region extends below the upper end of the insulator in the trench,
Having a first insulating film provided on an upper surface of the second base region,
The second trench is arranged in parallel with the first trench, penetrates the second base region and the first base region from the upper surface of the second base region, reaches the inside of the source region, and is separated from the drift region. Having a trench,
It has a conductor which connects the both or either the source region of the first base region at the inside of the second trench and the second base region,
A second insulating film provided on an upper portion of the conductor,
Said first contact and said drain region in the exposed portion of the trench sidewall, having a first Ri written on the upper surface of the insulating film, the buried until insulator upper surface to said first trench drain electrodes Rukoto And
(2) In the semiconductor device described in (1) above, it is preferable that a second conductivity type collector region is formed in a sidewall portion of the first trench in the drain region.
(3) In the semiconductor device according to (1) or (2), the integrated concentration in the diffusion direction of the drift region is 8.0 × 10 ¹¹ / cm ² or more and 1.2 × 10 ¹² / cm ² or less. And good.
(4) In the semiconductor device according to any one of (1) to (3), an integrated concentration of the first and second base regions is 1.2 × 10 toward the source region from the lower end of the drift region. It is good that they are ¹² / cm ² or more and 1.0 × 10 ¹⁴ / cm ² or less.
(5) In the semiconductor device according to any one of (1) to (4), the concentration of the second base region may increase from the upper surface of the second base region toward the source region. .
(6) In the semiconductor device according to any one of (1) to (5), the first trench may be arranged in a honeycomb structure.
(7) In the semiconductor device according to any one of (1) to (6), the first base region or the second base region is adjacent to the bottom of the second trench and the top surface of the source region. It is preferable that a second conductivity type contact region having a high concentration be formed.

(8) In the semiconductor device according to (1) or (2), the first base region is formed over the entire sidewall portion of the second trench, and the first base in the sidewall portion of the second trench is formed. when d ₁ the distance between the region and the drift region, the distance between the first base region in contact with the upper surface of the source region and the drift region and the d _2, longer d ₂ than d ₁ Good.

(9) In the semiconductor device described in (1) or (2) above, an insulator on the semiconductor substrate is used instead of the source electrode connected to the lower surface of the source region, and the conductor inside the second trench is the source. It may be connected to the electrode.
(10) In the semiconductor device according to (1), a second conductivity type region in contact with the drain region is provided in the drift region on a side wall portion of the first trench, and the second conductivity type region is grounded. It is preferable to be connected to a potential.

  According to the structure of the present invention, the voltage drop when holes flow in the p-type base region when the VDMOS is turned off is sufficiently small by arranging the short-circuit trench separated from the drift region in parallel with the gate trench. Therefore, latch-up of the parasitic BJT can be suppressed. Further, by forming the n-type drift region on the side wall of the gate trench, it is not necessary to form the layer of the n-type drift region on the entire surface of the wafer or chip. As a result, it becomes unnecessary to deeply etch back the conductor inside the short-circuiting trench. In addition, strict restrictions on the height of the upper surface of the conductor in the conventional structure are not required in the structure of the present invention. That is, it is only necessary that the n-type source region and the p-type base region are short-circuited through the conductor on the side wall of the short-circuit trench, and the conductor is in contact with the drain electrode formed on the upper surface portion of the chip. If not, it ’s good. As a result, manufacturing becomes much easier.

It is principal part sectional drawing of the semiconductor device concerning Example 1 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. It is principal part sectional drawing of the semiconductor device concerning Example 3 of this invention. It is principal part sectional drawing of the semiconductor device concerning Example 4 of this invention. It is a principal part top view of the semiconductor device concerning Example 4 of this invention. It is principal part sectional drawing of the semiconductor device concerning Example 5 of this invention. It is principal part sectional drawing of the semiconductor device concerning Example 6 of this invention. It is principal part sectional drawing of the semiconductor device of a prior art example. It is a principal part top view of the semiconductor device of a prior art example. It is principal part sectional drawing of the semiconductor device of a prior art example. It is principal part sectional drawing of the semiconductor device of a prior art example. It is principal part sectional drawing of the semiconductor device of a prior art example. It is an enlarged view of the principal part cross-section part in the semiconductor device concerning Example 2 of this invention. It is an enlarged view of the principal part cross-section part in the semiconductor device of a prior art example. It is principal part sectional drawing of the semiconductor device concerning Example 7 of this invention. It is a principal part top view of the semiconductor device concerning Example 6 of this invention. It is a top view of this part in the example which changed a part of Example 6 of this invention. It is a principal part top view in the example which changed a part of Example 6 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 8 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 8 of this invention. It is principal part sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 8 of this invention.

  Embodiments of the invention will be described in the following examples. Hereinafter, the first conductivity type will be described as n-type, and the second conductivity type will be described as p-type. However, the present invention can be similarly realized even if the n-type and p-type are interchanged.

FIG. 1 is a cross-sectional view of an essential part in Embodiment 1 of a back source type VDMOS of the present invention. An n ⁺ source region 4 made of a high concentration n-type substrate of 1.0E18 atoms / cm ³ or more is provided, and the lower surface of the n ⁺ source region 4 is connected to the source electrode 5. Here, 1.0E18 means 1.0 × 10 ¹⁸ . A first p ⁺ base region 2 a is provided adjacent to the upper surface of the n ⁺ source region 4. Wherein the upper surface of the 1p ⁺ base region 2a, a 2p of lower concentration than the first 1p ⁺ base region 2a ^- base regions 2b are disposed adjacent to each. A first trench is provided in a stripe shape in a direction perpendicular to the paper surface so as to penetrate from the upper surface of the second p ⁻ base region 2 b to the n ⁺ source region 4. A gate insulating film 3 is formed. A gate electrode 1 made of a conductor such as polysilicon is provided inside the gate insulating film 3. The upper end portion of the gate electrode 1 is arranged at a height over the inside of the second p ⁻ base region 2b. An n drift region 6 is formed in the side wall portion of the first trench. The lower end of the n drift region 6 is configured to extend from the upper surface of the second p ⁻ base region 2b to a position lower than the upper end portion of the gate electrode, and is separated from the first p ⁺ base region 2a. . An insulator 7 is provided on the gate electrode 1. Further, an n ⁺ drain region 8 is formed so as to be sandwiched between the sidewall portion of the first trench and the n drift region 6. The lower end of the n ⁺ drain region 8 is shallower than the lower end of the n drift region 6. An interlayer insulating film 10 is provided on the upper surface of the second p ⁻ base region 2b. And a second trench is arranged in the first trench, the trench of said second claim 2p ^- wherein the upper surface of the base region 2b the 2p ^- the base region 2b first 1p ⁺ base region 2a and the It penetrates to the n ⁺ source region 4 and is separated from the n drift region 6. A conductor 12 is embedded in the second trench so as to be connected to the n ⁺ source region 4, the first p ⁺ base region 2a, and the second p ⁻ base region 2b. An insulator 7 is provided on the conductor 12. A drain electrode 9 is formed on the upper surfaces of the interlayer insulating film 10 and the insulator 7. The drain electrode 9 is in contact with the n ⁺ drain region 8 in the upper part of the first trench, and is separated from the conductor 12 formed in the second trench through the insulator 7. doing.

The inversion layer channel of the MOS gate is opposed to the gate electrode 1 through the gate oxide film 3 on the trench side walls of the second p ⁻ base region 2 b and the first p ⁺ base region 2 a by controlling the potential of the gate electrode 1. Formed as follows. The impurity concentration distribution of the first p ⁺ base region 2a gradually increases in the direction from the drain electrode 9 on the front surface toward the source electrode 5 on the rear surface. By making the p-type base region have such a concentration distribution, the channel resistance is reduced as compared with the p-type base region having a uniform concentration distribution in the depth direction. As a result, since the transconductance of VDMOS can be increased, the on-resistance can be reduced. The threshold value of the MOS gate is determined by the point that the net doping concentration of the first p ⁺ base region 2a is maximized. Also, the integrated concentration value (also referred to as Gummel index) when the concentrations of the second p ⁻ base region 2b and the first p ⁺ base region 2a are integrated over the depth direction from the lower end of the n drift region 6 to the n ⁺ source region 4. Is set to a value (1.2E12 atoms / cm ² or more) at which the depletion layer extending inside the second p ⁻ base region 2b and the first p ⁺ base region 2a does not punch through to the n ⁺ source region 4 when turned off. On the other hand, if the threshold value of the MOS gate becomes too high, the transconductance becomes low. For example, when the gate drive voltage is ± 15V, the threshold value of the MOS gate is preferably 5 to 7V. In this case, the maximum net doping concentration of the first p ⁺ base region 2a is preferably about 2.0E16 atoms / cm ³ . At this time, if the length from the lower end of the n drift region 6 to the upper surface of the n ⁺ source region 4 is about 2 μm for the second p ⁻ base region 2b and the first p ⁺ base region 2a, the value of the integrated concentration is 1. Since 0E14 atoms / cm ² , this value should not be exceeded.

Further, since the impurity concentration of the second p ⁻ base region 2b is sufficiently low, the concentration distribution control of the low concentration n drift region 6 can be easily performed. Here, the first p ⁺ base region 2a and the second p ⁻ base region 2b may be a continuous region (that is, one p base region), and the above-described integrated concentration only needs to satisfy the above value. .

The n drift region 6 is provided so as to diffuse laterally from the side wall of the first trench. As will be described later, since the n drift region 6 is ion-implanted after the gate electrode 1 is etched back by, for example, polysilicon, the lower end of the n drift region 6 is self-aligned with the upper surface of the gate electrode 1. Therefore, the area where the n drift region 6 and polysilicon (gate electrode 1) overlap can be made sufficiently small, so that the gate-drain capacitance (Cgd) can be reduced. Also, the integrated value of the impurity concentration in the diffusion depth direction (left and right direction on the paper surface) of the n drift region 6 is 8.0E11 / cm ² or more and 1.2E12 / cm ² or less, preferably 1.0E12 / cm ² . For example, the so-called RESURF (Reduced Surface Electric Field) effect can increase the impurity concentration per unit volume of the n drift region 6, while reducing the resistance (drift resistance) of the n drift region 6. Since the length in the depth direction of 6 can be reduced, both low on-resistance and high breakdown voltage can be realized. Here, when the integrated value of the impurity concentration is 8.0E11 / cm ² or less, the concentration of the n drift region 6 becomes smaller than about 1.0E15 / cm ³ , and the on-resistance reduction effect is almost lost. Similarly, when the integrated value of the impurity concentration is 1.2E12 / cm ² or more, the breakdown voltage is determined by the electric field strength at the pn junction parallel to the side wall formed by the n drift region 6 and the second p ⁻ base region 2b when OFF. The pressure resistance is drastically reduced. Therefore the integral value of the impurity concentration in the diffusion depth of the n drift region 6, the above 8.0E11 / cm ² or more 1.2E12 / cm ² or less.

Further, in the first embodiment, when the gate is in the OFF state, the depletion layer extending inside the n drift region 6 and the second p ⁻ base region 2b is formed in the vicinity of the side wall of the first trench and the second p ⁻ base region 2b. It differs from the vicinity of the upper surface (that is, the upper surface portion of the chip). That is, in the vicinity of the side wall of the first trench, the depletion layer extending in the direction perpendicular to the side wall extends wider in the n drift region 6 than in the second p ⁻ base region 2b. Whereas the 2p ^- in the vicinity of the upper surface of the base region 2b, the depletion layer extending parallel to the upper surface, the 2p ^- spread wider than the internal n drift region 6 towards the interior of the base region 2b. The reason is that the n drift region 6 is formed so as to be self-aligned with the upper surface of the gate electrode 1 and diffused laterally from the side wall of the first trench. As a result, on the upper surface of the second p ⁻ base region 2 b, the applied voltage can be supported not by the n drift region 6 but by the depletion layer of the second p ⁻ base region 2 b. Therefore, even if the concentration of the n drift region 6 is further increased, a high breakdown voltage can be maintained, and the concentration of the n drift region 6 can be increased, so that the on-resistance can also be reduced.

In order to suppress the latch-up of the parasitic BJT at the time of turn-off, the n ⁺ source region 4 is composed of the high concentration first p ⁺ base region 2a and the low concentration second p ^{− in the} conductor 12 filled in the second trench. It is electrically short-circuited with the base region 2b.

Here, the first embodiment of the present invention is characterized in that the conductor 12 is provided after forming the gate electrode 1 of the first trench and the insulator 7 in contact with the upper surface thereof, as will be described later in the second embodiment. is there. Originally, the short-circuit conductor 12 is intended to short-circuit the n ⁺ source region 4 and / or the first p ⁺ base region 2a or the second p ⁻ base region 2b, and therefore may be at the bottom of the trench. . However, in the conventional back source type VDMOS, the layer of the n drift region 6 must be formed over the entire surface of the chip or wafer on the upper surface of the p-type base region as thick as necessary to maintain the withstand voltage. In addition, the short-circuit conductor 12 must not contact the n drift region 6. This is because the pn junction between the second p ⁻ base region 2b and the n drift region 6 must hold the power supply voltage applied between the drain and source when turned off. Therefore, the upper surface of the short-circuiting conductor 12 must be lower than the lower end of the drift region, for example, 110 in FIG. 8 or 71 in FIG. 9, and the conductor (metal) filled in the second trench. Must be etched back to that depth.

  On the other hand, in the first embodiment of the present invention, since the n drift region 6 is formed on the first trench sidewall as described above, the n drift region 6 is formed over the entire upper surface of the p type base region as in the conventional type. No need to form. Therefore, the conductor 12 filling the second shorting trench can be separated from the drain electrode 9 by the interlayer insulating films 7 and 10 without contacting the n drift region 6. From the above, as a result of the configuration of the present invention, it is possible to form the second trench for short-circuiting with a significant reduction in the number of processes.

In addition, various forms are possible for forming the conductor 12 in the second trench. For example, since the conductor 12 does not contact the n drift region 6, as will be described later in Example 2, the conductor 12 is insulated from the insulator 7 formed on the upper portion of the gate electrode 1. It is possible to fill up to the same height as the upper surface of the body 7. This method is the most simple method for forming the conductor 12 because the amount of etch back may be small, and has the configuration of the second trench and the conductor 12 shown in FIG. In addition, a metal (aluminum, titanium nitride, platinum, etc.) having a thickness smaller than half the width of the second trench is formed on the side wall inside the second trench, and the remaining void is made of an insulator or polysilicon (dope) However, it may be configured by a method of embedding with a conductive material or non-doped high resistance material. The metal only has to serve as a conductor 12 for short-circuiting the n ⁺ source region 4 and / or the first p ⁺ base region 2a and / or the second p ⁻ base region 2b. May be formed, or may not reach the upper end. Alternatively, the conductor 12 may be embedded only in the bottom of the second trench, and most of the inside of the second trench may be filled with the insulator 7. In any case, it suffices if either or both of the first p ⁺ base region 2a and the second p ⁻ base region 2b and the n ⁺ source region 4 are short-circuited via the conductor 12, and the conductor It is sufficient if 12 is not in contact with the drain electrode 9 when the chip is completed.

  Further, since the second trench only needs to have a width that can be filled with the conductor 12, the second trench can be narrower than the first trench, and as a result, the chip itself can be reduced in size.

  A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to cross-sectional views at respective manufacturing steps shown in FIGS. The difference between the second embodiment and the first embodiment is that a thick oxide film 15 is provided at the bottom of the first trench.

(FIG. 2-1) An n-type silicon substrate used as the n ⁺ source region 4 is used as a semiconductor substrate. As the silicon substrate 4, a bulk cut wafer such as a CZ wafer or an FZ wafer is used. Here, a control circuit and a passive element are formed in the same process or different processes in a region where the VDMOS is not formed on the upper surface of the wafer. A first p ⁺ base region 2a and then a second p ⁻ base region 2b are formed on the upper surface of the wafer by epitaxial growth. At this time, the distribution of the impurity doping concentration of the first p ⁺ base region 2a may be uniform, but the distribution gradually increases from the upper surface of the second p ⁻ base region 2b toward the n ⁺ source region 4 as described above. It is good to be.

(FIG. 2-2) Next, a thermal oxide film 10 is formed on the wafer surface (the upper surface of the second p ⁻ base region 2b). Thereafter, patterning is performed to open a part of the thermal oxide film 10. Subsequently, anisotropic etching of silicon is performed to form a first trench 14 in the opening. Thereafter, well-known sacrificial oxidation or the like is performed to remove etching damage remaining on the side wall of the trench 14. The depth of the first trench 14 is set so that the bottom of the first trench 14 reaches the inside of the n ⁺ source region 4.

  (FIG. 2-3) Next, a thick oxide film 15 is formed only at the bottom of the trench 14. The thick oxide film 15 may be a thermal oxide film by a well-known LOCOS (Local Oxidation of Silicon) or an oxide film formed by CVD (Chemical Vapor Deposition). By forming such a thick oxide film, the gate-source capacitance Cgs can be reduced. Thereafter, the gate oxide film 3 is formed over the entire inner wall of the trench. This gate oxide film may also be a thermal oxide film or a deposited film.

(FIG. 2-4) Next, polysilicon 16 which becomes the gate electrode 1 is deposited in the trench 14, and the inside of the trench 14 is filled with the polysilicon 16.
(FIG. 2-5) Subsequently, the polysilicon 16 in the trench 14 is etched back to a desired depth. This depth is about the depth of the n drift region 6 to be formed later. At this time, the polysilicon deposited on the wafer surface is removed.

(FIG. 2-6) Next, the n drift region 6 is formed so as to be self-aligned with the polysilicon gate electrode 1 on the inner wall of the first trench. Specifically, it is formed as follows. An ion implantation 36 of phosphorus or the like is performed at an angle from the surface to the inner wall of the first trench. At this stage, phosphorus ions are implanted in a range from the surface side (upper side of the drawing) of the side wall portion of the first trench to the upper surface of the gate electrode 1 in which the polysilicon of the portion is embedded. The acceleration energy at the time of ion implantation is set to such a value that the implanted phosphorus ions penetrate the gate oxide film 3 and stop in the thermal oxide film 1. For example, the n drift region 6 is formed by performing heat treatment at a temperature of about 1000 ° C. to 1050 ° C. and a time of about several seconds to 30 minutes. In FIG. 10A, the partial cross section of the 1st trench of Example 2 is expanded and displayed. However, the description of the first p ⁺ base region 2a and the n ⁺ source region 4 is omitted. By performing the treatment in this way, in the n drift region 6, the width parallel to the wafer surface becomes the diffusion depth of phosphorus by the ion implantation 36 and the heat treatment, and is about 0.5 to 1.0 μm. As a result, the depth of the overlapping portion 37 (overlapping portion 37 in FIG. 10-1) where the lower end of the n drift region 6 reaches the depth of the polysilicon (gate electrode 1) in the first trench is overlapped. 6 or less, which is about 80% (0.4 to 0.8 μm) of the phosphorus diffusion depth.

FIG. 10-2 (a) is an enlarged cross-sectional view of a conventional trench 14. Further, FIG. 10-2 (b) shows a net doping concentration distribution in the depth direction corresponding to FIG. 10 (a). For example, when the n drift region 6 is formed by ion implantation from the surface and thermal diffusion or epitaxial growth as in this conventional example, the lower end of the n drift region 6 is made of the polysilicon (gate electrode 1) of the trench 14. A depth 37 is reached so that a portion 37 is formed which overlaps the upper end of the polysilicon. At this time, in order to supply electrons from the inversion layer channel formed on the trench sidewall of the first p base region 2b with a low resistance toward the n drift region 6, the maximum net doping concentration of the overlapping portion 37 is, for example, A concentration of 1.0E14 / cm ³ or more is required. For example, if the n drift region 6 has a concentration of 5.0E14 / cm ³ and a diffusion depth of 2 μm, the portion 37 that reaches the polysilicon depth of the first trench 14 and overlaps with it is 1 A depth of about 0.0 to 1.5 μm is required, and the overlapping portion 37 must be made longer than the case shown in FIG. Therefore, in the case of the second embodiment, the length (area in the chip) of the overlapping portion 37 can be reduced to about 50% as compared with the conventional structure. As a result, the gate-drain capacitance (Cgd) can be reduced by about 50%.

(FIG. 2-7) Subsequently, a material to be an insulator, for example, a BPSG film is deposited so as to fill a gap above the polysilicon (gate electrode 1).
(FIG. 2-8) Thereafter, a resist is applied, patterning is performed by exposure and development so that the resist remains in the interlayer insulating film 10, and the insulator 7 is etched. Here, the finished depth of the upper end surface of the insulating film by etching is approximately the depth of the lower end of the n ⁺ drain region 8 to be formed later. Then, the resist is removed.

(FIG. 2-9) Next, the n ⁺ drain region 8 is formed so as to be self-aligned with the upper surface of the insulator 7 described above. Specifically, it is formed as follows. An ion implantation 36 of phosphorus or the like is performed at an angle from the surface to the inner wall of the first trench. At this stage, phosphorus ions are implanted in a range from the surface side (upper side of the drawing) of the side wall portion of the first trench to the upper surface of the insulator 7 described above. Then, the n ⁺ drain region 8 is formed by performing heat treatment at a temperature of about 950 ° C. to 1000 ° C. and a time of about several seconds to 30 minutes, for example.

(FIG. 2-10) Next, the thermal oxide film 10 on the upper surface of the second p ⁻ base region 2b is patterned, and an opening 26 is formed in a part of the thermal oxide film 10 by etching.
(FIG. 2-11) Subsequently, anisotropic etching of silicon is performed to form a second trench 35 in the opening 26. Thereafter, known sacrificial oxidation or heat treatment at about 900 ° C. to 1000 ° C. may be performed to remove etching damage remaining on the side wall of the second trench 35. The depth of the second trench 35 is set so that the bottom of the trench reaches the inside of the n ⁺ source region 4.

  (FIG. 2-12) Subsequently, the conductor 12 (for example, aluminum or its alloy, refractory metal such as titanium nitride or platinum, or polysilicon doped in high concentration n-type or p-type) is formed in the second trench. 35 is filled.

  (FIG. 2-13) Subsequently, the conductor 12 is etched back. The amount of etch back at this time may be such that the conductor 12 does not remain on the upper surface of the insulator 7 and the surface of the thermal oxide film 10 in the first trench 14.

(FIG. 2-14) Next, for example, a silicon nitride film 7 is deposited as an interlayer insulating film on the wafer surface, and the silicon nitride film 7 is patterned to leave the silicon nitride film 7 only on the second trench 35. Etch. A conductor mainly composed of aluminum is deposited on the wafer surface, and a drain electrode 9 is formed by patterning and etching.
(FIG. 2-15) Finally, the source electrode 5 is formed on the lower surface of the n ⁺ source region 4 corresponding to the rear surface of the wafer by depositing aluminum, titanium, nickel, gold or the like.

    FIG. 3 is a sectional view showing a semiconductor device according to Example 3 of the present invention. The difference from the first embodiment is that a p-type region 11 connected to the ground potential is disposed inside the n drift region 6 on the side wall side of the first trench. In order to connect the p-type region 11 to the ground potential, a conductor 12 connected to the ground via an insulator 7 is disposed on the gate electrode 1 in the trench, and the conductor 12 and the p-type region 11 are connected. Connect. On the conductor 12, the drain electrode 9 and the insulator 7 for insulating the conductor 12 are disposed. Due to the presence of the p-type region 11, the depletion layer spreads from two directions with respect to the n drift region 6 when the voltage is held. That is, a depletion layer spreads from two junctions, a pn junction formed by the n drift region 6 and the first p base region 2 b and a pn junction formed by the n drift region 6 and the p-type region 11. Due to the RESURF effect in both pn junctions, the impurity concentration of the n drift region 6 can be further increased, and the on-resistance can be further reduced. This is generally referred to as a double RESURF structure.

FIG. 4A is a cross-sectional view illustrating the semiconductor device according to the fourth embodiment of the present invention. The difference between the back source type VDMOS of the fourth embodiment and the first embodiment is that the source region is formed on the upper surface of an SOI (Silicon on Insulator) substrate in which the insulator 4 is provided on the semiconductor substrate 19 in the fourth embodiment. That is. In this case, the source electrode terminal (source pad) is formed on the surface of the chip. FIG. 4-2 is a plan view of the semiconductor device of Example 4 when viewed from the top surface of the chip. A cross-sectional view taken along the line from position A ₁ to position A ₂ described in FIG. 4-2 corresponds to FIG. A portion of the drain pad 22 corresponds to the VDMOS portion of FIG. A drain electrode 9 made of aluminum or the like formed on the upper surface of the VDMOS portion is connected to the drain pad 22. The gate pad 21 is made of a conductor such as aluminum and is connected to the gate electrode 1 formed of the polysilicon or the like at the end of the first trench. Similarly, the source pad 23 is made of a conductor such as aluminum. The source electrode of the VDMOS part is made of a conductive material such as aluminum filled in the second trench at the end of the second trench 35 (on the side opposite to the gate pad 21). Connected with the body. As a set of VDMOSs shown in FIG. 4B, several VDMOS parts are arranged on the SOI substrate, and the respective VDMOS regions are insulated by known dielectric isolation or junction isolation. This makes it possible to use the VDMOS even in a state where the potential of the source electrode 4 is relatively high, that is, the so-called high side.

FIG. 5 is a sectional view showing a semiconductor device according to Example 5 of the present invention. The difference from the first embodiment is that the first p ⁺ base region 2 a is formed along the side wall of the second trench in addition to the upper surface of the n ⁺ source region 4. The distance between the first p ⁺ base region 2a and the n drift region 6 in the side wall portion of the second trench is d ₁ , and the distance between the first p ⁺ base region 2a in contact with the upper surface of the n ⁺ source region 4 and the drift region is d. when a _2, a longer d ₂ than d _1. Therefore, the avalanche breakdown that occurs when a voltage corresponding to the withstand voltage is applied between the drain and source electrodes occurs _first from the depletion layer that spreads in the direction of d ₁ . Holes generated by impact ionization at the time of avalanche voltage breakdown flow into the conductor 12 formed inside the second trench through the first p ⁺ base region 2a in the second trench sidewall. Accordingly, no holes are generated around the pn junction formed by the first p ⁺ base region 2a and the n ⁺ source region 4 due to avalanche breakdown. That is, by setting d ₂ longer than d ₁ in this way, it is possible to suppress the occurrence of latch-up in the parasitic BJT portion including the low-concentration second p ^- base region due to the hole current generated by the avalanche breakdown. It becomes.

Further, since there is the first p ⁺ base region 2a on the side wall of the second trench, a depletion layer extending in the second p ⁻ base region 2b in the off state reaches the conductor 12 formed in the second trench. A through state can be prevented. As a result, the distance between the first trench and the second trench can be reduced, and the pitch of the unit cell (the basic element of the repetitive pattern on the upper surface of the chip) can be reduced, thereby further reducing the on-resistance. it can.

  FIG. 12A is a top plan view of the sixth embodiment. The difference from the first embodiment is that the distribution pattern on the chip upper surface of the first trench 14 and the second trench 35 is not a stripe pattern but a dot pattern pattern. A cross-sectional view when the cross section is cut from positions A1 to A2 in FIG. 12 corresponds to FIG. For example, the first trench 14 has a circular shape as shown in FIG. 12-1, or a polygonal or circular ring shape (or also called a donut shape) as shown in FIG. 35 is a circle, and the first trench and the second trench are arranged in a triangular lattice pattern on the upper surface of the chip. A unit cell in FIG. 12A is a portion 27 surrounded by a thick broken line in the figure. When the unit cell is arranged as shown in FIG. 12A, the ratio of the area of the second trench in the unit cell 27 is 10% or less, and an extremely low on-resistance can be achieved without impairing the latch-up resistance. It becomes. Further, as shown in FIG. 13, by adopting a honeycomb structure as the first trench arrangement shape, it is not necessary to arrange a gate runner on the chip upper surface necessary for the structure of FIG. That is, in FIG. 12A, when the gate electrode 1 embedded in each first trench is connected between the first trenches and connected to the gate pad as shown in FIG. A structure in which a polysilicon layer is separately formed on the upper surface and the gate electrodes 1 in the respective first trenches are connected to each other, that is, a so-called gate runner is required. However, if the first trench is arranged in a honeycomb structure as shown in FIG. 13, the first trench and the gate electrode 1 in the first trench can all be connected on the chip, so the gate runner is unnecessary. It becomes. Therefore, it is possible to achieve the same effect as FIG. 12-1 with a simpler design. Similarly to the first embodiment, the width of the second trench may be narrower than that of the first trench.

FIG. 11 is a cross-sectional view showing a semiconductor device according to Example 7 of the present invention. The difference from the first embodiment is that the seventh embodiment has an IGBT (insulated gate bipolar transistor) structure. That is, the drain electrode 9 is replaced with the collector electrode 41, the source electrode 5 is replaced with the emitter electrode 42, and the n ⁺ source region 4 is replaced with the n ⁺ emitter region 40, and the n ⁺ drain region 8 is interposed between the collector electrode 41 and the n ⁺ drain region 8. A higher concentration p ⁺ collector region 38 is provided, and the n ⁺ drain region 8 is used as an n ⁺ buffer region 39. By providing the p ⁺ collector region 38, by the same operation principle as known IGBT, since holes which are minority carriers from the p ⁺ collector region 38 are injected into the n drift region 6 when the gate electrode 1 is on, It becomes possible to achieve a lower ON resistance (ON voltage as an IGBT) by modulating the conductivity. Further, if a part of the n ⁺ buffer region 39 is short-circuited with the collector electrode 41, a reverse conducting IGBT can be obtained.

14-1, 14-2, and 14-3 are cross-sectional views showing the steps of the semiconductor device of Example 8 of the present invention and the part of the manufacturing process of Example 8 that is different from the manufacturing process of Example 2 described above. FIG. The difference from the second embodiment is that the trench etching of the second trench 35 is divided into two times, and boron (B ⁺ or BF) is formed at the bottom of the second trench 35 between the first etching and the second etching. ₂ ⁺ ) is ion-implanted and annealed (FIG. 14-1) to form the p ⁺ contact region 44 in the vicinity of the bottom of the second trench 35. As described in the first embodiment, there is an upper limit for the integrated concentration and the maximum concentration of the first p ⁺ base region 2a or the second p ⁻ base region 2b. Therefore, when the first p ⁺ base region 2a or the second p ⁻ base region 2b and the n ⁺ source region 4 are short-circuited by the conductor 12 in the second trench, the contact resistance with the conductor 12 may be increased. . Therefore, the p ⁺ contact region 44 having a higher concentration than the first p ⁺ base region 2a or the second p ⁻ base region 2b is formed so as to be shallower than the bottom of the second trench. As a process, first, the first trench etching of the second trench 35 is stopped slightly above the n ⁺ source region 4. Boron (B ⁺ or BF ₂ ⁺ ) is ion-implanted at an inclination angle of 0 ° and annealed to form a p ⁺ contact region 44 (FIG. 14-1). If the implantation angle is inclined here, it is necessary to pay attention because boron is implanted into the n ⁺ drain region 8 that has already been formed, and the n ⁺ drain region 8 is compensated. Thereafter, the second trench 35 is etched again so that the bottom of the second trench 35 reaches the n ⁺ source region 4 and is deeper than the p ⁺ contact region 44 (FIG. 14-2). . After that, the same process as in the second embodiment is performed to complete the VDMOS (FIG. 14-3). By forming the p ⁺ contact region 44 in this way, the contact resistance can be made sufficiently low without increasing the threshold value of the MOS gate.

Further, this configuration may be applied to the IGBT of the seventh embodiment. In the case of an IGBT, holes as majority carriers flow through the first p ⁺ base region 2a or the second p ⁻ base region 2b during turn-off. At this time, the hole current is several times larger than the displacement current at the time of turn-off of the MOSFET, and there is a possibility that the well-known parasitic thyristor is easily latched up. Therefore, if the p ⁺ contact region 44 as described above is formed, the voltage drop in the hole current path can be reduced, and the effect of suppressing latch-up becomes significant.

  By using a back source type VDMOSFET which is a semiconductor device of the present invention and forming it on one chip together with a control circuit and a passive element, an RFIC (Integrated Circuit) for RF power amplifier which is smaller and more efficient than conventional ones, and Is provided with a plurality of MOSFETs used as electrical relays, and an IC formed on a single chip together with a control circuit can be provided.

DESCRIPTION OF SYMBOLS 1 Gate electrode 2a 1st p ⁺ base region 2b 2nd p-base region 3 Gate oxide film 4 n ⁺ Source region 5 Source electrode 6 n Drift region 7 Insulator 8 n ⁺ Drain region 9 Drain electrode 10 Interlayer insulating film 11 P-type region 12 Conductor 14 First Trench 15 Thick Oxide Film 16 Polysilicon 21 Gate Electrode Pad 22 Drain Electrode Pad 23 Source Electrode Pad 24 Pad Opening 26 Opening 27 Unit Cell 35 Second Trench 36 Ion Implant 37 Overlap Part 38 p ⁺ collector region 39 n ⁺ buffer region 40 n ⁺ emitter region 41 collector electrode 42 emitter electrode 43 triangular lattice line 44 p ⁺ contact region

Claims (10)

A first conductivity type source region;
A source electrode connected to the lower surface of the source region;
A second conductivity type first base region provided adjacent to an upper surface of the source region;
A second conductivity type second base region provided adjacent to an upper surface of the first base region and having a lower concentration than the first base region;
A first trench that penetrates the second base region and the first base region from the upper surface of the second base region and reaches the inside of the source region;
A gate insulating film provided inside the first trench,
A gate electrode is provided inside the gate insulating film, and an upper end portion of the gate electrode has a height such that the gate electrode covers the second base region;
A first conductivity type drift region is provided between the sidewall of the first trench and the second base region from the upper surface portion of the second base region along the first trench sidewall , and the drift region Lower end of the gate electrode is lower than the upper end of the gate electrode,
An insulator is provided on the gate electrode,
The upper surface of the insulator is deeper than the upper surface of the second base region, and the upper surface of the insulator and the upper surface of the gate insulating film are flush with each other,
Exposing the first trench sidewall above the top surface of the insulator;
A first conductivity type drain region having a concentration higher than that of the drift region is formed between the sidewall portion of the first trench and the drift region along the first trench sidewall from the upper surface portion of the second base region. And
The lower end of the drain region extends below the upper end of the insulator in the trench,
Having a first insulating film provided on an upper surface of the second base region,
The second trench is arranged in parallel with the first trench, penetrates the second base region and the first base region from the upper surface of the second base region, reaches the inside of the source region, and is separated from the drift region. Having a trench,
It has a conductor which connects the both or either the source region of the first base region at the inside of the second trench and the second base region,
A second insulating film provided on an upper portion of the conductor,
The first at the exposed portion of the trench sidewall in contact with the drain region, Ri written on the upper surface of the first insulating film, a drain electrode embedded in the first trench to the insulator upper surface,
The first insulating film is a semiconductor device which is characterized that you have been sandwiched between the drain electrode and the second base region.   2. The semiconductor device according to claim 1, wherein a second conductivity type collector region is formed on a side wall portion of the first trench in the drain region. 3. The semiconductor device according to claim 1, wherein an integrated concentration in a diffusion direction of the drift region is 8.0 × 10 ¹¹ / cm ² or more and 1.2 × 10 ¹² / cm ² or less. apparatus. 4. The semiconductor device according to claim 1, wherein an integrated concentration of the first and second base regions is 1.2 × 10 ¹² / cm ² from the lower end of the drift region toward the source region. The above semiconductor device is 1.0 × 10 ¹⁴ / cm ² or less. The semiconductor device according to any one of claims 1 to 4,
The concentration of the second base region increases from the upper surface of the second base region toward the source region. The semiconductor device according to any one of claims 1 to 5,
A semiconductor device, wherein the first trench is arranged in a honeycomb structure. The semiconductor device according to any one of claims 1 to 6,
A semiconductor having a second conductivity type contact region having a higher concentration than the first base region or the second base region formed adjacent to the bottom of the second trench and the upper surface of the source region. apparatus. 3. The semiconductor device according to claim 1, wherein the first base region is formed over the entire sidewall portion of the second trench, and the first base region and the drift region of the sidewall portion of the second trench are formed. d ₁ the distance between, and the distance between the source region and the first base region and the drift region in contact with the upper surface of a d _2, characterized in that to increase the d ₂ than d ₁ Semiconductor device.   3. The semiconductor device according to claim 1, wherein an insulator on the semiconductor substrate is used instead of the source electrode connected to the lower surface of the source region, and the conductor inside the second trench is connected to the source electrode. A featured semiconductor device.   2. The semiconductor device according to claim 1, wherein a second conductivity type region in contact with the drain region in the drift region is provided in a side wall portion of the first trench, and the second conductivity type region is connected to a ground potential. A semiconductor device.

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