JP2003051598A - High frequency power MOSFET - Google Patents

Abstract

(57) [Abstract] [Purpose] A high frequency with reduced source inductance, reduced feedback capacitance, output capacitance and input capacitance and improved high frequency characteristics by forming a source electrode on the back surface and grounding the source without a bonding wire An object is to provide a power MOSFET and a method for manufacturing the same. A source electrode is formed on a back surface of a first conductivity type substrate, and a second conductivity type base layer and a second base layer are sequentially formed on the first conductivity type substrate.
A groove extending from the surface of the base layer 13 to the substrate 11 is formed, a gate electrode 23 is formed below the groove via an insulating film, and the upper and lower portions of the gate electrode 23 in the groove are filled with an insulator.
A vertical field-effect transistor in which a drift region and a source diffusion region are formed on a side surface of a groove in a self-aligned manner with respect to a gate electrode, and a drain region is formed on a surface of a second base layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used as a high frequency and high speed switching device and a power device and a method of manufacturing the same, and more particularly to a vertical insulated gate semiconductor device having a trench side surface as a current path and The manufacturing method is related.

[0002]

2. Description of the Related Art Conventionally, a vertical field effect transistor having a U groove (hereinafter referred to as U-MOSFET) is a lateral MOS.
It has advantages such as lower on-resistance and smaller chip size than FETs, and is used in various fields such as power supply field, motor control field and communication field.

FIG. 22 shows a sectional structural view of a conventional U-MOSFET. For simplification, the n channel will be described. That is, the first conductivity type is n-type and the second conductivity type is p-type. In FIG. 22, the n + substrate 119 is used as a drain region, the n− epitaxial layer 129 is used as a drift region, and the n + layer 26 formed inside the p base layer 25 is used as a source region. Further, a U groove is formed on the surface, a gate oxide film 19 is formed on the surface, and a gate electrode 23 made of polysilicon or the like is formed inside the U groove. Further, the drain electrode 21 is provided on the back surface of the n + substrate 119, and
The structure is such that the metal source electrode 22 is taken out from the + region 26.

[0004]

SUMMARY OF THE INVENTION Such a U-MOS
When using the FET as a device for high frequency and high speed switching, there are the following problems.

(1) Since the back surface is used as the drain electrode 21, a bonding wire is required to ground the source electrode 22. Therefore, the parasitic inductance Ls on the source side increases, and the frequency characteristics deteriorate. Further, as a power device for high frequency, it is necessary to consider both heat dissipation and insulation, and BeO, Al
It becomes necessary to separate the drain electrode 21 from the ground plane (source) by using an expensive high thermal conductive insulating substrate such as N.

(2) Since the gate and the drain face each other via the thin oxide film at the bottom of the U groove, the feedback capacitance (gate.
Drain capacitance) Crss is large. (3) Since the gate and source are separated by the thin gate oxide film 19,
Input capacitance (gate-source capacitance) Ciss is large.
Further, (4) since the drain and the source are connected via a wide pn junction between the base and the drain, the output capacitance (drain-source capacitance) Coss is large and the frequency characteristic is deteriorated.

FIG. 23 shows a cross-sectional structural view of an improved example of the conventional U-MOSFET. In FIG. 23, the drain region and the source region are exchanged, and the drift region 1 is formed on the base region 12.
This is a structure provided with 13. In this example, the source electrode 22
Since it is on the back side, source bonding wire is unnecessary,
The parasitic inductance Ls on the source side is reduced.
However, the feedback capacitance Crss and the output capacitance Coss are larger than those in FIG. 22, the improvement of the input capacitance Ciss is not seen, and the operation at high frequency is limited. Further, the n-p junction formed by the drift region 113 and the base region 12 is exposed at the end of the chip, and it is predicted that it is difficult to secure the drain breakdown voltage.

Therefore, an object of the present invention is to improve the feedback capacitance C by improving the shape around the gate electrode and the drift region.
It is an object of the present invention to provide a novel structure of a U-MOSFET in which the rss and the output capacitance Coss can be significantly reduced and the input capacitance Ciss can be easily reduced, and a manufacturing method thereof.

Another object of the present invention is to form a source electrode on the back surface and ground the source without using a bonding wire to reduce the source inductance, thereby significantly reducing the input capacitance, the output capacitance, especially the feedback capacitance, and at the same time, the heat radiation characteristic. To provide a structure of a U-MOSFET excellent in high frequency and high output characteristics and a manufacturing method thereof.

Still another object of the present invention is to provide a structure of a U-MOSFET having a high reproducibility by self-aligning a drift region between a gate and a drain and a method of manufacturing the U-MOSFET.

Still another object of the present invention is to provide a structure of a U-MOSFET in which the source region is determined in a self-aligned manner with the gate electrode in a self-aligned manner and the gate-source capacitance Ciss can be easily reduced, and a manufacturing method thereof. is there.

Still another object of the present invention is to provide a structure of a U-MOSFET in which the drain region and its contact region are opened in a self-aligned manner to reduce the chip size and output capacitance and to improve the high frequency characteristics, and the structure thereof. It is to provide a manufacturing method.

Still another object of the present invention is to provide a structure of a U-MOSFET and a method of manufacturing the same, which suppresses an increase in gate resistance even if a short channel is used to improve high frequency characteristics.

Yet another object of the present invention is U-MOSFE which eliminates the need for a dedicated drain wire bonding pad.
To provide a structure of T and a manufacturing method thereof.

Still another object of the present invention is to provide a structure for conducting an embedded gate electrode in silicon and a gate wiring formed on a chip surface and a method for manufacturing the same.

Still another object of the present invention is to provide a structure of a U-MOSFET having a stable high frequency characteristic by connecting a base region and a source region forming a channel, and a manufacturing method thereof.

[0017]

In order to achieve the above-mentioned object, according to the present invention, as shown in FIG. 1 as an example, the source electrode 22 is on the back surface of the first conductivity type substrate 11, and the drain electrode 21 is the first conductivity type. It is based on a vertical insulated gate transistor formed on the surface of a semiconductor region formed on the surface side of a substrate. As shown in FIG. 1, the first feature of the present invention is that the first semiconductor region 1 of the first conductivity type having a high impurity concentration serves as a source region.
1, a second semiconductor region 12 of the second conductivity type formed on the first semiconductor region 11, and a second semiconductor region 12
The third semiconductor region 13 of the second conductivity type formed on the upper part of the
And a U groove portion 31 formed so as to reach the first semiconductor region from the surface of the third semiconductor region 13, and a U groove portion 31 formed on the surface of the third semiconductor region 13 and on both sides of the U groove portion 31. No. 5, the drain region 15, the gate insulating film 19 and the gate electrode 23 formed under the U groove 31, and the fourth drift region 14 is on the gate insulating film 19 and the side surface of the U groove 31. Can be formed in other U-MO
This is a major feature different from SFET. Further, it has an insulator 17 filled in the upper portion of the gate electrode 23 and the gate insulating film 19 in the groove 31, and a substantially flat drain electrode 21 formed in the upper portion of the insulator 17 and the drain region 15. In addition, according to this structure, it is easy to thicken the oxide film at the bottom of the groove as shown in FIG. 10, and it is also easy to make the impurity distribution in the drain region in two stages as shown in FIG. . The vertical insulated gate transistor of FIG. 8 is different from the device of FIG. 1 in that the shape of the groove above the gate electrode 23 is V-shaped and the thermal oxide film 19 on the slope is left.

The second feature of the present invention is that it can be easily and stably manufactured by the process shown in FIG. (A) A second semiconductor region 12 (base region) and a third semiconductor region 13 (second base region) are continuously epitaxially grown on the first conductivity type high impurity concentration substrate 11 (source region),
A first step of forming a U-shaped groove 31 from the surface, and (b) a second step of forming a gate oxide film 19 and forming a good conductive material 23 which is buried in the bottom of the U-shaped groove and serves as a gate electrode, (C) The oxide film on the upper portion of the gate electrode 23 is removed, and an insulator 17 containing an n-type impurity and serving as a solid-phase diffusion source later is embedded in the upper portion of the gate electrode 23 in the trench to form the third semiconductor region 13 Ions of n-type high concentration impurities are implanted into the surface (I
/ I) the third step and (d) the fourth step of simultaneously forming the fourth drift region 14 and the fifth drain region 15 by applying heat treatment.

The third feature of the present invention is that the semiconductor device of FIG. 8 can be manufactured by the process shown in FIG. (A)
A second semiconductor region 12 (base region) and a third semiconductor region 13 (second base region) are continuously epitaxially grown on the first conductivity type high impurity concentration substrate 11 (source region), and a V-shaped groove 32 is formed from the surface. A first step of forming
(B) The V-shaped groove 32 is filled with an insulator 33,
Forming a U-groove 34 that reaches the substrate 11 from the surface of the second
Step (c), the insulator 33 is removed, and the gate oxide film 1 is formed.
And (d) forming a good conductive material 23 to be embedded in the bottom of the U groove and serving as a gate electrode, and forming slopes of the second and third semiconductor regions 12 and 13 in the V-shaped groove. A fourth step of implanting n-type impurity ions into (I / I),
(E) The insulator 17 is embedded in the groove above the gate electrode 23, and n-type high concentration ions are implanted into the surface of the third semiconductor region 13 (I / I) Fifth step, and (f) Heat treatment And a sixth step of simultaneously forming the fourth drift region 14 and the fifth drain region 15 are added.

The fourth feature of the present invention is as shown in FIG.
A through hole is formed on the embedded gate electrode 23, and the connection line 2
By embedding the gate electrode 4, the gate electrode 23 and the gate wiring 20 on the chip surface are electrically connected.

The fifth feature of the present invention is, as shown in FIG. 12, a first insulator 19 containing an n-type impurity at the bottom of the U groove.
9 is formed, a gate insulating film 19 and a gate electrode 23 are formed on the gate insulating film 19, and a second insulator 17 containing an n-type impurity is further embedded on the gate insulating film 19 and the gate electrode 23. The diffusion region 111 is characterized in that it can be formed in a self-aligned manner. In addition, according to this structure, it is easy to thicken the first insulator 199 at the bottom of the groove as shown in FIG. The vertical insulated gate transistor of FIG. 14 is different from the semiconductor device of FIG. 12 in that the shape of the groove is V-shaped.

The sixth feature of the present invention is that it can be easily and stably manufactured by the process shown in FIG. That is, (a) a second conductivity type second semiconductor region 12 and a third conductivity type semiconductor region 13 are continuously epitaxially grown on the first conductivity type high impurity concentration substrate 11, and a U groove portion 31 is formed from the surface. A first step of forming a first insulator 199 containing an n-type impurity at the bottom of the groove 31 and serving as a solid layer diffusion source later,
It is characterized by comprising the following four steps (b), (c), and (d) similar to FIG. 7.

As shown in FIGS. 14 and 15, the seventh feature of the present invention is that it can be easily manufactured in a V-shaped groove by a simple process.

As shown in FIGS. 16 and 17, the eighth feature of the present invention is that it can be easily manufactured by a method of selectively performing continuous epitaxial growth on the first conductivity type high impurity concentration substrate 11.

The ninth feature of the present invention is that the base region 12 on the first conductivity type high impurity concentration substrate 11 is a single layer, as shown in FIGS.

[0026]

According to the first feature of the present invention, the drift region is U
Since the groove is formed on the side surface of the groove in a shallow and low impurity concentration, the second and third semiconductor regions 12 and 13 and the fourth drift region 1 are formed.
The depletion layer of the pn junction formed in No. 4 extends into the drift region as the applied voltage increases, reaches the silicon surface, and the fifth drain region 15 and the gate electrode 23 are isolated by the depletion layer. The capacity Crss is significantly reduced. Further, the fifth drain region 15 is formed in a self-aligned manner by the U groove 31, and the area can be reduced to a range where the processing accuracy and the contact resistance with the electrode do not affect the output capacitance Coss. . Further, as shown in FIG. 4, the impurity concentration of the fourth drift region 14 and the third
If the impurity concentration and the width Ld of the semiconductor region 13 are appropriately selected, the depletion layers of the left and right pn junctions facing each other are connected to each other, so that the output capacitance Coss is significantly reduced.
As shown in FIG. 11, the drain region 15 is highly concentrated to 15
If 5 has a low-concentration two-step structure, it is effective in reducing the output capacitance Coss of the semiconductor device and the peripheral portion of FIG. As shown in FIG. 10, if the insulating film below the gate electrode is thickened, the input capacitance Ciss can be reduced. Further, the increase in gate resistance, which is a problem in shortening the channel, can be suppressed by increasing the width in the lateral direction (= the width of the groove) so as to compensate for the decrease in the gate electrode thickness. From the above, the high frequency characteristics are significantly improved. Since the source electrode 22 is formed on the bottom of the substrate,
The source is easily grounded, the source bonding wire is not required, the source inductance Ls is reduced, and the high frequency operation is facilitated. Further, the heat dissipation substrate does not need an insulating substrate, heat dissipation becomes easy, and high output can be achieved.

According to the second feature of the present invention, as shown in FIG. 7, it has a feature that it can be manufactured easily and stably. Since the fourth drift region 14 and the fifth drain region 15 are formed in a self-aligned manner, high frequency characteristics are improved.

According to the third feature, as shown in FIG. 8, since the fourth drift region 14 is formed in the V-shaped groove by the ion implantation method, the impurity concentration of the drift region 14 can be obtained with higher accuracy.

According to the fourth feature of the present invention, since the buried gate electrode 23 and the gate wiring 20 are connected by the gate connection line 24, good conduction is obtained and the controllability of the gate is improved.

According to the fifth feature of the present invention, as shown in FIG. 12, since the first thick insulating film 199 is interposed between the gate electrode 23 and the source substrate 11, the input capacitance Ciss.
Is reduced. In addition, the first insulating film 199 for the gate electrode
Since the source diffusion region 111 is formed in a self-aligned manner, the gate electrode 23 and the source diffusion region 111 do not overlap each other, and thus the input capacitance Ciss is further reduced. Since the channel length is determined by the thickness of the gate electrode 23, its variation is reduced. Further, in the structure of FIG. 14, the ion implantation method can be applied to the formation of the fourth drift region 14, and the impurity concentration of the drift region becomes more accurate.

According to the sixth feature of the present invention, as shown in FIG. 13, the first step is performed before the gate oxide film 19 is formed in the step of FIG.
It suffices to form the insulator 199, and has a feature that it can be easily and stably manufactured. Since the fourth drift region 14, the fifth drain region 15, and the sixth source diffusion region 111 are formed in a self-aligned manner, high frequency characteristics are improved.

According to the seventh characteristic, FIG. 14 and FIG.
As shown in, it can be easily and accurately manufactured in the V groove.

According to the eighth characteristic, FIG. 16 and FIG.
As shown in, the desired semiconductor device structure can be easily obtained by the selective epitaxial growth method.

According to the ninth feature, since the structure is simpler, it can be manufactured at low cost.

[0035]

1 is a block diagram of a semiconductor device according to an embodiment of the present invention. In the figure, an n-channel type will be described as an example. That is, the first conductivity type is n-type and the second conductivity type is p-type. Vertical U-MOSFET of FIG.
In, the source electrode 22 is arranged on the back surface of the n + substrate 11, and the drain electrode 21 is arranged on the surface of the epitaxial growth layer 13 above the n + substrate.

A structural feature of the semiconductor device of the present invention is that the drift region 14 is provided on the side surface of the U groove that penetrates the epitaxial layer and reaches the source region 11.
That is, the gate oxide film 1 is formed below the U groove 31 that penetrates the second base layer 13 and the base layer 12 and reaches the source region 11.
9. The buried gate electrode 23 is formed, and the fourth drift region 14 is formed on the side surface of the groove in self-alignment with the gate electrode 23. The fifth drain region 15 is also formed by the groove in a self-aligning manner. The buried gate electrode 23 may be doped polysilicon, but W, Mo, Ti may be used in high frequency operation where gate resistance is a problem.
A high melting point metal such as or a silicide thereof is preferable. Since the U-groove is filled with the insulator 17, the drain electrode 21 can be formed substantially flat, so that the upper portion of the active region can be used as the bonding pad 219. Therefore, it is not necessary to prepare a special pad, and the chip area can be reduced. The base region preferably has a fixed potential with respect to the source region. Base region 1 as shown in FIG.
2 Since the pn junction 210 of the source region 11 is exposed at the end of the chip, it conducts at this portion and the potential of the base region 12 is fixed to the potential of the source region 11. The structure of the gate electrode will be described later.

The structural constant of the U-MOSFET of FIG. 1 is determined from the required electrical characteristics. That is, the base region 12 is determined by the desired Vth, and the impurity concentration thereof is approximately 1e16 to 1e18 / cm3. The second base region 13 and the drift region 14 are determined by the drain breakdown voltage and the on resistance. The impurity concentration of the second base region 13 is 1
e16 to 1e18 / cm3, and the impurity concentration of the drift region 14 is about 1e17 to 1e18 / cm3. According to this configuration, the drift region during operation is filled with the depletion layer, and the feedback capacitance Crss can be significantly reduced. Considering high frequency applications, the channel length is 0.3 to 1.5 μm and the drift region 1
4 has a length of 0.5 to 5 μm and a gate oxide film thickness of 10 to 5
About 0 nm is desirable.

FIG. 2 is a plan view of the semiconductor device of the present invention. Drain bonding pad 219 and gate bonding pad 209 are shown in the figure. As can be seen from the figure, almost the entire area of the drain electrode 21 becomes a pad, and it is not necessary to provide a special pad. The A part shows the extraction part of the gate electrode 23, and the B part shows the potential fixing means of the base region 12. A schematic cross-sectional view in the direction of 1--6 in the figure is shown in FIG.

FIG. 3 is a schematic cross-sectional view taken along the 1--3 direction of FIG. Noteworthy is the gate electrode extraction portion (A portion).
After formation of the passivation film 18, the passivation film 18,
A hole that penetrates the insulator 17 and reaches the gate electrode 23 is opened, and a good conductive material 24 is embedded therein to be a connection line with the gate wiring 20. Further, FIG. 6 is a schematic cross-sectional view taken along the line 1--2 of FIG. 2 (B portion). Since the pn junction 210 of FIG. 1 is conductive, it is not always necessary, but it can be applied when it is desired to secure the fixed potential of the base region 12. After the passivation film 18 is formed, a hole penetrating from the surface of the passivation film 18 to the source region 11 is opened, and a good conductive material 245 is embedded as a short-circuit line so as to cover at least the source region 11 and the base region 12. Electrode 2
Reference numeral 50 serves as a lid that closes the hole for ensuring reliability. It is also possible to form a gate protection diode by inserting a diode array made of polycrystalline silicon between the electrode 250 and the gate bonding pad 209.

FIG. 4 is a schematic cross-sectional view of the main part of the active region of the semiconductor device of the present invention. A broken line 220 in the drawing represents a depletion layer. If the impurity concentration of the second base region 13, the distance Lb between the pn junction between the second base region 13 and the drift region 14 and the impurity concentration of the drift region 14 are appropriately selected, the depletion layers on the left and right sides are formed as shown in FIG. The depletion layer between the connected drain and source is the pn of the drain region 15 and the second base region 13.
It becomes thicker than the depletion layer generated in the junction, and the output capacitance Co
ss can be significantly reduced.

FIG. 5 is a perspective view of a cross section of a main part of a trapezoid similar to FIG. The column-shaped base region 12 is provided on the source region 11 having the protrusion, and the gate electrode 23 is present on the opposite side surface of the base region 12 with the insulating film 19 interposed therebetween. The drift region 14 is formed in the base region 12 above the gate electrode 23, and the drain region 15 is formed on the top of the base region 12.

A method of manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIG.

(A) As shown in FIG. 7A, n having an impurity concentration of 1e19 to 1e21 / cm3 to be the source region 11 is formed.
Impurity concentration 1e16 to 1e serving as a base region on the substrate
An 18 / cm3 p-layer is epitaxially grown to 1 to 3 μm, and an impurity concentration of 1e to be the second base region 13 is formed thereon.
A p layer of about 16 to 1e18 / cm3 is epitaxially grown to 1 to 5 μm. Since this epitaxial growth is desired to be performed at a temperature as low as possible, SiH2Cl2 or SiH4
Epitaxial growth with hydrogen is desirable. Then, a field oxide film 16 is formed around the device region (active region).
To form. This may be formed by a known method such as LOCOS. Next, the U groove 31 is formed by a normal photolithography technique using a photoresist. ECR ion etching or the like using C3F8 or CHF3 can be applied to the formation of this groove.

(B) After removing the insulating film in the active region and removing the processing damage layer by sacrificial oxidation etching or the like,
A 50 nm gate oxide film 19 is formed. Gate electrode 2
3 may be formed by filling the groove 31 with a good conductive material such as doped polysilicon, W, Mo, or Ti by low pressure CVD, and then shaving to a predetermined thickness by sputter etching, or by directivity such as a sputtering method. It may be deposited in a predetermined thickness in the groove by a deposition method having

(C) Next, the oxide film above the gate electrode is removed, and an oxide containing an n-type impurity is embedded in the groove 31 by the low pressure CVD method to form the insulator 17. Arsenic is preferable as the n-type impurity because of its high diffusion rate. After that, high-concentration ion implantation of arsenic is performed on the surface of the second base region which will be the drain region.

(D) Next, a heat treatment is performed at 800 ° C. to 1000 ° C. for about 30 minutes to solid-diffuse impurities from the n-type insulator 17 to form the drift region 14, and at the same time activate the ion implantation layer to drain the drain region 15. To form.

Although the example of using the solid layer diffusion for forming the drift region 14 has been described above, it is possible to form the drift region 14 by using an ion implantation method from an oblique direction as described later, and the same applies to the following. Is.

FIG. 8 is a schematic sectional view showing the second embodiment. The difference from FIG. 1 is that the drift region 14 is formed on the slope of the V-shaped groove and the gate oxide film 19 remains. Since the effect of connecting the left and right depletion layers in FIG. 4 is small, the two-stage drain structure described later has an output capacitance C.
It is effective in reducing oss.

A method of manufacturing the semiconductor device shown in FIG. 8 will be described with reference to FIG.

(A) The base layer 12 and the second base layer 13 are sequentially epitaxially grown on the (100) substrate 11. Next, a VOH groove 32 is formed by anisotropically etching silicon using a KOH solution.

(B) The V-shaped groove 32 is filled with the insulator 33 by low pressure CVD. Then, a U groove 34 reaching the source region 11 from the surface of the insulator 33 is formed.

(C) After removing the insulator 33 and etching the processing damage layer, the gate oxide film 19 is formed.

(D) After a good conductive material 23 having a predetermined thickness is embedded to form a gate electrode, arsenic to be the drift region 14 is ion-implanted.

(E) The V-shaped groove above the gate electrode 23 is filled with the insulator 17. Then, high-concentration arsenic to be the drain region 15 is ion-implanted.

(F) A heat treatment is applied to activate the implanted ions to form the drift region 14 and the drain region 15 at the same time.

FIG. 10 is a sectional view of an essential part of an active region showing a third embodiment. In this embodiment, the insulating film below the gate electrode 23 is thick, so that the input capacitance Ciss can be reduced. To form a thick film, there is a method such that oxygen is ion-implanted in advance at the bottom of the groove before gate oxidation.

FIG. 11 is a sectional view of an essential part of an active region showing a fourth embodiment. In this embodiment, the drain region is composed of the high-concentration drain region 15 and the low-concentration drain region 155. By using the ion implantation method of phosphorus for the low concentration layer and arsenic for the high concentration layer, a two-step structure can be obtained by one heat treatment. By setting the impurity concentration of the drain region to two levels, the depletion layer extends toward the drain region 155 and the width of the entire depletion layer is increased, so that the output capacitance Coss can be reduced. Of course, not only two steps but also multi steps may be used, and the impurity concentration may be continuously reduced.
In short, any structure may be used as long as the depletion layer easily extends to the drain region. The structure described in this embodiment can be applied to all structures described in this specification.

FIG. 12 is a sectional view of the essential parts showing the fifth embodiment. A structural feature of the semiconductor device of the present invention is that the fourth drift region 14 and the sixth source diffusion region 111 are arranged on the side surface of the U groove that penetrates the epitaxial layer and reaches the source region 11. That is, the first thick insulator 199, the gate oxide film 19, and the buried gate electrode 23 are formed on the bottom of the U groove that penetrates the second base layer 13 and the base layer 12 and reaches the source region 11, and the first thick insulator 199 is formed on the gate electrode 23. A second insulator 17 is formed on the side surface of the trench in a self-aligned manner with respect to the gate electrode 23 of the second insulator
4. Source diffusion region 111 is formed. Similarly, the drain region 15 is also formed by the U groove in a self-aligned manner.

The difference between this structure and FIG. 4 is that the base region 12 also exists under the gate electrode 23 and the sixth source diffusion region 111 exists on the side surface thereof.

FIG. 1 shows a method of manufacturing the semiconductor device shown in FIG.
This will be described with reference to FIG. (A) As shown in FIG. 13A, on the n substrate having the impurity concentration of 1e19 to 1e21 / cm3 to be the source region, p of the impurity concentration of the order of 1e17 / cm3 to be the base region is formed.
A layer is epitaxially grown to 1 to 3 μm, and an impurity concentration of 1e16 to 1e18 / cm3 to be the second base region is formed thereon.
A p layer of about 1 to 5 μm is epitaxially grown. Since we want to perform this epitaxial growth at the lowest possible temperature,
Epitaxial growth using SiH2Cl2 or SiH4 and hydrogen is desirable. Next, device area (active area)
A field oxide film 16 is formed around the area. This is LO
It may be formed by a known method such as COS. Next, by the usual photolithography technique using photoresist, U
The groove 31 is formed. ECR ion etching or the like using C3F8 or CHF3 can be applied to the formation of this groove.
After removing the insulating film in the active region, the processing damage layer is removed by sacrificial oxidation etching or the like, and then the first insulating film 199 containing a high concentration of n-type impurities is formed at the bottom of the U groove. Arsenic is desirable as the n-type impurity because of its high diffusion rate.

(B) After that, a gate oxide film 19 having a thickness of 10 to 50 nm is formed. The gate electrode 23 is formed by using a conductive material such as doped polysilicon, W, Mo and Ti under reduced pressure CV.
The groove 31 may be filled with D and then etched to a predetermined thickness by sputter etching or the like, or may be deposited to a predetermined thickness in the groove by a directional deposition method such as a sputtering method.

(C) Next, the oxide film above the gate electrode is removed, and an insulator containing n-type impurities is buried in the groove 31 by the low pressure CVD method to form the second insulator 17. Arsenic is preferable as the n-type impurity because of its high diffusion rate. After that, high-concentration ion implantation of arsenic is performed on the surface of the second base region 13, which will be the drain region.

(D) Next, heat treatment is performed at 800 ° C. to 1000 ° C. for about 30 minutes to solid-diffuse the impurities from the first insulating film 199 containing the n-type impurities to form the source diffusion region 111. The impurity is solid-diffused from the second insulator 17 to form the drift region 14, and at the same time, the ion implantation layer is activated to form the drain region 15. The source diffusion region 111 is gradually formed by heat treatment such as gate oxidation before this step.

FIG. 14 is a schematic sectional view showing a sixth embodiment. The difference from FIG. 12 is that the source diffusion region 111 and the drift region 14 are formed on the slope of the V-shaped groove.

A method of manufacturing the semiconductor device shown in FIG. 14 will be described with reference to FIG.
This will be described with reference to Nos. 4 and 15. That is, (a) (10
0) The base region 12 and the second base region 13 are continuously epitaxially grown on the n substrate 11 to form the second base region 13
Forming a V-shaped groove 32 reaching the substrate 11 from the surface of
First insulator 1 containing n-type impurities at the bottom of the groove 32
To form 99.

(B) After forming the gate oxide film 19, a good conductive material 23 having a predetermined thickness to serve as a gate electrode is embedded in the groove on the first insulator 199, and then the drift region 1 is formed.
The n-type impurity which becomes 4 is ion-implanted.

(C) The second insulator 17 is buried in the groove above the gate electrode 23, and the surface of the second base region 13 is ion-implanted with an n-type high-concentration impurity to be the drain region 15.

Then, by heat treatment, the source diffusion region 11 is formed.
The structure shown in FIG. 14 can be obtained by forming the first drift region 14, the drain region 14, and the drain region 15.

A method of manufacturing the seventh embodiment shown in FIG. 17 having a structure similar to that of the semiconductor device shown in FIG. 12 is shown in FIGS.
(A) A first insulating film 197 containing an n-type high-concentration impurity is formed on the n substrate 11 except for the regions where the base layer 12 and the second base layer 13 are formed.

(B) The base region 12 and the second base region 13 are selectively epitaxially grown continuously on the exposed silicon portion of the surface of the substrate 11 to form the U groove portion 35.

(C) After forming the gate oxide film 19, a good conductive material 23 having a predetermined thickness to serve as a gate electrode is embedded inside the groove on the first insulator 197.

(D) After removing the oxide film on the side wall of the groove above the gate electrode 23, the second insulator 17 containing n-type impurities is buried. After that, a field oxide film 161 is formed in the peripheral portion other than the active region, and a high concentration n-type impurity is ion-implanted into the surface of the second base region 13.

Heat treatment is performed at 800 to 1000 ° C. for about 30 minutes to form the source diffusion region 111 and the drift region 14,
At the same time, the implanted ions are activated to form the drain region 15, and the structure of FIG. 17 is completed. Source diffusion region 1
11 is gradually formed by heat treatment such as gate oxidation.

FIG. 18 is a perspective view of a trapezoidal main section similar to FIGS. 12 and 17. A columnar base region 12 is provided on the source region 11, a control electrode 23 is formed on opposite side faces of the base region 12 via an insulating film 19, and drift regions are formed above and below the control electrode 23 on the side face of the base region 12, respectively. 14, a source diffusion region 111 is formed, and a drain region 15 is formed on top of the base region 12.

19 and 20 are sectional views showing the eighth and ninth embodiments. Although the base region 12 has a single-layer structure,
The effect described in the two-layer structure can be maintained, and the chip can be manufactured at low cost due to the simple structure.

FIG. 21 shows a sectional view and an impurity concentration for explaining the tenth embodiment. The structure is such that the impurity concentration of the drift region 14 increases from the gate side toward the drain side. Therefore, the electric field strength near the gate of the drift region 14 is reduced, and the on-resistance can be reduced while maintaining the breakdown voltage.

The above structure can be realized by using an ion implantation method. That is, as shown in FIG. 21, when the drift region 14 is formed after the gate electrode is formed, ion implantation is performed obliquely to the groove 31 and the incident angle of the implantation is changed to change the impurity from the gate to the drain. A structure with increasing concentration can be obtained. It is self-evident that the impurity concentration of the drift region 14 formed will be uniform if the incident angle of implantation is kept constant without changing.

Further, after the gate electrode is formed, it can be obtained by increasing the impurity concentration of the insulator 17 filling the U groove portion 31 toward the upper part.

In the present specification, for simplification, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type.
The same effect can be obtained even if the second conductivity type is n-type.

Although silicon has been described as the subject material for the semiconductor material, the present invention can be applied to other semiconductor materials, for example, compound semiconductors such as silicon carbide.

As described above in detail, in the present invention, the electrical characteristics particularly important in the high frequency power MOSFET,
The feedback capacitance Crss and the output capacitance Coss can be significantly reduced, and the increase in gate resistance due to the shortening of the channel can be suppressed. Further, the input capacitance Ciss can be reduced, and the variation in channel length can be reduced. Further, by disposing the source electrode on the back surface of the chip, the source inductance Ls is significantly reduced. Furthermore, the insulating substrate of the heat dissipation substrate is unnecessary, and the heat dissipation performance is improved. It can be said that the semiconductor device is suitable as a high frequency power MOSFET.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device (vertical insulated gate field effect transistor) according to a first embodiment of the present invention.

FIG. 2 is a plan view of FIG.

FIG. 3 is a sectional view taken along the line 1--3 of FIG.

FIG. 4 is a main-portion cross-sectional view illustrating a state of a depletion layer in an active region.

5 is a perspective view of a cross section of a main part of a trapezoid similar to FIG. 1. FIG.

FIG. 6 is a sectional view taken along the line 1--2 of FIG.

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a sectional view of a third embodiment of the present invention.

FIG. 11 is a sectional view of a fourth embodiment of the present invention.

FIG. 12 is a sectional view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 13 is a sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 14 is a sectional view of a sixth embodiment of the present invention.

FIG. 15 is a sectional view illustrating the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention.

FIG. 16 is a sectional view illustrating the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention.

FIG. 17 is a sectional view of a seventh embodiment of the present invention.

18 is a perspective view of a cross section of a main part of a trapezoid similar to FIG.

FIG. 19 is a sectional view of an eighth embodiment of the present invention.

FIG. 20 is a sectional view of a ninth embodiment of the present invention.

FIG. 21 is a sectional view of a tenth embodiment of the present invention.

FIG. 22 is a cross-sectional view of a conventional U-MOSFET.

FIG. 23 is a cross-sectional view of a conventional improved U-MOSFET.

[Explanation of symbols]

11 semiconductor substrate (n +), first conductivity type substrate 111 Source diffusion region 113,129 Drift region 12 Second semiconductor region Base region 13 Third semiconductor region Second base region 14 Drift region 144 Ion-implanted (drift) region 15 Drain region (n +) 155 Second drain region 16 161 Field oxide film 17,199,197 Insulator 18 passivation film 19 Gate insulating film 195 thick insulating film 20 gate wiring 209 Gate bonding pad 21 drain electrode 219 Drain bonding pad 22 Source electrode 23 Gate electrode 24 gate connection line 245 Base-source short-circuit wire 25 base area 26 Source Area 31, 34, 35 groove 32 V-shaped groove 33 Insulator 220 depletion layer Part A Gate contact part B part Base-source short circuit part

Claims (34)

[Claims] 1. A first-conductivity-type high-impurity-concentration first semiconductor region serving as a source region, a second-conductivity-type second semiconductor region formed on the first semiconductor region, A groove formed so as to reach the inside of the first semiconductor region from the surface of the second semiconductor region; a gate electrode formed at the bottom of the groove through an insulating film formed in the groove; A fourth drift region of the first conductivity type formed on the side surface of the second semiconductor region of the groove in a self-aligned manner with respect to the gate electrode; and an insulator filling the groove above the gate electrode.
A semiconductor device comprising: a second drain region having a high impurity concentration of the first conductivity type and formed in a self-aligned position and size on the surface of the second semiconductor region. 2. A first-conductivity-type high-concentration first semiconductor region serving as a source region, a second-conductivity-type second semiconductor region formed on the first semiconductor region, A second semiconductor region of the second conductivity type formed above the second semiconductor region; a groove formed so as to reach the inside of the first semiconductor region from the surface of the third semiconductor region; A gate electrode formed at the bottom of the groove via an insulating film formed in the groove, and formed on the side surfaces of the second and third semiconductor regions of the groove in a self-aligning manner with respect to the gate electrode. A fourth drift region of the first conductivity type, an insulator filling the groove above the gate electrode, and a position and a size of which are formed in a self-aligned manner on the surface of the third semiconductor region. A semiconductor device having a fifth drain region of high conductivity type conductivity Place 3. The semiconductor device according to claim 2, wherein the impurity concentration of the third semiconductor region is lower than the impurity concentration of the second semiconductor region. 4. The semiconductor device according to claim 1, wherein the fourth drift region is formed on the slope of the V-shaped groove. 5. The insulating film below the gate electrode is thicker than the gate insulating film on the side surface.
5. The semiconductor device according to any one of 3 and 4. 6. A state in which at least most of the fourth drift region is filled with a depletion layer, and a state in which the depletion layers of the left and right pn junctions facing each other are in contact with each other and are continuous in the second semiconductor region. Claim 1, characterized in that
4. The semiconductor device according to any one of 4 and 5. 7. A state in which at least most of the fourth drift region is filled with a depletion layer exists, and in at least a third semiconductor region, there is a state in which the depletion layers of the left and right pn junctions facing each other are in contact and continuous. The semiconductor device according to claim 2, 3, 4, or 5. 8. (1) A second semiconductor region of the second conductivity type and a third semiconductor region of the second conductivity type are continuously epitaxially grown on an upper part of the first conductivity type high impurity concentration substrate to be a source region, A first step of forming a groove portion extending from the surface of the third semiconductor into the first semiconductor region; and (2) forming an insulating film on the bottom and side walls of the groove and further forming a buried gate electrode on the bottom. A second step of forming a good conductive material, and (3) removing the insulating film formed on the side wall above the gate electrode, burying an insulator inside the trench above the gate electrode, and A third step of ion-implanting impurities of the first conductivity type into the surface of the semiconductor region and (4) a single heat treatment to form a fourth drift region on the side surfaces of the second and third semiconductor regions, By activating the implanted ions on the surface of the third semiconductor region, A fourth step of forming a drain region, the method for manufacturing a semiconductor device. 9. The third step of claim 8 is that "removing the insulating film formed on the side wall above the gate electrode" is performed on the side wall above the gate electrode from the first conductivity type obliquely. 9. The method for manufacturing a semiconductor device according to claim 8, wherein the impurities are replaced with “ion-implanted”. 10. (1) A second semiconductor region of a second conductivity type and a third semiconductor region of a second conductivity type are continuously epitaxially grown on a first conductivity type high impurity concentration substrate to be a source region. A first step of forming a V-shaped groove reaching the surface of the second semiconductor region from the surface of the third semiconductor region; and (2) burying an insulator inside the V-shaped groove, and A second step of forming a groove reaching the inside of the first semiconductor region; (3) a third step of removing the insulating material and forming an insulating film on the groove bottom and side walls; and (4) A fourth step of forming a good conductive material to be an embedded gate electrode inside the groove, and ion-implanting impurities of the first conductivity type into the side surfaces of the second and third semiconductor regions; and (5) the gate electrode An insulator is embedded in the groove above the first semiconductor region and the first conductivity type is formed on the surface of the third semiconductor region. A fifth step of ion-implanting a high-concentration impurity and (6) a single heat treatment activates the implanted ions on the side surfaces of the second and third semiconductor regions to form a fourth drift region, And a sixth step of activating the high concentration ions implanted in the surface of the third semiconductor region to form a fifth drain region. 11. A gate electrode embedded in silicon, an insulator above the gate electrode, a drain electrode from which a part above the insulator is removed, an insulating film above the drain electrode, and the drain. A hole reaching the gate electrode from the surface of the insulating film in the removed portion of the electrode, and having a connection line of a good conductive material filled in the hole, and a gate wiring above the insulating film, A semiconductor device, wherein the gate electrode and the gate wiring are electrically connected via a connection line. 12. A first-conductivity-type high-impurity-concentration first semiconductor region serving as a source region, a second-conductivity-type second semiconductor region formed on the first semiconductor region, Second semiconductor region from the surface to the inside of the first semiconductor region, a first insulator formed at the bottom of the groove, and an insulating film formed on the sidewall of the groove. A gate electrode formed on the first insulator via
A second insulator filling the groove above the gate electrode, and a sixth source formed on the side surface of the second semiconductor region below the gate electrode in a self-aligning manner with respect to the gate electrode. A diffusion region, a fourth drift region of the first conductivity type formed on the side surface of the second semiconductor region above the gate electrode in the groove in a self-aligned manner with the gate electrode, and the second drift region. A semiconductor device comprising: a fifth drain region having a first conductivity type and a high impurity concentration, which is formed in a self-aligned position and dimension on the surface of the semiconductor region. 13. A first-conductivity-type high-concentration first semiconductor region serving as a source region, a second-conductivity-type second semiconductor region formed on the first semiconductor region, The third semiconductor region of the second conductivity type formed above the second semiconductor region and the surface of the third semiconductor region,
Of the groove formed so as to reach the inside of the semiconductor region, the first insulator formed on the bottom of the groove, and the insulating film formed on the side wall of the groove on the first insulator. Formed on the gate electrode, a second insulator filling the groove above the gate electrode, and a side surface of the second semiconductor region below the gate electrode in a self-aligned manner with respect to the gate electrode. And the sixth source diffusion region formed on the side surface of the first and second conductive regions formed on the side surfaces of the second and third semiconductor regions above the gate electrode in the groove in a self-aligned manner with respect to the gate electrode. A semiconductor having a fourth drift region and a fifth drain region having a high impurity concentration of the first conductivity type formed in a self-aligned position and dimension on the surface of the third semiconductor region. apparatus. 14. The semiconductor device according to claim 12, wherein the sixth source diffusion region and the fourth drift region are formed on the slope of the V-shaped groove. 15. A state in which at least almost the entire fourth drift region is filled with a depletion layer, and there is a state in which depletion layers of the left and right pn junctions facing each other in the second semiconductor region are in contact with each other and are continuous with each other. The semiconductor device according to claim 12, wherein the semiconductor device is a semiconductor device. 16. A state in which at least substantially the entire fourth drift region is filled with a vacancy layer exists, and at least left and right pns facing each other in the third semiconductor region.
15. The semiconductor device according to claim 13, wherein there is a state in which the depletion layers of the junction are in contact with each other and are continuous with each other. 17. (1) A second semiconductor region of the second conductivity type is provided on the first conductivity type high impurity concentration substrate to be the source region, and a second semiconductor region of the second conductivity type is provided on the second semiconductor region. A third step of continuously epitaxially growing the third semiconductor region to form a groove portion from the surface of the third semiconductor to reach the first semiconductor region, and forming a first insulator at the bottom of the groove portion,
(2) Second step of forming an insulating film on the sidewall of the trench above the first insulator and further forming a good conductive material to be a buried gate electrode on the insulator inside the trench When,
(3) The insulating film formed on the side wall above the gate electrode is removed, the second insulator is buried in the groove above the gate electrode, and the first conductivity type is formed on the surface of the third semiconductor region. Third step of ion-implanting high-concentration impurities and (4) heat treatment are performed to form a sixth source diffusion region on the side surface of the second semiconductor region below the gate electrode and a first source diffusion region above the gate electrode. A fourth step of forming a fourth drift region on the side surfaces of the second and third semiconductor regions and activating the high concentration ions implanted in the surface of the third semiconductor region to form a fifth drain region. A method of manufacturing a semiconductor device, comprising: 18. The third step of claim 17 is that "removing the insulating film formed on the side wall above the gate electrode" is performed on the side wall above the gate electrode from the first conductivity type obliquely. 18. The method for manufacturing a semiconductor device according to claim 17, wherein the impurities are replaced with “ion-implanted”. 19. (1) A second semiconductor region of the second conductivity type is provided on the first conductivity type high impurity concentration substrate to be a source region, and a second semiconductor region of the second conductivity type is provided on the second semiconductor region. The third semiconductor region is continuously epitaxially grown to form a V-shaped groove from the surface of the third semiconductor region to the first semiconductor region, and the first insulator is formed at the bottom of the groove. And (2) forming an insulating film on the sidewall of the groove above the first insulator, and further forming a good conductive material to be a buried gate electrode on the insulator inside the groove, A second step of implanting ions of the first conductivity type impurity into the side surfaces of the second and third semiconductor regions above the gate electrode, and (3) forming a second insulator inside the groove above the gate electrode. A third step of burying and ion-implanting a high-concentration impurity of the first conductivity type into the surface of the third semiconductor region Extent and (4) a heat treatment, from the gate electrode on the side surfaces of the lower portion of the second semiconductor region sixth upper portion of said 2,3 than the source diffusion region and the gate electrode of the
Forming a fourth drift region on the side surface of the semiconductor region and activating the high-concentration ions implanted on the surface of the third semiconductor region to form a fifth drain region. A method for manufacturing a characteristic semiconductor device. 20. In the second step of claim 19, the step of "implanting ions of the first conductivity type into the side surfaces of the second and third semiconductor regions above the gate electrode" is defined as "the side wall above the gate electrode." 20. The method of manufacturing a semiconductor device according to claim 19, further comprising: removing the insulating film formed in. 21. (1) A first step of partially forming a first insulator on a first conductivity type high impurity concentration substrate to be a source region, and (2) exposure of silicon in the source region. A second step of selectively epitaxially growing a second semiconductor region of the second conductivity type on the formed surface and a third semiconductor region of the second conductivity type on the second semiconductor region to form a groove. And (3) forming an insulating film on the side wall of the groove,
Third step of burying a good conductive material for the gate electrode on the insulator of (4), (4) removing the insulating film on the side wall, and burying the second insulator in the groove above the gate electrode A fourth step of forming an oxide film on the periphery of the surface of the third semiconductor region other than the active region to form a field oxide film, and ion-implanting a high-concentration impurity of the first conductivity type into the surface of the third semiconductor region And (5) heat treatment is performed to form a sixth source diffusion region on the side surface of the second semiconductor region below the gate electrode and a fourth side surface of the second and third semiconductor regions above the gate electrode. Forming a drift region and activating the high-concentration ions implanted in the surface of the third semiconductor region to form a fifth drain region. Method. 22. The second step of the second step of claim 21.
22. The method of manufacturing a semiconductor device according to claim 21, wherein the formation of the first-conductivity-type high-concentration impurity region is added before the formation of the semiconductor region. 23. The impurity concentration of the fourth drift region increases continuously or in multiple steps from the gate side toward the drain region.
17. The semiconductor device according to any one of 12, 13, 14, 15, and 16. 24. In a method of forming a fourth drift region on a side surface of a trench portion of a semiconductor, a vertical impurity concentration distribution of the drift region is changed by changing an incident angle of implantation during ion implantation. A method of manufacturing a semiconductor device, comprising: 25. A method of forming a fourth drift region on a side surface of a trench portion of a semiconductor, wherein an impurity concentration of an insulating material filled in the trench is changed in a vertical direction so that the impurity concentration in the vertical direction of the drift region is increased. A method of manufacturing a semiconductor device, characterized in that a distribution is changed. 26. The fifth drain region is configured in the order of high impurity concentration and low impurity concentration from the surface of the second semiconductor region, in order.
16. The semiconductor device according to any one of 2, 14, and 15. 27. The fifth drain region is formed in order of high impurity concentration and low impurity concentration from the surface of the third semiconductor region,
17. The semiconductor device according to any one of 7, 13, 14, and 16. 28. A first-conductivity-type first semiconductor substrate having a protrusion, a second-conductivity-type second semiconductor region on the protrusion of the semiconductor substrate having a columnar cross section, and a columnar first semiconductor region. And a control electrode provided on the opposite side surfaces of the second semiconductor region via an insulating film, and a fourth conductive type fourth electrode formed on the surface of the side surface of the second semiconductor region above the control electrode. A semiconductor device comprising: a semiconductor region; and a fifth semiconductor region of a first conductivity type formed on a top surface of the second semiconductor region. 29. The semiconductor device according to claim 28, wherein an insulating material is provided on the control electrode. 30. A first semiconductor substrate of a first conductivity type having a convex portion, a second semiconductor region of a second conductivity type having a columnar cross section on the convex portion of the semiconductor substrate, and a columnar first semiconductor region. And a control electrode provided on the opposite side surfaces of the second semiconductor region via an insulating film, and a fourth conductive type fourth electrode formed on the surface of the side surface of the second semiconductor region above the control electrode. A semiconductor region, a fifth semiconductor region of the first conductivity type formed on the top surface of the second semiconductor region, and a surface of a side surface of the second semiconductor region below the control electrode. A semiconductor device having a sixth semiconductor region of the first conductivity type. 31. A first semiconductor substrate of a first conductivity type,
A second semiconductor region having a columnar cross section of the second conductivity type on the semiconductor substrate; a control electrode provided on an opposing side surface of the columnar second semiconductor region through an insulating film; A fourth semiconductor region of the first conductivity type formed on the surface of the side surface of the second semiconductor region above the working electrode, and a fifth semiconductor of the first conductivity type formed on the top surface of the second semiconductor region. And a semiconductor region of the first conductivity type, which is formed on the surface of the second semiconductor side surface below the control electrode. 32. The insulating material is provided on the upper part and the lower part of the control electrode.
1. The semiconductor device according to 1. 33. The impurity concentration distribution of the second conductive type columnar second semiconductor region is changed in the vertical direction, according to any one of claims 28, 29, 30, 31, 32. The semiconductor device according to the item. 34. The impurity concentration distribution of the fourth semiconductor region of the first conductivity type is changed in the vertical direction, according to any one of claims 28, 29, 30, 31, 32, 33. The semiconductor device according to the item.