JP5596773B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a conductive path is formed between a semiconductor substrate having an integrated circuit formed on one surface and the other surface using a substrate through hole, and a method for manufacturing the same.

  Conventionally, in order to electrically connect the front surface and the back surface of a semiconductor substrate, a through hole penetrating the semiconductor substrate is formed, and a conductive path is disposed in the through hole (see, for example, Non-Patent Document 1). When a plurality of conductive paths are desired, the same number of through holes as the required conductive paths are formed in the semiconductor substrate.

Hirokazu Kikuchi, Yusuke Yamada, Atif Mossad Ali, Jun Liang, Takafumi Fukushima, Tetsu Tanaka, and Mitsumasa Koyanagi, “Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs”, Japanese Journal of Applied Physics, Vol. 47, No. 4 , 2008, pp. 2801-2806

  In the conventional method, with the miniaturization of elements formed on the surface of the semiconductor substrate, in order to form a plurality of conductive paths that electrically connect the surface and the back surface of the semiconductor substrate, the diameter ratio of the through hole is increased. Reducing the size of the through hole, improving the formation density of the through hole, etc., and forming a high aspect ratio through hole, forming a uniform metal thin film in the through hole, and depositing metal in the through hole by plating. There is a problem that the creation process of the through hole and the conductive path is required to be sophisticated and complicated, such as suppression of the generation of voids. Moreover, there existed a subject that board | substrate mechanical strength fell because a through-hole exists in high density.

  The present invention has been made in view of the above, and an object of the present invention is to form a conductive path that electrically connects a front surface and a back surface of a semiconductor substrate with high density.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including: an integrated circuit on a first surface; and a plurality of wiring portions that are electrically connected to the integrated circuit. Forming a substrate through hole from the corresponding position until the plurality of wiring portions are exposed , forming a metal thin film on a bottom surface and an inner inner wall of the substrate through hole, and applying a resist to the second surface. A step of forming a resist pattern that divides the bottom of the substrate through hole in accordance with the positions of the plurality of wiring portions, and electrically connecting the plurality of wiring portions and the second surface after forming the resist pattern Forming a metal deposited layer to be a plurality of conductive paths, and removing the resist and removing a metal thin film in a region where the metal deposited layer is not formed by being covered with the resist. Characterized in that it.

  The method for manufacturing a semiconductor device may further include a step of forming an insulating film on the inner inner wall of the substrate through hole before the step of forming the metal thin film.

  In the method of manufacturing a semiconductor device, in the step of forming the metal deposition layer serving as the plurality of conductive paths, a high frequency coplanar line using the plurality of conductive paths is formed.

  According to the present invention, conductive paths that electrically connect the front surface and the back surface of a semiconductor substrate can be formed with high density.

It is sectional drawing which shows the structure of the semiconductor device in this Embodiment. FIG. 2 is a plan view showing a configuration of a wiring portion arranged on the surface of the semiconductor device of FIG. 1. FIG. 2 is a plan view showing a configuration of conductive paths arranged on the back surface of the semiconductor device of FIG. 1. It is a figure which shows the manufacturing method of the semiconductor device of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to the present embodiment. The semiconductor device shown in FIG. 2 is used to appropriately electrically connect the elements 2 constituting the integrated circuit such as a semiconductor element, a capacitor, a resistor, and an inductance to the surface of the indium phosphorus substrate 1 (upper side in the figure). A plurality of wiring portions 4A, 4B, 4C and an insulating film 7 are arranged to obtain electrical connection to the wiring 3, the back surface of the indium phosphorous substrate 1 (the lower side in the figure). A substrate through-hole penetrating the indium phosphorous substrate 1 is formed immediately below the wiring portions 4A, 4B, and 4C, and electrically connected to the electroplating seed layer 5 and the wiring portions 4A, 4B, and 4C, respectively, in the substrate through-hole. Conductive paths 6A, 6B, and 6C are arranged to electrically connect the wiring portions 4A, 4B, and 4C to the back surface of the indium phosphorous substrate 1.

  FIG. 2 is a plan view showing the configuration of the wiring portions 4A, 4B, and 4C arranged on the surface of the indium phosphorus substrate 1. FIG. The wiring portions 4A, 4B, 4C in the present embodiment have a configuration divided into three. Each of the wiring portions 4A, 4B, 4C is connected to an integrated circuit formed on the indium phosphorous substrate 1 via the wiring 3. Further, substrate through holes are formed in the lower surfaces of the wiring portions 4A, 4B, and 4C, and the wiring portions 4A, 4B, and 4C are electrically connected to the conductive paths 6A, 6B, and 6C, respectively. In the present embodiment, substrate through holes are formed corresponding to the circular central portions of the wiring portions 4A, 4B, 4C shown in FIG. In the present embodiment, the wiring portions 4A, 4B, and 4C obtained by dividing the circle into three are shown, but the present invention is not limited to this.

  FIG. 3 is a plan view showing the configuration of the conductive paths 6A, 6B, 6C as seen from the back side of the indium phosphorus substrate 1. FIG. In the present embodiment, as shown in FIG. 3, two slots are provided between the conductive paths 6A, 6B, and 6C, and the conductive paths 6A, 6B, and 6C constitute a high frequency coplanar line (CPW). When CPW is formed according to the present embodiment, the gap between the signal line and the ground line can be adjusted more easily with a resist pattern than when high-frequency wiring is formed using three substrate through holes. The degree can be easily improved.

  Next, a method for manufacturing a semiconductor device in the present embodiment will be described.

  First, as shown in FIG. 4A, the element 2, the wiring 3, the wiring portions 4A, 4B, 4C, the insulating film 7 and the like are formed on the indium phosphorous substrate 1.

  Subsequently, the back surface of the indium phosphorous substrate 1 is polished so that the thickness of the indium phosphorous substrate 1 is, for example, 50 to 100 μm.

  Subsequently, as shown in FIG. 4B, the lower surfaces of the wiring portions 4A, 4B, and 4C are exposed from the back surface of the indium phosphorous substrate 1 to corresponding predetermined positions immediately below the wiring portions 4A, 4B, and 4C. The substrate through-hole 10 is formed using a laser or reactive ion etching (RIE) method. At this time, the size of the substrate through hole 10 is, for example, 60 μm in diameter.

  Subsequently, as shown in FIG. 4C, the bottom surface of the substrate through-hole 10 (the lower surfaces of the wiring portions 4A, 4B, 4C) and the inner side so as to obtain electrical connection with the wiring portions 4A, 4B, 4C. A metal thin film for use as the electroplating seed layer 5 is formed on the side wall by sputtering or the like. Before forming the metal thin film, an insulating film may be formed on the inner side wall of the substrate through hole 10 by a chemical vapor deposition (CVD) method or the like.

  Subsequently, a resist 11 is applied to the back surface of the indium phosphorous substrate 1, and as shown in FIG. 4D, the bottom of the substrate through hole 10 is divided into three regions in accordance with the positions of the wiring portions 4A, 4B, 4C. Thus, a resist pattern is formed.

  Thereafter, as shown in FIG. 4 (e), metal deposited layers to be conductive paths 6A, 6B, 6C that electrically connect the front surface and the back surface are formed by electrolytic plating or the like so as to have a thickness of 2 to 5 μm.

  Then, as shown in FIG. 4F, after the resist 11 is removed, the metal thin film in the region that is not plated and grown because of being covered with the resist 11 is removed by the RIE method or the like.

  Through the above steps, the conductive paths 6A, 6B, and 6C electrically connected to the wiring portions 4A, 4B, and 4C can be simultaneously formed in one substrate through-hole 10, respectively.

  In this embodiment, an example in which an indium phosphide substrate is used as a semiconductor substrate has been described. However, the effect of the present invention does not vary depending on the semiconductor material of the substrate, and the present invention can be applied to a silicon substrate or a gallium arsenide substrate. It is clear that the same effect as the embodiment can be obtained.

In the present embodiment, the example in which the three conductive paths 6A, 6B, and 6C are formed in the substrate through hole has been described. However, the present invention is not limited to this, and a plurality of conductive paths are formed in one substrate through hole. Anything to do. Note that the upper limit of the number of conductive paths formed without the substrate through hole is determined by a technique for forming a resist pattern on the substrate through hole. In terms of the effect of the present invention, the larger the number, the better. The size and shape of the substrate through hole are not particularly limited. The lower limit of the size of the substrate through-hole is determined by the substrate through-hole processing technique.

  There is no particular limitation on the substrate thickness. The thinner the substrate thickness, the less the aspect ratio of the substrate through-hole. Therefore, it is desirable that the substrate thickness be thinner as the through-hole processing technology, while ensuring a certain substrate thickness considering the mechanical strength of the substrate itself. Therefore, it is required to determine an appropriate substrate thickness from these balances.

  It is also possible to form a plurality of substrate through holes on the semiconductor substrate, and to form a plurality of conductive paths for each of the formed substrate through holes.

  As described above, according to the present embodiment, by forming a plurality of conductive paths 6A, 6B, and 6C that electrically connect the front surface and the back surface of the indium phosphorous substrate 1 in one substrate through hole, While avoiding the advancement of substrate through-hole and through-electrode manufacturing techniques, it is possible to easily realize high-density conductive paths. In addition, since the number of substrate through holes can be suppressed and the diameter of the substrate through holes can be prevented from decreasing, the mechanical strength of the substrate is reduced and the resistance of the conductive path is increased due to the reduction in the diameter of the substrate through holes. The deterioration of the band and the passage loss can be suppressed.

DESCRIPTION OF SYMBOLS 1 ... Indium phosphorus substrate 2 ... Element 3 ... Wiring 4A, 4B, 4C ... Wiring part 5 ... Electrolytic plating seed layer 6A, 6B, 6C ... Conductive path 7 ... Insulating film 10 ... Substrate through-hole 11 ... Resist

Claims (3)

The plurality of wiring portions are exposed from positions corresponding to the plurality of wiring portions on the second surface of the semiconductor substrate in which the integrated circuit and the plurality of wiring portions electrically connected to the integrated circuit are arranged on the first surface. Forming a substrate through-hole until
Forming a metal thin film on a bottom surface and an inner inner wall of the substrate through hole;
Applying a resist to the second surface, and forming a resist pattern that divides the bottoms of the substrate through holes in accordance with the positions of the plurality of wiring portions;
Forming a metal deposition layer to be a plurality of conductive paths that electrically connect the plurality of wiring portions and the second surface after forming the resist pattern;
Removing the resist and removing the metal thin film in the region where the metal deposition layer is not formed by being covered with the resist;
A method for manufacturing a semiconductor device, comprising: Before the step of forming the metal thin film, a method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming an insulating film inside the inner wall of the substrate through hole. Wherein the plurality of forming a conductive path to become a metal deposition layer, a method of manufacturing a semiconductor device according to claim 1, wherein forming a high-frequency coplanar line with the plurality of conductive paths.

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