JP2011204979A - Semiconductor chip, semiconductor multilayer circuit, and method of manufacturing semiconductor chip - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the attenuation of an electric signal without increasing a manufacturing time nor cost by utilizing a conventional known semiconductor technology so as to provide a semiconductor chip having connection wiring for propagating the electric signal from a top surface to a reverse surface.SOLUTION: The semiconductor chip includes a semiconductor substrate 20, surface wiring 30, and wiring 40 for connection. The semiconductor substrate has a hole 25 decreasing in area from a first principal surface 20a to a second principal surface 20b. The surface wiring is formed on the first principal surface of the semiconductor substrate. Furthermore, the wiring for connection is formed on a side face of the hole, and connected to the surface wiring.

Description

  The present invention relates to a semiconductor chip having a wiring structure for transmitting signals from the front surface side to the back surface side, a semiconductor multilayer circuit on which the semiconductor chip is mounted, and a method for manufacturing the semiconductor chip.

  Due to the explosive increase in the amount of information communication, LSIs that process electrical signals are also required to have high speed operation and space saving technology. In order to realize such a technique, attempts have been made to three-dimensionally mount semiconductor chips, such as mounting a semiconductor chip on a multilayer substrate.

  When mounting a semiconductor chip on a lower substrate, a wiring structure is required to transmit electrical signals processed on the front surface (upper surface) side of the semiconductor chip to the underlying substrate on the back surface (lower surface) side or other semiconductor chips. It becomes. A through via structure is known as a wiring structure for transmitting an electrical signal to the back side.

  With reference to FIG. 7, a method of forming this through via structure will be described. FIG. 7 is a process diagram for explaining a conventional method for forming a through via structure, and shows a cut end surface of a main part.

  First, a deep opening 125 is formed in the silicon substrate 122 (FIG. 7A).

  In order to transmit a high-frequency electric signal (high-frequency signal), it is required that the high-frequency signal propagating on the surface of the semiconductor chip is not reflected or attenuated by the via hole. For example, the characteristic impedance of the through electrode provided in the via hole becomes a desired value when the diameter near the middle of the opening 125 that becomes a via hole in a later process becomes large, for example, the shape near the entrance of the opening 125 is overhanged. In other words, the reflection of the high-frequency signal may be increased (for example, see Non-Patent Document 1).

The Bosch method is known as a method for forming an opening whose side surface is vertical and has a constant diameter, that is, an opening having a large aspect ratio. The Bosch method is an etching method performed by alternately flowing SF ₆ and C ₄ F ₈ .

  Next, the inside of the opening 125 is filled with metal plating to form the through electrode 140 (FIG. 7B). The damascene process is well known as a wiring technology for copper plating as metal plating. However, the copper plating inside the opening 125 has different optimum conditions for the damascene process depending on the diameter, depth, distribution density, and the like of the opening 125, so optimization of this condition is not easy. If copper plating is performed without finding a sufficient optimum condition, a gap remains in the opening 125.

  In order to prevent this, various additives called accelerators, inhibitors, and smoothing agents have been added to the copper plating solution to control the growth of copper plating.

  Another copper plating technique is electroless plating (see, for example, Non-Patent Document 2).

  Next, the metal plated in unnecessary regions is removed by polishing, and the back surface of the silicon substrate 120 is polished to complete a through via structure (FIG. 7C).

Polishing a silicon substrate is an established technology at present. However, when unnecessary copper deposited on the surface after copper plating is removed, and when the back surface of the silicon substrate 120 is polished in the vicinity of the through electrode 140, the cross section of the through electrode 140 is recessed on the plate. A phenomenon called erosion occurs in which dishing and the silicon substrate 120 as well as the through electrode 140 are scraped more than necessary. In order to prevent these phenomena, the polishing liquid and the polishing apparatus have been devised, and some reduction has been made (for example, see Non-Patent Document 3).

  Thus, good results have been reported for each of an etching technique for forming an opening, a metal plating technique, and a metal and semiconductor polishing technique used to form a through via structure.

Manabu Tomisaka et al. “Chip through-electrode formation technology for 3D packaging” Denso Technical Review Vol. 6, no. 2, 2001 Z. Wang et al. , “Bottom-Up Fill for Submicrometer Copper Via Holes of ULSIs by Electroless Platting”, Journal of The Electrochemical Society, 781-151 (781) Tominaga Shigeru et al., “Fundamental study of electrochemical polishing method for Cu wiring materials (3)” Bulletin of Saitama University Regional Joint Research Center, Vol. 6 (2005) p. 10-15

  However, good results with the above-described conventional etching, metal plating and polishing techniques are only obtained under special conditions, respectively, and all these techniques are applied to general semiconductor manufacturing processes. Optimization is expected to increase time and cost.

As for the etching technique, the Bosch method capable of forming an opening having a large aspect ratio can be realized only with a special etching apparatus. In addition, it is inevitable that fine irregularities due to alternating flow of SF ₆ and C ₄ F ₈ occur on the side surface of the opening. Since the characteristic impedance of the through electrode does not become a desired value due to the unevenness, it can cause reflection of an electric signal.

  Although it is possible to reduce the unevenness by optimizing the etching conditions in the Bosch method, there is a possibility that the process takes a long time.

  In addition, in the metal plating technique based on the damascene process, there are various types of additives that are used to prevent voids from remaining in the openings. For this reason, it takes time to find the optimum conditions for the type and amount of additives, and it is very difficult for those who do not have specialized knowledge and experience to find the optimum conditions.

  On the other hand, in the case of electroless plating, the time required for the plating process becomes long. Non-Patent Document 2 describes an example in which filling is performed with a plating time of about 1 hour. However, since the depth of the opening is about several μm, in order to realize a through via structure, a semiconductor substrate is finally used. Must be polished to a thickness of several μm. Such thinning leads to breakage of the semiconductor chip in a later process, and a problem with handling of the semiconductor chip becomes large.

  In the polishing process, the polishing liquid and the polishing apparatus are devised to reduce dishing and erosion to some extent. However, a highly versatile polishing technique is not known.

  The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to attenuate an electric signal that can use a conventionally well-known semiconductor technology and does not increase manufacturing time and cost. The present invention provides a semiconductor chip capable of suppressing the above, a semiconductor multilayer circuit on which the semiconductor chip is mounted, and a method for manufacturing the semiconductor chip.

  In order to achieve the above-described object, the semiconductor chip of the present invention includes a semiconductor substrate, a surface wiring, and a connection wiring. The semiconductor substrate has an opening whose area decreases from the first main surface toward the second main surface. The surface wiring is formed on the first main surface of the semiconductor substrate. Further, the connection wiring is formed on the side surface of the opening and is connected to the surface wiring.

  In the semiconductor multilayer circuit of the present invention, the semiconductor chip is provided on a lower substrate having solder bumps, and connection wiring is connected to the solder bumps.

  The method for manufacturing a semiconductor chip according to the present invention includes the following steps. First, a concave portion whose area decreases toward the second main surface is formed on the first main surface side of the semiconductor substrate. Next, surface wiring is formed on the first main surface of the semiconductor substrate, and connection wiring connected to the surface wiring is formed on the side surface of the recess. Next, the semiconductor substrate is thinned from the second main surface side until it reaches at least the recess. In addition, another embodiment of the semiconductor chip manufacturing method of the present invention includes the following steps. First, a concave portion whose area decreases toward the second main surface is formed on the first main surface side of the semiconductor substrate. Next, an opening is formed by thinning the semiconductor substrate from the second main surface side until it reaches at least the recess. Next, surface wiring is formed on the first main surface of the semiconductor substrate, and connection wiring connected to the surface wiring is formed on the side surface of the opening.

  According to the semiconductor chip, the semiconductor multilayer circuit, and the semiconductor chip manufacturing method of the present invention, the connection wiring is formed on the side surface of the opening whose area decreases from the first main surface to the second main surface of the semiconductor chip. Has been. According to this configuration, since the side surface of the opening is formed to be inclined with respect to the first main surface, the connection wiring can be formed on the side surface by a normal metal vapor deposition technique. For this reason, the connection wiring can be easily formed as compared with the conventional technique using the damascene process or electroless plating.

  Further, since the connection wiring is formed by vapor deposition, a high aspect ratio is not required for forming the recess, and the recess can be formed using a normal etching technique. Further, dishing or erosion does not occur during polishing of the semiconductor substrate.

It is the schematic for demonstrating one Embodiment of a semiconductor chip and a semiconductor multilayer circuit. It is the schematic for demonstrating the wiring for a connection with which a semiconductor chip is provided. It is process drawing for demonstrating the manufacturing method of a semiconductor chip. It is a schematic diagram of the multilayer circuit used for calculation of an impedance. It is a figure which shows the calculation result of the characteristic impedance with respect to the thickness of a semiconductor substrate. It is the schematic which shows the structure where the circumference | surroundings of the coplanar track | line were filled with resin. It is process drawing for demonstrating the formation method of the conventional through-via structure.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the shape, size, and arrangement relationship of each component are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described. However, the material and numerical conditions of each component are merely preferred examples. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

  The semiconductor chip and the semiconductor multilayer circuit will be described with reference to FIGS. FIG. 1 is a schematic diagram for explaining an embodiment of a semiconductor chip and a semiconductor multilayer circuit. FIG. 1A shows a three-dimensional view of a semiconductor chip, and FIG. 1B shows a cut end surface of a main part of a semiconductor multilayer circuit on which the semiconductor chip is mounted. FIG. 2 is a schematic diagram for explaining the connection wiring provided in the semiconductor chip. FIG. 2A shows a cut end surface of a main part of the semiconductor chip, and FIG. 2B shows an enlarged view of the connection wiring portion of FIG. In FIG. 1A, the component elements are hatched, but this hatching does not display a cross section, but merely highlights the region of each component element.

  The semiconductor chip 10 includes a semiconductor substrate 20, a surface wiring 30 and a connection wiring 40. The semiconductor chip 10 is disposed on a base substrate or another semiconductor chip. In the following description, the base substrate or other semiconductor chip is referred to as the lower substrate 50. A wiring pattern 62 is formed on the main surface 50a of the lower substrate 50 on the side on which the semiconductor chip 10 is mounted. Further, solder bumps 60 connected to the wiring pattern 62 are formed on the main surface 50 a of the lower substrate 50.

  For example, a silicon substrate (silicon wafer) is used as the semiconductor substrate 20. The thickness of a silicon wafer is standardized by an industry organization such as SEMI (Semiconductor Equipment and Materials International). The thickness of the silicon wafer is determined so as to increase in proportion to the diameter. The thickness of the silicon wafer having a diameter of 3 inches is 380 μm, and the thickness of the silicon wafer having a diameter of 4 inches is 525 μm. .

  Although an example in which a silicon substrate is used as a semiconductor substrate is described here, the semiconductor substrate is not limited to a silicon substrate. The semiconductor substrate may be a compound semiconductor substrate such as a GaAs substrate or an InP substrate.

  An opening 25 is formed in the semiconductor substrate 20 from the first main surface (front surface) 20a which is one main surface to the second main surface (back surface) 20b which is the other main surface. The side surface 25a of the opening 25 is inclined with respect to the front surface 20a and the back surface 20b, and the area of the opening 25 decreases from the front surface 20a to the back surface 20b.

  The surface wiring 30 is used for transmission of electric signals and is formed on the surface 20 a of the semiconductor substrate 20. The surface wiring 30 can be configured as a so-called coplanar line including a transmission line 32 and a pair of ground lines 34 at positions sandwiching the transmission line 32, for example.

  The connection wiring 40 is used for connection between the surface wiring 30 and the solder bump 60 provided in the lower substrate 50. That is, the connection wiring 40 is formed on the side surface 25 a of the opening 25 from the front surface 20 a to the back surface 20 b of the semiconductor substrate 20. Similar to the surface wiring 30, the connection wiring 40 can be configured as a so-called coplanar line including a transmission line 42 and a pair of ground lines 44 at positions sandwiching the transmission line 42. The transmission line 42 of the connection wiring 40 is connected to the transmission line 32 of the surface wiring 30, and the pair of ground lines 44 of the connection wiring 40 are connected to the pair of ground lines 34 of the surface wiring 30, respectively. In mounting the semiconductor chip 10 on the lower substrate 50, the semiconductor chip 10 is disposed so that the connection wiring 40 is connected to the solder bump 60.

  Here, the inclination angle θ of the side surface 25a of the opening 25 is preferably an angle within a range of 30 to 60 degrees with respect to the front surface 20a and the back surface 20b of the semiconductor substrate 20.

  This is because when the inclination angle θ of the side surface 25a of the opening 25 is close to 90 degrees, the side surface 25a becomes almost vertical, and the connection wiring 40 cannot be formed by photolithography and metal deposition.

  On the other hand, when the length of the connection wiring 40 is determined, the semiconductor substrate 20 needs to be thin when the inclination angle θ is 1 to 20 degrees. Accordingly, the semiconductor chip is likely to be cracked or chipped and difficult to handle. Further, when the thickness of the semiconductor substrate 20 is set to a certain value or more, the area of the opening 25 is inevitably increased. As the area of the opening 25 increases, the area of the semiconductor chip 10 increases, which leads to an increase in cost and is not preferable from the viewpoint of space saving.

  On the other hand, when the inclination angle θ is set to an angle in the range of 30 to 60 degrees, the semiconductor substrate 20 having sufficient strength and the thickness of the semiconductor substrate 20 is 100 μm. The length from 20a to the back surface 20b is at most about twice the thickness of the semiconductor substrate 20, and the length is about 120 to 200 μm.

  With the formation technique of the solder bump 60, one having a height of 20 μm or more and an interval of 25 μm or more can be manufactured. In accordance with the structure of the solder bump 60, the line width of the transmission lines 32 and 42 of the surface wiring 30 and the connection wiring 40 configured as a coplanar line and the distance between the transmission lines 32 and 42 and the ground lines 34 and 44 are adjusted. For example, the characteristic impedance can be controlled.

  With reference to FIG. 3, a method of manufacturing a semiconductor chip will be described. 3A to 3D are process diagrams for explaining a method of manufacturing a semiconductor chip, and show a cut end surface of a main part.

  First, the resist pattern 100 is formed on the first main surface 22a of the semiconductor substrate 22 by using a photolithography technique. This resist pattern 100 exposes the semiconductor substrate 22 in a region (aperture forming region) 23 in which an opening is formed, and covers other portions. In forming the resist pattern 100, the edge portion may be rounded by reflow after exposure and development (FIG. 3A).

  Next, for example, the recess 26 is formed by etching with argon (Ar) ions using an electron cyclotron resonance plasma etching method (ECR plasma etching method). In this case, the inclination angle of the side surface 26a of the recess 26 can be controlled by inclining the semiconductor substrate 24 with respect to the etching gas movement direction (indicated by arrow I in FIG. 3B). The recess 26 formed in this way has a smaller area from the first main surface (front surface) 24a to the second main surface (back surface) 24b of the semiconductor substrate 24 (FIG. 3B).

  Next, the surface wiring 30 is formed on the first main surface 24 a of the semiconductor substrate 24, and the connection wiring 40 is formed on the side surface 26 a of the recess 26. The connection wiring 40 is formed on the side surface 26 a of the recess 26 from the first main surface 24 a of the semiconductor substrate 24 toward the bottom surface 26 b of the recess 26. The surface wiring 30 and the connection wiring 40 are formed by well-known photolithography, metal deposition, and lift-off. Note that photolithography is performed using a stepper as an exposure apparatus (FIG. 3C).

  Next, the semiconductor substrate 20 is polished and thinned from the second main surface 20b side. This polishing is performed until reaching the recess 26, that is, until the bottom surface 26b of the recess 26 is removed and the opening 25 is formed. The configuration of this embodiment does not use a conventional through via structure in which a via hole is embedded with a through electrode, so that the occurrence of dishing or erosion is not considered, and this polishing is performed by any suitable method such as a CMP method. This can be performed using a conventionally known technique (FIG. 3D).

  As described above, according to the semiconductor chip, the semiconductor multilayer circuit, and the semiconductor chip manufacturing method of this embodiment, the area of the connection wiring decreases from the first main surface to the second main surface of the semiconductor chip. It is formed on the side surface of the aperture. According to this configuration, since the side surface of the opening is formed to be inclined with respect to the first main surface, the connection wiring can be formed on the side surface by a normal metal vapor deposition technique. For this reason, the connection wiring can be easily formed as compared with the conventional technique using the damascene process or electroless plating.

  Further, since the connection wiring is formed by vapor deposition, a high aspect ratio is not required for forming the recess, and the recess can be formed using a normal etching technique. Further, dishing or erosion does not occur during polishing of the semiconductor substrate.

  Further, in this manufacturing method, a semiconductor chip having a back surface connection wiring can be easily manufactured using a conventional semiconductor chip manufacturing apparatus without introducing a new apparatus. In addition, in each process of etching, metal plating, and polishing, a semiconductor chip can be manufactured without taking time to obtain optimum conditions.

  In the manufacturing method described with reference to FIG. 3, the formation of the recess by etching, the formation of the front surface wiring and the connection wiring, and the polishing from the back surface of the semiconductor substrate are performed in this order, but the present invention is not limited to this. After the formation of the recess by etching, a step of first polishing the semiconductor substrate from the back surface to form an opening and then forming a surface wiring and a connection wiring may be performed.

  In the configuration described with reference to FIG. 1, the space between the semiconductor chip 10 and the lower substrate 50 is filled with air. However, the transmission lines 32 and 42 and the solder bumps 60 whose surroundings are filled with air tend to have a large characteristic impedance. Therefore, it is preferable to fill the space between the semiconductor chip 10 and the lower substrate 50 with an insulating material such as an ultraviolet curable resin.

  The characteristic impedance when the space between the semiconductor chip 10 and the lower substrate 50 is filled with resin will be described in comparison with the case where it is filled with air.

  As the resin, for example, a commercially available resin such as an ultraviolet curable silicone resin manufactured by Three Bond Co., Ltd. or AL Polymer (trade name) manufactured by Asahi Glass Co., Ltd. can be used. These resins are in a liquid form, and are dropped and filled with a dropper or the like between the semiconductor chip 10 and the lower substrate 50, and then cured by irradiating with ultraviolet rays or at a temperature of 200 to 300 ° C. it can.

E. Chen et al. "Characteristics of Coplanar Transmission Lines on Multilayer Substrates: Modeling and Experiments", IEEE Trans. Microwave Theory and Techniques, Vol. 45, 939 (1997) discloses an equation for calculating the characteristic impedance of a coplanar line formed on a five-layer multilayer substrate. Here, a three-layer multilayer substrate shown in FIGS. 4A and 4B is considered. 4A and 4B are schematic views of a multilayer substrate used for calculation of impedance. FIG. 4A is a perspective view, and FIG. 4B shows a cut end surface of a main part in a direction orthogonal to the transmission line.

  This multilayer substrate has a three-layer structure of the lower substrate 50, the resin 70, and the semiconductor substrate 20. The lower substrate 50 is a silicon substrate, and its thickness h1 is 300 μm. The resin 70 is AL Polymer manufactured by Asahi Glass Co., Ltd., and its thickness h2 is 100 μm. The resin thickness h <b> 2 corresponds to the height of the solder bump 60. The semiconductor substrate 20 is composed of a silicon substrate, and its thickness h3 is a thickness after polishing, and is 100 μm.

  The relative dielectric constant of the lower substrate 50 and the semiconductor substrate 20 is ε1, and the relative dielectric constant of the resin 70 is ε2. When the lower substrate 50 and the semiconductor substrate 20 are silicon substrates, the relative dielectric constant ε1 is about 11.9. When the resin 70 is AL Polymer, the relative dielectric constant ε2 is about 2.5. Here, the surface wiring 30 and the connection wiring 40 are coplanar lines. Here, a direction parallel to the first main surface 20a and orthogonal to the transmission line 32 is defined as an x-axis. The x coordinate of the center of the transmission line 32 in the x-axis direction is defined as an origin 0. The coplanar line is considered to be axisymmetric with respect to an axis (indicated by I in FIG. 4B) that passes through the origin 0 and is orthogonal to the first main surface 20a. To do.

  The coordinates of the end of the transmission line 32 are xa, the coordinates of the end of the ground line 34 on the transmission line 32 side, and the coordinates of the opposite end are xb and xc, respectively. If the width of the transmission line 32 and the ground line 34 is 100 μm, and the distance between the transmission line 32 and the ground line 34 is 50 μm, xa, xb and xc are 50, 100 and 200, respectively.

  When there is no dielectric around the coplanar line, the coplanar line has a capacitance C0, the lower substrate has a capacitance C1, the resin has a capacitance C2, and the semiconductor substrate has a capacitance. Is C3, the electrostatic capacitance Ccpw of the entire coplanar line is expressed by the following equation (1).

Ccpw = C0 + C1 + C2 + C3 (1)
Here, C0, C1, C2, and C3 are respectively given by the following formulas (2) to (5). Here, K (k) represents the first type complete elliptic integral.

  When these are used, the effective dielectric constant εeff of the coplanar line is given by the following expression (6), and the characteristic impedance Z0 can be expressed by the following expression (7).

  Therefore, from the above formulas (1) to (7), 52 to 53Ω is obtained as the characteristic impedance in the surface wiring 30. Here, the characteristic impedance in the connection wiring 40 may be calculated in the same manner by changing the thickness h3 of the semiconductor substrate 20 from 100 μm to 0 μm.

  FIG. 5 shows the calculation result of the characteristic impedance with respect to the thickness of the semiconductor substrate. In FIG. 5, the horizontal axis represents the thickness of the semiconductor substrate, and the vertical axis represents the characteristic impedance. In FIG. 5, a curve I indicates a calculation result when the space between the semiconductor substrate and the base substrate is filled with a resin, that is, when a resin layer is provided. Further, in FIG. 5, a curve II indicates a calculation result when the resin layer is not provided.

  In a coplanar line formed on a normal silicon substrate, the characteristic impedance hardly changes when the thickness of the silicon substrate is 100 μm or more. When the thickness is 100 μm or less, the characteristic impedance tends to decrease and the characteristic impedance increases. Therefore, the case where the thickness of the silicon substrate is 100 μm or less is particularly shown here. Also, the characteristic impedance is compared depending on whether the space between the semiconductor chip 10 and the lower substrate 50 is filled with air or resin.

  When the resin 70 is not provided (curve II), the characteristic impedance may exceed 100Ω, but when the resin 70 is provided (curve I), the characteristic impedance can be suppressed to 90Ω or less.

  Next, the characteristic impedance of the solder bump will be described. If the size of the solder is ignored, the solder bump 60 has a structure filled with a resin 70 as shown in FIG. FIG. 6 is a schematic view showing a structure in which the periphery of the solder bump 60 is filled with the resin 70. C. P. Wen, “Coplanar Waveguide: A Surface Strip Transmission Line Suiteable for Nonregenerative Gyromagnetic Devices Applications”, IEEE Trans. Microwave Theory and Techniques, Vol. According to 17 1087 (1969), if xa and xb are converted into a and b, respectively, by conformal mapping, the capacitance C of the coplanar line is given by the following equation (8).

  In this case, the phase velocity ν in the coplanar line is given by the following equation (9), and the characteristic impedance Z0 is obtained by the following equation (10).

  Assuming that the width W of each solder bump 60 is 100 μm and the interval G is 50 μm, when the periphery of the solder bump 60 is filled with resin (ε2 = 2.5), the characteristic impedance Z0 of the solder bump is 76.2 ohms. It becomes. On the other hand, when it is not filled with resin, the characteristic impedance Z0 of the solder bump is 120.5Ω, which is greatly different from 50Ω.

  Therefore, in order to reduce the attenuation of the electric signal propagating from the surface 20a of the semiconductor substrate 20 to the lower substrate 50 as much as possible, it is advantageous to fill the space between the semiconductor substrate 20 and the lower substrate 50 with resin.

  Further, for the line formed on the main surface of the lower substrate 50, in order to realize a characteristic impedance of 50Ω, it is preferable to apply a resin to the surface with a thickness of 10 μm.

  As described above, when the space between the semiconductor substrate and the lower substrate constituting the semiconductor chip is filled with resin, the characteristic impedance Z0 can be brought close to 50Ω by the connection wiring, the solder bump, or the like.

DESCRIPTION OF SYMBOLS 10 Semiconductor chip 20, 22, 24 Semiconductor substrate 25 Opening 26 Recessed part
30 Surface wiring 32, 42 Transmission line 34, 44 Ground line
40 Wiring for connection
50 Lower substrate 60 Solder bump 62 Wiring pattern 70 Resin

Claims (8)

A semiconductor substrate having an aperture that decreases in area from the first main surface toward the second main surface;
Surface wiring formed on the first main surface of the semiconductor substrate;
A semiconductor chip comprising: a connection wiring formed on a side surface of the opening and connected to the surface wiring. 2. The semiconductor chip according to claim 1, wherein an inclination angle of a side surface of the opening is an angle within a range of 30 to 60 degrees with respect to the first main surface. A lower substrate with solder bumps;
A semiconductor chip having a hole whose area decreases from the first main surface toward the second main surface, a surface wiring formed on the first main surface of the semiconductor substrate, and the hole The semiconductor chip including a connection wiring connected to the surface wiring, formed on the side surface of
A semiconductor multilayer circuit, wherein the semiconductor chip is provided on the lower substrate, and the connection wiring is connected to the solder bump. 4. The semiconductor multilayer circuit according to claim 3, wherein an inclination angle of a side surface of the opening is an angle within a range of 30 to 60 degrees with respect to the first main surface. 5. The semiconductor multilayer circuit according to claim 3, wherein a resin is filled between the lower substrate and the semiconductor chip. Forming a recess having a smaller area toward the second main surface on the first main surface side of the semiconductor substrate;
Forming a surface wiring on the first main surface of the semiconductor substrate, and forming a connection wiring connected to the surface wiring on a side surface of the recess;
And a step of thinning the semiconductor substrate from the second main surface side until it reaches at least the concave portion. Forming a recess having a smaller area toward the second main surface on the first main surface side of the semiconductor substrate;
Forming the hole by thinning the semiconductor substrate from the second main surface side until reaching at least the recess;
Forming a surface wiring on the first main surface of the semiconductor substrate, and forming a connection wiring connected to the surface wiring on a side surface of the opening. Manufacturing method. 8. The semiconductor according to claim 6, wherein in forming the recess, an inclination angle of a side surface of the recess is set to an angle within a range of 30 to 60 degrees with respect to the first main surface. 9. Chip manufacturing method.

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